74HC2G126; 74HCT2G126 Dual buffer/line driver; 3-state Rev. 04 — 24 September 2009 Product data sheet 1. General description The 74HC2G126; 74HCT2G126 is a high-speed Si-gate CMOS device. The 74HC2G126; 74HCT2G126 provides two non-inverting buffer/line drivers with 3-state output. The 3-state output is controlled by the output enable input pin nOE. A LOW at pin nOE causes the output to assume a high-impedance OFF-state. The bus driver output currents are equal compared to the 74HC126 and 74HCT126. 2. Features n n n n n n Wide operating voltage from 2.0 V to 6.0 V Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: u HBM JESD22-A114F exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number 74HC2G126DP Package Temperature range Name Description Version −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm 74HCT2G126DP 74HC2G126DC 74HCT2G126DC 74HC2G126GD 74HCT2G126GD 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state 4. Marking Marking codes[1] Table 2. Type number Marking code 74HC2G126DP H26 74HCT2G126DP T26 74HC2G126DC H26 74HCT2G126DC T26 74HC2G126GD H26 74HCT2G126GD T26 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 2 1 5 7 1Y 1A 2 6 1OE 1 2Y 2A 1 6 EN1 Y A 5 3 3 2OE 7 OE mna947 mna946 Fig 1. Logic symbol Fig 2. mna127 IEC logic symbol Fig 3. Logic diagram (one driver) 6. Pinning information 6.1 Pinning 74HC2G126 74HCT2G126 74HC2G126 74HCT2G126 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 001aak029 Transparent top view 001aad984 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8U) 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 2 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state 6.2 Pin description Table 3. Pin description Symbol Pin Description 1OE, 2OE 1, 7 output enable input 1A, 2A 2, 5 data input 1Y, 2Y 6, 3 data output GND 4 ground (0 V) VCC 8 supply voltage 7. Functional description Table 4. Function table[1] Input Output nOE nA nY H L L H H H L X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to (VCC + 0.5 V) [1] ICC supply current - 70 mA IGND ground current −70 - mA Tstg storage temperature −65 +150 °C - 300 mW [2] total power dissipation Ptot Min Max −0.5 +7.0 V - ±20 mA - ±20 mA - ±35 mA [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74HC_HCT2G126_4 Product data sheet Unit © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 3 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC2G126 Min Typ 74HCT2G126 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter Tamb = −40 °C to +85 °C Tamb = −40 °C to +125 °C Unit Conditions Min Typ Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - V 74HC2G126 VIH VIL VOH VOL HIGH-level input voltage VCC = 6.0 V 4.2 3.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - V IO = −6.0 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V IO = −7.8 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V LOW-level output VI = VIH or VIL voltage IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 V IO = 6.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V VI = VCC or GND; VCC = 6.0 V - - ±1.0 - ±1.0 µA - - ±5.0 - ±10 µA LOW-level input voltage HIGH-level output voltage VI = VIH or VIL II input leakage current IOZ OFF-state output VI = VIH or VIL; current VO = VCC or GND; VCC = 6.0 V 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 4 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter Tamb = −40 °C to +85 °C Tamb = −40 °C to +125 °C Unit Conditions VI = VCC or GND; IO = 0 A; VCC = 6.0 V Min Typ Max Min Max - - 10 - 20 µA ICC supply current CI input capacitance - 1.0 - - - pF CO output capacitance - 1.5 - - - pF 74HCT2G126 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = −20 µA 4.4 4.5 - 4.4 - V IO = −6.0 mA 3.84 4.32 - 3.7 - V - 0 0.1 - 0.1 V - 0.16 0.33 - 0.4 V - - ±1.0 - ±1.0 µA LOW-level output VI = VIH or VIL; VCC = 4.5 V voltage IO = 20 µA VOL IO = 6.0 mA II input leakage current VI = VCC or GND; VCC = 5.5 V IOZ OFF-state output VI = VIH or VIL; VO = current VCC or GND; VCC = 5.5 V - - ±5.0 - ±10 ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 10 - 20 µA ∆ICC additional supply current per input; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; IO = 0 A - - 375 - 410 µA CI input capacitance - 1.0 - - - pF CO output capacitance - 1.5 - - - pF 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8. Symbol Parameter Tamb = −40 °C to +85 °C Tamb = −40 °C to +125 °C Unit Conditions Min Typ[1] Max Min Max VCC = 2.0 V - 35 115 - 135 ns VCC = 4.5 V - 11 23 - 27 ns VCC = 5.0 V; CL = 15 pF - 10 - - - ns VCC = 6.0 V - 8 20 - 23 ns 74HC2G126 tpd propagation delay [2] nA to nY; see Figure 6 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 5 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8. Symbol Parameter ten enable time Tamb = −40 °C to +85 °C Tamb = −40 °C to +125 °C Unit Conditions Min Typ[1] Max Min Max VCC = 2.0 V - 40 115 - 135 ns VCC = 4.5 V - 11 23 - 27 ns - 8 20 - 23 ns VCC = 2.0 V - 25 125 - 150 ns VCC = 4.5 V - 12 25 - 30 ns - 10 21 - 26 ns VCC = 2.0 V - 18 75 - 90 ns VCC = 4.5 V - 6 15 - 18 ns - 5 13 - 15 ns output enabled - 11 - - - pF output disabled - 1 - - - pF nOE to nY; see Figure 7 [2] VCC = 6.0 V tdis disable time nOE to nY; see Figure 7 [2] VCC = 6.0 V tt transition time [2] nY; see Figure 6 VCC = 6.0 V CPD power dissipation capacitance per buffer; VI = GND to VCC [3] 74HCT2G126 tpd propagation delay [2] nA to nY; see Figure 6 VCC = 4.5 V - 15 30 - 36 ns VCC = 5.0 V; CL = 15 pF - 12 - - - ns ten enable time nOE to nY; see Figure 7; VCC = 4.5 V [2] - 11 31 - 38 ns tdis disable time nOE to nY; see Figure 7; VCC = 4.5 V [2] - 11 35 - 42 ns tt transition time nY; see Figure 6; VCC = 4.5 V [2] - 6 15 - 18 ns CPD power dissipation capacitance per buffer; VI = GND to VCC − 1.5 V [3] output enabled - 11 - - - pF output disabled - 1 - - - pF [1] All typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 6 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state 12. Waveforms VI VM nA input GND tPLH tPHL VOH VI 90% VM nY output 10% VOL tTHL tTLH mna948 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay input (nA) to output (nY) and transition time output (nY) VI nOE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mna949 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Enable and disable times Table 9. Measurement points Type Input Output VM VM VX VY 74HC2G126 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V 74HCT2G126 1.3 V 1.3 V VOL + 0.3 V VOH − 0.3 V 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 7 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Test circuit for measuring switching times Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC2G126 GND to VCC ≤ 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HCT2G126 GND to 3 V ≤ 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 8 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Package outline SOT505-2 (TSSOP8) 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 9 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA MO-187 EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 10. Package outline SOT765-1 (VSSOP8) 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 10 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm B D SOT996-2 A A E A1 detail X terminal 1 index area e1 v w b e L1 1 4 8 5 C C A B C M M y y1 C L2 L X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 L2 v w y y1 mm 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 1.5 0.5 0.3 0.15 0.05 0.6 0.4 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT996-2 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 11. Package outline SOT996-2 (XSON8U) 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 11 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT2G126_4 20090924 Product data sheet - 74HC_HCT2G126_3 - 74HC_HCT2G126_2 Modifications: 74HC_HCT2G126_3 Modifications: • Table 2: Marking codes table added. 20090507 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Quick reference data removed Added type numbers 74HC2G126GD and 74HCT2G126GD (XSON8U package) Section 8: derating factor for TSSOP8, VSSOP8 and XSON8U package added 74HC_HCT2G126_2 20051215 Product data sheet - 74HC_HCT2G126_1 74HC_HCT2G126_1 20030303 Product data sheet - - 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 12 of 14 74HC2G126; 74HCT2G126 NXP Semiconductors Dual buffer/line driver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT2G126_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 24 September 2009 13 of 14 NXP Semiconductors 74HC2G126; 74HCT2G126 Dual buffer/line driver; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 September 2009 Document identifier: 74HC_HCT2G126_4