74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger Rev. 05 — 2 July 2007 Product data sheet 1. General description 74AHC1G79 and 74AHCT1G79 are high-speed Si-gate CMOS devices. They provide a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features n n n n n n Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options ESD protection: u HBM JESD22-A114E: exceeds 2000 V u MM JESD22-A115-A: exceeds 200 V u CDM JESD22-C101C: exceeds 1000 V n Specified from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number 74AHC1G79GW Package Temperature range Name Description Version −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753 74AHCT1G79GW 74AHC1G79GV 74AHCT1G79GV 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger 4. Marking Table 2. Marking codes Type number Marking 74AHC1G79GW AP 74AHC1G79GV A79 74AHCT1G79GW CP 74AHCT1G79GV C79 5. Functional diagram 1 D Q 4 1 2 2 CP 4 D CP mna441 mna440 Fig 1. Logic symbol Fig 2. IEC logic symbol CP C C D C C TG TG C C C Q C TG TG C C mna442 Fig 3. Logic diagram 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 2 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger 6. Pinning information 6.1 Pinning 74AHC1G79 74AHCT1G79 D 1 CP 2 GND 3 5 VCC 4 Q 001aaf091 Fig 4. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description D 1 data input CP 2 clock pulse input GND 3 ground (0 V) Q 4 data output VCC 5 supply voltage 7. Functional description Table 4. Function table[1] Inputs Output CP D Q+1 ↑ L L ↑ H H L X Q [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; Q + 1 = state after the next LOW-to-HIGH CP transition. 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 3 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage IIK input clamping current VI < −0.5 V IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V IO output current −0.5 V < VO < VCC + 0.5 V [1] Min Max Unit −0.5 +7.0 V −0.5 +7.0 V −20 - mA - ±20 mA - ±25 mA ICC supply current - 75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 250 mW Tamb = −40 °C to +125 °C total power dissipation Ptot [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For both TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC1G79 Min Typ 74AHCT1G79 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V VI input voltage 0 - 5.5 0 - 5.5 V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V For type 74AHC1G79 VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 4 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH VOL 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 µA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.0 - 10 - 40 µA CI input capacitance - 1.5 10 - 10 - 10 pF For type 74AHCT1G79 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.8 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 µA IO = −8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.0 - 10 - 40 µA ∆ICC additional per input pin; VI = 3.4 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 1.5 10 - 10 - 10 pF 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 5 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; tr = tf = ≤ 3.0 ns. For test circuit see Figure 6. For waveforms see Figure 5. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 4.9 8.4 1.0 9.8 1.0 11.5 ns - 6.9 12.0 1.0 14.0 1.0 15.5 ns CL = 15 pF - 3.5 5.6 1.0 7.0 1.0 8.0 ns CL = 50 pF - 5.1 8.0 1.0 10.0 1.0 11.0 ns For type 74AHC1G79 tpd propagation delay CP to Q VCC = 3.0 V to 3.6 V [1] [2] CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V [3] tsu set-up time D to CP 3.0 1.0 - 3.0 - 4.0 - ns th hold time D to CP +2.0 −1.0 - 2.0 - 3.0 - ns tW pulse width clock HIGH or LOW 3.0 - - 3.0 - 4.0 - ns fmax maximum frequency 90 - - 90 - 70 - MHz CPD power per buffer; dissipation CL = 50 pF; f = 1 MHz; capacitance VI = GND to VCC - 15 - - - - - pF - 3.5 5.0 1.0 6.0 1.0 8.0 ns [4] For type 74AHCT1G79 tpd propagation delay CP to Q VCC = 4.5 V to 5.5 V [1] [3] CL = 15 pF - 5.0 8.0 1.0 10.0 1.0 11.0 ns tsu set-up time D to CP CL = 50 pF 3.0 1.0 - 3.0 - 4.0 - ns th hold time D to CP +2.0 −1.0 - 2.0 - 3.0 - ns tW pulse width clock HIGH or LOW 3.0 - - 3.0 - 4.0 - ns fmax maximum frequency 90 - - 90 - 70 - MHz CPD power per buffer; dissipation CL = 50 pF; f = 1 MHz; capacitance VI = GND to VCC - 16 - - - - - pF [1] [4] tpd is the same as tPLH and tPHL. [2] Typical values are measured at VCC = 3.3 V. [3] Typical values are measured at VCC = 5.0 V. [4] CPD is used to determine the dynamic power dissipation PD (µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 6 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger 12. Waveforms VI VM D input GND th th t su t su 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Q output VOL mna647 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output. Fig 5. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold times and maximum clock pulse frequency Table 9. Measurement points Type Inputs Output VI VM VM 74AHC1G79 GND to VCC 0.5 × VCC 0.5 × VCC 74AHCT1G79 GND to 3.0 V 1.5 V 0.5 × VCC VCC PULSE GENERATOR VI VO DUT RT CL mna101 Test data is given in Table 8. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Load circuitry for switching times 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 7 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 7. Package outline SOT353-1 (TSSOP5) 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 8 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 8. Package outline SOT753 (SC-74A) 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 9 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT1G79_5 20070702 Product data sheet - 74AHC_AHCT1G79_4 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. • Quick reference data and Soldering sections removed. Package SOT353 changed to SOT353-1 in Section 3 and Section 13. Figure 5 updated to include waveform definitions for set-up, hold, pulse width and maximum frequency. 74AHC_AHCT1G79_4 20020606 Product specification - 74AHC_AHCT1G79_3 74AHC_AHCT1G79_3 20020218 Product specification - 74AHC_AHCT1G79_2 74AHC_AHCT1G79_2 20010222 Product specification - 74AHC_AHCT1G79_1 74AHC_AHCT1G79_1 19990518 Product specification - - 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 10 of 12 74AHC1G79; 74AHCT1G79 NXP Semiconductors Single D-type flip-flop; positive-edge trigger 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74AHC_AHCT1G79_5 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 05 — 2 July 2007 11 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 July 2007 Document identifier: 74AHC_AHCT1G79_5