PHILIPS DAC1627D1G25

DAC1627D1G25
Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and
x8 interpolating
Rev. 1 — 29 April 2011
Objective data sheet
1. General description
The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter
(DAC) with selectable ×2, ×4 and ×8 interpolating filters optimized for multi-carrier and
broadband wireless transmitters at sample rates of up to 1.25 Gsps. Supplied from a
3.3 V and a 1.8 V source, the DAC1627D1G25 integrates a differential scalable output
current up to 31.8 mA.
The DAC1627D1G25 is capable of meeting multi-carrier GSM specifications. For
example, with an output frequency of 150 MHz and a DAC clock frequency of 1.22 Gsps
the full-scale dynamic range is:
• SFDRRBW = 85 dBc (bandwidth = 250 MHz)
• IMD3 = 85 dBc
The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25.
The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data
Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR
interface accepts a multiplex input data stream such as interleaved or folded. An internal
LVDS input auto-calibration ensures the robustness and stability of the interface.
Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. The
mixer frequency is set by a 40-bit Numerically Controlled Oscillator (NCO). High resolution
internal gain, phase and offset control provide outstanding image and Local Oscillator
(LO) signal rejection at the system analog modulator output.
An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at
the DAC output.
Multiple device synchronization allows synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
The DAC1627D1G25 includes a very low noise capacitor-free integrated Phase-Locked
Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.
The DAC1627D1G25 is available in a HVQFN72 package (10 mm × 10 mm).
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
2. Features and benefits
„ Dual 16-bit resolution
„ 1.25 Gsps maximum update rate
„ Selectable ×2, ×4 and ×8 interpolation
filters
„ Very low noise capacitor-free integrated
Phase-Locked Loop (PLL)
„ Embedded Numerically Controlled
Oscillator (NCO) with 40-bit
programmable frequency
„ Embedded complex modulator
„ 1.8 V and 3.3 V power supplies
„ LVDS DDR compatible input interface
with on-chip 100 Ω terminations
„ LVDS DDR input clock up to 312.5 MHz
„ LVDS or LVPECL compatible DAC clock
„ Interleaved or folded I and Q data input
mode
„ Synchronization of multiple DAC
devices
„ 3 or 4 wires mode SPI interface
„ Differential scalable output current from
6.95 mA to 31.8 mA
„ External analog offset control
(10-bit auxiliary DACs)
„ High resolution internal digital gain and
offset control to support high
performance IQ-modulator image
rejection
„ Internal phase correction
„ Inverse (sin x) / x function
„ Power-down mode and Sleep mode;
5-bit NCO low power mode
„ On-chip 1.25 V reference
„ Industrial temperature range −40 °C to
+85 °C
„ 72 pins small form factor HVQFN
package
3. Applications
„
„
„
„
„
„
„
Wireless infrastructure: MG_GSM, LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1.
Ordering information
Type number
DAC1627D1G25
DAC1627D1G25
Objective data sheet
Package
Name
Description
Version
HVQFN72
plastic thermal enhanced very thin quad flat package; no leads;
72 terminals; body 10 × 10 × 0.85 mm
SOT813-3
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
2 of 69
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SDO
SDIO
SCS_N
SCLK
DAC1627D
NCO
40-bit frequency setting
16-bit phase adjustment
SPI
cos
10-BIT
OFFSET
CONTROL
LDCLKP
CDI
x2
FIR 3
x2
FIR 1
FIR 2
-
FIR 3
+
LDCLKN
x2
x2
x2
IOUTAP
+
MDS
COARSE
16
AUXAN
+
X
sin X
PHASE
COMP
DAC A
OFFSET
CONTROL
X
sin X
PHASE
COMP
IOUTAN
+
REF.
BANDGAP
AND
BIASING
+
GAPOUT
VIRES
IOUTBP
DAC B
IOUTBN
10-BIT
ANALOG GAIN
CONTROL
CLKP
CLOCK GENERATOR/PLL
CLKN
COMPLEX MODULATOR
MDSP
MDSN
10-BIT
OFFSET
CONTROL
MULTI-DAC
SYNCHRONIZATION
Fig 1.
Block diagram
AUXBP
AUXBN
001aan827
3 of 69
© NXP B.V. 2011. All rights reserved.
DAC1627D1G25
RESET_N
AUX.
DAC
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Rev. 1 — 29 April 2011
All information provided in this document is subject to legal disclaimers.
LD(15)N to
LD(0)N
x2
16
FIR 2
PHASE COMPENSATION
DIGITAL GAIN/OFFSET
ALIGNP
LVDS
DDR/
DIF
AUXAP
10-BIT
ANALOG GAIN
CONTROL
FIR 1
LD(15)P to
LD(0)P
AUX.
DAC
sin
DCMSU
ALIGNN
NXP Semiconductors
DAC1627D1G25
Objective data sheet
5. Block diagram
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
6. Pinning information
55 VDDA(1V8)_D
56 IOUTBN
57 IOUTBP
58 VDDA(1V8)_D
59 VDDA(3V3)
60 AUXBP
61 AUXBN
62 VDDA(1V8)_P1
63 VIRES
64 GAPOUT
65 VDDA(1V8)_P2
66 AUXAN
67 AUXAP
68 VDDA(3V3)
69 VDDA(1V8)_D
70 IOUTAP
terminal 1
index area
71 IOUTAN
72 VDDA(1V8)_D
6.1 Pinning
CLKP
1
54 RESET_N
CLKN
2
53 SCS_N
MDSP
3
52 SCLK
MDSN
4
51 SDIO
TM
5
50 SDO
ALIGNP
6
49 IO0
ALIGNN
7
48 IO1
LD[15]P
8
47 LD[0]N
LD[15]N
9
46 LD[0]P
DAC1627D1G25
LD[14]P 10
45 LD[1]N
44 LD[1]P
LD[14]N 11
43 VDDD(1V8)
VDDD(1V8) 12
VDDD(1V8) 36
LD[5]N 35
LD[5]P 34
LD[6]N 33
LD[6]P 32
LD[7]N 31
LD[7]P 30
GND_DP 29
LCKN 28
VDDD(1V8) 26
LCKP 27
LD[8]N 25
37 LD[4]P
LD[8]P 24
38 LD[4]N
LD[11]N 18
LD[9]N 23
39 LD[3]P
LD[11]P 17
LD[9]P 22
40 LD[3]N
LD[12]N 16
LD[10]N 21
41 LD[2]P
LD[12]P 15
LD[10]P 20
42 LD[2]N
LD[13]N 14
VDDD(1V8) 19
LD[13]P 13
001aan828
Transparent top view
Fig 2.
Pin configuration
6.2 Pin description
DAC1627D1G25
Objective data sheet
Table 2.
Pin description
Symbol
Pin
Type[1]
Description
CLKP
1
I
DAC clock positive input
CLKN
2
I
DAC clock negative input
MDSP
3
IO
multi-device synchronization positive signal
MDSN
4
IO
multi-device synchronization negative signal
TM
5
I
Test mode selection (connect to GND)
ALIGNP
6
I
positive input for data alignment
ALIGNN
7
I
negative input for data tanglement
LD[15]P
8
I
LVDS positive input bit 15[2]
LD[15]N
9
I
LVDS negative input bit 15[2]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 2.
DAC1627D1G25
Objective data sheet
Pin description …continued
Symbol
Pin
Type[1]
Description
LD[14]P
10
I
LVDS positive input bit 14[2]
LD[14]N
11
I
LVDS negative input bit 14[2]
VDDD(1V8)
12
P
1.8 V digital power supply
LD[13]P
13
I
LVDS positive input bit 13[2]
LD[13]N
14
I
LVDS negative input bit 13[2]
LD[12]P
15
I
LVDS positive input bit 12[2]
LD[12]N
16
I
LVDS negative input bit 12[2]
LD[11]P
17
I
LVDS positive input bit 11[2]
LD[11]N
18
I
LVDS negative input bit 11[2]
VDDD(1V8)
19
P
1.8 V digital power supply
LD[10]P
20
I
LVDS positive input bit 10[2]
LD[10]N
21
I
LVDS negative input bit 10[2]
LD[9]P
22
I
LVDS positive input bit 9[2]
LD[9]N
23
I
LVDS negative input bit 9[2]
LD[8]P
24
I
LVDS positive input bit 8[2]
LD[8]N
25
I
LVDS negative input bit 8[2]
VDDD(1V8)
26
P
1.8 V digital power supply
LCKP
27
I
LVDS positive data clock input
LCKN
28
I
LVDS negative data clock input
GND_DP
29
G
connect to ground
LD[7]P
30
I
LVDS positive input bit 7[2]
LD[7]N
31
I
LVDS negative input bit 7[2]
LD[6]P
32
I
LVDS positive input bit 6[2]
LD[6]N
33
I
LVDS negative input bit 6[2]
LD[5]P
34
I
LVDS positive input bit 5[2]
LD[5]N
35
I
LVDS negative input bit 5[2]
VDDD(1V8)
36
P
1.8 V digital power supply
LD[4]P
37
I
LVDS positive input bit 4[2]
LD[4]N
38
I
LVDS negative input bit 4[2]
LD[3]P
39
I
LVDS positive input bit 3[2]
LD[3]N
40
I
LVDS negative input bit 3[2]
LD[2]P
41
I
LVDS positive input bit 2[2]
LD[2]N
42
I
LVDS negative input bit 2[2]
VDDD(1V8)
43
P
1.8 V digital power supply
LD[1]P
44
I
LVDS positive input bit 1[2]
LD[1]N
45
I
LVDS negative input bit 1[2]
LD[0]P
46
I
LVDS positive input bit 0[2]
LD[0]N
47
I
LVDS negative input bit 0[2]
IO1
48
IO
IO port bit 1
IO0
49
IO
IO port bit 0
SDO
50
O
SPI data output
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 2.
Pin description …continued
Symbol
Pin
Type[1]
Description
SDIO
51
IO
SPI data input/output
SCLK
52
I
SPI clock
SCS_N
53
I
SPI chip select (active LOW)
RESET_N
54
I
general reset (active LOW)
VDDA(1V8)_D
55
P
1.8 V analog power supply (DAC core)
IOUTBN
56
O
complementary DAC B output current
IOUTBP
57
O
DAC B output current
VDDA(1V8)_D
58
P
1.8 V analog power supply (DAC core)
VDDA(3V3)
59
P
3.3 V analog power supply
AUXBP
60
O
auxiliary DAC B output current
AUXBN
61
O
complementary auxiliary DAC B output current
VDDA(1V8)_P1
62
P
1.8 V analog power supply (PLL)
VIRES
63
IO
DAC biasing resistor
GAPOUT
64
IO
band gap input/output voltage
VDDA(1V8)_P2
65
P
1.8 V analog power supply (PLL)
AUXAN
66
O
complementary auxiliary DAC A output current
AUXAP
67
O
auxiliary DAC A output current
VDDA(3V3)
68
P
3.3 V analog power supply
VDDA1V8_D
69
P
1.8 V analog power supply (DAC core)
IOUTAP
70
O
DAC A output current
IOUTAN
71
O
complementary DAC A output current
VDDA(1V8)_D
72
P
1.8 V analog power supply (DAC core)
GND
H
G
ground (exposed die pad)
[1]
P: power supply; G: ground; I: input; O: output.
[2]
The LVDS input data bus order can be reversed and each element can be swapped between P and N using
dedicated registers (see Table 86, Table 87 and Table 88).
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Min
Max
Unit
VDDA(3V3) analog supply voltage
(3.3 V)
Symbol
Parameter
Conditions
−0.5
+4.6
V
VDDD(1V8) digital supply voltage
(1.8 V)
−0.5
+2.5
V
−0.5
+2.5
V
[1]
VDDA(1V8) analog supply voltage
(1.8 V)
DAC1627D1G25
Objective data sheet
VI
input voltage
input pins referenced to GND
−0.5
<tbd>
V
VO
output voltage
pins IOUTAP, IOUTAN,
IOUTBP, IOUTBN, AUXAP,
AUXAN, AUXBP and AUXBN
referenced to GND
−0.5
+4.6
V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 3.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Tstg
Min
Max
Unit
storage temperature
−55
+150
°C
Tamb
ambient temperature
−40
+85
°C
Tj
junction temperature
−40
+125
°C
[1]
Conditions
The analog 1.8 V power supply must be connected to pins VDDA1V8_D, VDDA1V8_P1, and
VDDA1V8_P2.
8. Thermal characteristics
Table 4.
Symbol
Objective data sheet
Parameter
Conditions
Rth(j-a)
thermal resistance from junction
to ambient
[1]
Rth(j-c)
thermal resistance from junction
to case
[1]
[1]
DAC1627D1G25
Thermal characteristics
Typ
Unit
16.2
K/W
6.7
K/W
Value for six layers board in still air with a minimum of 49 thermal vias.
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Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
9. Characteristics
Table 5.
Characteristics
VDDA(1V8) = 1.8 V; VDDD(1V8) = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 22; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
Min
Typ
Max
Unit
[1]
VDDA(3V3)
analog supply
voltage (3.3 V)
C
3.15
3.3
3.45
V
VDDD(1V8)
digital supply
voltage (1.8 V)
C
1.7
1.8
1.9
V
VDDA(1V8)
analog supply
voltage (1.8 V)
C
1.7
1.8
1.9
V
IDDA(3V3)
analog supply
current (3.3 V)
Aux DAC on
C
<tbd>
63
<tbd>
mA
IDDD(1V8)
digital supply
current (1.8 V)
fs = 983.04 67;
×4 interpolation; no NCO;
MDS on
C
<tbd>
520
<tbd>
mA
fs = 620 Msps;
×2 interpolation; NCO on;
no MDS
C
<tbd>
440
<tbd>
mA
analog supply
current (1.8 V)
fs = 983.04 Msps; 1 V (p-p)
C
<tbd>
210
<tbd>
mA
fs = 620 Msps; 1 V (p-p)
C
<tbd>
210
<tbd>
mA
total power
dissipation
fs = 1228.8 Msps;
×4 interpolation; NCO on;
MDS off
C
-
1770
-
mW
fs = 983.04 Msps;
×4 interpolation; 5-bit NCO;
MDS off
C
-
1530
-
mW
fs = 983.04 Msps;
×4 interpolation; NCO off;
MDS off
C
-
<tbd>
-
mW
fs = 737.28 Msps;
×4 interpolation; 5-bit NCO;
MDS off
C
-
1540
-
mW
-
1400
-
mW
C
-
1.2
-
mW
C
200
-
2000
mV
IDDA(1V8)
Ptot
[2]
[2]
fs = 620 Msps;
×2 interpolation; 40-bit NCO;
MDS off
full power-down
Clock inputs (pins CLKP, CLKN)
Vi(clk)dif
differential clock
input voltage
peak-to-peak
Ri
input resistance
D
-
<tbd>
-
MΩ
Ci
input capacitance
D
-
<tbd>
-
pF
Digital inputs (pins LD[15]P to LD[0]P, LD[15]N to LD[0]N, LCKP and LCKN)
Vi
input voltage
|Vgpd| < 50 mV[3]
C
825
-
1575
mV
Vidth
input differential |Vgpd| < 50 mV[3]
threshold voltage
C
−100
-
+100
mV
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
8 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 5.
Characteristics …continued
VDDA(1V8) = 1.8 V; VDDD(1V8) = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 22; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
Min
Typ
Max
Unit
[1]
Ri
input resistance
D
-
100
-
Ω
Ci
input capacitance
D
-
<tbd>
-
pF
C
-
600
-
mV
Digital inputs/outputs (pins MDSN, MDSP)
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
Co(L)
output load
capacitance
between GND and pin
MDSN or MDSP
D
-
-
<tbd>
pF
Ci
input capacitance between GND and pin
MDSN or MDSP
D
-
<tbd>
-
pF
Ri
input resistance
D
-
100
-
Ω
Vi
input voltage
mV[3]
C
825
-
1575
mV
Vidth
input differential |Vgpd| < 50 mV[3]
threshold voltage
C
−100
-
+100
mV
-
0.3VDD(1V8) V
|Vgpd| < 50
Digital inputs/outputs (pins SDO, SDIO, SCLK, SCS_N, RESET_N)
VIL
LOW-level input
voltage
C
GND
VIH
HIGH-level input
voltage
C
0.7VDD(1V8) -
VDD(1V8)
V
VOL
LOW-level output pins SDO and SDIO
voltage
C
0
-
<tbd>
V
VOH
HIGH-level
output voltage
pins SDO and SDIO
C
<tbd>
-
VDD(1V8)
V
IIL
LOW-level input
current
VIL = <tbd> V
I
-
<tbd>
-
μA
IIH
HIGH-level input
current
VIH = <tbd> V
I
-
<tbd>
-
μA
Ci
input capacitance
D
-
<tbd>
-
pF
controlled by the analog
D
GAIN registers (see Table 46
to Table 49)
6.19
-
31.8
mA
default value
D
-
20
-
mA
compliance range
D
<tbd>
-
VDDA(3V3)
V
Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN)
IO(fs)
full-scale output
current
VO
output voltage
VO(cm)
common-mode
output voltage
D
-
2.8
-
V
Ro
output resistance
D
-
250
-
kΩ
Co
output
capacitance
D
-
3
-
pF
NDAC(mono)
DAC
monotonicity
D
-
<tbd>
-
bits
DAC1627D1G25
Objective data sheet
guaranteed
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
9 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 5.
Characteristics …continued
VDDA(1V8) = 1.8 V; VDDD(1V8) = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 22; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
Min
Typ
Max
Unit
[1]
ΔEO
offset error
variation
D
-
<tbd>
-
ppm/°C
ΔEG
gain error
variation
D
-
<tbd>
-
ppm/°C
Reference voltage output (pin GAPOUT)
VO(ref)
reference output
voltage
Tamb = +25 °C
I
<tbd>
1.25
<tbd>
V
IO(ref)
reference output
current
1.25 V external voltage
D
-
40
-
μA
ΔVO(ref)
reference output
voltage variation
C
-
<tbd>
-
ppm/°C
Analog auxiliary outputs (pins AUXAP, AUXAN, AUXBP and AUXBN)
IO(fs)
VO(aux)
full-scale output
current
auxiliary output
voltage
NDAC(aux)mono auxiliary DAC
monotonicity
auxiliary DAC A;
differential outputs
I
-
2.2
-
mA
auxiliary DAC B;
differential outputs
I
-
2.2
-
mA
compliance range
C
0
-
2
V
guaranteed
D
-
10
-
Bits
input; ×2 interpolation
C
<tbd>
-
312.5
MHz
input; ×4 interpolation
C
<tbd>
-
312.5
MHz
LVDS input timing
fdata
data rate
input; ×8 interpolation
tsk(clk-D)
skew time from
clock to data
input
C
<tbd>
-
156.25
MHz
C
−<tbd>
-
+<tbd>
ps
C
-
-
1250
Msps
D
-
20
-
ns
C
-
-
1000
Msps
D
-
−500
-
MHz
DAC output timing
fs
sampling rate
ts
settling time
to ± 0.5 LSB
Internal PLL timing
fs
sampling rate
40-bit NCO frequency range; fs = 1000 Msps
fNCO
NCO frequency
two’s complement coding
reg value = 8000000000h
fstep
step frequency
DAC1627D1G25
Objective data sheet
reg value = FFFFFFFFFFh D
-
−0.9095
-
mHz
reg value = 0000000000h
D
-
0
-
Hz
reg value = 0000000001h
D
-
+0.9095
-
mHz
reg value = 7FFFFFFFFFh D
-
+499.99909 -
MHz
D
-
0.9095
mHz
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Table 5.
Characteristics …continued
VDDA(1V8) = 1.8 V; VDDD(1V8) = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 22; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
Min
Typ
Max
Unit
-
−500
-
MHz
[1]
Low power NCO frequency range; fs = 1000 MHz
fNCO
NCO frequency
two’s complement coding
reg value = F8000000000h
fstep
D
reg value = F8000000000h
D
-
−31.25
-
MHz
reg value = 00000000000h
D
-
0
-
Hz
reg value = 08000000000h
D
-
+31.25
-
MHz
reg value = 7FFFFFFFFFh
D
-
+468.75
-
MHz
D
-
31.25
-
MHz
I
-
83
-
dBc
I
-
85
-
dBc
BW = 100 MHz
I
-
90
-
dBc
BW = 180 MHz
I
-
<tbd>
-
dBc
BW = 100 MHz
I
-
<tbd>
-
dBc
BW = 180 MHz
I
-
<tbd>
-
dBc
fdata = 245.76 MHz;
fs = 983.04 Msps;
fo1 = 20 MHz; fo2 = 21 MHz;
×4 interpolation;
output level = −1 dBFS
I
-
93
-
dBc
fdata = 245.76 MHz;
fs = 983.04 Msps;
fo1 = 152 MHz;
fo2 = 155.1 MHz;
fs = 1228.8 MHz;
×4 interpolation;
output level = −1 dBFS
I
-
85
-
dBc
step frequency
Dynamic performance
SFDR
spurious-free
dynamic range
fdata = 307.2 MHz;
fs = 1228.8 Msps; BW = fs / 2
fo = 20 MHz at −1 dBFS;
fdata = 245.76 MHz;
fs = 983.04 Msps; BW = fs / 2
fo = 20 MHz at −1 dBFS
SFDRRBW
restricted
bandwidth
spurious-free
dynamic range
fdata = 245.76 MHz;
fs = 983.04 Msps;
fo = 150 MHz
fdata = 307.2 MHz;
fs = 1228.8 Msps;
fo = 210 MHz
IMD3
third-order
intermodulation
distortion
DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 5.
Characteristics …continued
VDDA(1V8) = 1.8 V; VDDD(1V8) = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 22; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
Min
Typ
Max
Unit
[1]
ACPR
NSD
adjacent channel fs = 1228.8 Msps;
power ratio
×4 interpolation;
fo = 210 MHz
noise spectral
density
1 carrier; BW = 5 MHz
D
-
77
-
dBc
2 carriers; BW = 10 MHz
D
-
73
-
dBc
4 carriers; BW = 20 MHz
D
-
72
-
dBc
fs = 983.04 Msps;
×4 interpolation;
fo = 20 MHz at −1 dBFS
D
-
-164
-
dBm/Hz
fs = 983.04 Msps;
×4 interpolation;
fo = 153.6 MHz at −1 dBFS
D
-
-161
-
dBm/Hz
[1]
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2]
VDDA(1V8)_D, VDDA(1V8)_P1 and VDDA(1V8)_P2 must be connected to the same 1.8 V analog power supply. it is recommended to use
dedicated filters for the three power pins.
[3]
|Vgpd| represents the ground potential difference voltage. This voltage is the result of current flowing through the finite resistance and the
inductance between the receiver and the driver circuit ground voltages.
10. Application information
10.1 General description
The DAC1627D1G25 is a dual 16-bit DAC operating up to 1250 Msps. Each DAC consists
of a segmented architecture, comprising a 6-bit thermometer sub-DAC and a 10-bit binary
weighted sub-DAC.
A maximum input LVDS DDR data rate of up to 312.5 MHz and a maximum output
sampling rate of 1250 Msps ensure more flexibility for wide bandwidth and multi-carrier
systems. The internal 40-bit NCO of the DAC1627D1G25 simplifies the frequency
selection of the system. The DAC1627D1G25 provides ×2, ×4 or ×8 interpolation filters
that are very useful for removing the undesired images.
Each DAC generates two complementary current outputs on pins IOUTAP and IOUTAN
and pins IOUTBP and IOUTBN. These outputs provide a full-scale output current (IO(fs)) of
up to 31.8 mA. An internal reference is available for the reference current which is
externally adjustable using pin VIRES.
High resolution internal gain, phase and offset control provide outstanding image and
Local Oscillator (LO) signal rejection at the system analog modulator output.
Multiple device synchronization enables synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
All functions can be set using an SPI interface.
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.2 Serial Peripheral Interface (SPI)
10.2.1 Protocol description
The DAC1627D1G25 serial interface is a synchronous serial communication port ensures
easy interface with many industry microprocessors. It provides access to the registers that
define the operating modes of the chip in both write and read mode.
This interface can be configured as a 3-wire type (pin SDIO as bidirectional pin) or 4-wire
type (pins SDIO and SDO as unidirectional pins, input and output port respectively). In
both configurations, SCLK acts as the serial clock and SCS_N as the serial chip select.
Figure 3 shows the SPI protocol. Each read/write operation is followed by an SCS_N
signal and enabled by a LOW assertion to drive the chip with two to five bytes, depending
on the content of the instruction byte (see Table 7).
RESET_N
(optional)
SCS_N
SCLK
SDIO
R/W
N1
N0
A4
A3
A2
A1
A0
SDO
(optional)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
001aan829
Fig 3.
SPI protocol
R/W indicates the mode access (see Table 6)
Table 6.
Read or Write mode access description
R/W
Description
0
Write mode operation
1
Read mode operation
Table 7 shows the number of bytes to be transferred. N1 and N0 indicate the number of
bytes transferred after the instruction byte.
Table 7.
Number of bytes to be transferred
N1
N0
Number of bytes transferred
0
0
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 bytes
A[4:0] indicates which register is being addressed. If a multiple transfer occurs, this
address concerns the first register. Next are those which follow directly in a decreasing
order (see Table 23, Table 55 and Table 79).
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
The DAC1627D1G25 incorporates more than the 32 SPI registers allowed by the address
value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each
containing 32 registers. The 32nd register of each page indicates which page is currently
addressed (00h, 01h or 0Ah).
10.2.2 SPI timing description
The SPI interface can operate at a frequency up to 15 MHz. The SPI timings are shown in
Figure 4.
tw(RESET_N)
RESET_N
(optional)
50 %
th(SCS_N)
tsu(SCS_N)
SCS_N
50 %
tw(SCLK)
SCLK
SDIO
50 %
50 %
th(SDIO)
tsu(SDIO)
Fig 4.
001aan830
SPI timing diagram
The SPI timing characteristics are given in Table 8.
Table 8.
SPI timing characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fSCLK
SCLK frequency
-
-
25
MHz
tw(SCLK)
SCLK pulse
width
30
-
-
ns
tsu(SCS_N)
SCS_N set-up
time
20
-
-
ns
th(SCS_N)
SCS_N hold
time
20
-
-
ns
tsu(SDIO)
SDIO set-up
time
10
-
-
ns
th(SDIO)
SDIO hold time
5
-
-
ns
tw(RESET_N)
RESET_N pulse
width
30
-
-
ns
10.3 Power-on sequence
There are three steps for the power-on sequence (see Figure 5):
1. The board is power-on. At the turn-on time, all DAC1627D1G25 supplies have
reached their specification ranges.
2. At least 1 μs after the turn-on time pin RESET_N must be released.
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
3. When the DAC clock and LVDS clock are stable, the SPI configuration is sent to the
DAC1627D1G25. Writing 0 in bits RST_DCLK and RST_LCLK of the register
MAIN_CNTRL (see Table 80) starts the automatic calibration. 30 μs after this
calibration, the DAC1627D1G25 is operational.
WRITE DAC CONFIGURATION
START CLOCK CALIBRATION
SPI bus
RESET_N
power supplies
ton
trst
power in
specification
range
Fig 5.
time
tspi_start
001aan810
Power-on sequence
10.4 LVDS Data Input Format (DIF) block
The Data Input Formatting (DIF) block captures and resynchronizes data on the LVDS bus
with its own LCLKP/LCLKN clock. Each LVDS input buffer has an internal resistance of
100 Ω, so an external resistor is not required. The DIF block includes two sub-blocks:
• LDVS receiver:
Provides high flexibility for the LVDS interface, especially for the PCB layout and the
control of the input port polarity and the input port mapping.
• Data format block:
Enables the adaptation, which ensures the support of several data encoding modes.
LD[15]P
16 PA[15..0]
16
I[15..0]
to DAC A
LD[15]N
LD[0]P
LD[0]N
16 PB[15..0]
LVDS
RECEIVER
DATA
FORMAT
16 Q[15..0]
to DAC B
LCLKP
LCLKN
Fig 6.
LCLK
001aan392
LVDS Data Input Format (DIF) block diagram
10.4.1 Input port polarity
The polarity of each individual LVDS input (LD[15]P to LD[0]P and LD[15]N to LD[0]N) can
be changed, ensuring a much easier PCB layout design. The input polarity is controlled
with bits LD_POL[7:0] in register LD_POL_LSB (see Table 86) and bits LD_POL[15:8] in
register LD_POL_MSB (see Table 87).
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.4.2 Input port mapping
Inverting the order of the LSB and the MSB of the LVDS bus using bit WORD_SWAP in
register LD_CNTRL (see Table 88) also simplifies the design of the PCB (see Table 9).
Table 9.
Input LVDS bus swapping
Internal LVDS bus
External LVDS bus
(WORD_SWAP = 0)
External LVDS bus
(WORD_SWAP = 1)
LDI[15]P,N
LD[15]P,N
LD[0]P,N
LDI[14]P,N
LD[14]P,N
LD[1]P,N
LDI[13]P,N
LD[13]P,N
LD[2]P,N
LDI[12]P,N
LD[12]P,N
LD[3]P,N
LDI[11]P,N
LD[11]P,N
LD[4]P,N
LDI[10]P,N
LD[10]P,N
LD[5]P,N
LDI[9]P,N
LD[9]P,N
LD[6]P,N
LDI[8]P,N
LD[8]P,N
LD[7]P,N
LDI[7]P,N
LD[7]P,N
LD[8]P,N
LDI[6]P,N
LD[6]P,N
LD[9]P,N
LDI[5]P,N
LD[5]P,N
LD[10]P,N
LDI[4]P,N
LD[4]P,N
LD[11]P,N
LDI[3]P,N
LD[3]P,N
LD[12]P,N
LDI[2]P,N
LD[2]P,N
LD[13]P,N
LDI[1]P,N
LD[1]P,N
LD[14]P,N
LDI[0]P,N
LD[0]P,N
LD[15]P,N
10.4.3 Input port swapping
The LVDS DDR receiver block internally maps the incoming LVDS data bus into two
buses with a single data rate (Figure 7).
A0
B0
A1
B1
A2
B2
A3
B3
A2
A3
B2
B3
to DAC A
PA[15..0]
A0
A1
LD[15..0]P/N
LVDS
RECEIVER
PB[15..0]
LCLKP/N
B0
B1
to DAC B
LCLK
001aan393
Fig 7.
LVDS DDR receiver mapping LDAB SWAP = 0
These two buses can be swapped internally using bit LDAB_SWAP of register
LD_CNTRL (see Table 88 and Figure 8).
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
B0
B1
PA[15..0]
A0
B0
A1
B1
A2
B2
A3
B3
B2
B3
A2
A3
to DAC A
LD[15..0]P/N
LVDS
RECEIVER
A0
A1
PB[15..0]
to DAC B
LCLK
LCLKP/N
001aan394
Fig 8.
LVDS DDR receiver mapping LDAB SWAP = 1
10.4.4 Input port formatting
The LVDS DDR input bus multiplexes two 16-bit streams. The LVDS receiver block
demultiplexes these two streams.
The two streams can carry two data formats:
• Folded
• Interleaved
The data format block is in charge of the data format adaptation (see Figure 9).
A0
A1
A2
A3
I0
A0
B0
A1
B1
A2
B2
A3
B3
I1
I2
I3
Q2
Q3
to DAC A
PA[15..0]
LD[15..0]P/N
LVDS
RECEIVER
B0
B1
B2
B3
DATA
FORMAT
Q0
LCLKP/N
Q1
to DAC B
PB[15..0]
LCLK
001aan395
Fig 9.
LVDS DDR data formats
The DAC1627D1G25 can correctly decode the input stream using bit IQ_FORMAT of
register LD_CNTRL (see Table 88), because it can determine which format is used on the
LVDS DDR bus.
Table 10 shows the format mapping between the LVDS input data and the data sent to the
two DAC channels depending on the data format selected.
Table 10.
Folded and interleaved format mapping
Data format
Data bit mapping
interleaved format (IQ_FORMAT = 1)
In[15..0] = An[15..0]; Qn[15..0] = Bn[15..0]
folded format (IQ_FORMAT = 0)
In[15..8] = An[15..8]; In[7..0] = Bn[15..8]
Qn[15..8] = An[7..0]; Qn[7..0] = Bn[7..0]
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.5 Input clock
The DAC1627D1G25 operates with two clocks, one for the LVDS DDR interface and one
for the DAC core.
10.5.1 LVDS DDR clock
The LVDS DDR clock can be interfaced as shown in Figure 10 because the clock buffer
contains a 100 Ω internal resistor.
DAC1627D
LCLKP
Z = 100 Ω
LVDS
100 Ω
LVDS
LCLKN
001aan811
Fig 10. LVDS DDR clock configuration
10.5.2 DAC core clock
The DAC core clock can achieve a frequency of up to 1.25 Gsps. It includes internal
biasing to support both AC-coupling and DC-coupling. The clock can be easily connected
to any LVDS, CML or PECL clock sources.
Depending on the interface selected, the hardware configuration varies
(see Figure 11 to Figure 13).
CLKP
Z = 100 Ω
100 Ω
LVDS
DAC1627D
CLKN
001aan813
a. DC-coupling
100 nF
CLKP
Z = 100 Ω
LVDS
100 Ω
100 nF
DAC1627D
CLKN
001aan812
b. AC-coupling
Fig 11. DAC core clock: LVDS configuration
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
50 Ω
3.3 V
100 nF
CLKP
Z = 50 Ω
DAC1627D
CML
100 nF
CLKN
Z = 50 Ω
50 Ω
3.3 V
001aan831
Fig 12. DAC core clock: CML configuration with AC-coupling
200 Ω
100 nF
CLKP
Z = 50 Ω
PECL
100 Ω
100 nF
DAC1627D
CLKN
Z = 50 Ω
200 Ω
001aan832
Fig 13. DAC core clock: PECL configuration with AC-coupling
10.6 Timing
The DAC1627D1G25 can operate at an update rate (fs) of up to 1.25 Gsps and with an
input data rate (fdata) of up to 312.5 MHz.
The sampling position of the LVDS data can be tuned using a 16-step compensation delay
clock. The delay clock (see Figure 14, signals LDCLKPcp and LDCLKNcp) is used
internally to obtain a control signal, which enables calibrating the compensation delay at
start-up and monitoring if the sampling position is properly aligned.
Figure 14 shows how the compensation delay helps to recover the LVDS DDR data on
both the A and B paths.
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
LDCLKN
LDCLKP
LD[i]N
Dn[i]
LD[i]P
Dn + 1[i]
Dn + 2[i]
tcmp
LDCLKNcp
LDCLKPcp
LDA[i]
Dn − 1[i]
Dn[i]
Dn + 2[i]
LDB[i]
Dn − 1[i]
Dn + 1[i]
Dn + 3[i]
001aan400
Fig 14. LVDS DDR demux timing (LVDS A and B paths not swapped; LDAB_SWAP = 0)
The compensation delay time, referred to as tcmp in Figure 14, can be tuned automatically
or manually.
Automatic tuning is recommended for a high-speed LVDS data rate (> 300 MHz). The
external LVDS data and clock signals aligns the rising and falling edges. The timing
requirement is defined in Figure 15 and in Table 5.
VIH
VIH
VIL
VIL
LVDS data
tsk(min)
tsk(max)
LVDS clock
001aan833
tsk(min) = minimum skew time
tsk(max) = maximum skew time
Fig 15. Timing requirement automatic tuning
When tuning manually, the compensation delay time (tcmp in Figure 14), can be tuned as
shown in Table 11 using bits LDCLK_DEL[3:0] of register MAN_LDCLKDEL
(see Table 81) and bit CAL_CNTRL of register MAIN_CNTRL (see Table 80).
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 11.
Compensation delay values for manual tuning
LDCLK_DEL[3:0]
CAL_CNTRL
Typical compensation delay
time
xxx
0
tcmp controlled by DCSMU
block (automatic control)
0000
1
360 ps to 405 ps
0001
1
435 ps to 540 ps
0010
1
525 ps to 645 ps
0011
1
600 ps to 720 ps
0100
1
690 ps to 825 ps
0101
1
780 ps to 900 ps
0110
1
885 ps to 1035 ps
0111
1
960 ps to 1200 ps
1000
1
1260 ps to 1980 ps
1001
1
1350 ps to 2160 ps
1010
1
1440 ps to 2340 ps
1011
1
1512 ps to 2556 ps
1100
1
1566 ps to 2754 ps
1101
1
1620 ps to 2952 ps
1110
1
1674 ps to 3060 ps
1111
1
1710 ps to 3186 ps
10.7 Operating modes
The DAC1627D1G25 requires two differential clocks:
• The LVDS clock (LDCLKP, LDCLKN) for the LVDS DDR interface
• The data clock (CLKP, CLKN) for the internal PLL and the dual DAC core
The Clock Domain Interface (CDI) and the PLL have to be set correctly to configure the
DAC1627D1G25 for an application mode. The default application is a ×2 upsampling
mode (see Section 10.7.1). The CDI can also support ×4 and ×8 upsampling modes
(see Section 10.7.2 and Section 10.7.3).
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.7.1 CDI mode 0 (x2 interpolation)
CDI mode 0 (×2 interpolation) is required when the value of the LVDS DDR clock is twice
the internal maximum CDI frequency. Table 12 shows examples of applications using an
internal PLL or an external clock for the DAC core.
Table 12.
CDI mode 0: operating modes examples
LVDS DDR
rate (MHz)
I rate;
Q rate
(Msps)
CDI
mode[1]
FIR mode[2]
320
320
0
320
320
0
SSBM
rate[3]
(Msps)
DAC rate
(Msps)
×2
640
640
320
enabled
2
×2
640
640
640
disabled
n.a.
[1]
Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 89).
[2]
Bits INTERPOLATION[1:0] of register TXCFG (see Table 25).
PLL configuration
DAC input
clock[4]
(MHz)
PLL
status[5]
PLL
divider[6]
[3]
If a Single Sideband Modulator (SSBM) is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 25).
[4]
Pins CLKP and CLKN (see Figure 2).
[5]
Bit PLL_PD of register PLLCFG (see Table 26).
[6]
Bits PLL_DIV[1:0] of register PLLCFG (see Table 26).
10.7.2 CDI mode 1 (x4 interpolation)
CDI mode 1 (×4 interpolation) is required when the values of the LVDS DDR clock and the
internal CDI frequency are equal. Table 13 shows examples of applications using an
internal PLL or an external clock for the DAC core.
Table 13.
CDI mode 1: operating modes examples
LVDS DDR
rate (MHz)
I rate;
Q rate
(Msps)
CDI
mode[1]
FIR mode[2]
250
250
1
250
250
1
SSBM
rate[3]
(Msps)
DAC rate
(Msps)
×4
1000
×4
1000
[1]
Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 89).
PLL configuration
DAC input
clock[4]
(MHz)
PLL
status[5]
PLL
divider[6]
1000
250
enabled
4
1000
1000
disabled
n.a.
[2]
Bits INTERPOLATION[1:0] of register TXCFG (see Table 25).
[3]
If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 25).
[4]
Pins CLKP and CLKN (see Figure 2).
[5]
Bit PLL_PD of register PLLCFG (see Table 26).
[6]
Bits PLL_DIV[1:0] of register PLLCFG (see Table 26).
DAC1627D1G25
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.7.3 CDI mode 2 (x8 interpolation)
CDI mode 2 (×8 interpolation) is required when the LVDS DDR clock is half the maximum
CDI frequency or less. Table 14 shows examples of applications using an internal PLL or
an external clock for the DAC core.
Table 14.
CDI mode 2: operating modes examples
LVDS DDR
rate (MHz)
I rate;
Q rate
(Msps)
CDI
mode[1]
FIR mode[2]
125
125
2
125
125
2
SSBM
rate[3]
(Msps)
DAC rate
(Msps)
×8
1000
1000
125
enabled
4
×8
1000
1000
1000
disabled
n.a.
[1]
Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 89).
[2]
Bits INTERPOLATION[1:0] of register TXCFG (see Table 25).
PLL configuration
DAC input
clock[4]
(MHz)
[3]
If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 25).
[4]
Pins CLKP and CLKN (see Figure 2).
[5]
Bit PLL_PD of register PLLCFG (see Table 26).
[6]
Bits PLL_DIV[1:0] of register PLLCFG (see Table 26).
PLL
status[5]
PLL
divider[6]
10.8 FIR filters
The DAC1627D1G25 integrates three selectable Finite Impulse Response (FIR) filters
which enable the use of the device with ×2, ×4 or ×8 interpolation rates. All three
interpolation FIR filters have a stop-band attenuation of at least 80 dBc and a pass-band
ripple of less than 0.0005 dB. Table 15 shows the coefficients of the interpolation filters.
001aao039
0
magnitude
(dB)
-20
-40
-60
-80
-100
0
0.1
0.2
0.3
0.4
0.5
NF (fs)
Fig 16. First stage half-band filter response
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
001aao040
0
magnitude
(dB)
-20
-40
-60
-80
-100
0
0.1
0.2
0.3
0.4
0.5
NF (fs)
Fig 17. Second stage half-band filter response
001aao041
0
magnitude
(dB)
-20
-40
-60
-80
-100
0
0.1
0.2
0.3
0.4
0.5
NF (fs)
Fig 18. Third stage half-band filter response
Table 15: Interpolation filter coefficients
DAC1627D1G25
Objective data sheet
First interpolation filter
Second interpolation filter
Third interpolation filter
Lower
Upper
Value
Lower
Upper
Value
Lower
Upper
Value
H(14)
-
65536
H(6)
-
32768
H(4)
-
1024
H(13)
H(15)
41501
H(5)
H(7)
20272
H(3)
H(5)
615
H(12)
H(16)
−13258
H(4)
H(8)
−5358
H(2)
H(6)
−127
H(11)
H(17)
7302
H(3)
H(9)
1986
H(1)
H(7)
27
H(10)
H(18)
−4580
H(2)
H(10)
−654
H(0)
H(8)
−3
H(9)
H(19)
2987
H(1)
H(11)
159
-
-
-
H(8)
H(20)
−1951
H(0)
H(12)
−21
-
-
-
H(7)
H(21)
1250
-
-
-
-
-
-
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 15: Interpolation filter coefficients …continued
First interpolation filter
Second interpolation filter
Third interpolation filter
Lower
Upper
Value
Lower
Upper
Value
Lower
Upper
Value
H(6)
H(22)
−773
-
-
-
-
-
-
H(5)
H(23)
456
-
-
-
-
-
-
H(4)
H(24)
−252
-
-
-
-
-
-
H(3)
H(25)
128
-
-
-
-
-
-
H(2)
H(26)
−58
-
-
-
-
-
-
H(1)
H(27)
22
-
-
-
-
-
-
H(0)
H(28)
−6
-
-
-
-
-
-
10.9 Single SideBand Modulator (SSBM)
The SSBM is a quadrature modulator that enables mixing the I data and Q data with the
sine and cosine signals generated by the NCO to generate path A and path B
(see Figure 19).
cos
A
I
sin
+/−
sin
+/−
B
Q
cos
+/−
001aan575
Fig 19. SSBM principle
The frequency of the NCO is programmed over 40 bits. NCO enables inverting the sine
component to operate a positive or negative, lower or upper SSB upconversion
(see register TXCFG in Table 25).
10.9.1 NCO in 40 bits
When using NCO, the frequency can be set over 40 bits by five registers, FREQNCO_B0
to FREQNCO_B4 (see Table 27 to Table 31).
The frequency is calculated with Equation 1.
M×f
f NCO = --------------s
40
2
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Where:
• M is the two’s complement coding representation of FREQ_NCO[40:0]
• fs is the DAC clock sampling frequency
The default settings are:
• fNCO = 96 MHz
• fs = 640 Msps
The phase of the NCO can be set by registers PHINCO_LSB and PHINCO_MSB over
16 bits from 0 to 360° (see Table 44 and Table 45).
10.9.2 NCO low power
When using NCO low power (bit NCO_LP_SEL; see Table 25), the frequency can be set
by the five MSB-bits of register FREQNCO_B4 (bits FREQ_NCO[39:35]; see Table 31).
The frequency is calculated with Equation 2.
M×f
f NCO = --------------s
5
2
(2)
Where:
• M is the two’s complement coding representation of FREQ_NCO[39:35]
• fs is the DAC clock sampling frequency
The phase of the NCO low power can be set by the five MSB-bits of register
PHINCO_MSB (see Table 45).
10.9.3 Complex modulator
The complex modulator upconverts the single side band by mixing NCO signals and I and
Q input signals. Table 16 shows the various possibilities set by bits MODULATION[2:0] of
register TXCFG (see Table 25).
Table 16.
Complex modulator operation mode
MODULATION[2:0] Mode
Path A
Path B
I( t)
Q(t)
000
bypass
001
positive
upper ssb
I ( t ) × cos ( ω NCO × t ) – Q ( t ) × sin ( ω NCO × t ) I ( t ) × sin ( ω NCO × t ) + Q ( t ) × cos ( ω NCO × t )
010
positive
lower ssb
I ( t ) × cos ( ω NCO × t ) + Q ( t ) × sin ( ω NCO × t ) I ( t ) × sin ( ω NCO × t ) – Q ( t ) × cos ( ω NCO × t )
011
negative
upper ssb
I ( t ) × cos ( ω NCO × t ) – Q ( t ) × sin ( ω NCO × t ) – I ( t ) × sin ( ω NCO × t ) – Q ( t ) × cos ( ω NCO × t )
100
negative
lower ssb
I ( t ) × cos ( ω NCO × t ) + Q ( t ) × sin ( ω NCO × t ) – I ( t ) × sin ( ω NCO × t ) + Q ( t ) × cos ( ω NCO × t )
others
not defined
-
DAC1627D1G25
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.9.4 Minus 3dB
In normal use, a full-scale pattern is also full-scale at the DAC output. Nevertheless, when
the I data and Q data come close to full-scale simultaneously, some clipping can occur.
The Minus 3dB function (bit MINUS_3DB of register DAC_OUT_CTRL; see Table 38) can
be used to reduce the 3 dB gain in the modulator. It retains a full-scale range at the DAC
output without added interferers.
10.10 Inverse sinx / x
A selectable FIR filter is incorporated to compensate the sinx / x effect caused by the
roll-off effect of the DAC. This filter introduces a loss of 3.4 dB at DC. The coefficients are
represented in Table 17.
Table 17.
Inversion filter coefficients
First interpolation filter
Lower
Upper
Value
H(1)
H(9)
+1
H(2)
H(8)
−4
H(3)
H(7)
+13
H(4)
H(6)
−51
H(5)
-
+610
10.11 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
• I OA ( fs ) = I IOUTAP + I IOUTAN
• I OB ( fs ) ) = I IOUTBP + I IOUTBN
The output current of DAC A depends on the digital input data and the gain factor defined
by bits DAC_A_DGAIN[7:0] of register DAC_A_DGAIN_LSB (see Table 34) and bits
DAC_A_DGAIN[11:8] of register DAC_A_DGAIN_MSB (see Table 35).
( DACADGAIN )
DATA
I IOUTAP = I OA ( fs ) × ----------------------------------------- × ⎛ ------------------------⎞
⎝
1024
( ( 65535 ) )⎠
(3)
( DACADGAIN )
DATA
I IOUTAN = I OA ( fs ) × ⎛ 1 – ----------------------------------------- × ⎛ ------------------------⎞ ⎞
⎝
⎝ ( ( 65535 ) )⎠ ⎠
1024
(4)
The output current of DAC B depends on the digital input data and the gain factor defined
by bits DAC_B_DGAIN[7:0] of register DAC_B_DGAIN_LSB (see Table 36) and bits
DAC_B_DGAIN[11:8] of register DAC_B_DGAIN_MSB (see Table 37).
( DACBDGAIN )
DATA
I IOUTBP = I OB ( fs ) × ----------------------------------------- × ⎛ ------------------------⎞
⎝ ( ( 65535 ) )⎠
1024
( DACBDGAIN )
DATA
I IOUTBN = I OB ( fs ) × ⎛ 1 – ----------------------------------------- × ⎛ ------------------------⎞ ⎞
⎝
⎝ ( ( 65535 ) )⎠ ⎠
1024
DAC1627D1G25
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
It is possible to define if the DAC1627D1G25 operates with a binary input or a
two's complement input (bit CODING; see Table 24).
Table 18 shows the output current as a function of the input data, when
IOA(fs) = IOB(fs) = 20 mA.
Table 18.
DAC transfer function
Data
I15 to I0/Q15 to Q0
(binary coding)
I15 to I0/Q15 to Q0
(two’s complement
coding
IOUTAP/IOUTBP
IOUTAN/IOUTBN
0
0000 0000 0000 0000
1000 0000 0000 0000
0 mA
20 mA
...
...
...
...
....
32768
1000 0000 0000 0000
0000 0000 0000 0000
10 mA
10 mA
...
...
...
...
...
65535
1111 1111 1111 1111
0111 1111 1111 1111
20 mA
0 mA
10.12 Full-scale current
10.12.1 Regulation
The DAC1627D1G25 reference circuitry integrates an internal band gap reference voltage
which delivers a 1.25 V reference on the GAPOUT pin. It is recommended to decouple pin
GAPOUT using a 100 nF capacitor.
The reference current is generated via an external resistor of 910 Ω (1 %) connected to
VIRES and a control amplifier sets the appropriate full-scale current (IOA(fs) and IOB(fs)) for
both DACs (see Figure 20)).
DAC1627D
BAND GAP
REFERENCE
100 nF
AGND
910 Ω (1 %)
AGND
GAPOUT
VIRES
DAC
CURRENT
SOURCES
ARRAY
001aan834
Fig 20. Internal reference configuration
Figure 20 shows the optimal configuration for temperature drift compensation because the
band gap reference voltage can be matched to the voltage across the feedback resistor.
The DAC current can also be adjusted by applying an external reference voltage to the
non-inverting input pin GAPOUT and by disabling the internal band gap reference voltage
(bit GAP_PON of the COMMON register; see Table 24).
10.12.2 Full-scale current adjustment
The default full-scale current (IO(fs)) is 20 mA but further adjustments can be made by the
user to both DACs independently via the serial interface from 6.95 mA to 28.7 mA, ±11 %.
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
The settings applied to DAC_A_GAIN_COARSE[3:0] (register 17h; see Table 46 and
register 18h see Table 47;) and to DAC_B_GAIN COARSE[3:0]
(register 19h; see Table 48 and register 1Ah see Table 49;) define the coarse variation of
the full-scale current (see Table 19).
Table 19. IO(fs) coarse adjustment
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
IO(fs) (mA)
Decimal
Binary
0
0000
6.95
1
0001
8.4
2
0010
9.85
3
0011
11.3
4
0100
12.75
5
0101
14.2
6
0110
15.65
7
0111
17.1
8
1000
18.55
9
1001
20
10
1010
21.45
11
1011
22.9
12
1100
24.35
13
1101
25.8
14
1110
27.25
15
1111
28.7
The settings applied to DAC_A_GAIN_FINE[5:0] (see register 17h in Table 46) and to
DAC_B_GAIN_FINE[5:0] (see register 19h in Table 48) define the fine variation of the
full-scale current (see Table 20).
Table 20. IO(fs) fine adjustment
Default settings are shown highlighted.
ΔIO(fs) (%)
DAC_GAIN_FINE[5:0]
Decimal
Two’s complement
−32
10 0000
−11
...
...
...
0
00 0000
0
...
...
...
+31
01 1111
+11
10.13 Digital offset adjustment
The DAC1627D1G25 provides digital offset correction (bits DAC_A_OFFSET[7:0] in
Table 40 and bits DAC_A_OFFSET[15:8] in Table 41 and register DAC_B_OFFSET[7:0]
in Table 42 and bits DAC_B_OFFSET[15:8] in Table 43) which can be used to adjust the
common-mode level at the output of each DAC. It adds an offset at the end of the digital
part, just before the DACs. Table 21 shows the range of variation of the digital offset.
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 21.
Digital offset adjustment
DAC_A_OFFSET[15:0]
DAC_B_OFFSET[15:0]
(two’s complement)
Offset applied
1000 0000 0000 0000
−32768
1000 0000 0000 0001
−32767
...
...
1111 1111 1111 1111
−1
0000 0000 0000 0000
0
0000 0000 0000 0001
+1
...
...
0111 1111 1111 1110
+32766
0111 1111 1111 1111
+32767
10.14 Analog output
The device has two output channels, producing two complementary current outputs,
which enable the reduction of even-order harmonics and noise. The pins are
IOUTAP/IOUTAN and IOUTBP/IOUTBN. They have to be connected via a load resistor RL
to the 3.3 V analog power supply (VDDA(3V3)).
Figure 21 shows the equivalent analog output circuit of one DAC. This circuit includes a
parallel combination of NMOS current sources and associated switches for each
segment.
3.3 V
3.3 V
RL
IOUTAP/IOUTBP
GND
RL
IOUTAN/IOUTBN
GND
001aan835
Fig 21. Equivalent analog output circuit
The cascode source configuration increases the output impedance of the source, which
improves the dynamic performance of the DAC because there is less distortion.
Depending on the application, the various stages and the targeted performances, the
device can be used for an output level of up to 2 V (p-p).
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.15 Auxiliary DACs
The DAC1627D1G25 integrates two auxiliary DACs, which are used to compensate any
offset between the DACs and the next stage in the transmission path. Both auxiliary DACs
have a 10-bit resolution and are current sources (referenced to ground).
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
• I OAUXA ( fs ) = IAUXAP + IAUXAN
• I OAUXB ( fs ) = IAUXBP + IAUXBN
The output current depends on the digital input data set by SPI registers
DAC_A_Aux_MSB (bits AUX_A[9:2]; see Table 50), DAC_A_Aux_LSB (bits AUX_A[1:0];
see Table 51), DAC_B_Aux_MSB (bits AUX_B[9:2]; see Table 52) and DAC_B_Aux_LSB
(bits AUX_B[1:0]; see Table 53).
DATAA
I AUXAP = I OAUXA ( fs ) × ⎛ --------------------⎞
⎝ 1023 ⎠
(7)
1023 – DATAA
I AUXAN = I OAUXA ( fs ) × ⎛ --------------------------------------⎞
⎝
⎠
1023
(8)
DATAB
I AUXBP = I OAUXB ( fs ) × ⎛ --------------------⎞
⎝ 1023 ⎠
(9)
1023 – DATAB
I AUXBN = I OAUXB ( fs ) × ⎛ --------------------------------------⎞
⎝
⎠
1023
(10)
Table 22 shows the output current as a function of the auxiliary DACs data DATAA and
DATAB above.
Table 22.
DAC1627D1G25
Objective data sheet
Auxiliary DAC transfer function
DATAA; DATAB
AUX_A[9:2]/AUX_A[1:0]; IAUXAP; IAUXBP (mA)
AUX_B[9:0]/AUX_B[1:0]
(binary coding
IAUXAN; IAUXBN (mA)
0
00 0000 0000
0
2.2
...
...
...
...
512
10 0000 0000
1.1
1.1
...
...
...
...
1023
11 1111 1111
2.2
0
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10.16 Output configuration
10.16.1 Basic output configuration
The use of a differentially coupled transformer output (see Figure 22) provides optimum
distortion performance. In addition, it helps to match the impedance and provides
electrical isolation.
3.3 V
DAC1627D
50 Ω
0 mA to 20 mA
IOUTAP/IOUTBP
2:1
50 Ω
0 mA to 20 mA
IOUTAN/IOUTBN
50 Ω
3.3 V
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.8 V
VO(dif) = 1 V
001aan836
Fig 22. 1 V (p-p) differential output with transformer
The DAC1627D1G25 can operate a differential output of up to 2 V (p-p). In this
configuration, it is recommended to connect the center tap of the transformer to a 62 Ω
resistor, which is connected to the 3.3 V analog power supply. This adjusts the DC
common-mode to around 2.7 V (see Figure 23).
3.3 V
3.3 V
DAC1627D
100 Ω
62 Ω
0 mA to 20 mA
IOUTAP/IOUTBP
4:1
50 Ω
0 mA to 20 mA
IOUTAN/IOUTBN
100 Ω
3.3 V
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.7 V
VO(dif) = 2 V
001aan837
Fig 23. 2 V (p-p) differential output with transformer
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.16.2 IQ-modulator - BGX7100 interface
The DAC1627D1G25 can be easily connected to the BGX7100 NXP IQ-modulator. The
offset compensation for local oscillator can be cancelled using the digital offset control in
the device.
Figure 24 shows an example of a connection between the DAC1627D1G25 and the
BGX7100 interface.
3.3 V
DAC1627D
BGX7100
IQ-modulator
51.1 Ω
51.1 Ω
BBAP/BBBP
IOUTAP/IOUTBP
IOUTAN/IOUTBN
BBAN/BBBN
0 mA to 20 mA
AUXAP/AUXBP
AUXAN/AUXBN
001aan814
Fig 24. DAC1627D1G25 with BGX7100 IQ-modulator interface
10.16.3 IQ-modulator - DC interface
When the system operation requires to keep the DC component of the spectrum, the
DAC1627D1G25 can use a DC interface to connect an IQ-modulator. In this case, the
offset compensation for local oscillator can be cancelled using the digital offset control in
the device.
Figure 25 shows an example of a connection to an IQ modulator with a 1.7 V common
input level.
3.3 V
IQ-modulator (VI(cm) = 1.7 V)
DAC1627D
51.1 Ω
51.1 Ω
442 Ω
BBAP/BBBP
IOUTAP/IOUTBP
442 Ω
IOUTAN/IOUTBN
BBAN/BBBN
0 mA to 20 mA
768 Ω
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.67 V
VO(dif) = 1.98 V
768 Ω
BBAP/BBAN
BBBP/BBBN
VI(cm) = 1.7 V
VI(dif) = 1.26 V
001aan838
Fig 25. IQ-modulator: DC interface with a 1.7 V common input level
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Figure 26 shows an example of a connection to an IQ-modulator with a 3.3 V common
input level.
DAC1627D
3.3 V
54.9 Ω
5V
54.9 Ω
750 Ω
IQ-modulator (VI(cm) = 3.3 V)
750 Ω
237 Ω
BBAP/BBBP
IOUTAP/IOUTBP
237 Ω
IOUTAN/IOUTBN
BBAN/BBBN
1.27 kΩ
1.27 kΩ
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.75 V
VO(dif) = 1.97 V
BBAP/BBAN
BBBP/BBBN
VI(cm) = 3.3 V
VI(dif) = 1.5 V
001aan839
Fig 26. IQ-modulator: DC interface with a 3.3 V common input level
The auxiliary DACs can be used to control the offset within an accurate range or with
accurate steps.
Figure 27 shows an example of a connection to an IQ-modulator with a 1.7 V common
input level and auxiliary DACs.
DAC1627D
3.3 V
51.1 Ω
51.1 Ω
442 Ω
BBAP/BBBP
IOUTAP/IOUTBP
442 Ω
IOUTAN/IOUTBN
BBAN/BBBN
0 mA to 20 mA
698 Ω
698 Ω
51.1 Ω
51.1 Ω
AUXAP/AUXBP
AUXAN/AUXBN
1.1 mA (typical)
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.67 V
VO(dif) = 1.94 V
BBAP/BBAN
BBBP/BBBN
VI(cm) = 1.7 V
VI(dif) = 1.23 V
offset correction = up to 50 mV
001aan840
Fig 27. IQ-modulator: DC interface with a 1.7 V common input level and auxiliary DACs
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
34 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Figure 28 shows an example of a connection to an IQ-modulator with a 3.3 V common
input level and auxiliary DACs.
3.3 V
DAC1627D
54.9 Ω
5V
54.9 Ω
237 Ω
750 Ω
750 Ω
BBAP/BBBP
IOUTAP/IOUTBP
237 Ω
BBAN/BBBN
IOUTAN/IOUTBN
634 Ω
634 Ω
442 Ω
442 Ω
AUXAP/AUXBP
AUXAN/AUXBN
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.75 V
VO(dif) = 1.96 V
BBAP/BBAN
BBBP/BBBN
VI(cm) = 3.3 V
VI(dif) = 1.5 V
offset correction = up to 36 mV
001aan841
Fig 28. IQ-modulator: DC interface with a 3.3 V common input level and auxiliary DACs
The constraints to adjust the interface are:
•
•
•
•
DAC1627D1G25
Objective data sheet
The output compliance range of the DAC
The output compliance range of the auxiliary DACs
The input common-mode level of the IQ-modulator
The range of offset correction
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35 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.16.4 IQ-modulator - AC interface
When the IQ-modulator common-mode voltage is close to ground, the DAC1627D1G25
must be used AC-coupled and the auxiliary DACs are required for local oscillator
cancellation.
Figure 29 shows an example of a connection to an IQ-modulator with a 0.5 V common
input level and auxiliary DACs.
3.3 V
DAC1627D
65.5 Ω
5V
65.5 Ω
10 nF
2 kΩ
IQ-modulator (VI(cm) = 0.5 V)
2 kΩ
BBAP/BBBP
IOUTAP/IOUTBP
10 nF
IOUTAN/IOUTBN
BBAN/BBBN
0 mA to 20 mA
174 Ω
174 Ω
34 Ω
34 Ω
AUXAP/AUXBP
AUXAN/AUXBN
1.1 mA (typical)
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.65 V
VO(dif) = 1.96 V
BBAP/BBAN
BBBP/BBBN
VI(cm) = 0.5 V
VI(dif) = 1.96 V
offset correction = up to 70 mV
001aan842
Fig 29. IQ-modulator: AC interface with a 0.5 V common input level and auxiliary DACs
10.17 Design recommendations
10.17.1 Power and grounding
Use a separate power supply regulator for the generation of the 1.8 V analog power
(pins 65, 62, 55, 69, 72 and 58) and the 1.8 V digital power (pins 12, 19, 36, 26 and 43) to
ensure optimal performance.
Also, include individual LC decoupling for the following six sets of power pins:
•
•
•
•
•
•
VDDA(1V8)_P1 (pin 62)
VDDA(1V8)_P2 (pin 65)
VDDA(1V8) (pins 55, 69, 72 and 58)
VDDD(1V8) (core: pins 12, 26 and 43)
VDDD(1V8) (LVDS: pins 19 and 36)
VDDA(3V3) (pins 59 and 68)
At least two capacitors must be used for each power pin decoupling. These capacitors
must be located as close as possible to the DAC1627D1G25 power pins.
DAC1627D1G25
Objective data sheet
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© NXP B.V. 2011. All rights reserved.
36 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
The die pad is used for both the power dissipation and electrical grounding. Insert several
vias (typically 7 × 7) to connect the internal ground plane to the top layer die area.
10.18 Configuration interface
10.18.1 Register description
The DAC1627D1G25 incorporates more than the 32 SPI registers allowed by the address
value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each
containing 32 registers. The 32nd register of each page indicates which page is currently
addressed (00h, 01h or 0Ah).
Page 00h (see Table 23) is dedicated to the main control of the DAC1627D1G25:
•
•
•
•
•
Mode selection
NCO control
Auxiliary DAC control
Gain/phase/offset control
Power-down control
Page 01h (see Table 55) is dedicated to:
• Multi-Device Synchronization (MDS)
• DAC analog core control (biasing current, Sleep mode)
Page 0Ah (seeTable 79) is dedicated to the LVDS input interface configuration.
DAC1627D1G25
Objective data sheet
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Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
37 of 69
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NXP Semiconductors
DAC1627D1G25
Objective data sheet
10.18.2 Page 0 register allocation map
Table 23 shows an overview of all registers on page 0 (00h in hexadecimal). See Section 10.18.3 for detailed descriptions of
the registers.
Table 23.
Page_00 register allocation map
Address
Register name
R/W
Bit definition
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
-
-
CODING
IC_PON
00h
COMMON
R/W
3W_SPI
SPI_RST
-
1
01h
TXCFG
R/W
NCO_ON
NCO_LP
_SEL
INV_SIN
_SEL
2
02h
PLLCFG
R/W
PLL_BP
PLL_BUF
_PD
PLL_PLL
_PD
4
04h
FREQNCO_B0
R/W
5
05h
FREQNCO_B1
6
06h
7
MODULATION[2:0]
Hex Dec
GAP_PON 1000
0111
87h
135
INTERPOLATION[1:0] 0000
0001
01h
1
A1h 161
FREQ_NCO[7:0]
0110
0110
66h
102
R/W
FREQ_NCO[15:8]
0110
0110
66h
102
FREQNCO_B2
R/W
FREQ_NCO[23:16]
0110
0110
66h
102
07h
FREQNCO_B3
R/W
FREQ_NCO[31:24]
0010
0110
66h
102
8
08h
FREQNCO_B4
R/W
FREQ_NCO[39:32]
0010
0110
26h
38
9
09h
PH_CORR_CTL0
R/W
PHASE_COR[7:0]
0000
0000
00h
0
10 0Ah
PH_CORR_CTL1
R/W
0000
0000
00h
0
11
0Bh
DAC_A_DGAIN_LSB
R/W
1101
0100
50h
80
12 0Ch
DAC_A_DGAIN_MSB
R/W
0000
1011
0Bh 11
13 0Dh
DAC_B_DGAIN_LSB
R/W
1101
0100
50h
14 0Eh
DAC_B_DGAIN_MSB
R/W
-
-
-
-
0000
0010
0Bh 11
15 0Fh
DAC_OUT_CTRL
R/W
-
-
-
-
-
-
PLL_PHASE[1:0]
PHASE_COR[12:8]
DAC_A_DGAIN[7:0]
-
-
-
-
DAC_A_DGAIN[11:8]
DAC_B_DGAIN[7:0]
DAC_B_DGAIN[11:8]
A_DGAIN_E
B_DGAIN_E
MINUS
_3DB
PLL_
OSC_PD
CLIPPING 0000
_ENA
0000
00h
80
0
DAC1627D1G25
38 of 69
© NXP B.V. 2011. All rights reserved.
1010
0001
PH_COR
_ENA
PLL_DIV[1:0]
Bin
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Rev. 1 — 29 April 2011
All information provided in this document is subject to legal disclaimers.
0
Bit 0
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Page_00 register allocation map …continued
Address
Register name
R/W
Bit definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Default
Bit 2
Bit 1
Bit 0
Bin
Hex Dec
R/W
CLIPPING_LEVEL[7:0]
1111
1111
FFh 255
17 11h
DAC_A_OFFSET_LSB
R/W
DAC_A_OFFSET[7:0]
0000
0000
00h
0
18 12h
DAC_A_OFFSET_MSB
R/W
DAC_A_OFFSET[15:8]
0000
0000
00h
0
19 13h
DAC_B_OFFSET_LSB
R/W
DAC_B_OFFSET[7:0]
0000
0000
00h
0
20 14h
DAC_B_OFFSET_MSB
R/W
DAC_B_OFFSET[15:8]
0000
0000
00h
0
21 15h
PHINCO_LSB
R/W
PH_NCO[7:0]
0000
0000
00h
0
22 16h
PHINCO_MSB
R/W
PH_NCO[15:8]
0000
0000
00h
0
23 17h
DAC_A_GAIN1
R/W
DAC_A_GAIN_
COARSE[1:0]
0100
0000
40h
64
24 18h
DAC_A_GAIN2
R/W
DAC_A_GAIN_
COARSE[3:2]
1000
0000
80h
128
25 19h
DAC_B_GAIN1
R/W
DAC_B_GAIN_
COARSE[1:0]
0100
0000
40h
192
26 1Ah
DAC_B_GAIN2
R/W
DAC_B_GAIN_
COARSE[3:2]
1000
0000
80h
128
27 1Bh
DAC_A_AUX_MSB
R/W
1000
0000
80h
128
28 1Ch
DAC_A_AUX_LSB
R/W
0000
0000
00h
0
29 1Dh
DAC_B_AUX_MSB
R/W
1000
0000
80h
128
30 1Eh
DAC_B_AUX_LSB
R/W
AUX_B
_PD
-
-
-
-
0000
0000
00h
0
31 1Fh
PAGE_ADDRESS
R/W
-
-
-
-
-
0000
0000
00h
0
DAC_A_GAIN_FINE[5:0]
-
-
-
-
-
DAC_B_GAIN_FINE[5:0]
-
-
-
-
-
-
AUX_A[9:2]
AUX_A
_PD
-
-
-
-
-
AUX_A[1:0]
AUX_B[9:2]
-
AUX_B[1:0]
PAGE_ADD[2:0]
DAC1627D1G25
39 of 69
© NXP B.V. 2011. All rights reserved.
DAC_CLIPPING
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Rev. 1 — 29 April 2011
All information provided in this document is subject to legal disclaimers.
16 10h
-
NXP Semiconductors
DAC1627D1G25
Objective data sheet
Table 23.
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.18.3 Page 0 bit definition detailed description
Table 24. Register COMMON (address 00h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
7
3W_SPI
R/W
6
2
SPI_RST
CODING
Value
serial interface bus type
0
4-wire SPI
1
3-wire SPI
R/W
serial interface reset
0
no reset
1
performs a reset on all registers except address 00h
R/W
coding of input word
0
1
1
0
IC_PON
GAP_PON
Description
R/W
two complement’s coding
unsigned format
IC power control
0
all circuits (digital and analog, except SPI) are in
power-down
1
all circuits (digital and analog, except SPI) are
switched on
R/W
internal band gap power control
0
band gap is power-down
1
internal band gap references are switched on
Table 25. Register TXCFG (address 01h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
7
NCO_ON
R/W
6
5
4 to 2
NCO_LP_SEL
INV_SIN_SEL
MODULATION[2:0]
DAC1627D1G25
Objective data sheet
Value
Description
NCO
0
NCO disabled, the NCO phase is reset to 0
1
NCO enabled
R/W
NCO low power selection
0
low power NCO disabled
1
low power NCO enabled (frequency and phase
given by the five MSB of the registers 06h and 08h,
respectively)
R/W
inverse (sin x) / x function selection
0
disable
1
enable
R/W
modulation
000
dual DAC: no modulation
001
positive upper single sideband upconversion
010
positive lower single sideband upconversion
011
negative upper single sideband upconversion
100
negative lower single sideband upconversion
others
not defined
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 25. Register TXCFG (address 01h) bit description …continued
Default values are shown highlighted.
Bit
Symbol
Access
1 to 0
INTERPOLATION[1:0]
R/W
Value
Description
interpolation
00
no interpolation
01
×2 interpolation
10
×4 interpolation
11
×8 interpolation
Table 26. Register PLLCFG (address 02h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
7
PLL_BP
R/W
6
PLL_BUF_PD
Value
PLL bypass
0
DAC clock generated by PLL
1
DAC clock provided via external pins CLKN and
CLKP (PLL bypass mode)
R/W
PLL test buffer control
0
1
5
4 to 3
PLL_PLL_PD
PLL_DIV[1:0]
R/W
0
PLL_PHASE[1:0]
PLL_OSC_PD
Power-down mode
enabled
PLL and CKGEN control
0
Power-down mode
1
enable
R/W
PLL divider factor
00
fs = 2 × fdata
01
fs = 4 × fdata
10
fs = 8 × f
11
2 to 1
Description
R/W
undefined
PLL phase shift
00
0 degrees phase shift of fs
01
120 degrees phase shift of fs
10
240 degrees phase shift of fs
11
240 degrees phase shift of fs
R/W
PLL oscillator output power-down
0
Power-down mode
1
enabled
Table 27. Register FREQNCO_B0 (address 04h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
FREQ_NCO[7:0]
R/W
Value
NCO frequency (two complement’s coding)
-
DAC1627D1G25
Objective data sheet
Description
least significant 8 bits for the NCO frequency setting
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 28. Register FREQNCO_B1 (address 05h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
FREQ_NCO[15:8]
R/W
Value
Description
NCO frequency
-
intermediate 8 bits for the NCO frequency setting
Table 29. Register FREQNCO_B2 (address 06h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
FREQ_NCO[23:16]
R/W
Value
Description
NCO frequency
-
intermediate 8 bits for the NCO frequency setting
Table 30. Register FREQNCO_B3 (address 07h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
FREQ_NCO[31:24]
R/W
Value
Description
NCO frequency
-
intermediate 8 bits for the NCO frequency setting
Table 31. Register FREQNCO_B4 (address 08h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
FREQ_NCO[39:32]
R/W
Value
Description
NCO frequency (MSB)
-
most significant 8 bits for the NCO frequency setting
Table 32. Register PH_CORR_CTL0 (address 09h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
PHASE_COR[7:0]]
R/W
Value
Description
DAC output phase correction factor (LSB)
-
least significant 8 bits for the DAC output phase
correction factor
Table 33. Register PH_CORR_CTL1 (address 0Ah)
Default values are shown highlighted.
Bit
Symbol
Access
7
PH_COR_ENA
R/W
Value
DAC output phase correction control
0
1
4 to 0
PHASE_COR[12:8]
Description
R/W
DAC output phase correction disabled
DAC output phase correction enabled
DAC output phase correction factor MSB
00000
most significant 5 bits for the DAC output phase
correction factor
Table 34. Register DAC_A_DGAIN_LSB (address 0Bh)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DAC_A_DGAIN[7:0]
R/W
Value
DAC A digital gain control
-
DAC1627D1G25
Objective data sheet
Description
least significant 8 bits for the DAC A digital gain
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42 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 35. Register DAC_A_DGAIN_MSB (address 0Ch)
Default values are shown highlighted.
Bit
Symbol
Access
3 to 0
DAC_A_DGAIN[11:8]
R/W
Value
Description
DAC A digital gain control
-
most significant 4 bits for the DAC A digital gain
Table 36. Register DAC_B_DGAIN_LSB (address 0Dh)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DAC_B_DGAIN[7:0]
R/W
Value
Description
DAC B digital gain control
-
least significant 8 bits for the DAC B digital gain
Table 37. Register DAC_B_DGAIN_MSB (address 0Eh)
Default values are shown highlighted.
Bit
Symbol
Access
3 to 0
DAC_B_DGAIN[11:8]
R/W
Value
Description
DAC B digital gain control
-
most significant 4 bits for the DAC B digital gain
Table 38. Register DAC_OUT_CTRL (address 0Fh)
Default values are shown highlighted.
Bit
Symbol
Access
3
A_DGAIN_E
R/W
2
B_DGAIN_E
Value
DAC A digital gain control
0
disable
1
enable
R/W
DAC B digital gain control
0
1
1
0
MINUS_3DB
CLIPPING_ENA
Description
R/W
disable
enable
DAC attenuation control
0
unity gain
1
−3 dB gain
R/W
Digital DAC output clipping control
0
disable
1
enable
Table 39. Register DAC_CLIPPING (address 10h)
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
CLIPPING_LEVEL[7:0]
R/W
-
Digital DAC output clipping level value
Table 40. Register DAC_A_OFFSET_LSB (address 11h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DAC_A_OFFSET[7:0]
R/W
Value
DAC A digital offset value
-
DAC1627D1G25
Objective data sheet
Description
least significant 8 bits for the DAC A digital offset
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 41. Register DAC_A_OFFSET_MSB (address 12h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DAC_A_OFFSET[15:8]
R/W
Value
Description
DAC A digital offset value
-
most significant 8 bits for the DAC A digital offset
Table 42. Register DAC_B_OFFSET_LSB (address 13h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DAC_B_OFFSET[7:0]
R/W
Value
Description
DAC B digital offset value
-
least significant 8 bits for the DAC B digital offset
Table 43. Register DAC_B_OFFSET_MSB (address 14h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DAC_B_OFFSET[15:8]
R/W
Value
Description
DAC B digital offset value
-
most significant 8 bits for the DAC B digital offset
Table 44. Register PHINCO_LSB (address 15h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
PH_NCO[7:0]
R/W
Value
Description
NCO phase offset LSB
-
least significant 8 bits for the NCO phase setting
Table 45. Register PHINCO_MSB (address 16h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
PH_NCO[15:8]
R/W
Value
Description
NCO phase offset MSB
-
most significant 8 bits for the NCO phase setting
Table 46. Register DAC_A_GAIN1 (address 17h)
Default values are shown highlighted.
Bit
Symbol
Value
Description
7 to 6
DAC_A_GAIN_COARSE[1:0] R/W
Access
-
DAC A analog coarse gain control (LSB)
5 to 0
DAC_A_GAIN_FINE[5:0]
-
DAC A analog fine gain control
Value
Description
R/W
Table 47. Register DAC_A_GAIN2 (address 18h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 6
DAC_A_GAIN_COARSE[3:2] R/W
DAC A analog gain coarse control (MSB)
Table 48. Register DAC_B_GAIN1 (address 19h)
Default values are shown highlighted.
Bit
Symbol
7 to 6
5 to 0
Value
Description
DAC_B_GAIN_COARSE[1:0] R/W
-
DAC B analog coarse gain control (LSB)
DAC_B_GAIN_FINE[5:0]
-
DAC B analog fine gain control
DAC1627D1G25
Objective data sheet
Access
R/W
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Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
44 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 49. Register DAC_B_GAIN2 (address 1Ah)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 6
DAC_B_GAIN_COARSE[3:2] R/W
Value
Description
-
DAC B analog coarse gain control (MSB)
Table 50. DAC_A_Aux_MSB register (address 1Bh) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
AUX_A[9:2]
R/W
-
most significant 8 bits for auxiliary DAC A
Table 51. DAC_A_Aux_LSB register (address 1Ch) bit description
Default values are shown highlighted.
Bit
Symbol
Access
7
AUX_A_PD
R/W
1 to 0
AUX_A[1:0]
R/W
Value
Description
auxiliary DAC A power
0
on
1
off
-
least significant 2 bits for auxiliary DAC A
Table 52. DAC_B_Aux_MSB register (address 1Dh) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
AUX_B[9:2]
R/W
-
most significant 8 bits for auxiliary DAC B
Table 53. DAC_B_Aux_LSB register (address 1Eh) bit description
Default values are shown highlighted.
Bit
Symbol
Access
7
AUX_B_PD
R/W
1 to 0
AUX_B[1:0]
R/W
Value
Description
auxiliary DAC B power
0
on
1
off
-
least significant 2 bits for auxiliary DAC B
Table 54. SPI_PAGE register (address 1Fh) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
2 to 0
PAGE[2:0]
R/W
-
SPI page address
DAC1627D1G25
Objective data sheet
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NXP Semiconductors
DAC1627D1G25
Objective data sheet
10.18.4 Page 1 allocation map
Table 55 shows an overview of all registers on page 1 (01h in hexadecimal). See Section 10.18.5 for detailed descriptions of
the registers.
Table 55.
Page 1 register allocation map
Address
Register name
R/W
Default[1]
Bit definition
Bit 7
Bit 6
MDS_EQCHECK[1:0]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bin
Hex
MDS_
RUN
MDS_
NCO
MDS_
NCO_
PULSE
MDS_
SREF_
DIS
MDS_
MASTER
MDS_
ENA
0000
0100
04h
MDS_MAIN
R/W
1
01h
MDS_WIN_PERIOD_A
R/W
MDS_WIN_PERIOD_A[7:0]
1000
0000
80h
2
02h
MDS_WIN_PERIOD_B
R/W
MDS_WIN_PERIOD_B[7:0]
0100
0000
40h
3
03h
MDS_MISCCNTRL0
R/W
0001
0000
10h
4
04h
MDS_MAN_ADJUSTDLY R/W
0100
0000
40h
5
05h
MDS_AUTO_CYCLES
R/W
1000
0000
80h
6
06h
MDS_MISCCNTRL1
R/W
0000
1111
0Fh
7
07h
MDS_OFFSET_DLY
RW
-
0000
0000
00h
8
08h
MDS_ADJDELAY
RW
-
0000
0000
00h
9
09h
MDS_STATUS0
R
EARLY
LATE
EQUAL
10
0Ah
MDS_STATUS1
R
-
-
ADD_ERR
14
0Eh
DAC_CURRENT_AUX
R/W
-
-
-
-
15
0Fh
DAC_CURRENT_0
R/W
-
-
-
16
10h
DAC_CURRENT_1
R/W
-
-
-
-
-
-
MDS_
MAN
MDS_
EVAL_
ENA
MDS_
PRERUN_E
MDS_PULSEWIDTH[2:0]
MDS_MAN_ADJUSTDLY[6:0]
MDS_AUTO_CYCLES[7:0]
MDS_SR_ MDS_SR_
MDS_
CKEN
LOCKOUT SR_LOCK
-
MDS_
RELOCK
-
MDS_LOCK_DELAY[3:0]
MDS_OFFSET_DLY[4:0]
MDS_ADJDELAY[6:0]
MDS_EQ
EARLY_
ERROR
LATE_
ERROR
EQUAL_
FOUND
MDS_
ACTIVE
uuuu
uuuu
uuh
MDS_
PRERUN
MDS_
LOCKOUT
MDS_
LOCK
uuuu
uuuu
uuh
DAC_AUX_BIAS[3:0]
0000
0011
03h
-
DAC_DIG_BIAS[3:0]
0000
0011
03h
-
DAC_MST_BIAS[3:0]
0000
0011
03h
MDS_EN_PHASE[1:0]
DAC1627D1G25
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© NXP B.V. 2011. All rights reserved.
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Rev. 1 — 29 April 2011
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0
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Page 1 register allocation map …continued
Address
Register name
R/W
Default[1]
Bit definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bin
Hex
11h
DAC_CURRENT_2
R/W
-
-
-
-
DAC_DRV_BIAS[3:0]
0000
0011
03h
18
12h
DAC_CURRENT_3
R/W
-
-
-
-
DAC_SLV_BIAS[3:0]
0000
0011
03h
19
13h
DAC_CURRENT_4
R/W
-
-
-
-
DAC_CK_BIAS[3:0]
0000
0011
03h
20
14h
DAC_CURRENT_5
R/W
-
-
-
-
DAC_CAS_BIAS[3:0]
0000
0011
03h
21
15h
DAC_CURRENT_6
R/W
-
-
-
-
DAC_BLD_BIAS[3:0]
0000
0011
03h
22
16h
DAC_PON_SLEEP
R/W
DAC_B_
PON
DAC_B_
SLEEP
DAC_B_
COM_PD
DAC_B_
BLEED_
PD
DAC_A_
PD
1011
1011
BBh
23
17h
DAC_CLKDIG_DELAY
R/W
-
-
-
-
-
PLL_DIG_DELAY[2:0]
0000
0010
02h
31
1Fh
PAGE_ADDRESS
R/W
-
-
-
-
-
PAGE[2:0]
0000
0000
00h
u = undefined at power-up or after reset.
DAC_A_
SLEEP
DAC_A_
COM_PD
DAC_A_
BLEED_
PD
DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Rev. 1 — 29 April 2011
All information provided in this document is subject to legal disclaimers.
17
[1]
NXP Semiconductors
DAC1627D1G25
Objective data sheet
Table 55.
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.18.5 Page 1 bit definition detailed description
Table 56. MDS_MAIN register (address 00h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
7 to 6
MDS_EQCHECK[1:0]
R/W
Value
lock mode
00
lock when (early = 1 and late = 1)
01
lock when (early = 1, late = 1 and equal = 1)
10
lock when equal = 1
11
5
4
3
2
MDS_RUN
MDS_NCO
MDS_NCO_PULSE
MDS_SREF_DIS
R/W
0
no action
1
(0 ≥ 1) transition restarts evaluation_counter
R/W
NCO synchronization
0
no action
1
enable
R/W
NCO pulse
0
no action
1
manual control NCO tuning
R/W
internal pulse generation
1
0
MDS_MASTER
MDS_ENA
force lock (equal-check = 1)
evaluation process restart control
0
1
Description
R/W
normal mode
disable
MDS mode selection
0
slave mode
1
master mode
R/W
MDS function control
0
disable
1
enable
Table 57. MDS_WIN_PERIOD_A register (address 01h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
MDS_WIN_PERIOD_A[7:0]
R/W
-
determines MDS window LOW time
Table 58. MDS_WIN_PERIOD_B register (address 02h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
MDS_WIN_PERIOD_B[7:0]
R/W
-
determines MDS window HIGH time
Table 59. MDS_MISCCNTRL0 register (address 03h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
4
MDS_EVAL_ENA
R/W
DAC1627D1G25
Objective data sheet
Value
Description
MDS evaluation
0
disable
1
enable
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 59. MDS_MISCCNTRL0 register (address 03h) bit description …continued
Default values are shown highlighted.
Bit
Symbol
Access
3
MDS_PRERUN_ENA
R/W
Value
automatic MDS start-up
0
1
2 to 0
MDS_PULSEWIDTH[2:0]
Description
R/W
no mds_win/mds_ref generation in advance
mds_win/mds_ref run-in before mds_evaluation
width of MDS (in output clk-periods)
000
1 DAC clk-period
001
2 DAC clk-periods
010 to 111
(mds_pulsewidth − 1) × 4 DAC clk-periods
Table 60. MDS_MAN_ADJUSTDLY register (address 04h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
7
MDS_MAN
R/W
6 to 0
Value
Description
adjustment delays mode
0
auto-control adjustment delays
1
manual control adjustment delays
MDS_MAN_ADJUSTDLY[6:0] R/W
adjustment delay value
-
if MDS_MAN = 0 then initial value adjustment delay
-
if MDS_MAN = 1 then controls adjustment delay
Table 61. MDS_AUTO_CYCLES register (address 05h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
MDS_AUTO_CYCLES[7:0]
R/W
-
number of evaluation cycles applied for MDS. If set to
255 then IC continuously generates/monitors the MDS
pulse
Table 62. MDS_MISCCNTRL1 register (address 06h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7
MDS_SR_CKEN
R/W
-
lock mode
6
MDS_SR_LOCKOUT
0
free-running MDS_SR_CKEN
1
MDS_SR_CKEN forced low
R/W
lockout detector soft reset
0
1
5
4
3 to 0
MDS_SR_LOCK
MDS_RELOCK
MDS_LOCK_DELAY[3:0]
DAC1627D1G25
Objective data sheet
R/W
MDS_SR_LOCKOUT forced low
lock detector soft reset
0
MDS_SR_LOCK in use
1
MDS_SR_LOCK forced low
R/W
R/W
MDS_SR_LOCKOUT in use
relock mode
0
no action
1
relock when lockout occurs
-
number of succeeding 'equal'-detections until lock
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 63. MDS_OFFSET_DLY register (address 07h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
MDS_OFFSET_DLY[6:0]
R/W
-
delay offset for dataflow (two’s complement [−16 to 15]
Table 64. MDS_ADJDELAY register (address 08h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
6 to 0
MDS_ADJDELAY[6:0]
R
-
actual value adjustment delay
Table 65. MDS_STATUS0 register (address 09h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
7
EARLY
R
6
5
LATE
EQUAL
Value
Description
early signal (sampled) from early-to-late detector
0
false
1
true
R
late signal (sampled) from early-to-late detector
0
false
1
true
R
equal signal (sampled) from early-to-late detector
0
false
1
4
3
2
1
MDS_LOCK
EARLY_ERROR
LATE_ERROR
EQUAL_FOUND
R
true
result equal-check
0
false
1
true
R
adjustment delay maximum value stops the search
0
false
1
true
R
adjustment delay minimum value stops the search
0
false
1
true
R
evaluation logic has detected equal condition
0
false
1
0
MDS_ACTIVE
R
true
evaluation logic active
0
false
1
true
Table 66. MDS_STATUS1 register (address 0Ah) bit description
Default values are shown highlighted.
Bit
Symbol
Access
5
ADD_ERR
R
DAC1627D1G25
Objective data sheet
Value
Description
adjustment delay error detection
0
OK
1
delay offset cannot be applied in available range
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 66. MDS_STATUS1 register (address 0Ah) bit description …continued
Default values are shown highlighted.
Bit
Symbol
Access
4 to 3
MDS_EN_PHASE[1:0]
R
2
1
MDS_PRERUN
MDS_LOCKOUT
Value
MDS enable phase
00
enable phase = 0
01
enable phase = 1 (only for ×2)
10
enable phase = 2 (only for ×2 and ×4)
11
enable phase = 3 (only for ×2)
R
MDS-PRERUN phase active flag
0
false
1
true
R
MDS_LOCKOUT detected flag
0
1
0
MDS_LOCK
Description
R
false
true
MDS_LOCK flag
0
false
1
true
Table 67. DAC_CURRENT_AUX register (address 0Eh) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
DAC_AUX_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 68. DAC_CURRENT_0 register (address 0Fh) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
DAC_DIG_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 69. DAC_CURRENT_1 register (address 10h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
DAC_MST_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 70. DAC_CURRENT_2 register (address 11h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
DAC_DRV_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 71. DAC_CURRENT_3 register (address 12h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
DAC_SLV_BIAS[3:0]
R/W
-
bias current control (see Table 75)
DAC1627D1G25
Objective data sheet
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51 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 72. DAC_CURRENT_4 register (address 13h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
DAC_CK_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 73. DAC_CURRENT_5 register (address 14h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
DAC_CAS_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 74. DAC_CURRENT_6 register (address 15h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
DAC_BLD_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 75.
Bias current control table
BIAS[3:0]
Deviation from nominal current
000
−30 %
001
−20 %
010
−10 %
011
0%
100
+10 %
101
+20 %
110
+30 %
111
+40 %
Table 76. DAC_PON_SLEEP register (address 16h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7
DAC_B_PON
R/W
-
DAC B power control
0
1
6
5
4
3
DAC_B_SLEEP
DAC_B_COM_PD
DAC_B_BLEED_PD
DAC_A_PON
DAC1627D1G25
Objective data sheet
R
power-down
power on
DAC B mode selection
0
normal operation
1
Sleep mode
R
commutator B control
0
disable (power-down)
1
enable
R
DAC B bleed current control
0
disable (power-down)
1
enable
R
DAC A power control
0
power-down
1
power on
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Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
52 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 76. DAC_PON_SLEEP register (address 16h) bit description …continued
Default values are shown highlighted.
Bit
Symbol
Access
2
DAC_A_SLEEP
R
Value
DAC B mode selection
0
1
1
0
DAC_A_COM_PD
DAC_A_BLEED_PD
Description
R
normal operation
Sleep mode
commutator A control
0
disable (power-down)
1
enable
R
DAC A bleed current control
0
disable (power-down)
1
enable
Table 77. DAC_TEST_8 register (address 17h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
2 to 0
PLL_DIG_DELAY[2:0]
R/W
-
digital clock delay offset of PLL/CKGEN_DIV8
Table 78. SPI_PAGE register (address 1Fh) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
2 to 0
PAGE[2:0]
R/W
-
SPI page address
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
53 of 69
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
DAC1627D1G25
Objective data sheet
10.18.6 Page A register allocation map
Table 79 shows an overview of all registers on page A (0Ah in hexadecimal). See Section 10.18.7 for detailed descriptions of
the registers.
Table 79.
Page_0A register allocation map
Address
Register name
R/W
Bit definition
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bin
Hex Dec
PD_CNTRL
CAL_
CNTRL
RST_
DCKL
RST_
LCKL
0000 03h 3
0011
MAIN_CNTRL
R/W
-
-
-
LD_PD
1
01h
MAN_LDCLKDEL
R/W
-
-
-
-
2
02h
DBG_LVDS
R/W
-
-
-
-
4
04h
RST_EXT_LDCLK
R/W
RST_EXT_LCLK_TIME[7:0]
0011 3Fh 63
1111
5
05h
RST_EXT_DCLK
R/W
RST_EXT_DCLK_TIME[7:0]
0010 20h 32
0000
6
06h
DCMSU_PREDIV
R/W
DCMSU_PREDIVIDER[7:0]
0001 1Eh 30
1110
8
08h
LD_POL_LSB
R/W
LD_POL[7:0]
0000 00h 0
0000
9
09h
LD_POL_MSB
R/W
LD_POL[15:8]
0000 00h 0
0000
10 0Ah
LD_CNTRL
R/W
PARITYC DESCRAMBLE
SEL_EN[1:0]
11
MISC_CNTRL
R/W
SR_CDI
I_LEV_
CNTRL[1:0]
12 0Ch
I_DC_LVL_LSB
R/W
I_DC_LEVEL[7:0]
0000 00h 0
0000
13 0Dh
I_DC_LVL_MSB
R/W
I_DC_LEVEL[15:8]
0100 20h 32
0000
14 0Eh
Q_DC_LVL_LSB
R/W
Q_DC_LEVEL[7:0]
0000 00h 0
0000
15 0Fh
Q_DC_LVL_MSB
R/W
Q_DC_LEVEL[15:8]
0100 20h 32
0000
27 1Bh
TYPE_ID
R
0Bh
DAC
RESERVED
FRONTEND[1:0]
LDCLK_DEL[3:0]
SBER
DUAL
WORD_SWAP
RESERVED
LDAB_
SWAP
Q_LEV_CNTRL[1:0]
DSP[1:0]
0000 00h 0
0000
IQ_
FORMAT
0000 00h 0
0000
EDGE_
LDCLK
CDI_MODE[1:0]
BIT_RES[1:0]
0000 03h 3
0011
0000 00h 0
0000
0011 3Ch 60
1010
DAC1627D1G25
54 of 69
© NXP B.V. 2011. All rights reserved.
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Rev. 1 — 29 April 2011
All information provided in this document is subject to legal disclaimers.
0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Page_0A register allocation map …continued
Address
Register name
R/W
Bit definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Default
Bit 2
Bit 1
Bit 0
Bin
Hex Dec
28 1Ch
DAC_VERSION
R
DAC_VERSION_ID[7:0]
0000 01h 1
0001
29 1Dh
DIG_VERSION
R
DIG_VERSION_ID[7:0]
0000 01h 1
0001
30 1Eh
LD_VERSION
R
LVDS_VERSION_ID[7:0]
0000 01h 1
0001
31 1Fh
PAGE_ADDRESS
R/W
-
-
-
-
-
NXP Semiconductors
DAC1627D1G25
Objective data sheet
Table 79.
PAGE_ADD[2:0]
0000 00h 0
0000
DAC1627D1G25
55 of 69
© NXP B.V. 2011. All rights reserved.
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Rev. 1 — 29 April 2011
All information provided in this document is subject to legal disclaimers.
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.18.7 Page A bit definition detailed description
Table 80. Register MAIN_CNTRL (address 00h)
Default values are shown highlighted.
Bit
Symbol
Access
4
LD_PD
R/W
3
2
1
PD_CNTRL
CAL_CNTRL
RST_DCLK
Value
LVDS interface power-down (control possible only
when PD_CNTRL = 1)
0
switched on
1
switched off
R/W
power-down modes controlled by
0
DCMSU block
1
SPI registers
R/W
compensation delay controlled by
0
DCMSU block (automatic calibration)
1
SPI registers (manual control)
R/W
reset DCLK
0
1
0
RST_LCLK
Description
R/W
disable
enable
reset LVDS clock
0
disable
1
enable
Table 81. Register MAN_LDCLKDEL (address 01h)
Default values are shown highlighted.
Bit
Symbol
Access
3 to 0
LDCLK_DEL[3:0]
R/W
Value
Description
LVDS clock compensation delay (control only if
CAL_CNTRL = 1)
-
4-bit compensation delay for LVDS clock
Table 82. Register DBG_LVDS (address 02h)
Default values are shown highlighted.
Bit
Symbol
Access
3
SBER
R/W
2 to 0
RESERVED
Value
Description
simple BER control
R/W
0
no action
1
simple BER active
000
reserved
Value
Description
Table 83. Register RST_EXT_LCLK (address 04h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
RST_EXT_LCLK_TIME[7:0]
R/W
specify extension time reset, expressed in LVDS clock
period
-
DAC1627D1G25
Objective data sheet
8 bits for the extension time reset
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 84. Register RST_EXT_DCLK (address 05h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
RST_EXT_DCLK_TIME[7:0]
R/W
Value
Description
specify extension time reset, expressed in
DCLK period
-
8 bits for the extension time reset
Table 85. Register DCSMU_PREDIV (address 06h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DCMSU_PREDIVIDER[7:0]
R/W
Value
Description
predivider value for the DCMSU, expressed in LVDS
clock period
-
8 bits for the predivider value
Table 86. Register LD_POL_LSB (address 08h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
LD_POL[7:0]
R/W
Value
Description
toggles polarity of corresponding bit pair within LD[7:0]
-
most significant 6 bits for the polarity toggle
Table 87. Register LD_POL_MSB (address 09h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
LD_POL[15:8]
R/W
Value
Description
toggles polarity of corresponding bit pair within LD[7:0]
-
most significant 6 bits for the polarity toggle
Table 88. Register LD_CNTRL (address 0Ah)
Default values are shown highlighted.
Bit
Symbol
Access
7
PARITYC
R/W
Value
parity check
0
1
6
5 to 4
DESCRAMBLE
SEL_EN[1:0]
R/W
WORD_SWAP
DAC1627D1G25
Objective data sheet
disable
enable
Descramble control
0
disable descrambling
1
enable descrambling
R/W
LDVS data enable
00
LDVS data enable = align signal from channel A
01
LDVS data enable = align signal from channel B
10
LDVS data enable = 0
11
3
Description
R/W
LDVS data enable = 1
reverse order for LVDS path
0
normal operation
1
MSB to LSB order reversed
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 88. Register LD_CNTRL (address 0Ah) …continued
Default values are shown highlighted.
Bit
Symbol
Access
2
LDAB_SWAP
R/W
Value
swaps LVDS A and LVDS B paths
0
1
1
0
IQ_FORMAT
EDGE_LDCLK
Description
R/W
normal operation
LVDS A and LVDS B paths are swapped
specify IQ supplied format
0
folded
1
interleaved
R/W
specify sampling edge for LVDS data path
0
falling edge of LDCLK
1
rising edge of LDCLK
Table 89. Register MISC_CNTRL (address 0Bh)
Default values are shown highlighted.
Bit
Symbol
Access
7
SR_CDI
R/W
Value
CDI block software reset control
0
1
6
RESERVED
R/W
5 to 4
I_LEV_CNTRL[1:0]
R/W
3 to 2
1 to 0
Q_LEV_CNTRL[1:0]
CDI_MODE[1:0]
DAC1627D1G25
Objective data sheet
Description
0
no action
perform a software reset on CDI
reserved
specifies output from CDI for I path
00
normal operation (CDI data output sent to digital
signal processing input)
01
if LDVS data enable = 1, then normal operation; if
LDVS data enable = 0, then digital signal processing
input = I_DC_LEVEL register value
10
digital signal processing input = I_DC_LEVEL
11
digital signal processing input = I_DC_LEVEL
R/W
specifies output from CDI for Q path
00
normal operation (CDI data output sent to digital
signal processing input)
01
if LDVS data enable = 1, then normal operation; if
LDVS data enable = 0, then digital signal processing
input = Q_DC_LEVEL register value
10
digital signal processing input = Q_DC_LEVEL
11
digital signal processing input = Q_DC_LEVEL
R/W
specifies CDI mode
00
cdi_mode 0 (×2 mode)
01
cdi_mode 1 (×4 mode)
10
cdi_mode 2 (×8 mode)
11
not used
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DAC1627D1G25
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Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 90. Register I_DC_LVL_LSB(address 0Ch)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
I_DC_LEVEL[7:0]
R/W
Value
Description
I_DC_LEVEL
-
least significant 8 bits for I_DC_LEVEL
Table 91. Register I_DC_LVL_MSB(address 0Dh)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
I_DC_LEVEL[15:8]
R/W
Value
Description
I_DC_LEVEL
-
most significant 8 bits for I_DC_LEVEL
Table 92. Register Q_DC_LVL_LSB(address 0Eh)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
Q_DC_LEVEL[7:0]
R/W
Value
Description
Q_DC_LEVEL
-
least significant 8 bits for Q_DC_LEVEL
Table 93. Register Q_DC_LVL_MSB(address 0Fh)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
Q_DC_LEVEL[15:8]
R/W
Value
Description
Q_DC_LEVEL
-
most significant 8 bits for Q_DC_LEVEL
Table 94. Register TYPE_ID (address 1Bh)
Default values are shown highlighted.
Bit
Symbol
Access
7
DAC
R
6 to 5
FRONTEND
1
calibrated device
R
01
LVDS input interface
0
DUAL
R
DSP
R
DAC1627D1G25
Objective data sheet
calibration
uncalibrated device
3 to 2
BIT_RES
Description
0
4
1 to 0
Value
dual DAC
internal digital signal processing
11
interpolation filter + SSBM
10
SSBM
01
interpolation filter
00
none
R
DAC bit resolution
00
16 bits
01
14 bits
10
12 bits
11
10 bits
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 95. Register DAC_VERSION (address 1Ch)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DAC_VERSION_ID[7:0]
R/W
Value
Description
DAC version number
-
8 bits for the DAC version number
Table 96. Register DIG_VERSION (address 1Dh)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
DIG_VERSION_ID[7:0]
R/W
Value
Description
digital version number
-
8 bits for the digital version number
Table 97. Register DIG_VERSION (address 1Eh)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0
LVDS_VERSION_ID[7:0]
R/W
Value
Description
LVDS receiver version number
-
8 bits for the LVDS receiver version number
Table 98. Register PAGE_ADD (address 1Fh)
Default values are shown highlighted.
Bit
Symbol
Access
2 to 0
PAGE_ADD[2:0]
R/W
Value
Page address
-
DAC1627D1G25
Objective data sheet
Description
current page address
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
11. Package outline
HVQFN72: plastic thermal enhanced very thin quad flat package; no leads;
72 terminals; body 10 x 10 x 0.85 mm
A
B
D
SOT813-3
terminal 1
index area
A
E
A1
c
detail X
e1
e
1/2 e
19
36
C
C A B
C
v
w
b
y1 C
y
37
18
e
e2
Eh
1/2 e
1
terminal 1
index area
54
72
55
X
Dh
0
5
scale
Dimensions
Unit
A
A1
b
max 1.00 0.05 0.30
nom 0.85 0.02 0.21
min 0.80 0.00 0.18
mm
10 mm
c
D(1)
Dh
E(1)
Eh
0.2
10.1
10.0
9.9
7.2
7.1
7.0
10.1
10.0
9.9
7.2
7.1
7.0
e
e1
0.5
8.5
e2
L
v
8.5
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT813-3
---
---
---
sot813-3_po
European
projection
Issue date
10-03-23
10-04-02
Fig 30. Package outline SOT813-3 (HVQFN72)
DAC1627D1G25
Objective data sheet
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DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
12. Abbreviations
Table 99.
DAC1627D1G25
Objective data sheet
Abbreviations
Acronym
Description
BW
BandWidth
BWA
Broadband Wireless Access
CDI
Clock Domain Interface
CDMA
Code Division Multiple Access
CML
Current Mode Logic
CMOS
Complementary Metal Oxide Semiconductor
DAC
Digital-to-Analog Converter
EDGE
Enhanced Data rates for GSM Evolution
FIR
Finite Impulse Response
GSM
Global System for Mobile communications
IF
Intermediate Frequency
IMD3
Third Order InterModulation
LMDS
Local Multipoint Distribution Service
LO
Local Oscillator
LVDS
Low-Voltage Differential Signaling
NCO
Numerically Controlled Oscillator
NMOS
Negative Metal-Oxide Semiconductor
PLL
Phase-Locked Loop
SFDR
Spurious-Free Dynamic Range
SPI
Serial Peripheral Interface
WCDMA
Wide band Code Division Multiple Access
WLL
Wireless Local Loop
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NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
13. Glossary
13.1 Static parameters
INL — IThe deviation of the transfer function from a best fit straight line (linear regression
computation).
DNL — The difference between the ideal and the measured output value between
successive DAC codes.
13.2 Dynamic parameters
Spurious-Free Dynamic Range (SFDR) — The ratio between the RMS value of the
reconstructed output sine wave and the RMS value of the largest spurious observed
(harmonic and non-harmonic, excluding DC component) in the frequency domain.
Decibels relative to full scale (dBFS) — Unit used in a digital system in order to
measure the amplitude level in decibel relative to the maximum peak value.
InterModulation Distortion (IMD) — From a dual-tone digital input sine wave (these two
frequencies being close together), the intermodulation distortion products IMD2 and IMD3
(second order and third order components) are defined below.
IMD2 — The ratio between the RMS value of either tone and the RMS value of the worst
second order inter modulation product.
IMD3 — The ratio between the RMS value of either tone and the RMS value of the worst
third order inter modulation product.
Total Harmonic Distortion (THD) — The ratio between the RMS value of the harmonics
of the output frequency and the RMS value of the output sine wave. Usually, the
calculation of THD is done on the first 5 harmonics.
Signal-to-Noise Ratio (SNR) — The ratio between the RMS value of the reconstructed
output sine wave and the RMS value of the noise excluding the harmonics and the DC
component.
Restricted BandWidth Spurious-Free Dynamic Range (SFDRRBW) — the ratio
between the RMS value of the reconstructed output sine wave and the RMS value of the
noise, including the harmonics, in a given bandwidth centered around foffset.
DAC1627D1G25
Objective data sheet
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NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
14. Revision history
Table 100. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
DAC1627D1G25 v.1
20110429
Objective data sheet
-
-
DAC1627D1G25
Objective data sheet
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NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
DAC1627D1G25
Objective data sheet
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© NXP B.V. 2011. All rights reserved.
65 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
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66 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
17. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15:
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6
Thermal characteristics . . . . . . . . . . . . . . . . . . .7
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read or Write mode access description . . . . .13
Number of bytes to be transferred . . . . . . . . . .13
SPI timing characteristics . . . . . . . . . . . . . . . .14
Input LVDS bus swapping . . . . . . . . . . . . . . . .16
Folded and interleaved format mapping . . . . . .17
Compensation delay values for manual
tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CDI mode 0: operating modes examples . . . .22
CDI mode 1: operating modes examples . . . .22
CDI mode 2: operating modes examples . . . .23
Interpolation filter coefficients . . . . . . . . . . . . .24
Complex modulator operation mode . . . . . . . .26
Inversion filter coefficients . . . . . . . . . . . . . . . .27
DAC transfer function . . . . . . . . . . . . . . . . . . .28
IO(fs) coarse adjustment . . . . . . . . . . . . . . . . . .29
IO(fs) fine adjustment . . . . . . . . . . . . . . . . . . . .29
Digital offset adjustment . . . . . . . . . . . . . . . . .30
Auxiliary DAC transfer function . . . . . . . . . . . .31
Page_00 register allocation map . . . . . . . . . . .38
Register COMMON (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
Register TXCFG (address 01h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
Register PLLCFG (address 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .41
Register FREQNCO_B0 (address 04h) . . . . . .41
Register FREQNCO_B1 (address 05h) . . . . . .42
Register FREQNCO_B2 (address 06h) . . . . . .42
Register FREQNCO_B3 (address 07h) . . . . . .42
Register FREQNCO_B4 (address 08h) . . . . . .42
Register PH_CORR_CTL0 (address 09h) . . . .42
Register PH_CORR_CTL1 (address 0Ah) . . .42
Register DAC_A_DGAIN_LSB (address 0Bh) .42
Register DAC_A_DGAIN_MSB (address 0Ch) 43
Register DAC_B_DGAIN_LSB (address 0Dh) 43
Register DAC_B_DGAIN_MSB (address 0Eh) 43
Register DAC_OUT_CTRL (address 0Fh) . . .43
Register DAC_CLIPPING (address 10h) . . . . .43
Register DAC_A_OFFSET_LSB
(address 11h) . . . . . . . . . . . . . . . . . . . . . . . . . .43
Register DAC_A_OFFSET_MSB
(address 12h) . . . . . . . . . . . . . . . . . . . . . . . . .44
Register DAC_B_OFFSET_LSB
(address 13h) . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 43. Register DAC_B_OFFSET_MSB
(address 14h) . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 44. Register PHINCO_LSB (address 15h) . . . . . . 44
Table 45. Register PHINCO_MSB (address 16h) . . . . . . 44
Table 46. Register DAC_A_GAIN1 (address 17h) . . . . . 44
Table 47. Register DAC_A_GAIN2 (address 18h) . . . . . 44
Table 48. Register DAC_B_GAIN1 (address 19h) . . . . . 44
Table 49. Register DAC_B_GAIN2 (address 1Ah) . . . . . 45
Table 50. DAC_A_Aux_MSB register (address 1Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 51. DAC_A_Aux_LSB register (address 1Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 52. DAC_B_Aux_MSB register (address 1Dh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 53. DAC_B_Aux_LSB register (address 1Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 54. SPI_PAGE register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 55. Page 1 register allocation map . . . . . . . . . . . . 46
Table 56. MDS_MAIN register (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 57. MDS_WIN_PERIOD_A register (address 01h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 58. MDS_WIN_PERIOD_B register (address 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 59. MDS_MISCCNTRL0 register (address 03h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 60. MDS_MAN_ADJUSTDLY register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 61. MDS_AUTO_CYCLES register (address 05h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 62. MDS_MISCCNTRL1 register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 63. MDS_OFFSET_DLY register (address 07h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 64. MDS_ADJDELAY register (address 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 65. MDS_STATUS0 register (address 09h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 66. MDS_STATUS1 register (address 0Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 67. DAC_CURRENT_AUX register (address 0Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 68. DAC_CURRENT_0 register (address 0Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 69. DAC_CURRENT_1 register (address 10h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51
continued >>
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
67 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 70. DAC_CURRENT_2 register (address 11h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 71. DAC_CURRENT_3 register (address 12h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 72. DAC_CURRENT_4 register (address 13h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 73. DAC_CURRENT_5 register (address 14h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 74. DAC_CURRENT_6 register (address 15h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 75. Bias current control table . . . . . . . . . . . . . . . . .52
Table 76. DAC_PON_SLEEP register (address 16h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 77. DAC_TEST_8 register (address 17h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 78. SPI_PAGE register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 79. Page_0A register allocation map . . . . . . . . . . .54
Table 80. Register MAIN_CNTRL (address 00h) . . . . . .56
Table 81. Register MAN_LDCLKDEL (address 01h) . . . .56
Table 82. Register DBG_LVDS (address 02h) . . . . . . . .56
Table 83. Register RST_EXT_LCLK (address 04h) . . . .56
Table 84. Register RST_EXT_DCLK (address 05h) . . . .57
Table 85. Register DCSMU_PREDIV (address 06h) . . . .57
Table 86. Register LD_POL_LSB (address 08h) . . . . . . .57
Table 87. Register LD_POL_MSB (address 09h) . . . . . .57
Table 88. Register LD_CNTRL (address 0Ah) . . . . . . . .57
Table 89. Register MISC_CNTRL (address 0Bh) . . . . . .58
Table 90. Register I_DC_LVL_LSB(address 0Ch) . . . . .59
Table 91. Register I_DC_LVL_MSB(address 0Dh) . . . . .59
Table 92. Register Q_DC_LVL_LSB(address 0Eh) . . . . .59
Table 93. Register Q_DC_LVL_MSB(address 0Fh) . . . .59
Table 94. Register TYPE_ID (address 1Bh) . . . . . . . . . .59
Table 95. Register DAC_VERSION (address 1Ch) . . . . .60
Table 96. Register DIG_VERSION (address 1Dh) . . . . .60
Table 97. Register DIG_VERSION (address 1Eh) . . . . .60
Table 98. Register PAGE_ADD (address 1Fh) . . . . . . . .60
Table 99. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 100. Revision history . . . . . . . . . . . . . . . . . . . . . . . .64
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
68 of 69
DAC1627D1G25
NXP Semiconductors
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.2.1
10.2.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.5
10.5.1
10.5.2
10.6
10.7
10.7.1
10.7.2
10.7.3
10.8
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.10
10.11
10.12
10.12.1
10.12.2
10.13
10.14
10.15
10.16
10.16.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics . . . . . . . . . . . . . . . . . . 7
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 12
General description . . . . . . . . . . . . . . . . . . . . 12
Serial Peripheral Interface (SPI) . . . . . . . . . . . 13
Protocol description . . . . . . . . . . . . . . . . . . . . 13
SPI timing description . . . . . . . . . . . . . . . . . . . 14
Power-on sequence . . . . . . . . . . . . . . . . . . . . 14
LVDS Data Input Format (DIF) block . . . . . . . 15
Input port polarity . . . . . . . . . . . . . . . . . . . . . . 15
Input port mapping . . . . . . . . . . . . . . . . . . . . . 16
Input port swapping . . . . . . . . . . . . . . . . . . . . 16
Input port formatting . . . . . . . . . . . . . . . . . . . . 17
Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LVDS DDR clock. . . . . . . . . . . . . . . . . . . . . . . 18
DAC core clock . . . . . . . . . . . . . . . . . . . . . . . . 18
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating modes . . . . . . . . . . . . . . . . . . . . . . 21
CDI mode 0 (x2 interpolation). . . . . . . . . . . . . 22
CDI mode 1 (x4 interpolation). . . . . . . . . . . . . 22
CDI mode 2 (x8 interpolation). . . . . . . . . . . . . 23
FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Single SideBand Modulator (SSBM). . . . . . . . 25
NCO in 40 bits . . . . . . . . . . . . . . . . . . . . . . . . 25
NCO low power . . . . . . . . . . . . . . . . . . . . . . . 26
Complex modulator . . . . . . . . . . . . . . . . . . . . 26
Minus 3dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Inverse sinx / x . . . . . . . . . . . . . . . . . . . . . . . . 27
DAC transfer function . . . . . . . . . . . . . . . . . . . 27
Full-scale current . . . . . . . . . . . . . . . . . . . . . . 28
Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Full-scale current adjustment . . . . . . . . . . . . . 28
Digital offset adjustment . . . . . . . . . . . . . . . . . 29
Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 30
Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 31
Output configuration . . . . . . . . . . . . . . . . . . . . 32
Basic output configuration . . . . . . . . . . . . . . . 32
10.16.2
10.16.3
10.16.4
10.17
10.17.1
10.18
10.18.1
10.18.2
10.18.3
10.18.4
10.18.5
10.18.6
10.18.7
11
12
13
13.1
13.2
14
15
15.1
15.2
15.3
15.4
16
17
18
IQ-modulator - BGX7100 interface . . . . . . . .
IQ-modulator - DC interface. . . . . . . . . . . . . .
IQ-modulator - AC interface . . . . . . . . . . . . . .
Design recommendations . . . . . . . . . . . . . . .
Power and grounding. . . . . . . . . . . . . . . . . . .
Configuration interface. . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . . .
Page 0 register allocation map . . . . . . . . . . .
Page 0 bit definition detailed description . . . .
Page 1 allocation map . . . . . . . . . . . . . . . . . .
Page 1 bit definition detailed description . . . .
Page A register allocation map . . . . . . . . . . .
Page A bit definition detailed description . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static parameters . . . . . . . . . . . . . . . . . . . . . .
Dynamic parameters . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
36
36
36
37
37
38
40
46
48
54
56
61
62
63
63
63
64
65
65
65
65
66
66
67
69
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 April 2011
Document identifier: DAC1627D1G25