PHILIPS 74LVC2G38GM

INTEGRATED CIRCUITS
DATA SHEET
74LVC2G38
Dual 2-input NAND gate
(open drain)
Product specification
Supersedes data of 2003 Oct 27
2004 Oct 18
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 V to 5.5 V
The 74LVC2G38 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
• 5 V tolerant outputs for interfacing with 5 V logic
• High noise immunity
Inputs can be driven from either 3.3 V or 5 V devices.
These feature allows the use of these devices as
translators in a mixed 3.3 V and 5 V environment.
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
The 74LVC2G38 provides the 2-input NAND function.
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24 mA output drive (VCC = 3.0 V)
The outputs of the 74LVC2G38 devices are open drain
and can be connected to other open-drain outputs to
implement active-LOW, wired-OR or active-HIGH
wired-AND functions.
• CMOS low power consumption
• Open drain outputs
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
tPZL/tPLZ
PARAMETER
propagation delay inputs nA and nB to
output nY
CI
input capacitance
CPD
power dissipation capacitance per gate
CONDITIONS
UNIT
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
3.0
ns
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
1.8
ns
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
2.5
ns
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
2.1
ns
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω
1.5
ns
2.5
pF
5
pF
VCC = 3.3 V; notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
2004 Oct 18
TYPICAL
2
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nA
nB
nY
L
L
Z
L
H
Z
H
L
Z
H
H
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
MARKING
74LVC2G38DP
−40 °C to +125 °C
8
TSSOP8
plastic
SOT505-2
Y38
74LVC2G38DC
−40 °C to +125 °C
8
VSSOP8
plastic
SOT765-1
Y38
74LVC2G38GM
−40 °C to +125 °C
8
XSON8
plastic
SOT833-1
Y38
PINNING
PIN
2004 Oct 18
SYMBOL
DESCRIPTION
1
1A
data input
2
1B
data input
3
2Y
data output
4
GND
ground (0 V)
5
2A
data input
6
2B
data input
7
1Y
data output
8
VCC
supply voltage
3
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
38
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
38
001aab829
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
001aab830
Transparent top view
Fig.1 Pin configuration TSSOP8 and VSSOP8.
handbook, halfpage
1
1A
2
1B
5
2A
6
2B
Fig.2 Pin configuration XSON8.
handbook, halfpage
1
1Y
7
2
2Y
3
5
&
7
&
3
6
MNB129
MNB130
Fig.3 Logic symbol.
2004 Oct 18
Fig.4 Logic symbol (IEEE/IEC).
4
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
Y
handbook, halfpage
A
B
GND
MNB131
Fig.5 Logic diagram (one gate).
2004 Oct 18
5
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
1.65
5.5
V
VI
input voltage
0
5.5
V
VO
output voltage
active mode
0
VCC
V
VCC = 1.65 V to 5.5 V; disable
mode
0
5.5
V
VCC = 0 V; Power-down mode
0
5.5
V
−40
+125
°C
VCC = 1.65 V to 2.7 V
0
20
ns/V
VCC = 2.7 V to 5.5 V
0
10
ns/V
Tamb
operating ambient temperature
tr, tf
input rise and fall times
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
−0.5
+6.5
V
IIK
input diode current
VI < 0 V
−
−50
mA
VI
input voltage
note 1
−0.5
+6.5
V
IOK
output diode current
VO > VCC or VO < 0 V
−
±50
mA
VO
output voltage
active mode; notes 1 and 2
−0.5
+6.5
V
Power-down mode; notes 1 and 2 −0.5
+6.5
V
IO
output source or sink current
−
±50
mA
ICC, IGND
VCC or GND current
−
±100
mA
Tstg
storage temperature
−65
+150
°C
PD
power dissipation
−
300
mW
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
2004 Oct 18
6
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
OTHER
Tamb = −40 °C to +85 °C; note 1
VIH
VIL
VOL
HIGH-level input voltage
LOW-level input voltage
1.65 to 1.95
0.65 × VCC −
−
V
2.3 to 2.7
1.7
−
−
V
2.7 to 3.6
2.0
−
−
V
4.5 to 5.5
0.7 × VCC
−
−
V
1.65 to 1.95
−
−
0.35 × VCC V
2.3 to 2.7
−
−
0.7
2.7 to 3.6
−
−
0.8
V
4.5 to 5.5
−
−
0.3 × VCC
V
V
LOW-level output voltage VI = VIH or VIL
IO = 100 µA
1.65 to 5.5
−
−
0.1
V
IO = 4 mA
1.65
−
0.08
0.45
V
IO = 8 mA
2.3
−
0.14
0.3
V
IO = 12 mA
2.7
−
0.19
0.4
V
IO = 24 mA
3.0
−
0.37
0.55
V
IO = 32 mA
4.5
−
0.43
0.55
V
ILI
input leakage current
VI = 5.5 V or GND
5.5
−
±0.1
±5
µA
Ioff
power OFF leakage
current
VI or VO = 5.5 V
0
−
±0.1
±10
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0 A
5.5
−
0.1
10
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0 A
2.3 to 5.5
−
5
500
µA
2004 Oct 18
7
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 °C to +125 °C
VIH
VIL
VOL
1.65 to 1.95
0.65 × VCC −
−
V
2.3 to 2.7
1.7
−
−
V
2.7 to 3.6
2.0
−
−
V
4.5 to 5.5
0.7 × VCC
−
−
V
1.65 to 1.95
−
−
0.35 × VCC V
2.3 to 2.7
−
−
0.7
V
2.7 to 3.6
−
−
0.8
V
4.5 to 5.5
−
−
0.3 × VCC
V
IO = 100 µA
1.65 to 5.5
−
−
0.1
V
IO = 4 mA
1.65
−
−
0.70
V
IO = 8 mA
2.3
−
−
0.45
V
IO = 12 mA
2.7
−
−
0.60
V
IO = 24 mA
3.0
−
−
0.80
V
IO = 32 mA
4.5
−
−
0.80
V
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage VI = VIH or VIL
ILI
input leakage current
VI = 5.5 V or GND
5.5
−
−
±20
µA
Ioff
power OFF leakage
current
VI or VO = 5.5 V
0
−
−
±20
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0 A
5.5
−
−
40
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0 A
2.3 to 5.5
−
−
5000
µA
Note
1. All typical values are measured at Tamb = 25 °C.
2004 Oct 18
8
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
AC CHARACTERISTICS
GND = 0 V.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
WAVEFORMS
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 °C to +85 °C; note 1
tPZL/tPLZ
propagation delay inputs nA
and nB to output nY
see Figs 6 and 7 1.65 to 1.95
1.2
3.0
8.6
ns
2.3 to 2.7
0.7
1.8
4.8
ns
2.7
0.7
2.5
4.4
ns
3.0 to 3.6
0.7
2.1
4.1
ns
4.5 to 5.5
0.5
1.5
3.3
ns
Tamb = −40 °C to +125 °C
tPZL/tPLZ
propagation delay inputs nA
and nB to output nY
1.2
−
10.8
ns
2.3 to 2.7
0.7
−
6.0
ns
2.7
0.7
−
5.5
ns
3.0 to 3.6
0.7
−
5.2
ns
4.5 to 5.5
0.5
−
4.2
ns
see Figs 6 and 7 1.65 to 1.95
Note
1. All typical values are measured at Tamb = 25 °C.
AC WAVEFORMS
VI
handbook, full pagewidth
nA, nB input
VM
GND
t PLZ
t PZL
VCC
nY output
VM
VX
VOL
MNB132
INPUT
VCC
VM
VX
VI
tr = tf
1.65 V to 1.95 V
0.5 × VCC
VOL + 0.15 V
VCC
≤ 2.0 ns
2.3 V to 2.7 V
0.5 × VCC
VOL + 0.15 V
VCC
≤ 2.0 ns
2.7 V
1.5 V
VOL + 0.3 V
2.7 V
≤ 2.5 ns
3.0 V to 3.6 V
1.5 V
VOL + 0.3 V
2.7 V
≤ 2.5 ns
4.5 V to 5.5 V
0.5 × VCC
VOL + 0.3 V
VCC
≤ 2.5 ns
Fig.6 Inputs nA and nB to output nY propagation delay times.
2004 Oct 18
9
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
VEXT
handbook, full pagewidth
VCC
PULSE
GENERATOR
VI
RL
VO
D.U.T.
CL
RT
RL
MNA616
VCC
VI
CL
RL
VEXT
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 V to 1.95 V
VCC
30 pF
1 kΩ
open
GND
2 × VCC
2.3 V to 2.7 V
VCC
30 pF
500 Ω
open
GND
2 × VCC
2.7 V
2.7 V
50 pF
500 Ω
open
GND
6V
3.0 V to 3.6 V
2.7 V
50 pF
500 Ω
open
GND
6V
4.5 V to 5.5 V
VCC
50 pF
500 Ω
open
GND
2 × VCC
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
2004 Oct 18
10
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
2004 Oct 18
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
11
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
2004 Oct 18
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
12
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.95 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.0
0.9
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
2004 Oct 18
13
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
Philips Semiconductors
Product specification
Dual 2-input NAND gate (open drain)
74LVC2G38
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Oct 18
14
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA76
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/02/pp15
Date of release: 2004
Oct 18
Document order number:
9397 750 13785