BUK964R7-80E N-channel TrenchMOS logic level FET 5 October 2012 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in a SOT404 package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 1.2 Features and benefits • AEC Q101 compliant • Repetitive avalanche rated • Suitable for thermally demanding environments due to 175 °C rating • True logic level gate with Vgst(th) rating of greater than 0.5V at 175 °C 1.3 Applications • 12V, 24V and 48V Automotive systems • Motors, lamps and solenoid control • Start-Stop micro-hybrid applications • Transmission control • Ultra high performance power switching 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 80 V ID drain current VGS = 5 V; Tmb = 25 °C; Tmb = 25 °C; - - 120 A Tmb = 25 °C; Fig. 2 - - 324 W VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11 - 3.6 4.7 mΩ VGS = 5 V; ID = 25 A; VDS = 64 V; - 28.9 - nC [1] Fig. 1 Ptot total power dissipation Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge Fig. 13; Fig. 14 [1] Continuous current is limited by package. Scan or click this QR code to view the latest information for this product BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol D mb G 1 S mbb076 2 3 D2PAK (SOT404) 3. Ordering information Table 3. Ordering information Type number Package BUK964R7-80E Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped) 4. Marking Table 4. Marking codes Type number Marking code BUK964R7-80E BUK964R7-80E 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 80 V VDGR drain-gate voltage RGS = 20 kΩ - 80 V VGS gate-source voltage Tj ≤ 175 °C; Pulsed -15 15 V -10 10 V [3] - 120 A [3] - 120 A [1][2] Tj ≤ 175 °C; DC ID drain current Tmb = 25 °C; Tmb = 25 °C; VGS = 5 V; Fig. 1 Tmb = 100 °C; VGS = 5 V; Fig. 1 IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4 - 667 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 324 W BUK964R7-80E Product data sheet All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 2 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Tstg Tj Conditions Min Max Unit storage temperature -55 175 °C junction temperature -55 175 °C - 120 A - 667 A - 384 mJ Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C [3] Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 120 A; Vsup ≤ 80 V; RGS = 50 Ω; [4][5] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 3 [1] [2] [3] [4] [5] Accumulated pulse duration up to 50 hours delivers zero defect ppm Significantly longer life times are achieved by lowering Tj and or VGS Continuous current is limited by package. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 003aah915 200 ID (A) 03aa16 120 Pder (%) 160 80 120 (1) 80 40 40 0 0 50 100 150 Tmb (° C) (1) Capped at 120A due to package Fig. 1. Continuous drain current as a function of mounting base temperature BUK964R7-80E Product data sheet 0 200 Fig. 2. 0 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 5 October 2012 50 © NXP B.V. 2012. All rights reserved 3 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET 003aah916 103 IAL (A) 102 (1) 10 (2) 1 (3) 10-1 10-3 Fig. 3. 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time 003aah917 103 ID (A) Limit RDSon = V DS / ID tp =10 µ s 102 100 µ s 10 DC 1 ms 1 10 ms 100 ms 10-1 10-1 Fig. 4. 1 10 102 103 V DS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 0.46 K/W Rth(j-a) thermal resistance from junction to ambient minimum footprint ; mounted on a printed-circuit board - 50 - K/W BUK964R7-80E Product data sheet All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 4 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET 003aah663 1 Zth(j-mb) (K/W) δ = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 P single shot tp 10 tp T δ= -3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 t T 10-1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 7. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 80 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 72 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.4 1.7 2.1 V - - 2.45 V 0.5 - - V VDS = 80 V; VGS = 0 V; Tj = 25 °C - 0.13 1 µA VDS = 80 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11 - 3.6 4.7 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; - 3.3 4.5 mΩ - - 11.7 mΩ Static characteristics V(BR)DSS VGS(th) Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 9 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 9 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 11 VGS = 5 V; ID = 25 A; Tj = 175 °C; Fig. 12; Fig. 11 Dynamic characteristics QG(tot) QGS total gate charge ID = 25 A; VDS = 64 V; VGS = 5 V; - 92.1 - nC gate-source charge Fig. 13; Fig. 14 - 25.7 - nC BUK964R7-80E Product data sheet All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 5 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) Conditions Min Typ Max Unit - 28.9 - nC VGS = 0 V; VDS = 25 V; f = 1 MHz; - 11500 15340 pF Tj = 25 °C; Fig. 15 - 744 892 pF - 360 493 pF VDS = 60 V; RL = 2.4 Ω; VGS = 5 V; - 54.2 - ns RG(ext) = 5 Ω - 95.7 - ns turn-off delay time - 112 - ns tf fall time - 82.3 - ns LD internal drain inductance from upper edge of drain mounting base to center of die - 2.5 - nH LS internal source inductance from source lead to source bonding pad - 7.5 - nH Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.77 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 49.8 - ns Qr recovered charge VDS = 25 V - 97.2 - nC 003aah919 240 4.5 VGS (V) = 10 ID (A) 003aah920 15 3 RDSon (mΩ ) 160 10 2.8 80 5 2.6 2.4 0 0 1 2 VDS(V) 0 3 Tj = 25 °C; tp = 300 μs Fig. 6. Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values BUK964R7-80E Product data sheet 0 5 7.5 V (V) 10 GS Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 5 October 2012 2.5 © NXP B.V. 2012. All rights reserved 6 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET 003aah922 360 003aah025 3 VGS(th) (V) 2.5 ID (A) max 240 2 typ 1.5 120 min 1 Tj = 175 °C 0.5 Tj = 25 °C 0 Fig. 8. 0 1 2 3 4 VGS (V) 0 -60 5 Transfer characteristics; drain current as a function of gate-source voltage; typical values Fig. 9. 003aah026 10-1 0 60 120 003aah925 2.4 RDSon (mΩ ) 10-2 180 Gate-source threshold voltage as a function of junction temperature 20 ID (A) Tj (° C) 2.6 2.8 3 15 min 10-3 typ max 10 10 -4 5 10-5 4.5 VGS (V) = 10 10-6 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage BUK964R7-80E Product data sheet 0 80 160 ID (A) 240 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 7 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET 003aae090 3 VDS a ID 2.4 VGS(pl) 1.8 VGS(th) VGS 1.2 QGS1 QGS2 QGS 0.6 QGD QG(tot) 003aaa508 0 -60 0 60 120 Tj (° C) Fig. 13. Gate charge waveform definitions 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature 003aah927 10 VGS (V) 003aah928 105 C (pF) 8 14 V Ciss 104 6 4 VDS = 64V 103 Coss 2 0 Crss 0 60 120 QG (nC) 180 Fig. 14. Gate-source voltage as a function of gate charge; typical values BUK964R7-80E Product data sheet 102 10-1 1 10 2 VDS (V) 10 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 8 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET 003aah929 300 IS (A) 240 180 120 Tj = 175 °C Tj = 25 °C 60 0 0 0.3 0.6 0.9 V (V) 1.2 SD Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK964R7-80E Product data sheet All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 9 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET 8. Package outline SOT404 Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) A A1 E mounting base D1 D HD 2 1 Lp 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-03-16 SOT404 Fig. 17. Package outline D2PAK (SOT404) BUK964R7-80E Product data sheet All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 10 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 9. 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BUK964R7-80E Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 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All rights reserved 11 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK964R7-80E Product data sheet All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 12 / 13 BUK964R7-80E NXP Semiconductors N-channel TrenchMOS logic level FET 10. Contents 1 1.1 1.2 1.3 1.4 Product profile ....................................................... 1 General description .............................................. 1 Features and benefits ...........................................1 Applications .......................................................... 1 Quick reference data ............................................ 1 2 Pinning information ............................................... 2 3 Ordering information ............................................. 2 4 Marking ................................................................... 2 5 Limiting values .......................................................2 6 Thermal characteristics .........................................4 7 Characteristics ....................................................... 5 8 Package outline ................................................... 10 9 9.1 9.2 9.3 9.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP B.V. 2012. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 5 October 2012 BUK964R7-80E Product data sheet All information provided in this document is subject to legal disclaimers. 5 October 2012 © NXP B.V. 2012. All rights reserved 13 / 13 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: BUK964R7-80E,118