PHILIPS 74ABTL3205BB

INTEGRATED CIRCUITS
74ABTL3205
10-bit BTL transceiver with registers
Product specification
1995 Jun 16
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
FEATURES
74ABTL3205
DESCRIPTION
• 10-bit BTL transceiver
• Drives heavily loaded backplanes with equivalent load
This transceiver is a 10 bit bidirectional transceiver and is intended
to provide the electrical interface to a high performance wired-OR
bus.
impedances down to 10 ohms
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good margins by limiting
the switching threshold to a narrow region centered at 1.55V.
• High drive 100mA BTL open collector drivers on B-port
• Allows incident wave switching in heavily loaded backplane buses
• Reduced BTL voltage swing produces less noise and reduces
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading (<6pF) by placing an internal series
diode on the drivers. BTL also provides incident wave switching, a
necessity for high performance backplanes.
power consumption
• Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Controlled output ramp and multiple GND pins minimize ground
To support live insertion, OEB is held Low during power on/off cycles
to insure glitch free B port drivers. Proper bias for B port drivers
during live insertion is provided by the BIAS V pin when at a 5V level
while VCC is Low. The BIAS V pin is a low current input which will
reverse bias the BTL driver series Schottky diode, and also bias the
B port output pins to a voltage between 1.62V and 2.1V. This bias
function is in accordance with IEEE BTL standard 1194.1. If live
insertion is not a requirement, the BIAS V pin should be tied to a
VCC pin.
bounce
• Tight output skew (0.5nsec typical)
• Glitch-free power up/down operation
• Low ICC current
• Supports live insertion
• High density packaging
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package. The LOGIC VCC and BUS VCC pins are also isolated
internally to minimize noise and may be externally decoupled
separately or simply tied together.
and 200V per Machine Model
This transceiver function is intended to operate in a half-duplex
mode. Low current in standby mode is obtained by powering down
unused circuitry. Likewise, transmit circuitry is powered down when
in receive mode and receive circuitry is powered down while in
transmit mode.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn
3.3
3.7
ns
tPLH
tPHL
Propagation delay
Bn to An
3.6
3.5
ns
COB
Output capacitance (B0 - B8) only)
6
pF
IOL
Output current (B0 - B8) only)
100
mA
ICC
Supply current
Standby
1
An to Bn
7
Bn to An
18
mA
ORDERING INFORMATION
PACKAGES
52-PIN PQFP
1995 Jun 16
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
–40°C to +85°C
74ABTL3205 BB
74ABTL3205 BB
SOT379-1
2
853-1802 15352
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
TTL Gnd
1
BUS GND
BClk1
VCC
Mode
OEB
OEA2
BiasV
OEA1
51 50 49 48 47 46 45 44 43 42 41 40
AClkin
TTL Gnd
52
VCC
AClk1
Recmode
PIN CONFIGURATION
39
BUS GND
38
B0
A0
2
A1
3
37
B1
TTL GND
4
36
BUS GND
A2
5
35
B2
A3
6
34
B3
TTL GND
7
33
BUS GND
32
BClk2
31
BUS GND
30
B4
29
B5
28
BUS GND
27
B6
AClk2
8
TTL GND
9
A4
10
A5
11
TTL GND
A6
12
13
B7
BUS GND
VCC
Transmode
IEA
M/S
Power Up
AFP
APAR
BG GND
BG VCC
A7
TTL Gnd
14 15 16 17 18 19 20 21 22 23 24 25 26
SA00138
PIN DESCRIPTION
SYMBOL
FUNCTION
ASSERTION
I/O
LOGIC
OEA1
Output enable data receiver group 1
Low
Input
TTL
OEA2
Output enable data receiver group 2
Low
Input
TTL
OEB
Output enable data transmitter
Low
Input
TTL
IEA
Output enable clock and framepulse receiver
Low
Input
TTL
M/S
Master/Slave select:
L:
Master, enable clock transmitter
H:
Slave, disable clock transmitter
Input
TTL
Input
TTL
Mode
Low:
High:
Data through mode
Registered data mode
Power Up
Power up mode, held low during power up to
disable clock and data transmitters
Low
Input
TTL
Recmode
Enables receiver
High
Input
TTL
Tranmode
Enables transmitter
High
Input
TTL
AClk1
Clock or data path
I/O
TTL
I/O
TTL
AClkln
IEA = H → Input for busclock
IEA = L → Output for busclock
A0..A3
data group 1
I/O
TTL
AClk2
Clock or data path
I/O
TTL
AFPIn
Alternate data path
Output
TTL
APAR
Alternate data path
Input
TTL
A4..A7
data group 2
I/O
TTL
BClk1
Clock or data path
I/O
BTL
B0..B3
data group 1
I/O
BTL
BClk2
Clock or data path
I/O
BTL
B4..B7
data group 2
I/O
BTL
1995 Jun 16
3
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LOGIC DIAGRAM
ACLKin
I/O
ACLK1
I/O
BCLK1
I/O
ACLK2
I/O
AFP
OUT
APAR
IN
D
BCLK2
Q
I/O
C
B0-B3
A0-A3
I/O
I/O
D
Q
C
B4-B7
A4-A7
I/O
I/O
D
Q
C
IEA
IN
Definition for the MUX:
OEB
IN
M/S
IN
OEA1
IN
OEA2
Low
IN
High
RECMODE
IN
MODE
IN
TRANMODE
IN
POWERUP
IN
SA00139
1995 Jun 16
4
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
FUNCTION TABLE
INPUTS
MODE
An
Bn
ACLK
in
ACLK
1
ACLK
2
BCLK
1
BCLK
2
OEA1
OEA2
OEB
APAR
IEA
M/S
MODE
REC
MODE
TRAN
MODE
POWER
UP
I
O
°
X
X
X
X
H
H
L
X
H
X
H
L
H
H
h
O
°
X
X
X
X
H
H
L
X
H
X
H
L
H
H
L
O
X
X
X
X
X
H
H
L
X
X
X
L
L
H
H
H
O
X
X
X
X
X
H
H
L
X
X
X
L
L
H
H
B0-B3
to
A A
A0-A3
(THROUGH)
O
L
X
X
X
X
X
L
X
H
X
X
X
X
H
L
L
O
H
X
X
X
X
X
L
X
H
X
X
X
X
H
L
L
B4-B7
to
A A
A4-A7
(THROUGH)
O
L
X
X
X
X
X
X
L
H
X
X
X
X
H
L
L
O
H
X
X
X
X
X
X
L
H
X
X
X
X
H
L
L
ACLK1
to
BCLK1
X
X
X
L
X
O
X
H
X
X
X
X
L
X
X
H
H
X
X
X
H
X
O
X
H
X
X
X
X
L
X
X
H
H
ACLK2
to
BCLK2
X
X
X
X
L
X
O
X
H
H
X
X
L
L
X
H
H
X
X
X
X
H
X
O
X
H
H
X
X
L
L
X
H
H
BCLK1
to
ACLK1
X
X
X
O
X
L
X
L
X
X
X
X
X
X
H
L
X
X
X
X
O
X
H
X
L
X
X
X
X
X
X
H
L
X
BCLK2
to
ACLK2
X
X
X
X
O
X
L
X
L
X
X
X
X
X
H
L
X
X
X
X
X
O
X
H
X
L
X
X
X
X
X
H
L
X
APAR
to
BCLK2
X
X
°
X
X
X
X
X
X
L
I
X
H
H
X
H
H
X
X
°
X
X
X
X
X
X
L
h
X
H
H
X
H
H
BCLK2
to
AFPIn
X
X
X
X
X
X
L
X
X
X
X
L
X
X
H
L
X
X
X
X
X
X
X
H
X
X
X
X
L
X
X
H
L
X
BCLK1
to
ACLKin
X
X
O
X
X
L
X
H
H
L
O
L
H
H
L
H
H
X
X
O
X
X
H
X
H
H
L
O
L
H
H
L
H
H
An to Bn
(REGISTERED)
AN to Bn
(THROUGH)
OUTPUTS
MODE
O
An
Bn
Input
Input
Input
Input
H*
L
H*
L
ACLK
in
X
X
X
X
ACLK1
ACLK2
BCLK1
BCLK2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AF
Pin
X
X
X
X
B0-B3
to
A A
A0-A3
(THROUGH)
H
Input
Input
X
X
X
X
X
L
B4-B7
to
A A
A4-A7
(THROUGH)
Input
Input
X
X
X
X
X
H
Input
Input
X
X
X
X
X
ACLK1
to
BCLK1
L
Input
Input
X
X
X
X
X
X
X
X
Input
X
H*
X
X
NOTES:
X
X
X
Input
X
L
X
X
H = High voltage level
ACLK2
to
BCLK2
X
X
X
X
Input
X
H*
X
L = Low voltage level
X
X
X
X
Input
X
L
X
h = High voltage level one set-up time prior to
BCLK1
to
ACLK1
X
X
X
H
X
Input
X
X
X
X
X
L
X
Input
X
X
BCLK2
to
ACLK2
X
X
X
X
H
X
Input
X
X
X
X
X
L
X
Input
APAR
to
BCLK2
X
X
Input
X
X
X
H*
X
X
Input
X
X
X
BCLK2
to
AFPIn
X
X
X
X
X
X
X
X
X
X
X
X
BCLK1
to
ACLKin
X
X
H
X
X
X
X
L
X
X
An to Bn
(REGISTERED)
AN to Bn
(THROUGH)
1995 Jun 16
Low to High ACLKin transition
l
= Low voltage level one set-up time prior to
X
°
= Low to High transition
X
Z = High impedance (off) state
L
X
H* = Goes to level of pull-up voltage
Input
H*
X = Don’t care
Input
L
O = Output
Input
X
X
Input
X
X
5
Low to High ACLKin transition
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LOGIC SYMBOL (IEEE/IEC)
Recmode
Transmode
Powerup
OEA1
EN1
OEA2
EN2
OEB
EN3
IEA
EN4
M/S
EN5
MODE
EN6
&
EN8
6C7
AClk1
AClkIn
A0
1
5
BClk1
4
1
7D
3
1
7D
3
1
7D
3
1
7D
3
B0
A1
A2
A3
AClk2
AFP
2
A5
A6
A7
B2
B3
BClk2
4
APAR
A4
5
B1
7D
8
2
7D
3
2
7D
3
2
7D
3
2
7D
3
B4
B5
B6
B7
SA00140
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted, these limits are over the operating free-air temperature range.
SYMBOL
PARAMETER
VCC
Supply voltage
VIN
Input voltage
IIN
Input current
UNIT
–0.5 to +7.0
V
TTL Signals
–1.2 to +7.0
V
BTL Signals
–1.2 to +5.5
V
–18 to +5
mA
–0.5 to +VCC
/v
A0 - A8
48
mA
B0 - B8
200
mA
Operating free-air temperature range
–40 to +85
°C
Storage temperature
–65 to +150
°C
VOUT
Voltage applied to output in High output state
IOUT
O
Current applied to output in Low output state
Tamb
TSTG
1995 Jun 16
RATING
6
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
LIMITS
TEST CONDITIONS1
PARAMETER
MIN
UNIT
TYP2
MAX
IOH
High level output current
BTL
VCC = MAX, VIL = MAX,
VIH = MIN, VOH = 1.9V
0.5
100
µA
IOFF
Power-off output current
BTL
VCC = 0.0V, VIL = MAX,
VIH = MIN, VOH = 1.9V
10
100
µA
2.85
3.4
V
VCC – 1.1
V
0.35
0.5
V
1.10
V
VCC = MIN, VIL = MAX,4
VIH = MIN, IOH = –3mA
VOH
High-level output voltage
TTL
TTL
VOL
Low-level output voltage
BTL
VIK
Input
In
ut clamp
clam voltage
II
Input current at maximum
input voltage
IIH
2.5
VCC = MIN to MAX, 4
VIL = MAX, VIH = MIN,
IOH = –10µA
VCC = MIN, VIL = MAX,
VIH = MIN, IOL = 24mA
VCC = MIN, VIL = MAX,
VIH = MIN, IOL = 100mA
0.75
1.0
VCC = MIN, VIL = MAX,
VIH = MIN, IOL = 4mA
0.5
0.7
V
TTL
VCC = MIN, II = IIK
0.8
–1.2
V
BTL
VCC = MIN, II = –18mA
0.8
–1.2
V
TTL
VCC = MAX,
VI = 0.5V or 5.5V
0.1
±50
µΑ
TTL
VCC = MAX, VI = 2.7V,
Bn = AIn = 0V
0.1
20
µΑ
0.1
100
Hi
hl
l iinputt currentt
High-level
BTL
VCC = MAX, VI = 1.9V
VCC = MAX, VI = 3.5V5
100
µΑ
mA
TTL
VCC = MAX, VI = 0.5V
0.1
–20
µΑ
BTL
VCC = MAX, VI = 0.75V
0.1
–100
µΑ
Off-state output current
TTL
VCC = MAX, VO = 2.7V
0.1
50
µΑ
IOZL
Off-state output current
TTL
VCC = MAX, VO = 0.5V
20
–50
µΑ
IOS
Short-circuit output
current3
TTL
VCC = MAX, VO = 0.0V
130
–150
mA
IIL
Low-level in
input
ut current
IOZH
ICC
Supply current (total)
–60
Recmode Low
Tranmode Low
VCC = MAX
1
3
mA
Recmode Low
Tranmode High
VCC = MAX
Mode = Low
7
12
mA
Recmode Low
Tranmode High
VCC = MAX
Mode = High
13
21
mA
Recmode High
Tranmode Low
VCC = MAX
18
25
mA
Recmode High
Tranmode High
VCC = MAX
29
43
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side.
5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally.
TTL signals CLKin, CLK-1/CLK-OUT, CLK-2/FP-OUT, /FP-IN, /PARITY t,A0..A7, OEB, MASTER/SLAVE, MODE, OEA1, OEA2
BTL signals CLK1BTL, CLK2BTL, B0..B7
1995 Jun 16
7
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LIVE INSERTION SPECIFICATIONS
LIMITS
SYMBOL
VBIASV
IBIASV
ǸBn
PARAMETER
Bias pin DC current
Bias pin
in DC current
Bus voltage during prebias
MIN
VCC = 0 to 5.25V, Bn = 0 to 2.0 V
NOM
4.5
MAX
UNIT
5.5
V
VCC = 0 to 4.75 V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
1
mA
VCC = 4.5 to 5.5V, Bn = 0 to 2.0 V,
Bias V = 4.5 to 5.5V
10
µA
2.1
V
B0 – B8 = 0V, Bias V = 5.0V
1.62
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = 5V
CL = 50pF, CL = 500Ω
Tamb = –40°C to +85°C
VCC = 5V ± 10%
CL = 50pF, CL = 500Ω
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
g
delay
y
Bn to An
Waveform 2
2.0
1.8
3.6
3.5
6.5
6.1
2.0
1.8
7.3
6.7
ns
tPLH
tPHL
Propagation
delay,
g
y
BCLK1 to ACLK1
Waveform 2
2.0
1.8
3.8
3.6
6.5
6.1
2.0
1.8
7.3
6.7
ns
tPLH
tPHL
Propagation
g
delay
y
BCLK1 to ACLKin
Waveform 2
2.0
1.8
3.7
3.7
6.5
6.1
2.0
1.8
7.3
6.7
ns
tPLH
tPHL
Propagation
g
delay
y
BCLK2 to ACLK2
Waveform 2
2.0
1.8
3.7
3.9
6.5
6.1
2.0
1.8
7.3
6.7
ns
tPLH
tPHL
Propagation
g
delay
y
BCLK2 to AFP
Waveform 2
2.0
1.8
3.8
3.9
6.5
6.1
2.0
1.8
7.3
6.7
ns
tPZH
tPLZ
Output Enable time
OEA1, OEA2, IEA to An
Waveform 1
1, 2
2.0
1.8
3.8
2.5
6.5
6.1
2.0
1.8
7.3
6.7
ns
tPHZ
tPLZ
Output Disable time
OEA1, OEA2, IEA to An
Waveform 4
4, 5
1.6
2.0
2.5
3.3
5.6
7.8
1.4
1.8
5.7
8.2
ns
tTLH
Output transition time, An Port
10% to 90%, 90% to 10%
Test Circuit and
Waveforms
3.0
7.0
1.7
4.0
tTHL
tSK(p)
Pulse skew2
|tPHL – tPLH| MAX
Waveform 3
2.0
ns
ns
NOTES:
1. | tPN actual – tPM actual | for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 Jun 16
8
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
AC ELECTRICAL CHARACTERISTICS
B PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = 5V
CD = 30pF, RU = 18.5Ω
Tamb = –40°C to +85°C
VCC = 5V ± 10%
CL = 30pF, RU = 18.5Ω
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
g
delay
y
An to Bn
Waveform 2
1.0
1.0
3.3
2.7
4.7
4.5
1.0
1.0
57
5.7
ns
tPLH
tPHL
Propagation
g
delay,
y
ACLKin to Bn
Waveform 1
1, 2
2.0
2.0
4.6
4.5
5.9
5.9
2.0
2.0
6.3
6.3
ns
tPLH
tPHL
Propagation
g
delay
y
ACLKin to BCLK2
Waveform 1
1, 2
2.0
2.0
4.6
4.5
7.3
7.3
2.0
2.0
7.6
7.6
ns
tPLH
tPHL
Propagation
g
delay
y
ACLK1 to BCLK1
Waveform 2
1.0
1.0
3.2
2.9
4.7
4.5
1.0
1.0
5.1
4.7
ns
tPLH
tPHL
Propagation
g
delay
y
ACLK2 to BCLK2
Waveform 2
1.0
1.0
3.1
3.1
5.7
5.5
1.0
1.0
6.0
5.6
ns
tPLH
tPHL
Enable/disable time
OEB to Bn or BCLK2
Waveform 1
1, 2
1.0
1.0
3.8
3.4
6.8
6.4
1.0
1.0
7.6
6.9
ns
tTLH
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.0
2.5
1.0
3.0
0.6
2.0
0.6
2.5
tTHL
tSK(p)
Pulse skew2
|tPHL – tPLH| MAX
Waveform 3
2.0
ns
ns
NOTES:
1. | tPN actual – tPM actual | for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = 5V
Tamb = –40°C to +85°C
VCC = 5V ± 10%
UNIT
CL = 50pF (A side) / CD = 30pF (B side)
RL = 500Ω (A side) / RU = 18.5Ω (B side)
MIN
TYP
MIN
MAX
ts(H)
ts(L)
Setup time
An to ACLKin
Waveform 6
1.9
1.3
2.0
1.5
ns
th(H)
th(L)
Hold time
An to ACLKin
Waveform 6
1.8
2.0
2.3
2.0
ns
1995 Jun 16
9
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
AC WAVEFORMS
VM = 1.55V for Bn, VM = 1.5V for all others
VM
VM
OEA
VM
VM
OEAn
tPLH
tPZH
tPHL
An
VM
tPHZ
VOH –0.3V
VM
0V
VM
An
SA00144
SA00141
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 1. Propagation Delay for Data or
Output Enable to Output
OEA
VM
VM
VM
VM
An, Bn
tPZL
tPHL
tPLH
An
tPLZ
VM
VOL +0.3V
Bn, An
VM
VM
SA00145
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
SA00142
ÉÉÉ ÉÉÉÉ ÉÉÉ
ÉÉÉ ÉÉÉÉ ÉÉÉ
ÉÉÉ ÉÉÉÉ ÉÉÉ
Waveform 2. Propagation Delay for Data to Output
An
or
Bn
An, Bn
VM
VM
VM
VM
tS(H)
th(H)
VM
th(L)
tS(L)
tSK(0)
ACLKin
An, Bn
VM
SA00349
SA00143
Waveform 6. Data Setup and Hold Times
Waveform 3. Output Skews
1995 Jun 16
VM
VM
10
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
TEST CIRCUIT AND WAVEFORMS
VCC
BIAS V
7.0V
VIN
RL
VOUT
D.U.T.
PULSE
GENERATOR
tW
90%
RT
RL
CL
90%
VM
NEGATIVE
PULSE
AMP (V)
VM
10%
10%
LOW V
tTHL (tF)
Test Circuit for 3-State Outputs on A Port
tTLH (tR)
tTLH (tR)
SWITCH POSITION
tTHL (tF)
90%
TEST
SWITCH
tPLZ, tPZL
closed
All other
open
POSITIVE
PULSE
AMP (V)
90%
VM
VM
10%
10%
tW
LOW V
VM = 1.55V for Bn or Bn, VM = 1.5V for all others
VCC
BIAS V
VIN
VOUT
PULSE
GENERATOR
Input Pulse Definition
2.0V (for RU = 9Ω)
2.1V (for RU = 16.5Ω)
RU
INPUT PULSE REQUIREMENTS
ABTL
RT
CD
tW
tTLH
tTHL
Amplitude
Low V
Rep. Rate
A Port
3.0V
0.0V
1MHz
500ns 2.5ns
2.5ns
B Port
2.0V
1.0V
1MHz
500ns 2.5ns
2.5ns
D.U.T.
Test Circuit for Outputs on B Port
DEFINITIONS
RL =
Load resistor; see AC CHARACTERISTICS for value.
CL =
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT =
Termination resistance should be equal to ZOUT of pulse
generators.
CD =
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RU =
Pull up resistor;
see AC CHARACTERISTICS for value.
SA00146
1995 Jun 16
11
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
1995 Jun 16
12
SOT379-1
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
NOTES
1995 Jun 16
13
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 01-00
Document order number:
1995 Jun 16
14
9397 750 06827