Freescale Semiconductor Quick Start Guide Document Number: MC13852434QSG Rev. 0, 11/2010 MC13852 Evaluation Board Quick Start — 434 MHz INTRODUCTION This evaluation board design demonstrates one possible design at 2.75 V and 4 or 5 mA that satisfies competing requirements for NF, IP3, gain, return losses and current consumption with unconditional stability. By changing any of the requirements, the performance for a particular parameter can be improved to meet a particular spec requirement. This circuit was designed to provide NF < 1.7 dB, S21 gain > 18 dB using R1 = 1.2 kΩ and 1.5 kΩ. OIP3 is preserved in bypass mode for high input signal conditions when the LNA is bypassed to lower gain and current draw. Return losses are also preserved in bypass mode for excellent matching. Gain or NF can be improved with matching changes to meet specific requirements. Input return loss can be improved by increasing L1 to 33 nH, with NF increasing by 0.25 dB. Resistor R3 is used to de--Q output inductor L2 and adjust gain and return losses. Lowering R3 lowers gain and improves return losses. Bias resistor R1 is used to adjust for the desired current drain and IP3 performance. The LNA is bias stabilized for variations in device and temperature. NOTE: Tables 1 and 2 list measured parameters on three typical evaluation boards and are meant as a guide to the RF performance possible for this application circuit. Variations in matching component performance may result in variation in evaluation board performance results. Table 1. Evaluation Board Measurements (434 MHz, VCC = 2.75 V, Frequency Spacing = 200 kHz, Non--Linear Measurements at Pin = --30 dBm) Serial # R1 Mode Input Power (dBm) Output Power (dBm) Power Gain (dB) Output IP3 (dBm) Input IP3 (dBm) Output Ref P1dB (dBm) Input Ref P1dB (dBm) NF (dB) ICC (mA) 11 1.2k Active --30 --9.76 20.24 10.49 --9.75 7.84 --12.4 1.66 5.25 11 1.2k Bypass --30 --38.4 --8.40 16.5 24.9 — — 8.82 106 nA 12 1.2k Active --30 --9.74 20.26 10.56 --9.7 7.76 --12.5 1.66 5.38 12 1.2k Bypass --30 --38.59 --8.59 16.51 25.1 — — 9.06 1.2 μA 13 1.2k Active --30 --9.57 20.43 10.78 --9.65 7.73 --12.7 1.64 5.5 13 1.2k Bypass --30 --38.6 --8.6 16.8 25.4 — — 8.97 86 nA 11 1.5k Active --30 --10.52 19.48 7.81 --11.67 5.98 --13.5 1.6 4.19 11 1.5k Bypass --30 --38.25 --8.25 16.35 24.6 — — 8.74 106 nA 12 1.5k Active --30 --10.56 19.44 7.79 --11.65 6.24 --13.2 1.6 4.27 12 1.5k Bypass --30 --38.30 --8.30 16.40 24.7 — — 8.85 1.2 μA 13 1.5k Active --30 --10.35 19.65 8.05 --11.6 6.35 --13.3 1.6 4.34 13 1.5k Bypass --30 --38.60 --8.60 16.80 25.4 — — 8.59 86 nA Table 2. S--Parameters (434 MHz, VCC = 2.75 V) Serial # R1 11 11 Mode S11 (dB) S21 (dB) S12 (dB) S22 (dB) Serial # R1 1.2k Active --6.69 20.11 --35.4 --14.4 11 1.5k 1.2k Bypass --16.6 --8.33 --9.34 --20.2 11 1.5k 12 1.2k Active --6.5 20.12 --35.4 --14.5 12 1.5k 12 1.2k Bypass --17.65 --8.34 --8.35 --20.47 12 13 1.2k Active --6.78 20.29 --35.9 --14.6 13 13 1.2k Bypass --17.35 --8.23 --8.24 --20.43 13 © Freescale Semiconductor, Inc., 2010. All rights reserved. RF Engineering Bulletin Freescale Semiconductor S11 (dB) S21 (dB) S12 (dB) S22 (dB) Active --5.5 19.20 --35.1 --13.87 Bypass --16.7 --8.34 --8.37 --20.32 Active --5.3 19.20 --35.1 --13.90 1.5k Bypass --17.7 --8.36 --8.35 --20.51 1.5k Active --5.56 19.41 --35.1 --13.98 1.5k Bypass --17.31 --8.21 --8.22 --20.49 Mode MC13852434QSG 1 Gain Enable GND VCC VCC L3 6 Gain Band RF IN C2 L1 Logic C5 R2 3 7 2 8 1 L3 RFIN L2 4 5 Enable C4 C3 R1 C4 C5 L2 Q1 RF OUT L1 R3 C1 C2 R2 RFOUT C3 R3 R1 Pin 1 RBIAS Emit C1 Pin 1 Locator on Package Piccolo Low Band MC13852 V1R1 Figure 1. MC13852 434 MHz Schematic Figure 2. MC13852 434 MHz Evaluation Circuit Component Layout Table 3. Evaluation Circuit Component Designations and Values Component Value Case Manufacturer Comments Impact C1 1.3 pF 402 C2 47 pF 402 Murata DC Block, Input match S11, NF Murata DC Block, Output match C3 22 pF 402 Murata Output match C4 C5 0.1 μF 402 Murata Low freq bypass 33 pF 402 Murata Bypass L1 27 nH 402 Murata Input match S11, NF L2 47 nH 402 Murata Output match, bias decouple S22, S11 L3 270 nH 402 Murata Bias couple to logic R1 1.2 kΩ 402 KOA Bias set point R2 30 Ω 402 KOA Stability, lower gain R3 82 Ω 402 KOA L2 de--Q Q1 MC13852 MLF 2x2 Freescale S11, NF S22, gain IP3 S22, S11, gain SiGe LNA Table 4. Truth Table Enable Disable Pin Function Pin Name Low Gain High Gain Low Gain High Gain Logic Circuit Bias VCC VCC 1 1 1 1 Toggles Gain Mode (Active or Bypass) Gain 0 1 0 1 Toggles LNA On/Off Enable 1 1 0 0 Selects the LNA Band 1 1 1 1 Notes: 1. Logic state “1” equals VCC voltage. Logic state of “0” equals ground potential. 2. VCC is inductively coupled to LNA Out pin and VCC pin. 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Freescalet and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. MC13852434QSG RF Engineering Bulletin MC13852434QSG Rev. 0, 11/2010 Freescale Semiconductor 3