DRM088 Designer Reference Manual
Devices Supported:
M9S08QD4
Document Number: DRM088
Rev. 0
07/2008
Pulse Width Modulation Controlled Fans Using the
M9S08QD4
Designer Reference Manual
by: Eddie Ng
Freescale Semiconductor, Inc.
Hong Kong
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
Feb, 22 2008
0.B
Description
Written by Eddie Ng, Edited by Ping Xu
Page
Number(s)
N/A
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Revision History
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Freescale Semiconductor
Contents
Chapter 1
Introduction
1.1
1.2
1.3
1.4
Introduction ................................................................................................................................... 11
Freescale’s Low Cost MCU Advantages and Features ................................................................. 11
BLDC Fan Reference Design Targets ........................................................................................... 13
Bi-Phase BLDC Motor ................................................................................................................... 13
Chapter 2
Motor Control
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Commutation ................................................................................................................................. 15
Rotor Position Control ................................................................................................................... 15
Commutation Waveforms .............................................................................................................. 16
Speed Control Mechanism ............................................................................................................ 16
Motor Startup ................................................................................................................................ 18
Fault Detection and Protection ...................................................................................................... 18
Use of Table Look-Up (TLU) and Closed Loop Speed Control Mechanism .................................. 19
Input Source Options .................................................................................................................... 19
Chapter 3
Implementation
3.1
3.2
3.3
3.4
Block Diagram ............................................................................................................................... 21
Hardware Resources .................................................................................................................... 22
Control Loop .................................................................................................................................. 22
Fan Speed Response to PWM Control Input Signal ..................................................................... 23
Appendix A
Schematic
Appendix B
Program Listing
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Tables
Design Targets 13
Measurement of PWM Control Input Signal and Fan Speed (RPM) 26
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Figures
Bi-Phase BLDC Fan Motor Diagram 13
Bi-Phase BLDC Fan Motor 15
Bi-Phase BLDC Motor Commutation Waveform 16
Commutation Waveform using Phase On/Off Delay Time Control Method 17
Commutation Waveform using PWM Control Method 18
MC9S08QD4 DC Fan Design Block Diagram 21
On Board DAC Block Diagram 22
Firmware Control Loop Flowchart 23
PWM Control Input Signal vs. Fan Speed 24
Measured PWM Control Input Signal vs. Fan Speed 25
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DRM088, Rev. 0
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Introduction
Chapter 1
Introduction
1.1
Introduction
This document describes the implementation of a Brushless DC (BLDC) fan controller using the Freescale
MC9S08QD4 8-bit Microcontroller (MCU). The design reads the standard 4 wire PWM controlled input
signal, which in turn controls the fan speed in a closed-loop feedback system. Complete coding and
schematic are included.
Brushless DC fans are widely used in CPU and graphic display card cooling and system ventilation
applications. The lack of a commutator makes the brushless DC fan more reliable than the conventional
DC fan. Microcontroller (MCU) based, intelligent, variable-speed brushless DC fans are needed to avoid
overheating and fulfill the rapidly changing electronics products requirement. Characteristics of flash
MCU based BLDC such as the MC9S08QD4 include variable speed control, low acoustic noise,
reliability, long lifetime, low power consumption, protection features, easy to maintain/upgrade and
communication interface capability.
There are several advantages of a MCU based closed-loop feedback design over traditional solutions:
• A targeted air flow can be achieved by constantly renewed fan speed adjustment based on
environment changes of the target system, such as temperature.
• Fan characteristics and behavior can be updated and changed easily for different end users by
modifying the Table Look-Up (TLU) in the flash memory of the MCU.
• Fault detection can be easily implemented by the MCU. For example, if the MCU detects a motor
jam or the air flow being blocked, the motor driver can be stopped completely to avoid further
damage. The automatic restart feature is also available.
• Digital feedback and output acknowledgment can be generated under a faulty situation.
• Sophisticated speed control algorithms can be easily implemented and modified in the flash based
MCU, if needed.
The MCU chosen for this purpose must be low cost and physically small in order to integrate it into the
fan controller Printed Circuit Board (PCB). The MC9S08QD4 is ideal for this application.
1.2
Freescale’s Low Cost MCU Advantages and Features
The Freescale MC9S08QD4 MCU is a low cost, small pin count device well suited for home appliances
and small geometry applications, such as the brushless control DC (BLDC) fan application. This device is
composed of standard on-chip modules, including a small and highly efficient HCS08 8-bit CPU core, 256
bytes RAM, 4 Kilobytes flash, two 16-bit modulo timers, four channels 10-bit ADC and keyboard
interrupt. The device is available in small 8-pin PDIP and SOIC packages.
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Introduction
Features of the MC9S08QD4 include:
• 8-bit 16 MHz HCS08 CPU (Central Processor Unit)
— HC08 instruction set with added BGND instruction
— Background debugging system
— Breakpoint capability to allow single breakpoint setting during in-circuit debugging
— Support for up to 32 interrupt/reset sources
• Memory
— 4096 bytes flash
— 256 bytes RAM
• Internal Clock Source module (ICS)
— Containing a frequency-locked-loop (FLL) controlled by internal or external reference
— Precision trimming of internal reference allows 0.2% resolution and 2% deviation over
temperature and voltage
• System protection
— Watchdog Computer Operating Properly (COP) reset with option to run from dedicated 32 kHz
internal clock source or bus clock
— Low-voltage detection with reset or interrupt
— Illegal opcode detection with reset
— Illegal address detection with reset
— Flash block protect
• ADC
— 4-channel, 10-bit analog-to-digital converter with automatic compare function, asynchronous
clock source and internal bandgap reference channel
— On-chip temperature sensor for ADC temperature compensation, by calibration at 3 points,
-40°C, 25°C and 105°C; the temperature accuracy is up to ±2.5°C
— ADC is hardware triggerable using the RTI counter
• TIM1
— 2-channel timer/pulse-width modulator
— Each channel can be used for input capture, output compare, buffered edge-aligned PWM, or
buffered center-aligned PWM
• TIM2
— 1-channel timer/pulse-width modulator
— Each channel can be used for input capture, output compare, buffered edge-aligned PWM, or
buffered center-aligned PWM
• KBI
— 4-pin keyboard interrupt module with software selectable polarity on edge or edge/level modes
• Package Options
— 8-pin PDIP
— 8-pin narrow body small outline integrated circuit (SOIC) package
— All package options are RoHS compliant
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Introduction
1.3
BLDC Fan Reference Design Targets
Table 1-1. Design Targets
Item
1.4
Requirement
Motor Type
Bi-Phase BLDC Motor
Fan Dimensions (HxLxW)
80mm x 80mm x 25mm
Operating Voltage
12V
Current Rating
0.17V (max.)
Speed
400 to 2400 RPM
Closed Loop Feedback
Yes
Fault Detection
Lock Detection
Other Features
Automatic Restart
Bi-Phase BLDC Motor
In the conventional DC fan motor, the stator of the permanent magnet is composed of two or more
permanent magnet pole pieces, and the rotor is composed of windings that are connected to a mechanical
brush (commutator). The opposite polarities of the energized winding and the stator magnet attract the
rotor, and the rotor will rotate until it is aligned with the stator. Just as the rotor reaches alignment, the
brushes move across the commutator contacts and energize the next winding. As a result, the fan rotor is
rotated continuously.
The brushless DC (BLDC) fan motor, however, is a rotating electric machine in which the stator is a classic
two-phase stator and the rotor has surface-mounted permanent magnets. In this respect, the BLDC fan is
equivalent to a reverse-conventional DC fan; the current polarity is altered by the electrical commutator
instead of mechanical brushes. The BLDC has no brushes on the rotor and the commutation is performed
electronically at certain rotor positions. An example of a BLDC fan motor is illustrated in Figure 1-1.
Figure 1-1. Bi-Phase BLDC Fan Motor Diagram
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Introduction
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Motor Control
Chapter 2
Motor Control
2.1
Commutation
The typical bi-phase BLDC has one pole-pair per phase. Each commutation rotates the rotor by 90 degrees
and four commutation steps complete a mechanical revolution. Each pole-pair is implemented by two
coils, with four coils in total for a bi-phase motor. Energizing a pair of coils, either coil A & C or coil B &
D (shown in Figure 2-1) induces magnetic fields that push the equal polarity rotor magnets away from the
energized coils. At the same time the opposite polarity rotor magnets are pulled toward the coils. When
rotation starts, it is called a commutation step. When the rotor magnetic pole is aligned with the energized
coils, the coils are deactivated and the previously un-energized pair of coils are then energized. As the
magnetic field switches to the next motor position or pole, the inertia of the rotor keeps the motor running.
As a result, two commutation steps move the rotor by 180 degrees or one motor phase. One mechanical
revolution is contributed by four commutation steps.
Figure 2-1. Bi-Phase BLDC Fan Motor
2.2
Rotor Position Control
The key idea to prevent a motor lockup involves rotor position detection. The time to switch the
commutation is critical. Energizing coil-pair too long will kill the rotor inertia and the motor stops running.
This is called motor lockup. Switching the commutation too soon will lose control to the rotor and
eventually stall the motor. The rotor position in this design is determined by a hall sensor which will
respond to the change in magnetic field. Hall sensor output toggles when the magnetic field changes its
polarity. Positioned between the coils at 45 degrees to the stator coils, as shown in Figure 2-1, the hall
sensor can effectively detect the rotor position. In this case, the hall sensor outputs toggle when the rotor
magnets are aligned to the coils. Commutation will switch at this time from one coil-pair to the next.
DRM088, Rev. 0
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Motor Control
2.3
Commutation Waveforms
In general, in a bi-phase motor design, alternate coils are tied together and give a single connection to the
driver. In this design, the driver connection for coil A and coil C is called L1 (see Figure 2-1). Similarly,
the driver connection for coil B and coil D is called L2. Driving to either of the connections will energize
a coil-pair. The commutation waveform is shown in Figure 2-2. The coil driving period is aligned with the
hall sensor output. When the sensor outputs toggle, coil driving is stopped, and the coils are de-energized
for a period of time before the next coil-pair is energized.
90o of rotation
Figure 2-2. Bi-Phase BLDC Motor Commutation Waveform
2.4
Speed Control Mechanism
Motor speed is normally defined as the mechanical Round Per Minute (rpm). In electrical terms, one
commutation contributes to 90 degrees of a revolution. Four commutation cycles complete one revolution
of the motor. Thus, control of the time taken per commutation can effectively control the overall speed of
the motor.
There are two methods to control the speed of the motor: one is called phase on/off delay time control
method, and the other is called PWM control method.
The phase on/off delay time control method is used to adjust the off time at phase switching. The rotation
speed can be adjusted by the length of the off time. The off time is inversely proportional to the energy
provided to the motor. That is, the longer the off time, the less energy is supplied to the stator coils, which
results in a lower speed of the motor. There is one condition that must be satisfied: it needs to be
synchronized to the feedback signal from the hall sensor (i.e. the commutation). The commutation
waveform is shown in Figure 2-3 to illustrate on the phase on/off delay time control method.
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Motor Control
Figure 2-3. Commutation Waveform using Phase On/Off Delay Time Control Method
Although the implementation of this speed control method is relatively simple, there are some
disadvantages in this method, such as the lower accuracy and higher acoustic noise level. Therefore, it may
not fit for the high-end motor system requirement. The accuracy of this type of the speed control method
is around ±10%, which depends on the maximum speed of BLDC, the maximum bus speed of the MCU,
and the number of bit in the timer. For example, if we drive the higher speed of the BLDC fan with the
lower speed of the MCU with a lower resolution timer, lower accuracy of the speed will occur. The PWM
control method is a better alternative for providing higher accuracy and a lower acoustic noise motor
system.
For the PWM control method, the speed is controlled by changing the duty cycle of the PWM. This drives
the two winding coils in the BLDC fan independently instead of changing the off-time period. The two
winding coils are turned on alternately, but the voltage of the coil is controlled by the duty cycle of the
PWM drive signal. The PWM frequency is a major design consideration. The PWM frequency can be
between 18 kHz to 60 kHz typically.
The PWM frequency range is chosen based on acoustic noise and efficiency. The acoustic noise will occur
if the PWM frequency is falling into the audible range of the human ear. In this method, the PWM
frequency should be set above 18 kHz, which is higher than the audible range of the human ear. This means
that the fan can be operated in a quieter manner. Plus, the use of a higher PWM frequency will also be more
efficient. Because the high speed PWM (18 kHz – 60 kHz) is much higher than the commutation period,
the current ripple is smaller. This is because the averaged DC voltage that is applied in the winding coil is
more stable when compared to the phase on/off time delay method. Figure 2-4 illustrates on the PWM
control method. In this reference design, PWM control method is demonstrated to control the BLDC Fan
speed.
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Motor Control
Figure 2-4. Commutation Waveform using PWM Control Method
2.5
Motor Startup
In this DC fan application, it is desirable to only allow the motor to operate uni-directionally, allowing the
airflow to the target system to always be in one direction. With the bi-phase motor design, it is difficult to
guarantee the direction of rotation. Commutation order or the coil energizing sequence is the same for both
directions of rotation. The rotor position or axis must initially be known in order to guarantee the direction
of rotation.
When the first commutation step is activated where the adjacent coil-pair to the initial axis is energized,
the rotor starts to move. Since the adjacent coil-pairs are connected together and energized at the same
time, there are equal pulling/pushing forces induced on the rotor in both directions. There is a chance for
the rotor to startup in either direction. It is necessary to monitor the initial direction of rotation. If the
direction is not correct, the motor must be locked back to the startup axis again, and the commutation step
must be repeated.
The direction of rotation can be detected by the hall sensor output. If the initial rotor axis is known, the
output edge polarity, rising edge or falling edge, determines the direction of rotation. In the modern
bi-phase motor design, the direction of rotation is normally defined by the manufacturer. The stator design
is not symmetric, so the motor will have a high tendency to rotate in one direction than the other. However,
the direction of rotation cannot be guaranteed without proper monitoring techniques in place.
2.6
Fault Detection and Protection
Motor fault is identified when the rotor is not moving, which is normally the case when the rotor is
jammed, which may be caused by blocked airflow. During each commutation step, the hall sensor output
is monitored. If it is not toggled within a defined duration (which is software configurable), commutation
sequence is terminated and all coils are de-energized. A “rotor locked” signal is then fed back and sent to
the external control system via the PWM 4-wire “Sense” pin.
Given a defined duration (which is also software configurable), the fan system goes through an automatic
restart sequence to re-initialize the whole fan system first and then to re-start the fan.
DRM088, Rev. 0
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Motor Control
2.7
Use of Table Look-Up (TLU) and Closed Loop Speed Control
Mechanism
In this reference design, Table Look-Up (TLU) is implemented so the end user can change their fan speed
profile instantly by reprogramming the TLU inside the built-in MCU flash memory. Based on the same set
of hardware, different behavior of BLDC fans can be tailor made via different TLU stored in the flash
memory in order to meet various end customer requirements.
To implement the TLU, the MCU first reads the DC input voltage via a ADC pin. It then converts the DC
voltage into a digital value. By the TLU, the digital value then points to a pre-defined output fan speed
(stored in the TLU) and the MCU changes the duty cycle of the PWM according to the pre-defined output
fan speed to alter the actual BLDC fan speed.
In order to increase the precision of the BLDC fan speed, a closed loop system is used. First, the actual fan
speed is monitored by the hall signal from time to time. The reading is then fed back and compared to the
pre-defined output fan speed stored in the TLU. If the actual fan speed is faster or slower than the
pre-defined speed, the duty cycle of the PWM will be adjusted according to the result from the comparison.
2.8
Input Source Options
In this reference design, there are four types of speed input options that can be configured by:
• A DC voltage source varied by input voltage via voltage divider (Jumper P4, Pin1 connected to
Pin2)
• A DC voltage which is varied through thermal sensor depending on temperature (Jumper P4, Pin2
connected to Pin3)
• A DC voltage generated through VR circuitry (Jumper P6, Pin1 connected to Pin2)
• A PWM signal generated from an external source either goes through a DAC circuitry to convert
the PWM signal into a DC voltage (Jumper P6, Pin2 connected to Pin3) or directly connects to the
MCU KBI pin to measure the PWM signal and then calculate the PWM input duty cycle for fan
speed.
It consumes quite a lot of MCU resources calculated in the PWM input duty cycle. However, it can save
the cost of DAC circuitry on the PCB.
In this reference design, the PWM input source is chosen as it is most commonly used in the BLDC fan
application, and the DAC circuitry is implemented for the PWM input signal.
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Motor Control
DRM088, Rev. 0
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Freescale Semiconductor
Implementation
Chapter 3
Implementation
3.1
Block Diagram
The block diagram of the DC fan design is illustrated in Figure 3-1. A 12 V low cost bi-phase BLDC motor
is used in this application. The MCU performs alternate outputs to the two NPN transistors that drive the
motor coils. An open drain output hall sensor is required, and it is positioned close to the rotor. The device
responds to magnetic field changes during the motor operation, digitizing output feedback of the rotor
position to the MCU for close loop motor control and fault detection. A 5 V external driven PWM signal
(based on the Intel 4-Wire PWM Controlled Fans Specification Rev. 1.2) feeds into the on board DAC
circuit via the 4-wire fan cable connector, illustrated in Figure 3-2. This depends on the duty cycle of the
PWM input signal and should be converted to an DC voltage and measured by ADC1P2 (Pin PTA2) to
check the voltage level. In a faulty situation such as motor jam, PTA4 is driven low and the “sense” pin
from the 4-wire fan cable connector receives a logic low signal to alert the system that the rotor is locked.
12V
VOLTAGE REGULATOR
HALL SENSOR
PTA5
VDD
PTA0
PTA4
PTA1
PTA2
4-WIRE FAN
CONNECTOR
“Sense” signal
DAC
“Control” signal
MC9S08QD4
Figure 3-1. MC9S08QD4 DC Fan Design Block Diagram
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21
Implementation
ADC1P2/
PTA2
5V, 21-28 kHz PWM
input Command
(Duty Cycle
0%-100%)
220nF
Figure 3-2. On Board DAC Block Diagram
3.2
Hardware Resources
In this application, the low cost MC9S08QD4 MCU is used. The device has two built-in 16-bit modulo
timers. Timer 2 channel 0 (pin PTA5) is used to monitor the hall sensor signal by enabling the input capture
mode. It is triggered by both edges setting, An interrupt will be generated if the hall sensor signal goes
from either “0” to “1” or “1” to “0”. Commutation switches from one coil-pair to the next coil-pair to keep
the motor moving. On the other hand, timer 1 channel 0 (pin PTA0) and channel 1 (pin PTA1) are used to
drive the L1 and L2 PWM output signals by enabling the edge-aligned PWM mode.
A 10-bit ADC channel (pin PTA2) is used to measure the DC voltage generated by the on-board DAC
circuit from the PWM input signal. It then converts it to a digitized value to pass it to the TLU. This gets
the target fan speed information. In this application ADC will update the fan speed information every 128
ms by setting the interrupt period in the programmable real time interrupt (RTI) module.
3.3
Control Loop
Figure 3-3 shows the firmware control loop flow chart. The hall sensor output is continuously monitored
for trigger signals within a defined time. A motor fault condition occurs when there are no trigger signals
and the firmware goes into the auto-stop and auto-start sequence. First, commutation is stopped. All
interrupts are disabled. “Lock” signal is sent out to “Sense” pin. It then waits for a configurable pre-defined
period, in this case, 5 seconds before it goes into the restart sequence and tries to restart the fan.
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Freescale Semiconductor
Implementation
The target PWM period (pre-stored in the TLU) is based on the input PWM duty cycle reading from the
4-wire fan cable connector. It is updated every 128 ms. On each 90 degrees rotation of the rotor (one
commutation step), the actual PWM period is compared with the target PWM period. If they are different,
the output PWM duty cycle is changed according to the fan speed comparison. For example, if the actual
fan speed is faster than the target fan speed, the output PWM duty cycle shall be reduced in order to slow
down the fan speed, which allows it to have a better match with the target fan speed. As a result, the actual
PWM period will gradually change towards the target PWM period.
Start
A
N
Initialization
Time
Out?
N
Hall
Edge?
Y
Wait for
Auto-Start
Is Hall
High?
Y
Drive L1 / L2
N
Y
Drive L1
Send “lock”
signal to SENSE
Read Speed
from CONTROL
Drive L2
Read Actual
Speed
Enable Interrupt
Time
Out?
Y
De-energize
L1 & L2
Send Actual
Speed to SENSE
N
Speed Command
vs Actual Speed
A
Disable Interrupt
Adjust PWM
Duty Cycle
Figure 3-3. Firmware Control Loop Flowchart
3.4
Fan Speed Response to PWM Control Input Signal
Based on the Intel 4-Wire PWM Controlled Fans Specification Rev. 1.2, the PWM input is delivered to the
fan through the “Control” signal and pin 4 of the cable wire. Fan speed response to this signal shall be a
continuous and monotonic function of the duty cycle of the signal, from 100% to the minimum specified
RPM. The fan Round Per Minute (RPM, as a percentage of maximum RPM) must match the PWM duty
cycle within ±10%. If no control signal is present, the fan will operate at maximum RPM. See Figure 3-4.
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Implementation
Figure 3-4. PWM Control Input Signal vs. Fan Speed
For all duty cycles less than the minimum duty cycle, the RPM must not be greater than the minimum
RPM. There are three recommended solutions to handle PWM duty cycles that are less than the minimum
operational RPM (as a percentage of maximum). These are based on the Intel 4-Wire PWM Controlled
Fans Specification Rev. 1.2.
In a Type A implementation, the fan will run at minimum RPM for all PWM duty cycle values less than
minimum duty cycle. The minimum fan speed is controlled by design and cannot be overridden by the
external fan speed controller.
In a Type B implementation, the fan will run at minimum RPM for all non-zero PWM duty cycle values
less than minimum duty cycle and turn off the motor at 0% PWM duty cycle.
In Type C implementation, the fan will stop running when the current to the motor windings is insufficient
to support commutation. The fan will not be damaged from this. The fan would also turn off the motor at
0% PWM duty cycle input.
In this application, Type A implementation is used. However, Type B and Type C solutions can also be
implemented easily by using the same set of hardware. All it needs is to modify the Table Look-Up. It is
one of the advantages of implementing the DC Fan application using flash based MCU like the
MC9S08QD4. The minimum PWM duty cycle is set to 20%, and the minimum operational RPM is set to
18%. See Figure 3-5 for the PWM control input signal vs. fan speed from the application measurement.
DRM088, Rev. 0
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Freescale Semiconductor
Implementation
Fan Speed vs Input PWM Duty Cycle
Fan Speed %
110%
100%
90%
Fan Speed %
80%
70%
60%
50%
40%
30%
20%
10%
95
%
10
0%
90
%
85
%
80
%
75
%
70
%
65
%
60
%
55
%
50
%
45
%
40
%
35
%
30
%
25
%
20
%
15
%
10
%
5%
0%
0%
Input PWM Duty Cycle
Figure 3-5. Measured PWM Control Input Signal vs. Fan Speed
In this application, the measured fan RPM (as a percentage of maximum RPM) matches the PWM duty
cycle within ±2%. If no control signal is present, the fan will operate at maximum RPM (around 2300
RPM), as there is an external pull-up to pull high the PWM input when the signal line is floating. See
Table 3-1 for the measurement data.
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Implementation
Table 3-1. Measurement of PWM Control Input Signal and Fan Speed (RPM)
Input PWM Measured
Duty Cycle DC Voltage
0%
0.0147
1%
4.744
5%
4.512
10%
4.2514
15%
3.9832
20%
3.7191
25%
3.4594
30%
3.2037
35%
2.9515
40%
2.7015
45%
2.4549
50%
2.2124
55%
1.9731
60%
1.7366
65%
1.503
70%
1.2714
75%
1.0436
80%
0.8182
85%
0.596
90%
0.3761
95%
0.1601
100%
0.0147
ADC Fan Speed % Target RPM Actual RPM
Readout
0
100.0%
2310
2322
248
18.3%
426
425
238
18.3%
426
424
222
18.3%
426
425
210
18.2%
426
423
196
18.3%
426
424
182
19.5%
446
452
168
20.4%
473
474
154
20.8%
488
484
142
23.0%
528
534
128
24.7%
574
575
116
34.9%
816
811
104
41.1%
942
954
92
46.8%
1075
1087
78
54.8%
1267
1272
66
66.3%
1546
1539
54
76.1%
1744
1766
42
85.9%
1961
1995
30
95.9%
2193
2226
18
99.1%
2259
2300
8
99.8%
2290
2316
0
100.0%
2310
2322
Error %
-0.5%
0.3%
0.5%
0.4%
0.9%
0.5%
-1.4%
-0.2%
0.9%
-1.1%
0.0%
0.7%
-1.2%
-1.1%
-0.4%
0.5%
-1.3%
-1.7%
-1.5%
-1.8%
-1.1%
-0.5%
DRM088, Rev. 0
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Freescale Semiconductor
Appendix A
Schematic
5
3
4
3
1
2
1K
1
1PMT5929BT1
P2
COM
L1
L2
GND
HALL
1
2
3
4
5
Z2
D
5V
FMMT619
5V
2
12V
2
1
R2
1
Q1
D
2
1
1
R4
12V
L1
L2
GND
HALL
U1
2
HALL
SENSE
5V
GND
BLDC FAN CONNECTOR
GND
3
1
1
PA5/IRQ/RST
PA4/BKGD/MS
VDD
VSS
PA0/KBI0/AD0
PA1/KBI1/AD1
PA2/KBI2/AD2
PA3/KBI3/AD3
8
7
6
5
OUT1
OUT2
PWM
R10
P4
2
7K5(1%)
1
2
3
1
9S08QD4DN
2
TH1
12V
1K
1
1PMT5929BT1
2
Z3
1
2
3
4
R3
Q2
2
FMMT619
DRM088, Rev. 0
HALL
SENSE
5V
GND
2
C
1-2: THERMAL CONTROL
2-3: VOLTAGE CONTROL
10K
GND
10K
C
P5
1
2
3
4
IRQ
BKGD
5V
GND
1
GND
R11
ICP CONNECTOR
2
10K(1%)
GND
1
1
R5
3
4K7(1%)
12V
5V
R12
5V
7K2(1%)
2
Q3
2
1
NDS7002A
2
LL4148
GND
12V_IN
1
1
D1
C3
2
560
0.1uF
1
B
GND
12V
SENSE
CONTROL
2
R1
1
2
3
4
1
P1
1
1
2
2
GND
B
4-WIRE FAN CONNECTOR
C1
Z1
1uF/10V
2
ZMM5231B
C2
2u2F/25V
2
5V
5V
GND
1
R14
1
1-2: INTERNAL CONTROL
2-3: EXTERNAL CONTROL
2
20K
1
R7
2
27K
R8
2
4K7
1-2: VOLTAGE DETECTION
2-3: DUTY CYCLE DETECTION
3
R6
1
2
1
INT
3
2
EXT
1
2
1
VR1
2
33K
7.5K(1%)
2
10K
A
3
3
1
1
2
P3
R9
1
A
R13
P6
1
Q4
1K2
MMBT4401
C4
2
220nF
2
GND
GND
GND
DESCRIPTION: MC9S08QD4 BLDC FAN DEMO BOARD
5
4
3
REV: 1.0
2
DATE: 20/12/07
SHEET 01 of 01
1
Schematic
27
Schematic
DRM088, Rev. 0
28
Freescale Semiconductor
Program Listing
Appendix B
Program Listing
;**************************************************************
;
; (c) copyright Freescale Semiconductor. 2007
; ALL RIGHTS RESERVED
;
;**************************************************************
;**************************************************************
;* DC Fan Coding for 9S08QD4
;*
;* Author: Eddie Ng
;* Date: Dec 2007
;*
;* PTA0/KBI0/AD0 L1 Output
;* PTA1/KBI1/AD1 L2 Output
;* PTA2/KBI2/AD2 DC Voltage Input
;* PTA3/KBI3/AD3 Unused
;* PTA4/BKGD/MS Sense Signal Output
;* PTA5/IRQ /RST Hall Signal Input
;*
;**************************************************************
; Include derivative-specific definitions
INCLUDE 'derivative.inc'
INCLUDE 'MC9S08QD4.inc'
;
; export symbols
;
XDEF _Startup
ABSENTRY _Startup
; variable/data section
ORG
Z_RAMStart
Flag
ds.b
1
Lock_Cnt
ds.b
1
Start_Cnt
ds.b
1
Sw_Cnt
ds.b
1
Tmp_ADCH
ds.b
1
Tmp_ADCL
ds.b
1
Tmp_FADCH
ds.b
1
Tmp_FADCL
ds.b
1
Tmp_CntH
ds.b
1
Tmp_CntL
ds.b
1
Tmp_OldH
ds.b
1
Tmp_OldL
ds.b
1
Tmp_Speedv ds.b
1
Tmp_OldADCH ds.b
1
Tmp_OldADCL ds.b
1
Tmp_CCH
ds.b
1
Tmp_CCL
ds.b
1
Tmp_AC
ds.b
1
Tmp_BC
ds.b
1
Tmp_OdHH
ds.b
1
Tmp_OdHL
ds.b
1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Insert your data definition here
Fan Status Flag
Lock Counter
Startup Counter
Software Counter
ADC value (8-bit conversion)
ADC value (8-bit conversion)
ADC value (8-bit conversion)
ADC value (8-bit conversion)
16-bit Counter New Upper byte
16-bit Counter New Lower byte
16-bit Counter Old Upper byte
16-bit Counter Old Lower byte
Speed + / -
; 16-bit Counter Old Upper byte
; 16-bit Counter Old Lower byte
DRM103, Rev. 0
Freescale Semiconductor
29
Program Listing
Tmp_OdLH
Tmp_OdLL
ds.b
ds.b
ORG
Tmp_Flag
ds.b
Q1_Flag
equ
Q2_Flag
equ
Fan_Lock
equ
Fan_Start
equ
Hall_Sensor equ
Q1
equ
Q2
equ
HALL
equ
1
1
RAMStart
1
0
1
2
3
4
0
1
5
;
; code section
;
ORG
ROMStart
; 16-bit Counter Old Upper byte
; 16-bit Counter Old Lower byte
; Insert your data definition here
;
;
;
;
;
;
;
;
Set if Q1 On flag
Set if Q2 on flag
Set if fan is locked
Set if fan startup OK
Set if hall signal present
Q1 connected in PTA0
Q2 connected in PTA1
Hall connected in PTA5
;**************************************************************
;* ICS Configure - Device is pre-trim to 16MHz ICLK frequency *
;* TRIM value are stored in $3FFA:$3FFB
*
;**************************************************************
ics_trim:
lda
NV_FTRIM
; Pre-trimed ICS = 16MHz
and
#%000000001
sta
ICSSC
; $FFAE -> ICSSC
lda
NV_ICSTRM
sta
ICSTRM
; $FFAF -> ICSTRIM
mov
#ICS_DIV_1, ICSC2 ; Use ICS/1 bus = 16MHz
rts
;------------------------------------------------------;Config System
;------------------------------------------------------sys_config:
lda
#(mSOPT1_COPT|mSOPT1_BKGDPE|mSOPT1_STOPE)
sta
SOPT1
; SOPT, COP disabled, Debug pin enable
lda
#%00111101
sta
SPMSC1
; Enable LVD (+ logic + Int) & bandgap,
LVR enable
sta
lda
#%01010100
SRTISC
ldhx
sthx
sthx
#$0078
TPM1C0VH
TPM1C1VH
; 128ms,
32kHz=bus/250000, RTI int. enable
; Initialize PWM DC from a slow start
; Store value to TPM1C0VH:L
; Store value to TPM1C1VH:L
; Timer Input Capture testing
----------------------------------------------------------------mov
#%01001100, TPM2C0SC
; Timer2 Ch0 config
;
||||||||
; (int enable, icap, rising & falling trigger)
;
||||||++-- 00 (unused)
;
|||||+---- ELSnA [ELSnB ELSnA: icap(01)rising/(10)falling/(11)both
;
||||+----- ELSnB ocmp(01)toggle/(10)clear/(11)set, PWMs(10)High-ture/(x1)Low-ture
;
|||+------ MSnA [MSnB:MSnA]: xx=port, 00=icap, 01=ocmp, 1x=edge-aligned
;
||+------- MSnB 1x=edge-aligned if CPWMS=0, xx=center-aligned if CPWMS=1
DRM103, Rev. 0
30
Freescale Semiconductor
Program Listing
;
;
|+-------- CHnIE (Chx int enable) 0=disable, 1=enable
+--------- CHnF (Chx int flag)
; Timer Overflow testing
----------------------------------------------------------------------; CPWMS=0, TPMnMOD in the range $0001 to &FFFF
ldhx #$0140
; $0140=320 (125nS*320=40us), PWM Freq=1/40us=25kHz
sthx TPM1MOD
; TPM1 clock[01]= 1/8MHz = 125nS, Period = 125nS*320=40us
mov
#%00001011, TPM2SC
; Timer2 Overflow disable
, clk = 1MHz
;
;
;
;
;
;
;
;
;
||||||||
; (int enable, tof, bus clock, div by 1) & reset timer
|||||||+-- PS0 [PS2:PS1:PS0]:
||||||+--- PS1 000=/1, 001=/2, 010=/4, 011=/8
|||||+---- PS2 100=/16, 101=/32, 110=/64, 111=/128
||||+----- CLKSA [CLKSB:CLKSA]: 00=TPM disable, 01=Bus Clock,
|||+------ CLKSB 10=bus clock for PLL/FLL OR OSC/2, 11=Ext Clock(Max bus clock/4)
||+------- CPWMS 0=Normal(icap/ocmp/edge-aligned PWM), 1=center-aligned PWM
|+-------- TOIE (TOF int enable) 0=disable, 1=enable
+--------- TOF (Timer overflow flag)
; ADC testing
---------------------------------------------------------------------------------ldhx #$0020
; for 10-bit (20,40,60,80,A0,C0,E0)
sthx ADC1CV
; Store value to compare value register
mov
;
;
;
;
;
;
#%01000010, ADC1SC1
; ADC status & control reg. 1
||||||||
; (int Enable, One converison mode, CH2)
|||+++++-- ADCH: CH0=00000, CH1=00001, CH2=00010, CH3=00011, CH26=11010
|||
CH27=11011, VREFH:11101, VREFL=11110, Module Disable=11111
||+------- ADCO Modes: 0=one converison, 1=Continuous converison
|+-------- AIEN (ADC int enable) 0=disable, 1=enable
+--------- COCO (Converison complete flag)
; ---------- Same Channel ----------------------------------------------------mov
#%01010000, ADC1SC2
; ADC status & control reg. 2
||||||||
; (HW trigger, CMP Disable, trigger if >or= )
||||++++-- 0000 (Unused, bit0 & bit1 must be 00)
|||+------ ADFGT (Compare function greater than)
|||
0=trigger if CH < compare level, 1=trigger if CH >or= compare level
||+------- ACFE (Compare function) 0=disable, 1=enable
|+-------- ADTRG (Trigger) 0=SW trigger, 1=HW trigger
+--------- ADACT (flag) 1=conversion in progress
mov
#%01110000, ADC1CFG
; ADC configuration reg
||||||||
; (High speed, i/p_clk/1, Long sample, 8-bit, bus clock)
|||||||+-- ADICLK0 [ADICLK1:ADICLK0]:
||||||+--- ADICLK1 00=Bus, 01=Bus/2, 10=Alternate clock(xx), 11=Async clock
|||||+---- MODE0 [MODE1:MODE0]:
||||+----- MODE1 00=8-bit, 01=reserved, 10=10-bit, 11=reserved
|||+------ ADLSMP (Long sample time) 0=Short sample, 1=Long sample
||+------- ADIV0 [ADIV1:ADIV0]:
|+-------- ADIV1 00=i/p_clk/1, 01=i/p_clk/2, 10= i/p_clk/4, 11=i/p_clk/8
+--------- ADLPC (Long power) 0=High speed, 1=Low power
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
mov
#(mAPCTL1_ADPC2), APCTL1
; Pin control 1 reg. (ADPC2) & (CH2) Enable
DRM103, Rev. 0
Freescale Semiconductor
31
Program Listing
rts
; ----------------------------------------------------------------------------; Subroutine <80ms Delay>
; Bus Clock = 8MHz, 1 Cycle=0.125uS
; In
: <nil>
; Out
: <nil>
; Call
: <nil>
; ----------------------------------------------------------------------------Delay_80ms:
ldx #$FF
; [2]256
Delay_Yms_X
lda #$FA
; [2]250
Delay_Yms_A
sta $FFFF
; [4] clear COP
nop
; [1]
nop
; [1]
nop
; [1]
dbnza Delay_Yms_A
; [3] 10*{A}=10A
dbnzx Delay_Yms_X
; [3] 10A*{X}+2+3=10AX+2+3
rts
; [3]
*
*
*
*
*
*
*
;Total= {[2]+[2]+10AX+[3]}*Bus Cycle
;Total= [7+(10*256*250)]*0.125uS = 80mS
; ----------------------------------------------------------------------------; Subroutine <50ms Delay>
; Bus Clock = 8MHz, 1 Cycle=0.125uS
; In
: <nil>
; Out
: <nil>
; Call
: <nil>
; ----------------------------------------------------------------------------Delay_50ms:
ldx #$A0
; [2]160
Delay_Y1ms_X
lda #$FA
; [2]250
Delay_Y1ms_A
sta $FFFF
; [4] clear COP
nop
; [1]
nop
; [1]
nop
; [1]
dbnza Delay_Y1ms_A
; [3] 10*{A}=10A
dbnzx Delay_Y1ms_X
; [3] 10A*{X}+2+3=10AX+2+3
rts
; [3]
*
*
*
*
*
*
*
;Total= {[2]+[2]+10AX+[3]}*Bus Cycle
;Total= [7+(10*160*250)]*0.125uS = 50mS
;
;
;
;
;
;
----------------------------------------------------------------------------Subroutine <5ms Delay>
Bus Clock = 8MHz, 1 Cycle=0.125uS
In
: <nil>
Out
: <nil>
Call
: <nil>
*
*
*
*
*
*
DRM103, Rev. 0
32
Freescale Semiconductor
Program Listing
; ----------------------------------------------------------------------------- *
Delay_5ms:
ldx #$50
; [2]80
Delay_Y2ms_X
lda #$32
; [2]50
Delay_Y2ms_A
sta $FFFF
; [4] clear COP
nop
; [1]
nop
; [1]
nop
; [1]
dbnza Delay_Y2ms_A
; [3] 10*{A}=10A
dbnzx Delay_Y2ms_X
; [3] 10A*{X}+2+3=10AX+2+3
rts
; [3]
;Total= {[2]+[2]+10AX+[3]}*Bus Cycle
;Total= [7+(10*80*50)]*0.125uS = 5mS
; Program start here after POR
_Startup:
ldhx
#RAMEnd+1
; initialize the stack pointer
txs
mainLoop:
sei
nop
jsr
jsr
; Mask interrupts
ics_trim
sys_config
; Fan Start here
Fan_Restart:
sei
clr
Flag
clr
Lock_Cnt
clr
Start_Cnt
clr
Sw_Cnt
clr
Tmp_OldH
clr
Tmp_OldL
clr
Tmp_OldADCH
clr
Tmp_OldADCL
clr
Tmp_AC
clr
Tmp_BC
lda
#%00000000
sta
PTAD
lda
#%00000011
sta
PTADD
bset Q1,PTAD
jsr
Delay_50ms
jsr
Delay_50ms
brset HALL,PTAD,Q2_On
jsr
Delay_50ms
brset HALL,PTAD,Q2_On
bra
Fan_Reverse
; Default PWM in TPM1CH0 and TPM1CH1 are enable
; Clear all flag
; Set Q1 and Q2 off first
; Default drive L1 first
; Read Hall status
Q2_On:
bclr
Q1,PTAD
; Q1 off
DRM103, Rev. 0
Freescale Semiconductor
33
Program Listing
bset Q2,PTAD
; Q2 on
jsr
Delay_50ms
brclr HALL,PTAD,Speed_Control
jsr
Delay_50ms
brclr HALL,PTAD,Speed_Control
bra
Fan_Stop
; Max lock delay in startup = 200ms
Fan_Reverse:
bclr Q1,PTAD
bclr Q2,PTAD
bset Q2,PTAD
jsr
Delay_50ms
jsr
Delay_50ms
brclr HALL,PTAD,Q1_On
jsr
Delay_50ms
brclr HALL,PTAD,Q1_On
bra
Fan_Stop
; Set Q1 and Q2 off first
; Max lock delay in startup = 200ms
Q1_On:
bclr
bset
jsr
brset
jsr
brset
jsr
brset
bra
Q2,PTAD
; Q2 off
Q1,PTAD
; Q1 on
Delay_50ms
HALL,PTAD,Speed_Control
Delay_50ms
HALL,PTAD,Speed_Control
Delay_50ms
HALL,PTAD,Speed_Control
Fan_Stop
Speed_Control:
bset Fan_Start,Flag
cli
; enable interrupts
Control_Loop:
jsr
Delay_50ms
jsr
Delay_50ms
inc
Lock_Cnt
brset 2,Lock_Cnt,Fan_Stop; Max lock delay in run = 200ms
bra
Control_Loop
Fan_Stop:
bclr
bclr
mov
mov
mov
bset
mov
Q1,PTAD
;
Q2,PTAD
#%00000000,TPM1SC ;
#%00001000,TPM1C0SC;
#%00001000,TPM1C1SC;
Fan_Lock,Flag
#$64, Sw_Cnt
Set Q1 and Q2 off first
TPM1 stop
PWM off, Port activte
PWM off, Port activte
; Fan is locked
; Delay 5s = 50ms * 100
Fan_Stop_Delay:
jsr
Delay_50ms
dbnz Sw_Cnt, Fan_Stop_Delay
jmp
Fan_Restart
; Restart Fan
BRA
* ;mainLoop
DRM103, Rev. 0
34
Freescale Semiconductor
Program Listing
;*************************************************************
; Interrupt Service Routine.
*
;*************************************************************
IRQ_ISR:
pshh
bset
pulh
rti
IRQSC_IRQACK, IRQSC
; Clear IRQF flag
LVI_ISR:
pshh
lda
ora
SPMSC1
#%01000000
sta
SPMSC1
; Clear LVDF flag
pulh
rti
KBI_ISR:
pshh
bset
KBISC_KBACK, KBISC
pulh
; Clear IRQF flag
rti
RTI_ISR:
pshh
lda
ora
sta
SRTISC
#%01000000
SRTISC
pulh
; Clear RTIF flag
rti
ADC_ISR:
pshh
lda
sta
lda
sta
brset
bra
DSUB_1: dec
D_rtn:
brset
ldhx
cphx
beq
ADC_FP:
lda
ldhx
tax
lda
sta
lda
inca
ldhx
tax
lda
; RTI need to be enabled for ADHWT
; ADHWT trigger period = 2* RTI period
ADC1RH
Tmp_ADCH
ADC1RL
Tmp_ADCL
0,Tmp_ADCL,DSUB_1
D_rtn
Tmp_ADCL
; 8-bit ADC to 8-bit actual speed lookup table
; Read 8-bit ADC value & clear COCO flag
7, Tmp_AC, ADC_FP
Tmp_OldADCH
Tmp_ADCH
ADC_SP
Tmp_ADCL
#$FD00
,x
Tmp_FADCH
Tmp_ADCL
; point to ADC to PWM Duty Cycle table page H:X=FD00
; point to corresponding speed A=>X
; Read the speed value to Acc
#$FD00
,x
; point to corresponding speed A=>X
; Read the speed value to Acc
DRM103, Rev. 0
Freescale Semiconductor
35
Program Listing
sta
ldhx
sthx
sthx
sthx
lda
ldhx
tax
lda
sta
lda
inca
ldhx
tax
lda
sta
ldhx
sthx
aix
sthx
aix
sthx
mov
mov
bset
inc
brset
bra
AC_Clr: clr
clr
pulh
rti
Tmp_FADCL
Tmp_FADCH
TPM1C0VH
TPM1C1VH
Tmp_CCH
Tmp_ADCL
#$FE00
,x
Tmp_FADCH
Tmp_ADCL
; Store value to TPM1C0VH:L
; Store value to TPM1C1VH:L
; point to ADC to Target RPM Speed table page H:X=FE00
; point to corresponding speed A=>X
; Read the speed value to Acc
#$FE00
; point to corresponding speed A=>X
,x
; Read the speed value to Acc
Tmp_FADCL
Tmp_FADCH
Tmp_OldH
; Store value to Tmp_OldH:L
#2
Tmp_OdHH
#-4
Tmp_OdLH
Tmp_ADCL,Tmp_OldADCL
Tmp_ADCH,Tmp_OldADCH
7, Tmp_AC
Tmp_BC
2, Tmp_BC,AC_Clr
ADC_SP
Tmp_AC
Tmp_BC
ADC_SP:
pulh
rti
T1CH0_ISR:
pshh
lda
and
sta
pulh
rti
T1CH1_ISR:
pshh
lda
and
sta
pulh
rti
T1TOF_ISR:
pshh
lda
and
; TPM1CH0 (pin8)
TPM1C0SC
#%01111111
TPM1C0SC
; clear CH0F in TPM1
; TPM1CH1 (pin7)
TPM1C1SC
#%01111111
TPM1C1SC
; clear CH1F in TPM1
; $FFFF=65535*125nS=8.19mS@8MHz bus if TPM1MOD=$FFFF
TPM1SC
#%01111111
DRM103, Rev. 0
36
Freescale Semiconductor
Program Listing
sta
TPM1SC
pulh
; clear TOF in TPM1
rti
T2CH0_ISR:
pshh
lda
TPM2C0SC
and
#%01111111
sta
TPM2C0SC
bclr Fan_Lock, Flag
clr
Lock_Cnt
ldhx TPM2CNTH
sthx Tmp_CntH
cphx Tmp_OdHH
bhi
ADD_Speed
speed
cphx Tmp_OdLH
blo
LOW_Speed
; TPM2CH0O (pin2) Input Capture
; clear CH0F in TPM2
; Fan unlock
; Clear lock counter
; Hall sensor counter > Target counter e.g. need to increase
Speed_Cont:
lda PTAD
eor #%00000011
sta PTAD
brclr Fan_Start,Flag,All_Off
brset Q1,PTAD,Q1_PWM_On
brset Q2,PTAD,Q2_PWM_On
bra
All_Off
ADD_Speed:
ldhx
aix
sthx
sthx
sthx
lda
sta
bra
TPM1C0VH
#1
TPM1C0VH
TPM1C1VH
Tmp_CCH
#$02
Tmp_Speedv
Speed_Cont
LOW_Speed:
ldhx
aix
sthx
sthx
sthx
lda
sta
bra
TPM1C0VH
#-1
TPM1C0VH
TPM1C1VH
Tmp_CCH
#$01
Tmp_Speedv
Speed_Cont
Q1_PWM_On:
Q2_PWM_Off:
mov
mov
mov
mov
clrx
clrh
sthx
; Toggles PTA0 & PTA1 when interrupt present
; Store value to TPM1C0VH:L
; Store value to TPM1C1VH:L
; Store value to TPM1C0VH:L
; Store value to TPM1C1VH:L
#%00000000,TPM1SC ;
#%00001000,TPM1C1SC;
#%00101000,TPM1C0SC;
#%00001000,TPM1SC ;
TPM1 stop
PWM off, Port activte
PWM On, Port disable
Timer Start
TPM2CNTH
DRM103, Rev. 0
Freescale Semiconductor
37
Program Listing
pulh
rti
Q2_PWM_On:
Q1_PWM_Off:
mov
mov
mov
mov
clrx
clrh
sthx
pulh
rti
#%00000000,TPM1SC ;
#%00001000,TPM1C0SC;
#%00101000,TPM1C1SC;
#%00001000,TPM1SC ;
TPM1 stop
PWM off, Port activte
PWM On, Port disable
Timer Start
TPM2CNTH
All_Off:
clrx
clrh
sthx
pulh
rti
TPM2CNTH
T2TOF_ISR:
pshh
lda
and
sta
; $FFFF=65535*125nS=8.19mS@8MHz bus
TPM2SC
#%01111111
TPM2SC
pulh
; clear TOF in TPM2
rti
SWI_ISR:
pshh
pulh
rti
; return
;**************************************************************
;* spurious - Spurious Interrupt Service Routine.
*
;*
(unwanted interrupt)
*
;**************************************************************
;spurious:
; placed here so that security value
;
NOP
; does not change all the time.
;
RTI
org $FD00
; Table 1
; This table is used for the QD4 BLDC Fan demo type board and PWM Duty Cycle (16 bits)
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
$01,$50,$01,$50,$01,$4C,$01,$48,$01,$44,$01,$40,$01,$3C,$01,$38
$01,$34,$01,$30,$01,$2C,$01,$28,$01,$24,$01,$20,$01,$1C,$01,$18
$01,$14,$01,$10,$01,$0C,$01,$08,$01,$04,$01,$00,$00,$FC,$00,$F8
$00,$F4,$00,$F0,$00,$EC,$00,$E8,$00,$E4,$00,$E0,$00,$DC,$00,$D8
$00,$D4,$00,$D0,$00,$CC,$00,$C8,$00,$C4,$00,$C0,$00,$BD,$00,$BA
$00,$B7,$00,$B4,$00,$B1,$00,$AF,$00,$AD,$00,$AB,$00,$A9,$00,$A7
$00,$A5,$00,$A3,$00,$A1,$00,$9F,$00,$9D,$00,$9B,$00,$99,$00,$97
$00,$95,$00,$93,$00,$92,$00,$91,$00,$90,$00,$8F,$00,$85,$00,$80
$00,$80,$00,$7F,$00,$7F,$00,$7E,$00,$7E,$00,$7D,$00,$7D,$00,$7C
;000-00F
;010-01F
;020-02F
;030-03F
;040-04F
;050-05F
;060-06F
;070-07F
;080-08F
DRM103, Rev. 0
38
Freescale Semiconductor
Program Listing
FCB
FCB
FCB
FCB
FCB
FCB
FCB
$00,$7C,$00,$7B,$00,$7B,$00,$7A,$00,$7A,$00,$79,$00,$79,$00,$79
$00,$79,$00,$78,$00,$78,$00,$78,$00,$78,$00,$78,$00,$78,$00,$77
$00,$77,$00,$77,$00,$77,$00,$76,$00,$76,$00,$76,$00,$76,$00,$76
$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75
$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75
$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75
$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75,$00,$75
;090-09F
;0A0-0AF
;0B0-0BF
;0C0-0CF
;0D0-0DF
;0E0-0EF
;0F0-0FF
org $FE00
; Table 2
; This table is used for the QD4 BLDC Fan demo type board and Target RPM (16 bits)
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
$19,$5D,$19,$5D,$19,$32,$19,$64,$19,$96,$19,$C8,$19,$D2,$19,$DC
$19,$E6,$19,$F0,$19,$FA,$1A,$04,$1A,$0E,$1A,$18,$1A,$68,$1A,$B8
$1B,$08,$1B,$58,$1B,$FA,$1C,$9C,$1D,$3E,$1D,$E2,$1E,$6B,$1E,$F4
$1F,$7D,$20,$08,$20,$D0,$21,$98,$22,$60,$23,$28,$23,$D7,$24,$86
$25,$35,$25,$E4,$27,$5B,$28,$D2,$2A,$49,$2B,$C0,$2D,$00,$2E,$40
$2F,$80,$30,$C0,$32,$00,$33,$1F,$34,$3E,$35,$5D,$36,$7C,$37,$9B
$38,$BA,$39,$D9,$3A,$F8,$3C,$92,$3E,$2C,$3F,$C6,$41,$60,$42,$FA
$44,$94,$46,$2E,$47,$C8,$49,$62,$4B,$00,$4B,$00,$5C,$F8,$66,$00
$66,$00,$68,$00,$68,$00,$6A,$80,$6A,$80,$6C,$80,$6C,$80,$6F,$00
$6F,$00,$71,$80,$71,$80,$75,$00,$75,$00,$78,$00,$78,$00,$78,$00
$78,$00,$7C,$00,$7C,$00,$7C,$00,$7C,$00,$7C,$00,$7C,$00,$80,$00
$80,$00,$80,$00,$80,$00,$83,$80,$83,$80,$83,$80,$83,$80,$83,$80
$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80
$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80
$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80
$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80,$89,$80
;000-00F
;010-01F
;020-02F
;030-03F
;040-04F
;050-05F
;060-06F
;070-07F
;080-08F
;090-09F
;0A0-0AF
;0B0-0BF
;0C0-0CF
;0D0-0DF
;0E0-0EF
;0F0-0FF
;**************************************************************
;*
Interrupt Vectors
*
;**************************************************************
ORG
$FFD0
DC.W RTI_ISR
; RTI
ORG
DC.W
$FFD8
ADC_ISR
; ADC
ORG
DC.W
$FFDA
KBI_ISR
; KBI
ORG
DC.W
$FFEA
T2TOF_ISR
; T2 Timer Overflow
ORG
DC.W
$FFEE
T2CH0_ISR
; T2 Ch0 Interrupt
ORG
DC.W
$FFF0
T1TOF_ISR
; T1 Timer Overflow
ORG
DC.W
$FFF2
T1CH1_ISR
; T1 Ch1 Interrupt
ORG
DC.W
$FFF4
T1CH0_ISR
; T1 Ch0 Interrupt
ORG
DC.W
$FFF8
IRQ_ISR
; IRQ
DRM103, Rev. 0
Freescale Semiconductor
39
Program Listing
ORG
DC.W
$FFFA
LVI_ISR
; LVI
ORG
DC.W
$FFFC
SWI_ISR
; SWI
ORG
DC.W
$FFFE
_Startup
; Reset
;**************************************************************
;*
End Program
*
;**************************************************************
DRM103, Rev. 0
40
Freescale Semiconductor
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DRM088
Rev. 0
06/2008