Features • Low-voltage Operation • • • • • • • • • • • • – 1.8V (VCC = 1.8V to 3.6V) – 2.5V (VCC = 2.5V to 5.5V) Internally Organized 131,072 x 8 Two-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 400 kHz (1.8V) and 1 MHz (5V, 2.5V) Clock Rate Write Protect Pin for Hardware and Software Data Protection 256-byte Page Write Mode (Partial Page Writes Allowed) Random and Sequential Read Modes Self-timed Write Cycle (5 ms Typical) High Reliability – Endurance: 1,000,000 Write Cycles/Page – Data Retention: 40 Years 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead Ultra Thin Small Array (SAP), and 8-ball dBGA2 Packages Die Sales: Wafer Form, Tape and Reel and Bumped Die Description Two-wire Serial EEPROM 1M (131,072 x 8) AT24C1024B with Two Device Address Inputs The AT24C1024B provides 1,048,576 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to four devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions. 8-lead PDIP 8-lead SOIC NC A1 A2 GND 1 2 3 4 8 7 6 5 8-lead dBGA2 VCC WP SCL SDA 8 1 7 2 6 3 5 4 NC A1 A2 GND Bottom View VCC WP SCL SDA NC A1 A2 GND 8 7 6 5 1 2 3 4 VCC WP SCL SDA 8-lead TSSOP NC A1 A2 GND 8 7 6 5 1 2 3 4 VCC WP SCL SDA 8-lead Ultra-Thin SAP VCC WP SCL SDA 8 1 7 2 6 3 5 4 NC A1 A2 GND Bottom View Rev. 5194F–SEEPR–1/08 Table 0-1. Pin Configurations Pin Name Function A1 Address Input A2 Address Input SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect 1. Absolute Maximum Ratings* Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA 2 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Figure 1-1. Block Diagram VCC GND WP START STOP LOGIC SERIAL CONTROL LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W EN H.V. PUMP/TIMING COMP LOAD DATA RECOVERY INC DATA WORD ADDR/COUNTER Y DEC X DEC SCL SDA EEPROM SERIAL MUX DOUT/ACK LOGIC DIN DOUT 2. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/ADDRESSES (A1/A2): The A1, A2 pin is a device address input that can be hardwired or left not connected for hardware compatibility with other AT24Cxx devices. When the A1, A2 pins are hardwired, as many as four 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the A1/A2 pins are left floating, the A1/A2 pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the A1/A2 pin to GND. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a write operation creates a software write-protect function. 3 5194F–SEEPR–1/08 3. Memory Organization AT24C1024B, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address. Table 3-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A1, SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. Table 3-2. DC Characteristics Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol Parameter VCC1 Supply Voltage VCC2 Supply Voltage ICC Supply Current VCC = 5.0V ICC Supply Current VCC = 5.0V ISB1 Standby Current ISB2 Standby Current ILI Input Leakage Current VIN = VCC or VSS ILO Output Leakage Current VOUT = VCC or VSS VIL Input Low Level(1) VIH (1) Input High Level VOL1 Output Low Level VCC = 1.8V Output Low Level VCC = 3.0V VOL2 Note: Test Condition VCC = 1.8V VCC = 3.6V VCC = 2.5V VCC = 5.5V Min Typ Max Units 1.8 3.6 V 2.5 5.5 V READ at 400 kHz 2.0 mA WRITE at 400 kHz 3.0 mA 1.0 µA 3.0 µA 2.0 µA 6.0 µA 0.10 3.0 µA 0.05 3.0 µA –0.6 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V IOL = 0.15 mA 0.2 V IOL = 2.1 mA 0.4 V VIN = VCC or VSS VIN = VCC or VSS 1. VIL min and VIH max are reference only and are not tested. Table 3-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 1.3 0.4 µs tHIGH Clock Pulse Width High 0.6 0.4 µs 4 Min Max 2.5, 5.0-volt Min 400 Max Units 1000 kHz AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Table 3-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Min 2.5, 5.0-volt Symbol Parameter Max Min ti Noise Suppression Time(1) tAA Clock Low to Data Out Valid 0.05 tBUF Time the bus must be free before a new transmission can start(1) 1.3 0.5 µs tHD.STA Start Hold Time 0.6 0.25 µs tSU.STA Start Set-up Time 0.6 0.25 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Set-up Time 100 100 ns 100 (1) 0.9 0.05 Max Units 50 ns 0.55 µs tR Inputs Rise Time 0.3 0.3 µs tF Inputs Fall Time(1) 300 100 ns tSU.STO Stop Set-up Time 0.6 0.25 µs tDH Data Out Hold Time 50 50 ns tWR Write Cycle Time Endurance(1) 25°C, Page Mode, 3.3V Notes: 5 5 1,000,000 ms Write Cycles 1. This parameter is ensured by characterization only. 2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 50 ns Input and output timing reference voltages: 0.5 VCC 4. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4-4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below. 5 5194F–SEEPR–1/08 START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 4-5 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 4-5 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C1024B features a low-power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Figure 4-1. Software Reset Dummy Clock Cycles Start bit SCL 1 2 Start bit 3 8 Stop bit 9 SDA Figure 4-2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O®) tHIGH tF tR tLOW SCL tSU.STA tLOW tHD.STA tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT 6 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Figure 4-3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) SCL SDA 8th BIT ACK WORDn (1) twr STOP CONDITION Note: START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4-4. Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE 7 5194F–SEEPR–1/08 Figure 4-5. Start and Stop Definition SDA SCL START Figure 4-6. STOP Output Acknowledge 1 SCL 8 9 DATA IN DATA OUT START ACKNOWLEDGE 5. Device Addressing The 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7-1 on page 11). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices. The 1024K uses the two device address bit, A1, A2, to allow up to four devices on the same bus. These A1, A2 bits must compare to the corresponding hardwired input pins. The A1, A2 pin uses an internal proprietary circuit that biases it to a logic low condition if the pin is allowed to float. The seventh bit (P0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. 8 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B DATA SECURITY: The AT24C1024B has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at VCC. 6. Write Operations BYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address. The word address field consists of the P0 bit of the device address, then the most significant word address followed by the least significant word address (see Figure 7-2 on page 11) A write operation requires the P0 bit and two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, TWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 7-2 on page 11). PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7-3 on page 11). The data word address lower 8 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “rollover” during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue. 7. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover” during read is from the last byte of the last memory page, to the first byte of the first page. 9 5194F–SEEPR–1/08 Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 7-4 on page 11). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 7-5 on page 12). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (see Figure 7-6 on page 12). 10 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Figure 7-1. Device Address A2 Figure 7-2. 0 Byte Write MOST SIGNIFICANT LEAST SIGNIFICANT P 0 Figure 7-3. Page Write MOST SIGNIFICANT LEAST SIGNIFICANT P 0 Figure 7-4. Current Address Read 11 5194F–SEEPR–1/08 Figure 7-5. Random Read High Byte ADDRESS Low Byte ADDRESS P 0 Figure 7-6. Sequential Read High Byte ADDRESS Low Byte ADDRESS Data n + 1 Data n + 2 Data n + X P0 12 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Ordering Information Ordering Code Voltage AT24C1024B-PU (Bulk form only) 1.8 Package 8P3 AT24C1024B-PU25 (Bulk form only) 2.5 8P3 AT24C1024BN-SH-B(1) (NiPdAu Lead Finish) 1.8 8S1 AT24C1024BN-SH-T(2) (NiPdAu Lead Finish) 1.8 8S1 2.5 8S1 (1) (NiPdAu Lead Finish) (2) (NiPdAu Lead Finish) AT24C1024BN-SH25-B 2.5 8S1 AT24C1024BW-SH-B(1) (NiPdAu Lead Finish) 1.8 8S2 AT24C1024BW-SH-T(2) (NiPdAu Lead Finish) 1.8 8S2 AT24C1024BW-SH25-B(1) (NiPdAu Lead Finish) 2.5 8S2 2.5 8S2 1.8 8A2 (NiPdAu Lead Finish) 1.8 8A2 (1) (NiPdAu Lead Finish) 2.5 8A2 (2) AT24C1024BN-SH25-T AT24C1024BW-SH25-T (2) (NiPdAu Lead Finish) AT24C1024B-TH-B(1) (NiPdAu Lead Finish) (2) AT24C1024B-TH-T AT24C1024B-TH25-B (NiPdAu Lead Finish) 2.5 8A2 AT24C1024BY7-YH-T(2) (NiPdAu Lead Finish) 1.8 8Y7 AT24C1024BY7-YH25-T(2) (NiPdAu Lead Finish) 2.5 8Y7 1.8 8U4-1 1.8 Die Sale AT24C1024B-TH25-T AT24C1024BU4-UU-T (2) (3) AT24C1024B-W-11 Notes: Operation Range Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) Industrial Temperature (–40°C to 85°C) 1. “-B” denotes bulk 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel. 3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.200” Wide Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y7 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) 8U4-1 8-ball, die Ball Grid Array Package (dBGA2) Options –1.8 Low-voltage (1.8V to 3.6V) –2.5 Low-voltage (2.5V to 5.5V) 13 5194F–SEEPR–1/08 8. Part marking scheme 8.1 8-SOIC(1.8V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 |---|---|---|---|---|---|---|---| 2 G B 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-SOIC(2.5V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 |---|---|---|---|---|---|---|---| 2 G B 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 2 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 14 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 8.2 WW = SEAL WEEK 02 = Week 2 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark AT24C1024B 5194F–SEEPR–1/08 AT24C1024B 8.3 8-TSSOP(1.8V) TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 2 G B Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: WW = SEAL WEEK 2010 2011 2012 2013 1 02 04 :: :: = = : : Week Week :::: :::: 2 4 : :: 50 = Week 50 |---|---|---|---|---| 52 = Week 52 BOTTOM MARK |---|---|---|---|---|---|---| P H |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator 8.4 8-TSSOP(2.5V) TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 2 G B 2 |---|---|---|---|---| Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: WW = SEAL WEEK 2010 2011 2012 2013 02 04 :: :: = = : : Week Week :::: :::: 2 4 : :: 50 = Week 50 52 = Week 52 BOTTOM MARK |---|---|---|---|---|---|---| P H |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator 15 5194F–SEEPR–1/08 8.5 8-PDIP(1.8V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L U Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 |---|---|---|---|---|---|---|---| 2 G B 52 = Week 52 | Pin 1 Indicator (Dot) Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-PDIP(2.5V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L U Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 |---|---|---|---|---|---|---|---| 2 G B | Pin 1 Indicator (Dot) WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 2 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| 8.7 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| 8.6 WW = SEAL WEEK 02 = Week 2 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-Ultra Thin SAP (1.8V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 2 G B 1 |---|---|---|---|---|---|---|---| Lot Number |---|---|---|---|---|---|---|---| * | Pin 1 Indicator (Dot) 16 Y = 6: 7: 8: 9: SEAL YEAR 2006 0: 2010 2007 1: 2011 2008 2: 2012 2009 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B 8.8 8-Ultra Thin SAP (2.5V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 2 G B 2 |---|---|---|---|---|---|---|---| Lot Number |---|---|---|---|---|---|---|---| * | Pin 1 Indicator (Dot) 8.9 Y = 6: 7: 8: 9: SEAL YEAR 2006 0: 2010 2007 1: 2011 2008 2: 2012 2009 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 dBGA2 TOP MARK LINE 1-------> LINE 2-------> 2GBU PYMTC |<-- Pin 1 This Corner P = COUNTRY OF ORIGIN Y = ONE DIGIT YEAR CODE 4: 2004 7: 2007 5: 2005 8: 2008 6: 2006 9: 2009 M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """"""" J = OCTOBER K = NOVEMBER L = DECEMBER TC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPOND WITH ATK TRACE CODE LOG BOOK) 17 5194F–SEEPR–1/08 9. Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL A b2 b3 b 4 PLCS Side View L NOM MAX NOTE – – 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 – – 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC L Notes: MIN 0.115 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 18 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B AT24C1024B 5194F–SEEPR–1/08 AT24C1024B 8S1 - JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Note: SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 θ 0° – 8° These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. 8S1 C 19 5194F–SEEPR–1/08 8S2 – EIAJ SOIC C 1 E E1 L N θ TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW SYMBOL MIN A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 MAX E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 θ 0° 8° e Notes: 1. 2. 3. 4. 5. NOM NOTE 2, 3 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 4/7/06 R 20 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. 8S2 REV. D AT24C1024B 5194F–SEEPR–1/08 AT24C1024B 8A2 - TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A b D MIN NOM MAX NOTE 2.90 3.00 3.10 2, 5 4.40 4.50 3, 5 E E1 e D A2 6.40 BSC 4.30 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 e Side View L 0.65 BSC 0.45 L1 Notes: 4 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B 21 5194F–SEEPR–1/08 8U4-1 - dBGA2 D A1 BALL PAD CORNER 5. b E A1 TOP VIEW A2 A1 BALL PAD CORNER 2 A SIDE VIEW 1 A B e C D (e1) d (d1) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) 8 SOLDER BALLS SYMBOL A A1 A2 b D E e e1 d 5. Dimension 'b' is measured at the maximum solder ball diameter. d1 MIN 0.81 0.15 0.40 0.25 NOM MAX NOTE 0.91 1.00 0.20 0.25 0.45 0.50 0.30 0.35 2.47 BSC 4.07 BSC 0.75 BSC 0.74 REF 0.75 BSC 0.80 REF This drawing is for general information only. 1/5/05 TITLE R 22 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 8U4-1, 8-ball, 2.47 x 4.07 mm Body, 0.75 mm pitch, Small Die Ball Grid Array Package (dBGA2) DRAWING NO. REV. PO8U4-1 A AT24C1024B 5194F–SEEPR–1/08 AT24C1024B 8Y7 – SAP PIN 1 INDEX AREA A D1 PIN 1 ID D E1 L A1 E e b e1 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A – – 0.60 A1 0.00 – 0.05 D 5.80 6.00 6.20 E 4.70 4.90 5.10 D1 3.30 3.40 3.50 E1 3.90 4.00 4.10 b 0.35 0.40 0.45 SYMBOL e 1.27 TYP e1 L NOTE 3.81 REF 0.50 0.60 0.70 10/13/05 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array Package (UTSAP) Y7 DRAWING NO. REV. 8Y7 B 23 5194F–SEEPR–1/08 10. Revision History 24 Doc. No. Date Comments 5194F 1/2008 Removed ‘NiPdAu’ from AT24C1024BU4-UU-T(2) Removed ‘Preliminary’ status 5194E 8/2007 Updated Part Marking Scheme Updated to new Template Updated to common figures Added Package Marking tables 5194D 5/2007 Changed ‘Advance Information’ to ‘Preliminary’ 5194C 4/2007 Reduced Pin Configuration sizes Changed Maximum Operating Voltage from 6.0 to 6.25 Removed Device Power Up & Power Down Recommendation Added A2 bit to Device Addressing Removed LSB from Figure 10 Current Address Read Removed reference to Waffle Pack Modified Ordering Code table lines Global change on Voltage from 3.6 to 5.5, Correct pg 1 drawings to include address inputs 5194B 2/2007 Correct pg 1 TSSOP drawing 5194A 1/2007 Initial Document Release AT24C1024B 5194F–SEEPR–1/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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