ATMEL AT45DB011B-XU

Features
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Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
Supports Page and Block Erase Operations
One 264-byte SRAM Data Buffer
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Fast Page Program Time – 7 ms Typical
120 µs Typical Page to Buffer Transfer Time
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
Hardware Data Protection Feature
100% Compatible with AT45DB011
Commercial and Industrial Temperature Ranges
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
1-megabit
2.7-volt Only
DataFlash®
AT45DB011B
Description
The AT45DB011B is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. In addition to the main memory, the AT45DB011B also contains one SRAM data buffer of 264
bytes. The buffer allows receiving of data while a page in the main memory is being
reprogrammed. EEPROM emulation (bit or byte alterability) is easily handled with a
self-contained three step Read-Modify-Write operation. Unlike conventional Flash
memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI serial interface to sequentially access its data. SPI
mode 0 and mode 3 are supported. The simple serial interface facilitates hardware
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Clock
CBGA Top View
through Package
1
2
3
SCK
GND
VCC
AT45DB011B
Preliminary 16Megabit 2.7-volt
Only Serial
DataFlash
A
B
SI
Serial Input
CS RDY/BSY WP
C
SO
Serial Output
WP
Hardware Page
Write Protect Pin
RESET
Chip Reset
RDY/BUSY
Ready/Busy
SOIC
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
SO
SI
RESET
TSSOP Top View
Type 1
RDY/BUSY
RESET
WP
VCC
GND
SCK
SO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CS
NC
NC
NC
NC
NC
SI
1984J–DFLASH–06/06
1
layout, increases system reliability, minimizes switching noise, and reduces package size and
active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. The device
operates at clock frequencies up to 20 MHz with a typical active read current consumption of
4 mA.
To allow for simple in-system reprogrammability, the AT45DB011B does not require high input
voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for
both the program and read operations. The AT45DB011B is enabled through the chip select
pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
When the device is shipped from Atmel, the most significant page of the memory array may
not be erased. In other words, the contents of the last page may not be filled with FFH.
Block Diagram
FLASH MEMORY ARRAY
WP
PAGE (264 BYTES)
BUFFER (264 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
Memory Array
2
I/O INTERFACE
SI
SO
To provide optimal flexibility, the memory array of the AT45DB011B is divided into three levels
of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram
illustrates the breakdown of each level and details the number of pages per sector and block.
All program operations to the DataFlash occur on a page by page basis; however, the optional
erase operations can be performed at the block or page level.
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Memory Architecture Diagram
BLOCK ARCHITECTURE
SECTOR ARCHITECTURE
SECTOR 0 = 2112 BYTES (2K + 64)
SECTOR 0
BLOCK 0
PAGE ARCHITECTURE
PAGE 0
8 Pages
PAGE 1
BLOCK 2
SECTOR 1 = 65,472 BYTES (62K + 1984)
SECTOR 1
BLOCK 3
BLOCK 0
BLOCK 1
PAGE 6
PAGE 7
PAGE 8
BLOCK 29
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 34
PAGE 9
BLOCK 1
BLOCK 30
PAGE 14
PAGE 15
PAGE 16
SECTOR 2
SECTOR 2 = 67,584 BYTES (64K + 2K)
PAGE 17
PAGE 18
BLOCK 61
PAGE 509
BLOCK 62
PAGE 510
BLOCK 63
PAGE 511
Block = 2112 bytes
(2K + 64)
Device
Operation
Page = 264 bytes
(256 + 8)
The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 through 4 (pages 11 and 12). A
valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and
the desired buffer or main memory address location. While the CS pin is low, toggling the SCK
pin controls the loading of the opcode and the desired buffer or main memory address location
through the SI (serial input) pin. All instructions, addresses, and data are transferred with the
most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8-BFA0 to denote
the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA8 - PA0 and BA8 - BA0 where PA8 - PA0
denotes the 10 address bits required to designate a page address and BA8-BA0 denotes the
nine address bits required to designate a byte address within the page.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from the
data buffer. The DataFlash supports two categories of read modes in relation to the SCK signal. The differences between the modes are in respect to the inactive state of the SCK signal
as well as which clock cycle data will begin to be output. The two categories, which are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock Polarity
High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to Table 1 on page 11 for a
complete list) is used to select which category will be used for reading. Please refer to the
“Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle
sequences for each mode.
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1984J–DFLASH–06/06
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory
array, the Continuous Array Read command can be utilized to sequentially read a continuous
stream of data from the device by simply providing a clock signal; no additional addressing
information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a
continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24
address bits and 32 don’t care bits. The first six bits of the 24-bit address sequence are
reserved for upward and downward compatibility to larger and smaller density devices (see
Notes under “Command Sequence for Read/Write Operations” diagram). The next nine
address bits (PA8-PA0) specify which page of the main memory array to read, and the last
nine bits (BA8-BA0) of the 24-bit address sequence specify the starting byte address within
the page. The 32 don’t care bits that follow the 24 address bits are needed to initialize the read
operation. Following the 32 don’t care bits, additional clock pulses on the SCK pin will result in
serial data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t care
bits, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one
page to the beginning of the next page). When the last bit in the main memory array has been
read, the device will continue reading back at the beginning of the first page of memory. As
with crossing over page boundaries, no delays will be incurred when wrapping around from
the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory read allows the user to read data directly from
any one of the 512 pages in the main memory, bypassing the data buffer and leaving the contents of the buffer unchanged. To start a page read, the 8-bit opcode, 52H or D2H, must be
clocked into the device followed by 24 address bits and 32 don’t care bits. In the
AT45DB011B, the first six address bits are reserved for larger density devices (see Notes on
page 15), the next nine address bits (PA8-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care
bits which follow the 24 address bits are sent to initialize the read operation. Following the 32
don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial
output) pin. The CS pin must remain low during the loading of the opcode, the address bits,
and the reading of data. When the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the beginning of the same page. A lowto-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from the data buffer using an opcode of 54H or D4H. To
perform a buffer read, the eight bits of the opcode must be followed by 15 don’t care bits, nine
address bits, and eight don’t care bits. Since the buffer size is 264 bytes, nine address bits
(BFA8- BFA0) are required to specify the first byte of data to be read from the buffer. The CS
pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and
the reading of data. When the end of the buffer is reached, the device will continue reading
back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the
read operation and tri-state the SO pin.
4
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
STATUS REGISTER READ: The status register can be used to determine the device’s
ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of 57H or D7H must be loaded into the
device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting
with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The
five most significant bits of the status register will contain device information, while the remaining three least significant bits are reserved for future use and will have undefined values. After
bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS
remains low and SCK is being toggled) starting again with bit 7. The data in the status register
is constantly updated, so each repeating sequence will output new data.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY/BUSY
COMP
0
0
1
1
X
X
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device
is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level
once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and
once the device is no longer busy, the state of SO will change from 0 to 1. There are eight
operations which can cause the device to be in a busy state: Main Memory Page to Buffer
Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with
Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase, Page Erase,
Block Erase, Main Memory Page Program, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated
using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches
the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page
does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the
AT45DB011B, the four bits are 0, 0, 1 and 1. The decimal value of these four binary bits does
not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of sixteen different density
configurations.
Program and
Erase Commands
BUFFER WRITE: Data can be shifted in from the SI pin into the data buffer. To load data into
the buffer, an 8-bit opcode of 84H is followed by 15 don’t care bits and nine address bits
(BFA8-BFA0). The nine address bits specify the first byte in the buffer to be written. The data
is entered following the address bits. If the end of the data buffer is reached, the device will
wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer
until a low-to-high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into
the buffer can be programmed into the main memory. An 8-bit opcode of 83H is followed by
the six reserved bits, nine address bits (PA8-PA0) that specify the page in the main memory
to be written, and nine additional don’t care bits. When a low-to-high transition occurs on the
CS pin, the part will first erase the selected page in main memory to all 1s and then program
the data stored in the buffer into the specified page in the main memory. Both the erase and
the programming of the page are internally self-timed and should take place in a maximum
time of tEP. During this time, the status register will indicate that the part is busy.
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1984J–DFLASH–06/06
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously
erased page within main memory can be programmed with the contents of the buffer. An 8-bit
opcode of 88H is followed by the six reserved bits, nine address bits (PA8-PA0) that specify
the page in the main memory to be written, and nine additional don’t care bits. When a low-tohigh transition occurs on the CS pin, the part will program the data stored in the buffer into the
specified page in the main memory. It is necessary that the page in main memory that is being
programmed has been previously erased. The programming of the page is internally selftimed and should take place in a maximum time of tP. During this time, the status register will
indicate that the part is busy.
Successive page programming operations without doing a page erase are not recommended.
In other words, changing bytes within a page from a “1” to a “0” during multiple page programming operations without erasing that page is not recommended.
PAGE ERASE: The optional Page Erase command can be used to individually erase any
page in the main memory array allowing the Buffer to Main Memory Page Program without
Built-in Erase command to be utilized at a later time. To perform a Page Erase, an opcode of
81H must be loaded into the device, followed by six reserved bits, nine address bits (PA8 PA0), and nine don’t care bits. The nine address bits are used to specify which page of the
memory array is to be erased. When a low-to-high transition occurs on the CS pin, the part will
erase the selected page to 1s. The erase operation is internally self-timed and should take
place in a maximum time of tPE. During this time, the status register will indicate that the part is
busy.
BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer to Main
Memory Page Program without Built-in Erase command to be utilized to reduce programming
times when writing large amounts of data to the device. To perform a Block Erase, an opcode
of 50H must be loaded into the device, followed by six reserved bits, six address bits (PA8PA3), and 12 don’t care bits. The six address bits are used to specify which block of eight
pages is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase
the selected block of eight pages to 1s. The erase operation is internally self-timed and should
take place in a maximum time of tBE. During this time, the status register will indicate that the
part is busy.
Block Erase Addressing
6
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Block
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
1
X
X
X
1
0
0
0
0
1
0
X
X
X
2
0
0
0
0
1
1
X
X
X
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
0
0
X
X
X
60
1
1
1
1
0
1
X
X
X
61
1
1
1
1
1
0
X
X
X
62
1
1
1
1
1
1
X
X
X
63
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of
the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations.
Data is first shifted into the buffer from the SI pin and then programmed into a specified page
in the main memory. An 8-bit opcode of 82H is followed by the six reserved bits and 18
address bits. The nine most significant address bits (PA8-PA0) select the page in the main
memory where data is to be written, and the next nine address bits (BFA8-BFA0) select the
first byte in the buffer to be written. After all address bits are shifted in, the part will take data
from the SI pin and store it in the data buffer. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When there is a low-to-high transition on the
CS pin, the part will first erase the selected page in main memory to all 1s and then program
the data stored in the buffer into the specified page in the main memory. Both the erase and
the programming of the page are internally self timed and should take place in a maximum of
time tEP. During this time, the status register will indicate that the part is busy.
Additional
Commands
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the
main memory to buffer. An 8-bit opcode of 53H is followed by the six reserved bits, nine
address bits (PA8-PA0) which specify the page in main memory that is to be transferred, and
nine don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode,
the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from
the main memory to the buffer will begin when the CS pin transitions from a low to a high state.
During the transfer of a page of data (t XFR), the status register can be read to determine
whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in the buffer. An 8-bit opcode of 60H is followed by 24 address bits
consisting of the six reserved bits, nine address bits (PA8-PA0) which specify the page in the
main memory that is to be compared to the buffer, and nine don’t care bits. The loading of the
opcode and the address bits is the same as described previously. The CS pin must be low
while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits from
the SI pin. On the low-to-high transition of the CS pin, the 264 bytes in the selected main memory page will be compared with the 264 bytes in the buffer. During this time (tXFR), the status
register will indicate that the part is busy. On completion of the compare operation, bit 6 of the
status register is updated with the result of the compare.
AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or multiple
pages of data are modified in a random fashion. This mode is a combination of two operations:
Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in
Erase. A page of data is first transferred from the main memory to the data buffer, and then the
same data (from the buffer) is programmed back into its original page of main memory. An 8bit opcode of 58H is followed by the six reserved bits, nine address bits (PA8-PA0) that specify the page in main memory to be rewritten, and nine additional don’t care bits. When a lowto-high transition occurs on the CS pin, the part will first transfer data from the page in main
memory to the buffer and then program the data from the buffer back into same page of main
memory. The operation is internally self-timed and should take place in a maximum time of tEP.
During this time, the status register will indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially page by page, then the programming
algorithm shown in Figure 1 on page 26 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in Figure 2 on page 27 is recommended. Each page within a sector must be
updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector.
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1984J–DFLASH–06/06
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT45DB011B
Com.
0°C to 70°C
Operating Temperature (Case)
Ind.
VCC Power Supply
Note:
8
(1)
-40°C to 85°C
2.7V to 3.6V
1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an operational mode is started.
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Operation Mode
Summary
The modes described can be separated into two groups – modes which make use of the Flash
memory array (Group A) and modes which do not make use of the Flash memory array
(Group B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer Transfer
3. Main Memory Page to Buffer Compare
4. Buffer to Main Memory Page Program with Built-in Erase
5. Buffer to Main Memory Page Program without Built-in Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program through Buffer
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer Read
2. Buffer Write
3. Status Register Read
If a Group A mode is in progress (not fully completed), then another mode in Group A should
not be started. However, during this time in which a Group A mode is in progress (other than
Main Memory Page Read), Status Register Read from Group B can be started. Furthermore,
during Page Erase and Block Erase operation in progress from Group A, any of the modes
from Group B can be started.
Pin Descriptions
SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data into the device.
The SI pin is used for all data input, including opcodes and address sequences.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data out from the
device.
SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow of
data to and from the DataFlash. Data is always clocked into the device on the rising edge of
SCK and clocked out of the device on the falling edge of SCK.
CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is
not selected, data will not be accepted on the SI pin, and the SO pin will remain in a highimpedance state. A high-to-low transition on the CS pin is required to start an operation, and a
low-to-high transition on the CS pin is required to end an operation.
WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot
be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect
pin high and then use the program commands previously mentioned. If this pin and feature are
not utilized it is recommended that the WP pin be driven high externally.
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1984J–DFLASH–06/06
RESET: A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset condition
as long as a low level is present on the RESET pin. Normal operation can resume once the
RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally.
READY/BUSY: This open-drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through a 1kΩ external pull-up resistor), will be pulled low during programming operations, compare operations,
and during page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
Power-on/Reset
State
When power is first applied to the device, or when recovering from a reset condition, the
device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and
a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode
will be automatically selected on every falling edge of CS by sampling the inactive clock state.
After power is applied and VCC is at the minimum datasheet value, the system should wait
20 ms before an operational mode is started.
System
Considerations
DataFlash is controlled by the Serial Clock (SCK) and Chip Select (CS) pins. These signals
must rise and fall monotonically and be free from noise. Excessive noise or ringing on these
pins can be misinterpreted as multiple edges and cause improper operation of the device. The
PC board traces must be kept to a minimum distance or appropriately terminated. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise
glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak currents for DataFlash occur during the programming and erase operations. The peak current during programming or erase of a DataFlash is 70 mA to 80 mA. The
regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption.
10
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Table 1. Read Commands
Command
SCK Mode
Opcode
Inactive Clock Polarity Low or High
68H
SPI Mode 0 or 3
E8H
Inactive Clock Polarity Low or High
52H
SPI Mode 0 or 3
D2H
Inactive Clock Polarity Low or High
54H
SPI Mode 0 or 3
D4H
Inactive Clock Polarity Low or High
57H
SPI Mode 0 or 3
D7H
Continuous Array Read
Main Memory Page Read
Buffer Read
Status Register Read
Table 2. Program and Erase Commands
Command
SCK Mode
Opcode
Buffer Write
Any
84H
Buffer to Main Memory Page Program with Built-in Erase
Any
83H
Buffer to Main Memory Page Program without Built-in Erase
Any
88H
Page Erase
Any
81H
Block Erase
Any
50H
Main Memory Page Program through Buffer
Any
82H
SCK Mode
Opcode
Main Memory Page to Buffer Transfer
Any
53H
Main Memory Page to Buffer Compare
Any
60H
Auto Page Rewrite through Buffer
Any
58H
Table 3. Additional Commands
Command
Note:
In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity
Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).
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1984J–DFLASH–06/06
Table 4. Detailed Bit-level Addressing Sequence
Opcode
Opcode
Reserved
Reserved
Reserved
Reserved
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
Address Byte
Reserved
Address Byte
Reserved
Address Byte
Additional
Don’t Care
Bytes
Required
50H
0 1 0 1 0 0 0 0
r
r
r
r
r
r
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
x
x
N/A
52H
0 1 0 1 0 0 1 0
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
4 Bytes
53H
0 1 0 1 0 0 1 1
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
N/A
54H
0 1 0 1 0 1 0 0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
1 Byte
57H
0 1 0 1 0 1 1 1
58H
0 1 0 1 1 0 0 0
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
N/A
60H
0 1 1 0 0 0 0 0
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
N/A
68H
0 1 1 0 1 0 0 0
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
4 Bytes
81H
1 0 0 0 0 0 0 1
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
N/A
82H
1 0 0 0 0 0 1 0
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
N/A
83H
1 0 0 0 0 0 1 1
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
N/A
84H
1 0 0 0 0 1 0 0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
N/A
88H
1 0 0 0 1 0 0 0
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
N/A
D2H
1 1 0 1 0 0 1 0
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
4 Bytes
D4H
1 1 0 1 0 1 0 0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
1 Byte
D7H
1 1 0 1 0 1 1 1
E8H
1 1 1 0 1 0 0 0
Note:
12
N/A
N/A
N/A
r
r
r
r = Reserved Bit
P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
AT45DB011B
r
r
N/A
N/A
r
P
P
P
P
P
P
P
N/A
N/A
P
P
B
B
B
B
B
B
N/A
B
B
B
4 Bytes
AT45DB011B
DC Characteristics
Symbol
Parameter
Condition
ISB
Standby Current
ICC1(1)
Typ
Max
Units
CS, RESET, WP = VIH, all inputs at
CMOS levels
2
10
µA
Active Current, Read Operation
f = 20 MHz; IOUT = 0 mA; VCC = 3.6V
4
10
mA
ICC2
Active Current, Program/Erase
Operation
VCC = 3.6V
10
25
mA
ILI
Input Load Current
VIN = CMOS levels
1
µA
ILO
Output Leakage Current
VI/O = CMOS levels
1
µA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6 mA; VCC = 2.7V
VOH
Output High Voltage
IOH = -100 µA
Note:
Min
2.0
V
0.4
VCC - 0.2V
V
V
1. Icc1 during a buffer read is 20mA maximum.
AC Characteristics
Symbol
Parameter
fSCK
Min
Typ
Max
Units
SCK Frequency
20
MHz
fCAR
SCK Frequency for Continuous Array Read
20
MHz
tWH
SCK High Time
22
ns
tWL
SCK Low Time
22
ns
tCS
Minimum CS High Time
250
ns
tCSS
CS Setup Time
250
ns
tCSH
CS Hold Time
250
ns
tCSB
CS High to RDY/BUSY Low
tSU
Data In Setup Time
5
ns
tH
Data In Hold Time
10
ns
tHO
Output Hold Time
0
ns
tDIS
Output Disable Time
18
ns
tV
Output Valid
20
ns
tXFR
Page to Buffer Transfer/Compare Time
120
200
µs
tEP
Page Erase and Programming Time
10
20
ms
tP
Page Programming Time
7
15
ms
tPE
Page Erase Time
6
10
ms
tBE
Block Erase Time
7
15
ms
tRST
RESET Pulse Width
tREC
RESET Recovery Time
200
10
ns
µs
1
µs
13
1984J–DFLASH–06/06
Input Test Waveforms and Measurement Levels
AC
DRIVING
LEVELS
2.4V
2.0
0.8
0.45V
AC
MEASUREMENT
LEVEL
tR, tF < 3 ns (10% to 90%)
Output Test Load
DEVICE
UNDER
TEST
30 pF
AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The
setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK
signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows
timing that is compatible with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
tCS
CS
tWH
tCSS
tWL
tCSH
SCK
tHO
tV
SO
HIGH IMPEDANCE
VALID OUT
tSU
SI
tDIS
HIGH IMPEDANCE
tH
VALID IN
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
tCS
CS
tCSS
tWL
tWH
tCSH
SCK
tV
SO
HIGH Z
tHO
VALID OUT
tSU
SI
14
tDIS
HIGH IMPEDANCE
tH
VALID IN
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Reset Timing (Inactive Clock Polarity Low Shown)
CS
tREC
tCSS
SCK
tRST
RESET
HIGH IMPEDANCE
HIGH IMPEDANCE
SO
SI
Note:
The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (Except Status Register Read)
SI
MSB
r r r r
CMD
r r XX
Reserved for
larger densities
Notes:
8 bits
8 bits
XXXX XXXX
Page Address
(PA8-PA0)
8 bits
XXXX XXXX
LSB
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0”.
3. For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density.
15
1984J–DFLASH–06/06
Write
Operations
The following block diagram and waveforms illustrate the various write sequences available.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER TO
MAIN MEMORY
PAGE PROGRAM
BUFFER (264 BYTES)
MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER
BUFFER
WRITE
I/O INTERFACE
SI
Main Memory Page Program through Buffer
· Completes writing into buffer
· Starts self-timed erase/program operation
CS
SI
r ···r , PA8-7
CMD
PA6-0, BFA8
BFA7-0
n
n+1
Last Byte
Buffer Write
· Completes writing into buffer
CS
SI
CMD
X
X···X, BFA8
BFA7-0
n
Last Byte
n+1
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS
SI
Each transition represents
8 bits and 8 clock cycles
16
CMD
r ···r , PA8-7
PA6-0, X
X
n = 1st byte written
n+1 = 2nd byte written
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Read
Operations
The following block diagram and waveforms illustrate the various read sequences available.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
MAIN MEMORY
PAGE TO
BUFFER
BUFFER (264 BYTES)
MAIN MEMORY
PAGE READ
BUFFER
READ
I/O INTERFACE
SO
Main Memory Page Read
CS
SI
CMD
r ···r , PA8-7
BA7-0
PA6-0, BA8
X
X
X
X
SO
n
n+1
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
CS
SI
CMD
r ···r , PA8-7
PA6-0, X
X
SO
Buffer Read
CS
SI
SO
Each transition represents
8 bits and 8 clock cycles
CMD
X
X···X, BFA8
BFA7-0
X
n
n+1
n = 1st byte read
n+1 = 2nd byte read
17
1984J–DFLASH–06/06
Detailed Bit-level Read Timing – Inactive Clock Polarity Low
Continuous Array Read (Opcode: 68H)
CS
SCK
1
2
63
64
0
1
X
X
65
66
67
68
tSU
SI
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D5
D2
D1
LSB
MSB
D0
D7
BIT 2111
OF
PAGE n
D6
D5
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: 52H)
CS
SCK
1
2
3
4
5
60
61
62
63
64
0
X
X
X
X
X
65
66
67
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
SO
18
HIGH-IMPEDANCE
DATA OUT
D7
MSB
D6
D5
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued)
Buffer Read (Opcode: 54H)
CS
SCK
1
2
3
4
5
36
37
38
39
40
0
X
X
X
X
X
41
42
43
tSU
COMMAND OPCODE
SI
1
0
1
0
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
MSB
D6
D5
Status Register Read (Opcode: 57H)
CS
SCK
1
2
0
1
3
4
5
6
7
8
1
1
9
10
11
12
16
17
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D7
MSB
D6
D5
D1
D0
LSB
D7
MSB
19
1984J–DFLASH–06/06
Detailed Bit-level Read Timing – Inactive Clock Polarity High
Continuous Array Read (Opcode: 68H)
CS
SCK
1
2
63
64
65
66
67
tSU
SI
1
0
X
X
X
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D5
D2
D1
LSB
MSB
D0
D7
BIT 2111
OF
PAGE n
D6
D5
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: 52H)
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
68
67
tSU
COMMAND OPCODE
SI
0
1
0
1
0
X
X
X
X
X
tV
SO
20
HIGH-IMPEDANCE
DATA OUT
D7
MSB
D6
D5
D4
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued)
Buffer Read (Opcode: 54H)
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
43
44
tSU
COMMAND OPCODE
SI
1
0
1
0
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D7
MSB
D6
D5
D4
Status Register Read (Opcode: 57H)
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
0
1
0
1
0
1
1
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D7
MSB
D6
D5
D4
D0
LSB
D7
MSB
D6
21
1984J–DFLASH–06/06
Detailed Bit-level Read Timing – SPI Mode 0
Continuous Array Read (Opcode: E8H)
CS
SCK
1
2
62
63
64
1
1
X
X
X
65
66
67
tSU
SI
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D5
D2
D1
LSB
MSB
D0
D7
BIT 2111
OF
PAGE n
D6
D5
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
SCK
1
2
3
4
5
60
61
62
63
64
0
X
X
X
X
X
65
66
67
tSU
COMMAND OPCODE
SI
1
1
0
1
tV
SO
HIGH-IMPEDANCE
DATA OUT
D7
D6
D5
D4
MSB
22
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Detailed Bit-level Read Timing – SPI Mode 0 (Continued)
Buffer Read (Opcode: D4H)
CS
SCK
1
2
3
4
5
36
37
38
39
40
0
X
X
X
X
X
41
42
43
tSU
COMMAND OPCODE
SI
1
1
1
0
tV
DATA OUT
HIGH-IMPEDANCE
SO
D7
D6
D5
D4
MSB
Status Register Read (Opcode: D7H)
CS
SCK
1
2
1
1
3
4
5
6
7
8
1
1
9
10
D7
MSB
D6
11
12
16
17
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D5
D4
D1
D0
LSB
D7
MSB
23
1984J–DFLASH–06/06
Detailed Bit-level Read Timing – SPI Mode 3
Continuous Array Read (Opcode: E8H)
CS
SCK
1
2
63
64
65
66
67
tSU
SI
1
1
X
X
X
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D5
D2
D1
LSB
MSB
D0
D7
BIT 2111
OF
PAGE n
D6
D5
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
67
68
tSU
COMMAND OPCODE
SI
1
1
0
1
0
X
X
X
X
X
tV
SO
24
HIGH-IMPEDANCE
DATA OUT
D7
MSB
D6
D5
D4
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Detailed Bit-level Read Timing – SPI Mode 3 (Continued)
Buffer Read (Opcode: D4H)
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
43
44
tSU
COMMAND OPCODE
SI
1
1
1
0
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D7
MSB
D6
D5
D4
Status Register Read (Opcode: D7H)
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
1
1
0
1
0
1
1
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D7
MSB
D6
D5
D4
D0
LSB
D7
MSB
D6
25
1984J–DFLASH–06/06
Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire Array
START
provide address
and data
BUFFER WRITE
(84H)
MAIN MEMORY PAGE PROGRAM
(82H)
BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H)
END
Notes:
26
1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Figure 2. Algorithm for Randomly Modifying Data
START
provide address of
page to modify
MAIN MEMORY PAGE
to BUFFER TRANSFER
(53H)
If planning to modify multiple
bytes currently stored within
a page of the Flash array
BUFFER WRITE
(84H)
MAIN MEMORY PAGE PROGRAM
(82H)
BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H)
(2)
Auto Page Rewrite
(58H)
INCREMENT PAGE
(2)
ADDRESS POINTER
END
Notes:
1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000
cumulative page erase/program operations within that sector.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000
cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note
AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
Sector Addressing
PA8
PA7
PA6
PA5
PA4
PA3
PA2 - PA0
Sector
0
0
0
0
0
0
X
0
0
X
X
X
X
X
X
1
1
X
X
X
X
X
X
2
27
1984J–DFLASH–06/06
Ordering Information
fSCK
(MHz)
ICC (mA)
Active
Standby
Ordering Code
Package
(1)
20
10
20
Note:
10
Operation Range
0.01
AT45DB011B-CC
AT45DB011B-SC
AT45DB011B-XC(1)
9C1
8S2
14X
Commercial
(0°C to 70°C)
0.01
AT45DB011B-CI(1)
AT45DB011B-SI
AT45DB011B-XI(1)
9C1
8S2
14X
Industrial
(-40°C to 85°C)
1. These packages are not recommended for new designs.
Green Package Options (Pb/Halide-free/RoHS Compliant)
ICC (mA)
fSCK
(MHz)
Active
Standby
20
10
0.01
Notes:
Ordering Code
Package
AT45DB011B-SU
AT45DB011B-XU(1)
8S2
14X
Operation Range
Industrial
(-40°C to 85°C)
1. This package is not recommended for new designs.
2. Green Packages cover lead-free requirements.
Package Type
9C1
9-ball (3 x 3 Array), 1.0 mm Pitch, 5 x 5 mm Plastic Chip-scale Ball Grid Array Package (CBGA)
8S2
8-lead, 0.210" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
14X
14-lead, 0.170" Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
28
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
Packaging Information
9C1 – CBGA
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
5.10(0.201)
4.90(0.193)
A1 ID
5.10(0.201)
4.90(0.193)
SIDE VIEW
TOP VIEW
0.25(0.010)MIN
1.20(0.047)MAX
2.0 (0.079)
1.50(0.059) REF
3
2
1
1.50(0.059) REF
A
B
1.00 (0.0394) BSC
NON-ACCUMULATIVE
2.0 (0.079)
C
0.40 (0.016)
DIA BALL TYP
1.00 (0.0394) BSC
NON-ACCUMULATIVE
BOTTOM VIEW
04/11/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
9C1, 9-ball (3 x 3 Array), 5 x 5 x 1.2 mm Body, 1.0 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
REV.
9C1
A
29
1984J–DFLASH–06/06
8S2 – EIAJ SOIC
C
1
E
E1
L
N
θ
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
SIDE VIEW
NOM
MAX
NOTE
A
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
θ
0°
8°
e
Notes: 1.
2.
3.
4.
5.
MIN
1.27 BSC
2, 3
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/7/06
R
30
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
D
AT45DB011B
1984J–DFLASH–06/06
AT45DB011B
14X – TSSOP
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
JEDEC Standard MO-153 AB-1.
INDEX MARK
PIN
1
4.50 (0.177) 6.50 (0.256)
4.30 (0.169) 6.25 (0.246)
5.10 (0.201)
4.90 (0.193)
0.65 (.0256) BSC
0.30 (0.012)
0.19 (0.007)
1.20 (0.047) MAX
0.15 (0.006)
0.05 (0.002)
SEATING
PLANE
0.20 (0.008)
0.09 (0.004)
0º~ 8º
0.75 (0.030)
0.45 (0.018)
05/16/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
14X (Formerly "14T"), 14-lead (4.4 mm Body) Thin Shrink
Small Outline Package (TSSOP)
DRAWING NO.
REV.
14X
B
31
1984J–DFLASH–06/06
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