CY7C1268XV18 CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations ■ 36-Mbit density (2 M × 18, 1 M × 36) With Read Cycle Latency of 2.5 cycles: ■ 633 MHz clock for high bandwidth CY7C1268XV18 – 2 M × 18 ■ Two-word burst for reducing address bus frequency CY7C1270XV18 – 1 M × 36 ■ Double data rate (DDR) interfaces (data transferred at 1266 MHz) at 633 MHz Functional Description ■ Available in 2.5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ DDR II+ Xtreme operates with 2.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW ■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to 1.6 V ❐ Supports 1.5 V I/O supply ■ HSTL inputs and variable drive HSTL output buffers ■ Available in 165-ball fine pitch ball grid array (FBGA) package (13 × 15 × 1.4 mm) ■ Offered in Pb-free packages ■ JTAG 1149.1 compatible test access port ■ Phase-locked loop (PLL) for accurate data placement The CY7C1268XV18, and CY7C1270XV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C1268XV18), or 36-bit words (CY7C1270XV18) that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. For a complete list of related documentation, click here. Selection Guide Description Maximum operating frequency Maximum operating current Cypress Semiconductor Corporation Document Number: 001-70329 Rev. *E • 198 Champion Court • 633 MHz 600 MHz Unit 633 600 MHz × 18 965 910 mA × 36 1230 1165 San Jose, CA 95134-1709 • 408-943-2600 Revised October 20, 2015 CY7C1268XV18 CY7C1270XV18 Logic Block Diagram – CY7C1268XV18 Write Reg CLK Gen. DOFF R/W BWS[1:0] 18 Output Logic Control R/W Read Data Reg. 36 VREF Read Add. Decode K 1M x 18 Array K Write Reg 1M x 18 Array LD Address Register Write Add. Decode 20 A(19:0) Control Logic 18 18 Reg. Reg. 18 Reg. 18 CQ CQ 18 DQ[17:0] QVLD K CLK Gen. DOFF VREF R/W BWS[3:0] Write Add. Decode K Write Reg 512K x 36 Array LD Address Register Write Reg 512K x 36 Array 19 A(18:0) Read Add. Decode Logic Block Diagram – CY7C1270XV18 36 Output Logic Control R/W Read Data Reg. 72 Control Logic 36 36 Reg. Reg. 36 Reg. 36 CQ CQ 36 DQ[35:0] QVLD Document Number: 001-70329 Rev. *E Page 2 of 28 CY7C1268XV18 CY7C1270XV18 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Read Operations ......................................................... 6 Write Operations ......................................................... 6 Byte Write Operations ................................................. 6 DDR Operation ............................................................ 7 Depth Expansion ......................................................... 7 Programmable Impedance .......................................... 7 Echo Clocks ................................................................ 7 Valid Data Indicator (QVLD) ........................................ 7 PLL .............................................................................. 7 Application Example ........................................................ 7 Truth Table ........................................................................ 8 Write Cycle Descriptions ................................................. 8 Write Cycle Descriptions ................................................. 9 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10 Disabling the JTAG Feature ...................................... 10 Test Access Port ....................................................... 10 Performing a TAP Reset ........................................... 10 TAP Registers ........................................................... 10 TAP Instruction Set ................................................... 10 TAP Controller State Diagram ....................................... 12 TAP Controller Block Diagram ...................................... 13 TAP Electrical Characteristics ...................................... 13 TAP AC Switching Characteristics ............................... 14 TAP Timing and Test Conditions .................................. 15 Identification Register Definitions ................................ 16 Scan Register Sizes ....................................................... 16 Instruction Codes ........................................................... 16 Document Number: 001-70329 Rev. *E Boundary Scan Order .................................................... 17 Power Up Sequence in DDR II+ Xtreme SRAM ............ 18 Power Up Sequence ................................................. 18 PLL Constraints ......................................................... 18 Maximum Ratings ........................................................... 19 Operating Range ............................................................. 19 Neutron Soft Error Immunity ......................................... 19 Electrical Characteristics ............................................... 19 DC Electrical Characteristics ..................................... 19 AC Electrical Characteristics ..................................... 20 Capacitance .................................................................... 20 Thermal Resistance ........................................................ 20 AC Test Loads and Waveforms ..................................... 21 Switching Characteristics .............................................. 22 Switching Waveforms .................................................... 23 Read/Write/Deselect Sequence ................................ 23 Ordering Information ...................................................... 24 Ordering Code Definitions ......................................... 24 Package Diagram ............................................................ 25 Acronyms ........................................................................ 26 Document Conventions ................................................. 26 Units of Measure ....................................................... 26 Document History Page ................................................. 27 Sales, Solutions, and Legal Information ...................... 28 Worldwide Sales and Design Support ....................... 28 Products .................................................................... 28 PSoC® Solutions ...................................................... 28 Cypress Developer Community ................................. 28 Technical Support ..................................................... 28 Page 3 of 28 CY7C1268XV18 CY7C1270XV18 Pin Configurations The pin configurations for CY7C1268XV18, and CY7C1270XV18 follow. [1] Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout CY7C1268XV18 (2 M × 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W BWS1 K NC/144M LD A A CQ B NC DQ9 NC A NC/288M K BWS0 A NC NC DQ8 C NC NC NC VSS A NC A VSS NC DQ7 NC D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 VSS A A A VSS NC NC NC P NC NC DQ17 A A QVLD A A NC NC DQ0 R TDO TCK A A A NC A A A TMS TDI 9 10 11 CY7C1270XV18 (1 M × 36) 1 2 3 4 A CQ B NC C D 5 6 7 8 NC/144M A DQ27 DQ18 R/W BWS2 K BWS1 LD A NC/72M CQ A BWS3 K BWS0 A NC NC DQ8 NC NC DQ28 VSS A NC A VSS NC DQ17 DQ7 NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS A A A VSS NC NC DQ10 P NC NC DQ26 A A QVLD A A NC DQ9 DQ0 R TDO TCK A A A NC A A A TMS TDI Note 1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-70329 Rev. *E Page 4 of 28 CY7C1268XV18 CY7C1270XV18 Pin Definitions Pin Name I/O Pin Description DQ[x:0] Input Output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven out on the rising edge of both the K and K clocks during read operations. When read access is deselected, Q[x:0] are automatically tristated. CY7C1268XV18 DQ[17:0] CY7C1270XV18 DQ[35:0] LD InputSynchronous load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus Synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K. BWS0, BWS1, BWS2, BWS3 InputByte Write Select 0, 1, 2 and 3 Active LOW. Sampled on the rising edge of the K and K clocks during Synchronous write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1268XV18 BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1270XV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device. A InputAddress inputs. Sampled on the rising edge of the K clock during active read and write operations. Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1268XV18, and 1 M × 36 (2 arrays each of 512 K × 36) for CY7C1270XV18. The address pins (A) can be assigned any bit order. R/W InputSynchronous read or write input. When LD is LOW, this input designates the access type (read when Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times around edge of K. QVLD Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. indicator K Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K. K Input Clock Negative input clock input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0]. CQ Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR II+ Xtreme. The timing for the echo clocks is shown in the Switching Characteristics on page 22. CQ Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR II+ Xtreme. The timing for the echo clocks is shown in the Switching Characteristics on page 22. ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 k or less pull up resistor. The device behaves in DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR I timing. Document Number: 001-70329 Rev. *E Page 5 of 28 CY7C1268XV18 CY7C1270XV18 Pin Definitions (continued) Pin Name I/O Pin Description TDO Output TCK Input Test clock (TCK) pin for JTAG. TDI Input Test data in (TDI) pin for JTAG. TMS Input Test mode select (TMS) pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/72M Input Not connected to the die. Can be tied to any voltage level. NC/144M Input Not connected to the die. Can be tied to any voltage level. NC/288M Input Not connected to the die. Can be tied to any voltage level. VREF VDD VSS VDDQ InputReference Test data out (TDO) pin for JTAG. Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. Power Supply Power supply inputs to the core of the device. Ground Ground for the device. Power Supply Power supply inputs for the outputs of the device. Functional Overview The CY7C1268XV18, and CY7C1270XV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of two and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input and output timing is referenced from the rising edge of the input clocks (K and K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the input clocks (K and K). All synchronous control (R/W, LD, BWS[X:0]) inputs pass through input registers controlled by the rising edge of the input clock (K). CY7C1268XV18 is described in the following sections. The same basic descriptions apply to CY7C1270XV18. Read Operations The CY7C1268XV18 is organized internally as two arrays of 1 M × 18. Accesses are completed in a burst of 2 sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register. Following the next two K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the input clock (K and K). To maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K). Document Number: 001-70329 Rev. *E When read access is deselected, the CY7C1268XV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the output following the next rising edge of the negative input clock (K). This enables for a transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When the write access is deselected, the device ignores all inputs after the pending write operations have been completed. Byte Write Operations Byte write operations are supported by the CY7C1268XV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation. Page 6 of 28 CY7C1268XV18 CY7C1270XV18 DDR Operation The CY7C1268XV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and DDR mode of operation. The CY7C1268XV18 requires two No Operation (NOP) cycle during transition from a read to a write cycle. At higher frequencies, some applications require third NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information is stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a Posted write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR II+ Xtreme to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR II+ Xtreme. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR II+ Xtreme. The timing for the echo clocks is shown in the Switching Characteristics on page 22. Valid Data Indicator (QVLD) QVLD is provided on the DDR II+ Xtreme to simplify data capture on high speed systems. The QVLD is generated by the DDR II+ Xtreme device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. PLL Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5 × the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 100 s of stable clock. The PLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 100 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR I mode (with one cycle latency and a longer access time). For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+. Application Example Figure 2 shows two DDR II+ Xtreme used in an application. Figure 2. Application Example (Width Expansion) SRAM#1 DQ[x:0] A LD R/W ZQ CQ/CQ BWS K K RQ SRAM#2 DQ[x:0] A LD R/W ZQ CQ/CQ BWS K RQ K DQ[2x:0] ADDRESS LD R/W BWS CLKIN1/CLKIN1 CLKIN2/CLKIN2 SOURCE K SOURCE K FPGA / ASIC Document Number: 001-70329 Rev. *E Page 7 of 28 CY7C1268XV18 CY7C1270XV18 Truth Table The truth table for the CY7C1268XV18, and CY7C1270XV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W Write cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. L–H L L D(A) at K(t + 1) D(A+1) at K(t + 1) Read cycle: (2.5 cycle Latency) Load address; wait two and half cycles; read data on consecutive K and K rising edges. L–H L H Q(A) at K(t + 2) Q(A+1) at K(t + 3) NOP: No operation L–H H X High Z High Z Stopped X X Previous State Previous State Standby: Clock stopped DQ DQ Write Cycle Descriptions The write cycle description table for CY7C1268XV18 follows. [2, 8] BWS0 BWS1 K K L L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – Comments During the data portion of a write sequence CY7C1268XV18 both bytes (D[17:0]) are written into the device. L–H During the data portion of a write sequence: CY7C1268XV18 both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence: CY7C1268XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L–H During the data portion of a write sequence CY7C1268XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence CY7C1268XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. L–H During the data portion of a write sequence CY7C1268XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. Notes 2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device powers up deselected with the outputs in a tristate condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well. 7. Ensure that when clock is stopped K = K. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Is based on a write cycle that was initiated in accordance with the Truth Table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-70329 Rev. *E Page 8 of 28 CY7C1268XV18 CY7C1270XV18 Write Cycle Descriptions The write cycle description table for CY7C1270XV18 follows. [9, 10] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Notes 9. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 10. Is based on a write cycle that was initiated in accordance with the Truth Table on page 8. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-70329 Rev. *E Page 9 of 28 CY7C1268XV18 CY7C1270XV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8 V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Access Port Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram on page 12. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 16). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High Z state. TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-70329 Rev. *E Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 13. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The Boundary Scan Order on page 17 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 16. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 16. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. Page 10 of 28 CY7C1268XV18 CY7C1270XV18 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High Z condition. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Reserved Document Number: 001-70329 Rev. *E These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 11 of 28 CY7C1268XV18 CY7C1270XV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 PAUSE-DR 0 0 0 1 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-70329 Rev. *E Page 12 of 28 CY7C1268XV18 CY7C1270XV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range Parameter [12, 13, 14] Description Test Conditions Min Max Unit VOH1 Output HIGH voltage IOH =2.0 mA 1.4 – V VOH2 Output HIGH voltage IOH =100 A 1.6 – V VOL1 Output LOW voltage IOL = 2.0 mA – 0.4 V VOL2 Output LOW voltage IOL = 100 A – 0.2 V VIH Input HIGH voltage – VIL Input LOW voltage – IX Input and output load current GND VI VDD 0.65 × VDD VDD + 0.3 V –0.3 0.35 × VDD V –5 5 A Notes 12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 19. 13. Overshoot: VIH(AC) < VDD + 0.3 V (Pulse width less than tTCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tTCYC/2). 14. All Voltage referenced to Ground. Document Number: 001-70329 Rev. *E Page 13 of 28 CY7C1268XV18 CY7C1270XV18 TAP AC Switching Characteristics Over the Operating Range Parameter [15, 16] Description Min Max Unit 50 – ns tTCYC TCK clock cycle time tTF TCK clock frequency – 20 MHz tTH TCK clock HIGH 20 – ns tTL TCK clock LOW 20 – ns tTMSS TMS setup to TCK clock rise 5 – ns tTDIS TDI setup to TCK clock rise 5 – ns tCS Capture setup to TCK rise 5 – ns tTMSH TMS hold after TCK clock rise 5 – ns tTDIH TDI hold after clock rise 5 – ns tCH Capture hold after clock rise 5 – ns tTDOV TCK clock LOW to TDO valid – 10 ns tTDOX TCK clock LOW to TDO invalid 0 – ns Setup Times Hold Times Output Times Notes 15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns. Document Number: 001-70329 Rev. *E Page 14 of 28 CY7C1268XV18 CY7C1270XV18 TAP Timing and Test Conditions Figure 3 shows the TAP timing and test conditions. [17] Figure 3. TAP Timing and Test Conditions 0.9 V ALL INPUT PULSES 1.8 V 0.9 V 50 TDO 0V Z0 = 50 (a) Slew Rate = 1 V/ns CL = 20 pF tTH GND tTL Test Clock TCK tTMSH tTMSS tTCYC Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Note 17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns. Document Number: 001-70329 Rev. *E Page 15 of 28 CY7C1268XV18 CY7C1270XV18 Identification Register Definitions Value Instruction Field CY7C1268XV18 Revision number (31:29) Description CY7C1270XV18 000 000 Cypress device ID (28:12) 11010111000010100 11010111000100100 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. 1 1 Indicates the presence of an ID register. ID register presence (0) Version number. Defines the type of SRAM. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-70329 Rev. *E Page 16 of 28 CY7C1268XV18 CY7C1270XV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number: 001-70329 Rev. *E Page 17 of 28 CY7C1268XV18 CY7C1270XV18 Power Up Sequence in DDR II+ Xtreme SRAM PLL Constraints DDR II+ Xtreme SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. ■ PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The PLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 100 s of stable clock to relock to the desired clock frequency. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. ■ Provide stable DOFF (HIGH), power and clock (K, K) for 100 s to lock the PLL. Figure 4. Power Up Waveforms Document Number: 001-70329 Rev. *E Page 18 of 28 CY7C1268XV18 CY7C1270XV18 Maximum Ratings Operating Range Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Range Commercial Storage temperature ................................ –65 °C to +150 °C Ambient Temperature (TA) 0 °C to +70 °C VDD [19] VDDQ [19] 1.8 ± 0.1 V 1.4 V to 1.6 V Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD Neutron Soft Error Immunity DC applied to outputs in High Z ........–0.5 V to VDDQ + 0.3 V DC input voltage [18] ........................... –0.5 V to VDD + 0.3 V Current into outputs (LOW) ........................................ 20 mA Parameter Test Conditions Typ Max* Unit LSBU Logical Single-Bit Upsets 25 °C 260 271 FIT/ Mb LMBU Logical Multi-Bit Upsets 25 °C 0 0.01 FIT/ Mb Single Event Latch up 85 °C 0 0.1 FIT/ Dev Static discharge voltage (MIL-STD-883, M 3015) ......................................... > 2,001 V Latch up current ..................................................... > 200 mA Description Maximum Junction Temperature..................................125 °C SEL * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Electrical Characteristics Over the Operating Range DC Electrical Characteristics Over the Operating Range Parameter [20] Description Test Conditions Min Typ Max Unit VDD Power supply voltage 1.7 1.8 1.9 V VDDQ I/O supply voltage 1.4 1.5 1.6 V VOH Output HIGH voltage Note 21 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V VOL Output LOW voltage Note 22 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V VOH(LOW) Output HIGH voltage IOH =0.1 mA, Nominal impedance VDDQ – 0.2 – VDDQ V VOL(LOW) Output LOW voltage IOL = 0.1 mA, Nominal impedance VSS – 0.2 V VIH Input HIGH voltage VREF + 0.1 – VDDQ + 0.15 V VIL Input LOW voltage –0.15 – VREF – 0.1 V IX Input leakage current GND VI VDDQ 2 – 2 A IOZ Output leakage current GND VI VDDQ, Output disabled 2 – 2 A Input reference voltage Typical value = 0.75 V 0.68 0.75 0.86 V VDD operating supply VDD = Max, IOUT = 0 mA, 633 MHz (× 18) f = fMAX = 1/tCYC (× 36) – – 965 mA – – 1230 600 MHz (× 18) – – 910 (× 36) – – 1165 VREF IDD [23] mA Notes 18. Overshoot: VIH(AC) < VDDQ + 0.3 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 19. Power up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ VDD. 20. All Voltage referenced to Ground. 21. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 22. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 23. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-70329 Rev. *E Page 19 of 28 CY7C1268XV18 CY7C1270XV18 Electrical Characteristics (continued) Over the Operating Range DC Electrical Characteristics (continued) Over the Operating Range Parameter [20] ISB1 Description Automatic power down current Test Conditions Max VDD, Both ports deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC, Inputs Static Min Typ Max Unit 633 MHz (× 18) – – 965 mA (× 36) – – 1230 600 MHz (× 18) – – 910 (× 36) – – 1165 Min Typ Max Unit mA AC Electrical Characteristics Over the Operating Range Parameter [24] Description Test Conditions VIH Input HIGH voltage VREF + 0.2 – VDDQ + 0.24 V VIL Input LOW voltage –0.24 – VREF – 0.2 V Max Unit Capacitance Parameter [25] Description CIN Input capacitance CO Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V 4 pF 4 pF Thermal Resistance Parameter [25] JA (0 m/s) JA (1 m/s) Description Thermal resistance (junction to ambient) Test Conditions Socketed on a 170 × 220 × 2.35 mm, eight-layer printed circuit board JA (3 m/s) 165-ball FBGA Unit Package 14.43 °C/W 13.40 °C/W 12.66 °C/W JB Thermal resistance (junction to board) 11.38 °C/W JC Thermal resistance (junction to case) 3.30 °C/W Notes 24. Overshoot: VIH(AC) < VDDQ + 0.3 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 25. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-70329 Rev. *E Page 20 of 28 CY7C1268XV18 CY7C1270XV18 AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms VREF = 0.75 V VREF 0.75 V VREF OUTPUT Z0 = 50 Device Under Test ZQ RL = 50 R = 50 ALL INPUT PULSES 1.25 V 0.75 V OUTPUT Device Under VREF = 0.75 V Test ZQ RQ = 250 (a) 0.75 V INCLUDING JIG AND SCOPE 5 pF [26] 0.25 V Slew Rate = 2 V/ns RQ = 250 (b) Note 26. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5. Document Number: 001-70329 Rev. *E Page 21 of 28 CY7C1268XV18 CY7C1270XV18 Switching Characteristics Over the Operating Range Parameters [27, 28] Cypress Parameter 633 MHz Description Consortium Parameter Min VDD (typical) to the first access [29] tPOWER Max 600 MHz Min Max Unit 1 – 1 – ms tCYC tKHKH K clock cycle time 1.58 8.4 1.66 8.4 ns tKH tKHKL Input clock (K/K) HIGH 0.4 – 0.4 – ns tKL tKLKH Input clock (K/K) LOW 0.4 – 0.4 – ns tKHKH tKHKH K clock rise to K clock rise (rising edge to rising edge) 0.71 – 0.75 – ns tSA tAVKH Address setup to K clock rise 0.23 – 0.23 – ns tSC tIVKH Control setup to K clock rise (LD, R/W) 0.23 – 0.23 – ns tSCDDR tIVKH Double data rate control setup to clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) 0.18 – 0.18 – ns tSD tDVKH D[X:0] setup to clock (K/K) rise 0.18 – 0.18 – ns tHA tKHAX Address hold after K clock rise 0.23 – 0.23 – ns tHC tKHIX Control hold after K clock rise (LD, R/W) 0.23 – 0.23 – ns tHCDDR tKHIX Double data rate control hold after clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) 0.18 – 0.18 – ns tHD tKHDX D[X:0] hold after clock (K/K) rise 0.18 – 0.18 – ns tCCQO tCHCQV K/K clock rise to echo clock valid tCQOH tCHCQX Echo clock hold after K/K clock rise tCQD tCQHQV Echo clock high to data valid tCQDOH tCQHQX tCQH tCQHCQL Setup Times Hold Times Output Times tCQHCQH tCQHCQH – 0.45 – 0.45 ns –0.45 – –0.45 – ns – 0.09 – 0.09 ns Echo clock high to data invalid –0.09 – –0.09 – ns Output clock (CQ/CQ) HIGH [30] 0.71 – 0.75 – ns 0.71 – 0.75 – ns CQ clock rise to CQ clock rise (rising edge to rising edge) tCHZ tCHQZ Clock (K/K) rise to high Z (active to high Z) tCLZ tCHQX1 Clock (K/K) rise to low Z [31, 32] tQVLD [33] [31, 32] [30] – 0.45 – 0.45 ns –0.45 – –0.45 – ns –0.15 0.15 –0.15 0.15 ns tCQHQVLD Echo clock high to QVLD valid tKC Var tKC Var Clock phase jitter – 0.15 – 0.15 ns tKC lock tKC lock PLL lock time (K) 100 – 100 – s tKC Reset tKC Reset K static to PLL reset [34] 30 – 30 – ns PLL Timing Notes 27. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 21. 28. When a part with a maximum frequency above 600 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 29. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(min) initially before a read or write operation can be initiated. 30. These parameters are extrapolated from the input timing parameters (tCYC/2 – 80 ps, where 80 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 31. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 21. Transition is measured 100 mV from steady-state voltage. 32. At any voltage and temperature tCHZ is less than tCLZ. 33. tQVLD specification is applicable for both rising and falling edges of QVLD signal. 34. Hold to >VIH or <VIL. Document Number: 001-70329 Rev. *E Page 22 of 28 CY7C1268XV18 CY7C1270XV18 Switching Waveforms Read/Write/Deselect Sequence Figure 6. Waveform for 2.5 Cycle Read Latency [35, 36, 37] NOP 1 READ 2 READ 3 NOP 5 NOP 4 WRITE 7 NOP 6 WRITE 8 READ 9 NOP 10 NOP 11 12 K t KH t KHKH tCYC t KL K LD tSC t HC R/W A A0 t SA t HA A1 A2 t QVLD t QVLD A3 A4 t QVLD QVLD tHD t HD tSD Q00 DQ Q01 Q10 Q11 D20 D21 D30 D31 Q40 tCHZ tCLZ (Read Latency = 2.5 Cycles) tSD t CQ D t CCQO t CQDOH t CQOH CQ t CQOH t CCQO tCQH tCQHCQH CQ D O N’T CA RE U N D EFIN ED Notes 35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1. 36. Outputs are disabled (High Z) one clock cycle after a NOP. 37. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-70329 Rev. *E Page 23 of 28 CY7C1268XV18 CY7C1270XV18 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 633 Package Diagram Part and Package Type Operating Range CY7C1268XV18-633BZXC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Commercial CY7C1270XV18-633BZXC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Ordering Code Ordering Code Definitions CY 7 C 12XX X V18 - XXX BZ X X Temperature Range: X = C C = Commercial; Pb-free Package Type: BZ = 165-ball FBGA Frequency Range: XXX = 633 MHz V18 = 1.8 V Die Revision X = Xtreme Part Identifier 12XX = 1268 (2 M × 18) or 1270 (1 M × 36) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-70329 Rev. *E Page 24 of 28 CY7C1268XV18 CY7C1270XV18 Package Diagram Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *G Document Number: 001-70329 Rev. *E Page 25 of 28 CY7C1268XV18 CY7C1270XV18 Acronyms Acronym Document Conventions Description Units of Measure DDR Double Data Rate EIA Electronic Industries Alliance °C degree Celsius FBGA Fine-Pitch Ball Grid Array k kilohm HSTL High-Speed Transceiver Logic MHz megahertz I/O Input/Output µA microampere JEDEC Joint Electron Devices Engineering Council µs microsecond JTAG Joint Test Action Group mV millivolt LSB Least Significant Bit mA milliampere LMBU Logical Multi-Bit Upsets ms millisecond LSBU Logical Single-Bit Upsets mm millimeter MSB Most Significant Bit ns nanosecond PLL Phase-Locked Loop ohm SEL Single Event Latch-up % percent SRAM Static Random Access Memory pF picofarad TAP Test Access Port V volt TCK Test Clock W watt TDI Test Data-In TDO Test Data-Out TMS Test Mode Select Document Number: 001-70329 Rev. *E Symbol Unit of Measure Page 26 of 28 CY7C1268XV18 CY7C1270XV18 Document History Page Document Title: CY7C1268XV18/CY7C1270XV18, 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-70329 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 3377091 VIDB 09/20/2011 New data sheet. *A 3532213 PRIT / GOPA 02/22/2012 Changed status from Preliminary to Final. *B 3774109 PRIT 10/11/2012 Updated Application Example (Updated Figure 2). Updated TAP Electrical Characteristics (Updated Note 13). Updated TAP AC Switching Characteristics (Updated Note 16). Updated TAP Timing and Test Conditions (Updated Note 17 and updated Figure 3). Updated Thermal Resistance (Changed value of JA parameter from 26.65 °C/W to 14.84 °C/W for 165-ball FBGA Package, changed value of JC parameter from 4.31 °C/W to 5.1 °C/W for 165-ball FBGA Package). Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)). *C 4441399 PRIT 07/14/2014 Updated Application Example: Updated Figure 2. Updated Thermal Resistance: Updated values of JA and JC parameters. Included JB parameter and its details. Updated to new template. *D 4574060 PRIT 11/19/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *E 4976464 PRIT 10/20/2015 Updated Ordering Information: Updated part numbers. Updated Package Diagram: spec 51-85180 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. Document Number: 001-70329 Rev. *E Page 27 of 28 CY7C1268XV18 CY7C1270XV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-70329 Rev. *E Revised October 20, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 28 of 28