CY7C1381D
CY7C1383D
CY7C1383F
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
Functional Description
■
Supports 133 MHz bus operations
■
512K × 36 and 1M × 18 common I/O
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O supply (VDDQ)
■
Fast clock-to-output time
❐ 6.5 ns (133 MHz version)
■
Provides high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
CY7C1381D available in JEDEC-standard Pb-free 100-pin
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
CY7C1383D available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1383F available in non Pb-free 165-ball FBGA
package.
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
ZZ sleep mode option
The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V,
512K × 36 and 1M × 18 synchronous flow through SRAMs,
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWx, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1381D/CY7C1383D/CY7C1383F allows interleaved
or linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be initiated
with the processor address strobe (ADSP) or the cache
controller address strobe (ADSC) inputs. Address advancement
is controlled by the address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
CY7C1381D/CY7C1383D/CY7C1383F operates from a +3.3 V
core power supply while all outputs operate with a +2.5 V or
+3.3 V supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
Description
6.5
8.5
ns
Maximum Operating Current
210
175
mA
Maximum CMOS Standby Current
70
70
mA
Errata: For information on silicon errata, see “Errata” on page 32. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05544 Rev. *U
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 25, 2016
Not Recommended for New Designs.
Features
CY7C1381D
CY7C1383D
CY7C1383F
Logic Block Diagram – CY7C1381D
(512K × 36) [1]
ADDRESS
REGISTER
A0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
DQ D , DQP D
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQ C , DQP C
DQ C , DQP C
BW C
WRITE REGISTER
WRITE REGISTER
DQ B , DQP B
MEMORY
ARRAY
DQ B , DQP B
BW B
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQP C
WRITE REGISTER
DQP D
WRITE REGISTER
DQ A , DQP
DQ A , DQP
BW A
BYTE
A
WRITE REGISTER
BYTE
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
Logic Block Diagram – CY7C1383D/CY7C1383F
(1M × 18) [1]
A0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
ADV
Q0
DQ B ,DQP B
BW B
DQ A ,DQP A
BW A
DQ B ,DQP B
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A ,DQP A
WRITE DRIVER
BWE
GW
CE 1
CE 2
CE 3
ENABLE
INPUT
REGISTERS
OE
SLEEP
CONTROL
Note
1. CY7C1383F have only 1 chip enable (CE1).
Document Number: 38-05544 Rev. *U
Page 2 of 37
Not Recommended for New Designs.
BW D
CY7C1381D
CY7C1383D
CY7C1383F
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Single Write Accesses Initiated by ADSP ................... 8
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Truth Table for Read/Write ............................................ 11
Truth Table for Read/Write ............................................ 11
IEEE 1149.1 Serial Boundary Scan (JTAG [14]) ........... 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 12
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 17
3.3 V TAP AC Output Load Equivalent ......................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Identification Register Definitions ................................ 18
Document Number: 38-05544 Rev. *U
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Timing Diagrams ............................................................ 24
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Errata ............................................................................... 32
Part Numbers Affected .............................................. 32
Product Status ........................................................... 32
Ram9 Sync ZZ Pin
& JTAG Issues Errata Summary ...................................... 32
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 37
Worldwide Sales and Design Support ....................... 37
Products .................................................................... 37
PSoC® Solutions ...................................................... 37
Cypress Developer Community ................................. 37
Technical Support ..................................................... 37
Page 3 of 37
Not Recommended for New Designs.
Contents
CY7C1381D
CY7C1383D
CY7C1383F
Pin Configurations
CY7C1383D
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see “Errata” on page 32.
Document Number: 38-05544 Rev. *U
Page 4 of 37
Not Recommended for New Designs.
NC
NC
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1381D
(512K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
VSS/DNU
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enable) [2]
CY7C1381D
CY7C1383D
CY7C1383F
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3 Chip Enable) [3, 4]
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
1
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
R
VDDQ
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A
A1
VSS
NC
TDO
A
A
A
A
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
CY7C1383F (1M × 18)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
BWB
NC
CE3
BWE
ADSC
ADV
A
A
NC/144M
A
CE2
NC
BWA
CLK
GW
OE
ADSP
A
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC/1G
NC
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
NC
DQA
NC
VSS
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
R
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
VSS
NC/576M
DQPA
DQA
Notes
3. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see “Errata” on page 32.
4. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 32.
Document Number: 38-05544 Rev. *U
Page 5 of 37
Not Recommended for New Designs.
CY7C1381D (512K × 36)
CY7C1381D
CY7C1383D
CY7C1383F
Pin Definitions
Name
A0, A1, A
I/O
Description
Input
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
Input
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWA, BWB,
BWC, BWD Synchronous on the rising edge of CLK.
CLK
Input
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is
Synchronous conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
Input
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
Input
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
Input
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Input
Asynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
s
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments
Synchronous the address in a burst cycle.
ADSP
Input
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
Input
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
Input
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
ZZ [5]
ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition with data
Input
Asynchronou integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal
s
pull down.
DQs
I/O
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/O
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
Note
5. Errata: The ZZ pin needs to be externally connected to ground. For more information, see “Errata” on page 32.
Document Number: 38-05544 Rev. *U
Page 6 of 37
Not Recommended for New Designs.
GW
CY7C1381D
CY7C1383D
CY7C1383F
Pin Definitions (continued)
Name
MODE
Description
Input Static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull-up.
Power Supply Power supply inputs to the core of the device.
VDDQ
VSS
I/O Power
Supply
Power supply for the I/O circuitry.
Ground
Ground for the core of the device.
I/O Ground
VSSQ
[6]
Ground for the I/O circuitry.
JTAG Serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
Output
not being used, this pin can be left unconnected. This pin is not available on TQFP packages.
Synchronous
TDI [6]
JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
Input
used, this pin can be left floating or connected to VDD through a pull-up resistor. This pin is not available
Synchronous on TQFP packages.
TMS [6]
JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
Input
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK [6]
NC
VSS/DNU
JTAG
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
–
No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
Ground/DNU This pin can be connected to ground or can be left floating.
Note
6. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 32.
Document Number: 38-05544 Rev. *U
Page 7 of 37
Not Recommended for New Designs.
VDD
TDO
I/O
CY7C1381D
CY7C1383D
CY7C1383F
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133 MHz device).
CY7C1381D/CY7C1383D/CY7C1383F supports secondary
cache in systems using a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that use a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with the processor address strobe
(ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter and/or
control logic, and later presented to the memory core. If the OE
input is asserted LOW, the requested data is available at the data
outputs with a maximum to tCDV after clock rise. ADSP is ignored
if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table for Read/Write on
Document Number: 38-05544 Rev. *U
page 11 for appropriate states that indicate a write) on the next
clock rise, the appropriate data is latched and written into the
device. Byte writes are allowed. All I/O are tristated during a byte
write. As this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered to
the memory core The information presented to DQ[A:D] is written
into the specified address location. Byte writes are allowed. All
I/O are tristated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
Burst Sequences
CY7C1381D/CY7C1383D/CY7C1383F provides an on-chip
two-bit wraparound burst counter inside the SRAM. The burst
counter is fed by A[1:0], and can follow either a linear or
interleaved burst order. The burst order is determined by the
state of the MODE input. A LOW on MODE selects a linear burst
sequence. A HIGH on MODE selects an interleaved burst order.
Leaving MODE unconnected causes the device to default to a
interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Page 8 of 37
Not Recommended for New Designs.
Functional Overview
CY7C1381D
CY7C1383D
CY7C1383F
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05544 Rev. *U
Page 9 of 37
Not Recommended for New Designs.
Interleaved Burst Address Table
CY7C1381D
CY7C1383D
CY7C1383F
Truth Table
The truth table for CY7C1381D/CY7C1383D/CY7C1383F follows. [7, 8, 9, 10, 11]
Address Used CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
X
X
X
L
H
L
X
X
X
L–H Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
Q
Q
Notes
7. X = Don't Care, H = Logic HIGH, L = Logic LOW.
8. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
9. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
10. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the
remainder of the write cycle.
11. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05544 Rev. *U
Page 10 of 37
Not Recommended for New Designs.
Cycle Description
CY7C1381D
CY7C1383D
CY7C1383F
Truth Table for Read/Write
Function (CY7C1381D)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
H
L
L
L
H
L
Truth Table for Read/Write
The truth table for CY7C1383D/CY7C1383F read/write follows. [12, 13]
Function (CY7C1383D/CY7C1383F)
GW
BWE
BWB
BWA
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Notes
12. X=Don't Care, H = Logic HIGH, L = Logic LOW.
13. The table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 38-05544 Rev. *U
Page 11 of 37
Not Recommended for New Designs.
The truth table for CY7C1381D read/write follows. [12, 13]
CY7C1381D
CY7C1383D
CY7C1383F
The CY7C1381D/CY7C1383F incorporates a serial boundary
scan test access port (TAP). This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V
I/O logic levels.
CY7C1381D/CY7C1383F contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
may be left unconnected. At power up, the device comes up in a
reset state, which does not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI ball on
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 19 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 18.
Note
14. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 32.
Document Number: 38-05544 Rev. *U
Page 12 of 37
Not Recommended for New Designs.
IEEE 1149.1 Serial Boundary Scan (JTAG [14])
CY7C1381D
CY7C1383D
CY7C1383F
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state, when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction when it is shifted in, the TAP controller needs to
be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.
IDCODE
BYPASS
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
EXTEST Output Bus Tri-State
SAMPLE Z
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tristate,” is latched into the preload register
during the Update-DR state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a high Z condition.
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a high Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
Document Number: 38-05544 Rev. *U
IEEE standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 37
Not Recommended for New Designs.
TAP Instruction Set
CY7C1381D
CY7C1383D
CY7C1383F
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
EXIT1-DR
0
1
Not Recommended for New Designs.
0
0
1
0
The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05544 Rev. *U
Page 14 of 37
CY7C1381D
CY7C1383D
CY7C1383F
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
. 2 1 0
Selection
Circuitry
TDO
Identification Register
x .
.
.
.
. 2 1 0
Not Recommended for New Designs.
Boundary Scan Register
TCK
TMS
Document Number: 38-05544 Rev. *U
TAP CONTROLLER
Page 15 of 37
CY7C1381D
CY7C1383D
CY7C1383F
TAP Timing
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
t CYC
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH Time
20
–
ns
tTL
TCK Clock LOW Time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05544 Rev. *U
Page 16 of 37
Not Recommended for New Designs.
Test Mode Select
CY7C1381D
CY7C1383D
CY7C1383F
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels ............................................... VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50 Ω
Z O= 50 Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [17]
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Test Conditions
Max
Unit
IOH = –4.0 mA
VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA
VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 8.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Min
GND < VIN < VDDQ
Note
17. All voltages referenced to VSS (GND).
Document Number: 38-05544 Rev. *U
Page 17 of 37
Not Recommended for New Designs.
1.25V
CY7C1381D
CY7C1383D
CY7C1383F
Identification Register Definitions
CY7C1383F
(1M × 18)
Revision Number (31:29)
000
000
Device Depth (28:24) [18]
01011
01011
000001
000001
Device Width (23:18) 165-ball FBGA
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
Describes the version number.
Reserved for internal use.
100101
010101
00000110100
00000110100
1
1
ID Register Presence Indicator (0)
Description
Defines the memory type and
architecture.
Defines the width and density.
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction Bypass
Bit Size (× 36)
Bit Size (× 18)
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (165-ball FBGA package)
89
89
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to high Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation.
RESERVED
101
Do Not Use. This instruction is reserved for future use.
RESERVED
110
Do Not Use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
18. Bit #24 is “1” in the register definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05544 Rev. *U
Page 18 of 37
Not Recommended for New Designs.
CY7C1381D
(512K × 36)
Instruction Field
CY7C1381D
CY7C1383D
CY7C1383F
Boundary Scan Order
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
89
Internal
29
F10
59
E1
30
E10
60
F1
Notes
19. Balls which are NC (No Connect) are pre-set LOW.
20. Bit# 89 is pre-set HIGH.
Document Number: 38-05544 Rev. *U
Page 19 of 37
Not Recommended for New Designs.
165-ball FBGA [19, 20]
CY7C1381D
CY7C1383D
CY7C1383F
Operating Range
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Range
Ambient
Temperature
Storage Temperature ............................... –65 °C to +150 °C
Commercial
0 °C to +70 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Industrial
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
–40 °C to +85 °C
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Neutron Soft Error Immunity
Test
Parameter Description Conditions
Typ Max [21] Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
361
394
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25 °C
0
0.01
FIT/
Mb
Single Event
Latch Up
85 °C
0
0.1
FIT/
Dev
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
VDD
SEL
Electrical Characteristics
Over the Operating Range
Parameter [22, 23]
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage [22]
Test Conditions
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
–
0.4
V
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
[22]
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
VIL
Input LOW Voltage
–0.3
0.7
V
IX
Input Leakage Current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input Current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Input Current of ZZ
IOZ
Output Leakage Current
GND VI VDD, Output Disabled
–5
5
A
IDD
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
–
210
mA
10 ns cycle,
100 MHz
–
175
mA
Notes
21. No LMBU or SEL events occurred during testing; this column represents a statistical c2, 95% confidence limit calculation. For more details refer to Application Note
AN54908, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates.
22. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
23. Tpower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05544 Rev. *U
Page 20 of 37
Not Recommended for New Designs.
Maximum Ratings
CY7C1381D
CY7C1383D
CY7C1383F
Electrical Characteristics (continued)
Parameter [22, 23]
Description
Automatic CE power-down
Current – TTL Inputs
ISB1
Test Conditions
Max VDD, Device Deselected,
VIN VIH or VIN VIL, f = fMAX,
inputs switching
Min
Max
Unit
7.5 ns cycle,
133 MHz
–
140
mA
10 ns cycle,
100 MHz
–
120
ISB2
Automatic CE power-down
Current – CMOS Inputs
Max VDD, Device Deselected,
All speeds
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, inputs static
–
70
mA
ISB3
Automatic CE power-down
Current – CMOS Inputs
7.5 ns cycle,
Max VDD, Device Deselected,
VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz
f = fMAX, inputs switching
10 ns cycle,
100 MHz
–
130
mA
–
110
–
80
ISB4
Automatic CE power-down
Current – TTL Inputs
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, inputs static
All Speeds
mA
Capacitance
Parameter [24]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP 165-ball FBGA Unit
Package
Package
5
9
pF
5
9
pF
5
9
pF
Thermal Resistance
Parameter [24]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
100-pin TQFP 165-ball FBGA Unit
Package
Package
28.66
20.7
°C/W
4.08
4.0
°C/W
Note
24. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05544 Rev. *U
Page 21 of 37
Not Recommended for New Designs.
Over the Operating Range
CY7C1381D
CY7C1383D
CY7C1383F
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
VT = 1.5 V
(a)
INCLUDING
JIG AND
SCOPE
Z0 = 50
VT = 1.25 V
(a)
Document Number: 38-05544 Rev. *U
R = 351
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
1 ns
(b)
GND
5 pF
R = 1538
(b)
90%
10%
90%
1 ns
R = 1667
2.5 V
OUTPUT
RL = 50
GND
5 pF
2.5 V I/O Test Load
OUTPUT
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
Page 22 of 37
Not Recommended for New Designs.
3.3 V I/O Test Load
CY7C1381D
CY7C1383D
CY7C1383F
Switching Characteristics
Over the Operating Range
Parameter [25, 26]
tPOWER
Description
VDD(typical) to the first access [27]
133 MHz
100 MHz
Unit
Min
Max
Min
Max
1
–
1
–
ms
tCYC
Clock cycle time
7.5
–
10
–
ns
tCH
Clock HIGH
2.1
–
2.5
–
ns
tCL
Clock LOW
2.1
–
2.5
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
–
8.5
ns
tDOH
Data output hold after CLK rise
2.0
–
2.0
–
ns
2.0
–
2.0
–
ns
0
4.0
0
5.0
ns
–
3.2
–
3.8
ns
0
–
0
–
ns
–
4.0
–
5.0
ns
[28, 29, 30]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [28, 29, 30]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[28, 29, 30]
OE HIGH to output high Z
[28, 29, 30]
Setup Times
tAS
Address setup before CLK rise
1.5
–
1.5
–
ns
tADS
ADSP, ADSC setup before CLK rise
1.5
–
1.5
–
ns
tADVS
ADV setup before CLK rise
1.5
–
1.5
–
ns
tWES
GW, BWE, BW[A:D] setup before CLK rise
1.5
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
1.5
–
ns
tCES
Chip enable setup
1.5
–
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
0.5
–
ns
tWEH
GW, BWE, BW[A:D] hold after CLK rise
0.5
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
0.5
–
ns
Hold Times
Notes
25. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
26. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.
27. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be
initiated.
28. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ±200 mV from steady-state voltage
29. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system condition.
30. This parameter is sampled and not 100% tested.
Document Number: 38-05544 Rev. *U
Page 23 of 37
Not Recommended for New Designs.
Clock
CY7C1381D
CY7C1383D
CY7C1383F
Timing Diagrams
Figure 5. Read Cycle Timing [31]
tCYC
CLK
t
t ADS
CH
t CL
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
X
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
31. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05544 Rev. *U
Page 24 of 37
Not Recommended for New Designs.
ADSP
CY7C1381D
CY7C1383D
CY7C1383F
Timing Diagrams (continued)
Figure 6. Write Cycle Timing [32, 33]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
32. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
33. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 38-05544 Rev. *U
Page 25 of 37
Not Recommended for New Designs.
t ADS
CY7C1381D
CY7C1383D
CY7C1383F
Timing Diagrams (continued)
Figure 7. Read/Write Cycle Timing [34, 35, 36]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSC
t AS
A1
ADDRESS
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
tCDV
Q(A4)
Q(A2)
Back-to-Back READs
Single WRITE
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
DON’T CARE
Back-to-Back
WRITEs
UNDEFINED
Notes
34. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
35. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
36. GW is HIGH.
Document Number: 38-05544 Rev. *U
Page 26 of 37
Not Recommended for New Designs.
ADSP
CY7C1381D
CY7C1383D
CY7C1383F
Timing Diagrams (continued)
Figure 8. ZZ Mode Timing [37, 38]
CLK
t
ZZ
ZZREC
ZZI
SUPPLY
I
DDZZ
t
ALL INPUTS
(except ZZ)
Outputs (Q)
RZZI
Not Recommended for New Designs.
I
t
t
ZZ
DESELECT or READ Only
High-Z
DON’T CARE
Notes
37. Device must be deselected when entering ZZ mode. See Truth Table on page 10 for all possible signal conditions to deselect the device.
38. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05544 Rev. *U
Page 27 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit
us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Ordering Code
CY7C1381D-133AXC [39]
MPN
Status
Package
Diagram
NRND
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Part and Package Type
Operating
Range
Commercial
CY7C1381D-133AXI [39]
CY7C1383D-133AXI
100
lndustrial
[39]
CY7C1381D-100AXC [39]
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1381D-100BZI [39]
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
CY7C1381D-100BZXI
[39]
Commercial
lndustrial
165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Ordering Code Definitions
CY
7
C 138X X - XXX XX
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Frequency Range: XXX = 133 MHz or 100 MHz
Die Revision: X = D or F
D 90 nm
F errata fix PCN084636
Part Identifier: 138X = 1381 or 1383
1381 = FT, 512Kb × 36 (18Mb)
1383 = FT, 1Mb × 36 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Note
39. These MPNs are not recommended for new designs.
Document Number: 38-05544 Rev. *U
Page 28 of 37
Not Recommended for New Designs.
CY7C1383D-133AXC [39]
CY7C1381D
CY7C1383D
CY7C1383F
Package Diagrams
Not Recommended for New Designs.
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 38-05544 Rev. *U
Page 29 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Package Diagrams (continued)
Not Recommended for New Designs.
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 38-05544 Rev. *U
Page 30 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
EIA
Electronic Industries Alliance
MHz
megahertz
FBGA
Fine-Pitch Ball Grid Array
µA
microampere
I/O
Input/Output
mA
milliampere
JEDEC
Joint Electron Devices Engineering Council
mm
millimeter
JTAG
Joint Test Action Group
ms
millisecond
LMBU
Logical Multi-Bit Upsets
mV
millivolt
LSB
Least Significant Bit
ns
nanosecond
LSBU
Logical Single-Bit Upsets
MSB
Most Significant Bit
OE
Output Enable
SEL
Single Event Latch Up
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
Document Number: 38-05544 Rev. *U
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Not Recommended for New Designs.
Acronyms
Page 31 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Errata
This section describes the Ram9 Sync ZZ pin and JTAG issues. Details include trigger conditions, the devices affected, proposed
workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
18Mb-Ram9 Synchronous SRAMs: CY7C138*D, CY7C138*F
100-pin TQFP
Commercial/
Industrial
165-ball FBGA
Industrial
All of the devices in the Ram9 18Mb Sync family are qualified and available in production quantities.
Ram9 Sync ZZ Pin & JTAG Issues Errata Summary
The following table defines the errata applicable to available Ram9 18Mb Sync family devices.
Item
Issues
Description
Device
Fix Status
1.
ZZ Pin
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
18M-Ram9 (90 nm)
For the 18M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
2.
JTAG
Functionality
During JTAG test mode, the Boundary scan
circuitry does not perform as described in the
datasheet.However, it is possible to perform
the JTAG test with these devices in “BYPASS
mode”.
18M-Ram9 (90 nm)
This issue will be fixed in the
new revision, which use the
65 nm technology. Please
contact your local sales rep for
availability.
Document Number: 38-05544 Rev. *U
Page 32 of 37
Not Recommended for New Designs.
Product Status
CY7C1381D
CY7C1383D
CY7C1383F
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
For the 18M Ram9 (90 nm) devices, there is no plan to fix this issue.
2. JTAG Functionality
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the JTAG test mode.During this mode, the JTAG circuitry can perform
incorrectly by delivering the incorrect data or the incorrect scan chain length.
■
TRIGGER CONDITIONS
Several conditions can trigger this failure mode.
1. The device can deliver an incorrect length scan chain when operating in JTAG mode.
2. Some Byte Write inputs only recognize a logic HIGH level when in JTAG mode.
3. Incorrect JTAG data can be read from the device when the ZZ input is tied HIGH during JTAG operation.
■
SCOPE OF IMPACT
The device fails for JTAG test. This does not impact the normal functionality of the device.
■
WORKAROUND
1.Perform JTAG testing with these devices in “BYPASS mode”.
2.Do not use JTAG test.
■
FIX STATUS
This issue will be fixed in the new revision, which use the 65 nm technology. Please contact your local sales rep for availability.
Document Number: 38-05544 Rev. *U
Page 33 of 37
Not Recommended for New Designs.
1. ZZ Pin Issue
CY7C1381D
CY7C1383D
CY7C1383F
Document History Page
Document Title: CY7C1381D/CY7C1383D/CY7C1383F, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
Document Number: 38-05544
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
254518
RKF
See ECN
New data sheet.
*A
288531
SYT
See ECN
Updated Features (Removed 117 MHz speed bin).
Updated Selection Guide (Removed 117 MHz speed bin).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [14]) (Edited description
for non-compliance with 1149.1)
Updated Electrical Characteristics (Removed 117 MHz speed bin).
Updated Switching Characteristics (Removed 117 MHz speed bin).
Updated Ordering Information (Added Pb-free information for 100-pin TQFP,
119-ball BGA and 165-ball FBGA package) and added comment of ‘Pb-free
BG packages availability’ below the Ordering Information.
*B
326078
PCI
See ECN
Changed status from Preliminary to Final.
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified as per JEDEC standard).
Updated TAP Instruction Set (Changed description of OVERVIEW and
EXTEST sub-sections, added a sub-section EXTEST Output Bus Tri-State).
Updated Identification Register Definitions (Splitted Device Width (23:18) row
into two rows Device Width (23:18) 119-ball BGA and another row Device Width
(23:18) 165-ball FBGA).
Updated Electrical Characteristics (Modified test conditions for VOL, VOH
parameters).
Updated Thermal Resistance (Changed JA for 100-pin TQFP Package from
31 C/W to 28.66 C/W, changed JC for 100-pin TQFP Package from 6 C/W
to 4.08 C/W, changed JA for 119-ball BGA Package from 45 C/W to
23.8 C/W, changed JC for 119-ball BGA Package from 7 C/W to 6.2 C/W,
changed JA for 165-ball FBGA Package from 46 C/W to 20.7 C/W, changed
JC for 165-ball FBGA Package from 3 C/W to 4.0 C/W).
Updated Ordering Information (Updated part numbers) and removed comment
of ‘Pb-free BG packages availability’ below the Ordering Information.
*C
351895
PCI
See ECN
Updated Ordering Information (Updated part numbers).
*D
416321
NXR
See ECN
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Updated Electrical Characteristics (Changed description of IX parameter from
Input Load Current to Input Leakage Current, changed the minimum value of
IX parameter corresponding to Input Current of MODE from –5 A to –30 A,
changed the maximum value of IX parameter corresponding to Input Current
of MODE from 30 A to 5 A, changed the minimum value of IX parameter
corresponding to Input Current of ZZ from –30 A to –5 A, changed the
minimum value of IX parameter corresponding to Input Current of ZZ from 5 A
to 30 A, Changed VIH < VDD to VIH < VDD in Note 23).
Updated Ordering Information (Updated part numbers) and replaced Package
Name column with Package Diagram in the Ordering Information table.
*E
475009
VKN
See ECN
Updated TAP AC Switching Characteristics (Changed the minimum values of
tTH, tTL parameters from 25 ns to 20 ns and changed the maximum value of
tTDOV parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*F
776456
VKN
See ECN
Added part numbers CY7C1381F and CY7C1383F and its related information.
Added Note 1 regarding Chip Enable.
Updated Ordering Information (Updated part numbers).
Document Number: 38-05544 Rev. *U
Page 34 of 37
Not Recommended for New Designs.
Description of Change
CY7C1381D
CY7C1383D
CY7C1383F
Document History Page (continued)
Document Title: CY7C1381D/CY7C1383D/CY7C1383F, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
Document Number: 38-05544
Rev.
ECN No.
Orig. of
Change
Submission
Date
*G
2752731
VKN /
PYRS
08/17/09
*H
2897182
NJY
03/22/2010
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
*I
3159479
NJY
02/01/2011
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
*J
3192403
NJY
03/10/2011
Updated to new template.
*K
3210400
NJY
03/30/2011
Updated Ordering Information (Removed pruned part CY7C1381F-133BGC).
*L
3440174
NJY
11/16/2011
Updated Ordering Information (Added two part numbers CY7C1383D-133AXC
and CY7C1383D-133AXI).
*M
3489571
NJY
01/10/2012
Updated Ordering Information (Added part number CY7C1383F-133BZI).
Updated Package Diagrams.
*N
3578427
PRIT
04/11/2012
Updated Features (Removed CY7C1381F related information, removed
119-ball BGA package related information, removed 165-ball FBGA package
related information for CY7C1383D, added 165-ball FBGA package related
information for CY7C1383F).
Updated Functional Description (Removed CY7C1381F related information,
removed the Note “For best practices or recommendations, refer to the
Cypress application note AN1064, SRAM System Design Guidelines on
www.cypress.com.” and its reference, removed the Note “CE3, CE2 are for
100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only
in 1 chip enable.”).
Updated Logic Block Diagram – CY7C1381D (Removed CY7C1381F related
information).
Updated Pin Configurations (Removed CY7C1381F related information,
removed 119-ball BGA package related information, removed 165-ball FBGA
package related information for CY7C1383D, added 165-ball FBGA package
related information for CY7C1383F).
Updated Pin Definitions (Removed the Note “CE3, CE2 are for 100-pin TQFP
and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip
enable.” and its reference).
Updated Functional Overview (Removed CY7C1381F related information,
removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA
packages only. 119-ball BGA is offered only in 1 chip enable.” and its
reference).
Updated Truth Table (Removed CY7C1381F related information).
Updated Truth Table for Read/Write (Removed CY7C1381F related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [14]) (Removed
CY7C1381F and CY7C1383D related information).
Updated Identification Register Definitions (Removed CY7C1381F and
CY7C1383D related information, removed 119-ball BGA package related
information).
Updated Scan Register Sizes (Removed 119-ball BGA package related
information).
Removed Boundary Scan Order (Corresponding to 119-ball BGA package).
Updated Capacitance (Removed 119-ball BGA package related information).
Updated Thermal Resistance (Removed 119-ball BGA package related information).
Document Number: 38-05544 Rev. *U
Description of Change
Page 35 of 37
Not Recommended for New Designs.
Added Neutron Soft Error Immunity.
Updated Ordering Information (By including parts that are available) and
modified the disclaimer for the Ordering information.
CY7C1381D
CY7C1383D
CY7C1383F
Document History Page (continued)
Document Title: CY7C1381D/CY7C1383D/CY7C1383F, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
Document Number: 38-05544
Rev.
ECN No.
Orig. of
Change
Submission
Date
*N (cont.)
3578427
PRIT
04/11/2012
Updated Package Diagrams (Removed 119-ball BGA package related
information).
*O
3945784
PRIT
03/27/2013
Updated Package Diagrams:
spec 51-85180 – Changed revision from *E to *F.
*P
3977530
PRIT
04/22/2013
Added Errata.
*Q
4068739
PRIT
07/20/2013
Added Errata footnotes (Note 2, 3, 4, 5, 6, 14).
Updated Pin Configurations:
Added Note 2 and referred the same note in Figure 1.
Added Note 3, 4 and referred the same note in Figure 2.
Updated Pin Definitions:
Added Note 5 and referred the same note in ZZ pin.
Added Note 6 and referred the same note in TDO, TDI, TMS, TCK pins.
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [14]):
Added Note 14 and referred the same note in JTAG in the heading.
Updated Errata.
Updated to new template.
*R
4150971
PRIT
10/08/2013
Updated Errata.
*S
4572829
PRIT
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Removed pruned part CY7C1470V25-167BZC.
*T
4739641
PRIT
04/24/2015
Updated to new template.
Completing Sunset Review.
*U
5190429
PRIT
03/25/2016
Added watermark “Not Recommended for New Designs.” across the
document.
Updated Ordering Information:
Updated part numbers.
Added a column “MPN Status”.
Added Note 39 and referred the same note in all MPNs.
Updated Package Diagrams:
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05544 Rev. *U
Page 36 of 37
Not Recommended for New Designs.
Description of Change
CY7C1381D
CY7C1383D
CY7C1383F
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
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assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 38-05544 Rev. *U
Revised March 25, 2016
Page 37 of 37
Not Recommended for New Designs.
Products