CY2305C
CY2309C
3.3 V Zero Delay Clock Buffer
3.3 V Zero Delay Clock Buffer
Features
100 MHz–133 MHz frequencies and have higher drive than the
-1 devices. All parts have on-chip phase locked loops (PLLs)
which lock to an input clock on the REF pin. The PLL feedback
is on-chip and is obtained from the CLKOUT pad.
■
10 MHz to 100–133 MHz operating range
■
Zero input and output propagation delay
■
Multiple low skew outputs
■
One input drives five outputs (CY2305C)
■
One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
■
50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
■
Test mode to bypass phase locked loop (PLL) (CY2309C) only,
see Select Input Decoding on page 6
■
Available in space saving 16-pin 150 Mil small outline
integrated circuit (SOIC) or 4.4 mm thin shrunk small outline
package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil
SOIC package (CY2305C)
■
3.3 V operation
■
Commercial, industrial and automotive-A flows available
The CY2309C has two banks of four outputs each that are
controlled by the select inputs as shown in the Select Input
Decoding on page 6. If all output clocks are not required, Bank
B is three-stated. The input clock is directly applied to the outputs
by the select inputs for chip and system testing purposes.
The CY2305C and CY2309C PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off. This
results in less than 12.0 A of current draw for commercial
temperature devices and 25.0 A for industrial and automotive-A
temperature parts. The CY2309C PLL shuts down in one
additional case as shown in the Select Input Decoding on page 6.
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves as a non-zero delay buffer in this mode and the
outputs are not three-stated.
Functional Description
The CY2305C and CY2309C are die replacement parts for
CY2305 and CY2309.
The CY2309C is a low-cost 3.3 V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305C is an 8-pin version of the
CY2309C. It accepts one reference input and drives out five low
skew clocks. The -1H versions of each device operate up to
The CY2305C or CY2309C is available in two or three different
configurations as shown in the Ordering Information on page 15.
The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H
or CY2309-1H is the high drive version of the -1. Its rise and fall
times are much faster than the -1.
For a complete list of related documentation, click here.
Logic Block Diagram – CY2305C
PLL
REF
CLKOUT
CLK1
CLK2
CLK3
CLK4
Cypress Semiconductor Corporation
Document Number: 38-07672 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 26, 2016
CY2305C
CY2309C
Logic Block Diagram – CY2309C
PLL
MUX
REF
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
S2
Select Input
Decoding
S1
CLKB2
CLKB3
CLKB4
Document Number: 38-07672 Rev. *O
Page 2 of 22
CY2305C
CY2309C
Contents
Pinouts .............................................................................. 4
Pin Definitions .................................................................. 5
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Select Input Decoding ................................................. 6
Zero Delay and Skew Control ..................................... 6
Absolute Maximum Conditions ....................................... 7
Operating Conditions ....................................................... 7
Operating Conditions ....................................................... 7
Electrical Characteristics ................................................. 8
Electrical Characteristics ................................................. 8
Test Circuits ...................................................................... 9
Thermal Resistance .......................................................... 9
Switching Characteristics .............................................. 10
Switching Characteristics .............................................. 11
Switching Characteristics .............................................. 12
Switching characteristics .............................................. 13
Document Number: 38-07672 Rev. *O
Switching Waveforms .................................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 3 of 22
CY2305C
CY2309C
Pinouts
Figure 1. 8-pin SOIC pinout (Top View)
CY2305C
8
CLKOUT
7
CLK4
3
6
VDD
4
5
CLK3
REF
1
CLK2
2
CLK1
GND
CY2305C
Figure 2. 16-pin SOIC / TSSOP pinout (Top View)
CY2309C
Document Number: 38-07672 Rev. *O
REF
CLKA1
1
16
2
15
CLKA2
VDD
3
4
13
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
CY2309C
14
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Page 4 of 22
CY2305C
CY2309C
Pin Definitions
8-pin SOIC
Pin
1
Signal
REF
[1]
Description
Input reference frequency
CLK2
[2]
Buffered clock output
3
CLK1
[2]
Buffered clock output
4
GND
2
Ground
5
CLK3
6
VDD
[2]
Buffered clock output
3.3 V supply
[2]
Buffered clock output
7
CLK4
8
CLKOUT [2]
Buffered clock output, internal feedback on this pin
Pin Definitions
16-pin SOIC / TSSOP
Pin
Signal
[1]
Description
Input reference frequency
1
REF
2
CLKA1 [2]
Buffered clock output, Bank A
3
CLKA2
[2]
Buffered clock output, Bank A
4
VDD
5
GND
Ground
6
CLKB1 [2]
Buffered clock output, Bank B
7
CLKB2 [2]
Buffered clock output, Bank B
8
S2
[3]
Select input, bit 2
[3]
Select input, bit 1
3.3 V supply
9
S1
10
CLKB3 [2]
Buffered clock output, Bank B
11
CLKB4
[2]
Buffered clock output, Bank B
12
GND
Ground
13
VDD
3.3 V supply
14
CLKA3 [2]
Buffered clock output, Bank A
15
[2]
Buffered clock output, Bank A
16
CLKA4
CLKOUT
[2]
Buffered output, internal feedback on this pin
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
Document Number: 38-07672 Rev. *O
Page 5 of 22
CY2305C
CY2309C
Functional Overview
Select Input Decoding
For CY2309C
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT [4]
Output Source
PLL Shutdown
0
0
Three state
Three state
Driven
PLL
N
0
1
Driven
Three state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB pins
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input or output delay.
For applications requiring zero input or output delay, all outputs
including CLKOUT are equally loaded. Even if CLKOUT is not
used, it must have a capacitive load equal to that on other
outputs for obtaining zero input or output delay.
For zero output to output skew, all outputs must be loaded
equally.
Even if CLKOUT is not used, it must have a capacitive load,
equal to that on other outputs, for obtaining zero input-output
delay. If input to output delay adjustments are required, use
Figure 3 to calculate loading differences between the CLKOUT
pin and other outputs.
Note
4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
Document Number: 38-07672 Rev. *O
Page 6 of 22
CY2305C
CY2309C
Absolute Maximum Conditions
Storage temperature ................................ –65 °C to +150 °C
Supply voltage to ground potential ..............–0.5 V to +4.6 V
DC input voltage (Except REF) .......... –0.5 V to VDD + 0.5 V
Junction temperature ................................................. 150 °C
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2,000 V
DC input voltage REF ......................... –0.5 V to VDD + 0.5 V
Operating Conditions
Operating Conditions Table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature devices.
Parameter
Description
Min
Max
Unit
3.0
3.6
V
0
70
°C
VDD
Supply voltage
TA
Operating temperature (ambient temperature)
CL
Load capacitance, below 100 MHz
–
30
pF
CL
Load capacitance, from 100 MHz to 133 MHz
–
10
pF
CIN
Input capacitance
–
7
pF
tPU
Power-up time for all VDDs to reach minimum specified voltage (power ramps are
monotonic)
0.05
50
ms
Operating Conditions
Operating Conditions Table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Industrial / Automotive-A Temperature
devices.
Parameter
Description
Min
Max
Unit
3.6
V
VDD
Supply voltage
3.0
TA
Operating temperature (ambient temperature)
–40
85
°C
CL
Load capacitance, below 100 MHz
–
30
pF
CL
Load capacitance, from 100 MHz to 133 MHz
–
10
pF
CIN
Input capacitance
–
7
pF
tPU
Power-up time for all VDDs to reach minimum specified voltage (power ramps are
monotonic)
0.05
50
ms
Document Number: 38-07672 Rev. *O
Page 7 of 22
CY2305C
CY2309C
Electrical Characteristics
Electrical Characteristics Table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature devices.
Parameter
Description
Min
Max
Unit
–
0.8
V
2.0
–
V
VIN = 0 V
–
50
A
Input HIGH current
VIN = VDD
–
100
A
Output LOW voltage [6]
IOL = 8 mA (–1)
–
0.4
V
2.4
–
V
REF = 0 MHz
–
12
A
Unloaded outputs at 66.67 MHz, SEL inputs at
VDD
–
32
mA
VIL
Input LOW voltage [5]
VIH
Input HIGH voltage
[5]
IIL
Input LOW current
IIH
VOL
VOH
[6]
Test Conditions
IOL = 12 mA (–1H)
Output HIGH voltage
IOH = –8 mA (–1)
IOH = –12 mA (–1H)
IDD (PD mode) Power-down supply current
IDD
Supply current
Electrical Characteristics
Electrical Characteristics Table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Industrial / Automotive-A Temperature
devices.
Parameter
VIL
Description
Input LOW voltage
[5]
[5]
VIH
Input HIGH voltage
IIL
Input LOW current
IIH
Input HIGH current
[6]
VOL
Output LOW voltage
VOH
Output HIGH voltage [6]
Test Conditions
Min
Max
Unit
–
0.8
V
2.0
–
V
VIN = 0 V
–
50
A
VIN = VDD
–
100
A
IOL = 8 mA (–1)
–
0.4
V
2.4
–
V
REF = 0 MHz
–
25
A
Unloaded outputs at 66.67 MHz, SEL inputs at
VDD
–
35
mA
IOL = 12 mA (–1H)
IOH = –8 mA (–1)
IOH = –12 mA (–1H)
IDD (PD mode) Power-down supply current
IDD
Supply current
Notes
5. REF input has a threshold voltage of VDD/2.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *O
Page 8 of 22
CY2305C
CY2309C
Test Circuits
Figure 4. Test Circuits
Test Circuit # 2
Test Circuit # 1
V DD
V DD
CLK
0.1 F
0.1 F
out
OUTPUTS
OUTPUTS
10 pF
C LOAD
GND
0.1 F
GND
1 k
V DD
V DD
0.1 F
1 k
GND
GND
For parameter t8 (output slew rate) on -1H devices
Thermal Resistance
Parameter [7]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow
standard test methods
and procedures for
measuring thermal
impedance, in
accordance with
EIA/JESD51.
8-pin SOIC
16-pin SOIC
16-pin TSSOP Unit
145
121
111
°C/W
62
53
26
°C/W
Note
7. These parameters are guaranteed by design and are not tested.
Document Number: 38-07672 Rev. *O
Page 9 of 22
CY2305C
CY2309C
Switching Characteristics
Switching Characteristics Table for CY2305CSXC-1 and CY2309CSXC-1 Commercial Temperature devices. All parameters are
specified with loaded outputs.
Parameter
t1
Description
Test Conditions
Output frequency
tDC
Output duty cycle
t3
Rise time [8]
t4
Fall time [8]
[8]
= t2 t1
[8]
Min
Typ
Max
Unit
30 pF load
10
–
100
MHz
10 pF load
10
–
133.33
MHz
Measured at 1.4 V, Fout > 50 MHz
40
50
60
%
Measured at 1.4 V, Fout 50 MHz
45
50
55
%
Measured between 0.8 V and 2.0 V
–
–
2.25
ns
Measured between 0.8 V and 2.0 V
–
–
2.25
ns
All outputs equally loaded
–
–
200
ps
t5
Output-to-output skew
t6A
Delay, REF rising edge to
CLKOUT rising edge [8]
Measured at VDD/2
–
0
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [8]
Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C
device only.
1
5
8.7
ns
t7
Device-to-device skew [8]
Measured at VDD/2 on the CLKOUT
pins of devices
–
0
700
ps
tJ
Cycle-to-cycle jitter, peak [8]
Measured at 66.67 MHz, loaded
outputs
–
50
175
ps
tLOCK
PLL lock time [8]
Stable power supply, valid clock
presented on REF pin
–
–
1.0
ms
Note
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *O
Page 10 of 22
CY2305C
CY2309C
Switching Characteristics
Switching Characteristics Table for CY2305CSXC-1H and CY2309CSXC-1H Commercial Temperature devices. All parameters are
specified with loaded outputs.
Parameter
t1
Description
Description
Output frequency
tDC
Output duty cycle
t3
Rise time [9]
t4
Fall time [9]
[9]
= t2 t1
[9]
Min
Typ
Max
Unit
30 pF load
10
–
100
MHz
10 pF load
10
–
133.33
MHz
Measured at 1.4 V, Fout > 50 MHz
40
50
60
%
Measured at 1.4 V, Fout 50 MHz
45
50
55
%
Measured between 0.8 V and 2.0 V
–
–
1.5
ns
Measured between 0.8 V and 2.0 V
–
–
1.5
ns
All outputs equally loaded
–
–
200
ps
t5
Output-to-output skew
t6A
Delay, REF rising edge to
CLKOUT rising edge [9]
Measured at VDD/2
–
0
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [9]
Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C
device only.
1
5
8.7
ns
t7
Device-to-device skew [9]
Measured at VDD/2 on the CLKOUT
pins of devices
–
0
700
ps
t8
Output slew rate [9]
Measured between 0.8 V and 2.0 V
using Test circuit #2
1
–
–
V/ns
tJ
Cycle-to-cycle jitter, peak [9]
Measured at 66.67 MHz, loaded
outputs
–
–
175
ps
tLOCK
PLL lock time [9]
Stable power supply, valid clock
presented on REF pin
–
–
1.0
ms
Note
9. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *O
Page 11 of 22
CY2305C
CY2309C
Switching Characteristics
Switching Characteristics Table for CY2305CSXI-1, CY2305CSXA-1, and CY2309CSXI-1 Industrial Temperature devices. All
parameters are specified with loaded outputs.
Parameter
t1
Description
Test Conditions
Output frequency
tDC
Output duty cycle
t3
Rise time [10]
t4
Fall time [10]
[10]
= t2 t1
[10]
Min
Typ
Max
Unit
30 pF load
10
–
100
MHz
10 pF load
10
–
133.33
MHz
Measured at 1.4 V, Fout > 50 MHz
40
50
60
%
Measured at 1.4 V, Fout < 50 MHz
45
50
55
%
Measured between 0.8 V and 2.0 V
–
–
2.25
ns
Measured between 0.8 V and 2.0 V
–
–
2.25
ns
All outputs equally loaded
–
–
200
ps
t5
Output-to-output skew
t6A
Delay, REF rising edge to
CLKOUT rising edge [10]
Measured at VDD/2
–
0
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [10]
Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C
device only.
1
5
8.7
ns
t7
Device-to-device skew [10]
Measured at VDD/2 on the CLKOUT
pins of devices
–
0
700
ps
tJ
Cycle-to-cycle jitter, peak [10]
Measured at 66.67 MHz, loaded
outputs
–
50
175
ps
tLOCK
PLL lock time [10]
Stable power supply, valid clock
presented on REF pin
–
–
1.0
ms
Note
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *O
Page 12 of 22
CY2305C
CY2309C
Switching characteristics
Switching Characteristics Table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H Industrial / Automotive-A Temperature
devices. All parameters are specified with loaded outputs.
Parameter
t1
Description
Description
Output frequency
tDC
Output duty cycle
t3
Rise time [11]
t4
Fall time [11]
[11]
= t2 t1
[11]
Min
Typ
Max
Unit
30 pF load
10
–
100
MHz
10 pF load
10
–
133.33
MHz
Measured at 1.4 V, Fout > 50 MHz
40
50
60
%
Measured at 1.4 V, Fout < 50 MHz
45
50
55
%
Measured between 0.8 V and 2.0 V
–
–
1.5
ns
Measured between 0.8 V and 2.0 V
–
–
1.5
ns
All outputs equally loaded
–
–
200
ps
t5
Output-to-output skew
t6A
Delay, REF rising edge to
CLKOUT rising edge [11]
Measured at VDD/2
–
0
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [11]
Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C
device only.
1
5
8.7
ns
t7
Device-to-device skew [11]
Measured at VDD/2 on the CLKOUT
pins of devices
–
0
700
ps
t8
Output slew rate [11]
Measured between 0.8 V and 2.0 V
using Test circuit #2
1
–
–
V/ns
tJ
Cycle-to-cycle jitter, peak [11]
Measured at 66.67 MHz, loaded
outputs
–
–
175
ps
tLOCK
PLL lock time [11]
Stable power supply, valid clock
presented on REF pin
–
–
1.0
ms
Note
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *O
Page 13 of 22
CY2305C
CY2309C
Switching Waveforms
Figure 5. Duty Cycle Timing
t1
t2
1.4 V
1.4 V
1.4 V
Figure 6. All Outputs Rise/Fall Time
OUTPUT
2.0 V
0.8 V
2.0 V
0.8 V
3.3 V
0V
t4
t3
Figure 7. Output-Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Figure 8. Input-Output Propagation Delay
VDD/2
INPUT
VDD/2
OUTPUT
t6
Figure 9. Device-Device Skew
CLKOUT, Device 1
VDD/2
VDD/2
CLKOUT, Device 2
t7
Document Number: 38-07672 Rev. *O
Page 14 of 22
CY2305C
CY2309C
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-free - CY2305C
CY2305CSXC-1
8-pin SOIC (150 Mil)
Commercial
CY2305CSXC-1T
8-pin SOIC (150 Mil) – Tape and Reel
Commercial
CY2305CSXC-1H
8-pin SOIC (150 Mil)
Commercial
CY2305CSXC-1HT
8-pin SOIC (150 Mil) – Tape and Reel
Commercial
CY2305CSXI-1
8-pin SOIC (150 Mil)
Industrial
CY2305CSXI-1T
8-pin SOIC (150 Mil) – Tape and Reel
Industrial
CY2305CSXI-1H
8-pin SOIC (150 Mil)
Industrial
CY2305CSXI-1HT
8-pin SOIC (150 Mil) – Tape and Reel
Industrial
CY2305CSXA-1H
8-pin SOIC (150 Mil)
Automotive-A
CY2305CSXA-1HT
8-pin SOIC (150 Mil) – Tape and Reel
Automotive-A
CY2309CSXC-1
16-pin SOIC (150 Mil)
Commercial
CY2309CSXC-1T
16-pin SOIC (150 Mil) – Tape and Reel
Commercial
CY2309CSXC-1H
16-pin SOIC (150 Mil)
Commercial
CY2309CSXC-1HT
16-pin SOIC (150 Mil) – Tape and Reel
Commercial
CY2309CSXI-1
16-pin SOIC (150 Mil)
Industrial
CY2309CSXI-1T
16-pin SOIC (150 Mil) – Tape and Reel
Industrial
CY2309CSXI-1H
16-pin SOIC (150 Mil)
Industrial
CY2309CSXI-1HT
16-pin SOIC (150 Mil) – Tape and Reel
Industrial
CY2309CZXC-1
16-pin TSSOP (4.4 mm)
Commercial
CY2309CZXC-1T
16-pin TSSOP (4.4 mm) – Tape and Reel
Commercial
CY2309CZXC-1H
16-pin TSSOP (4.4 mm)
Commercial
CY2309CZXC-1HT
16-pin TSSOP (4.4 mm) – Tape and Reel
Commercial
CY2309CZXI-1
16-pin TSSOP (4.4 mm)
Industrial
CY2309CZXI-1T
16-pin TSSOP (4.4 mm) – Tape and Reel
Industrial
CY2309CZXI-1H
16-pin TSSOP (4.4 mm)
Industrial
CY2309CZXI-1HT
16-pin TSSOP (4.4 mm) – Tape and Reel
Industrial
Pb-free - CY2309C
Document Number: 38-07672 Rev. *O
Page 15 of 22
CY2305C
CY2309C
Ordering Code Definitions
CY 230XC
X
X
X
– 1X
X
X = blank or T
blank = Tube; T = Tape and Reel
Output Drive: 1X = 1 or 1H
1 = Standard Drive; 1H = High Drive
Temperature Grade: X = C or I or A
C = Commercial; I = Industrial; A = Automotive
Pb-free
Package Type: X = S or Z
S = 8-pin SOIC or 16-pin SOIC; Z = 16-pin TSSOP
Base Device Part Number: 230XC = 2305C or 2309C
2305C = 5-output zero delay buffer, rev C
2309C = 9-output zero delay buffer, rev C
Company ID: CY = Cypress
Document Number: 38-07672 Rev. *O
Page 16 of 22
CY2305C
CY2309C
Package Diagrams
Figure 10. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *H
Document Number: 38-07672 Rev. *O
Page 17 of 22
CY2305C
CY2309C
Package Diagrams (continued)
Figure 11. 16-pin SOIC (150 Mil) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Figure 12. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Document Number: 38-07672 Rev. *O
Page 18 of 22
CY2305C
CY2309C
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
PLL
Phase Locked Loop
°C
degree Celsius
SOIC
Small Outline Integrated Circuit
kHz
kilohertz
TSSOP
Thin Shrunk Small Outline Package
MHz
megahertz
µA
microampere
mA
milliampere
ms
millisecond
ns
nanosecond
pF
picofarad
ps
picosecond
V
volt
Document Number: 38-07672 Rev. *O
Symbol
Unit of Measure
Page 19 of 22
CY2305C
CY2309C
Document History Page
Document Title: CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer
Document Number: 38-07672
Rev.
ECN No.
Issue Date
Orig. of
Change
**
224421
See ECN
RGL
New data sheet
*A
268571
See ECN
RGL
Added bullet for 5 V tolerant inputs in the features
*B
276453
See ECN
RGL
Minor Change: Moved one sentence from the features to the Functional
Description
*C
303063
See ECN
RGL
Updated data sheet as per characterization data
*D
318315
See ECN
RGL
Data sheet rewrite
*E
344815
See ECN
RGL
Minor Error: Corrected the header of all the AC/DC tables with the right part
numbers.
*F
127988938
See ECN
KVM
Changed title from “CY2305C/CY2309C‚ Low Cost 3.3 V Zero Delay Buffer” to
“CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer”.
Specified the VIL minimum value to -0.3 V
Specified the VIH maximum value to VDD + 0.3 V
Changed DC Input Voltage (REF) maximum value in Absolute Maximum
section
Removed references to 5 V tolerant inputs (pages 1 and 2)
Removed Pentium compatibility reference
Added CY2305C block diagram
Added ‚peak to the jitter specifications
Changed typical jitter from 75 ps to 50 ps for standard drive devices
For standard drive devices, tightened rise/fall times from 2.5 ns to 2.25 ns
Tightened cycle-to-cycle jitter from 200 ps to 175 ps
Tightened output-to-output skew from 250 ps to 200 ps
*G
1561504
See ECN
*H
2558537
08/27/08
KVM /
AESA
Updated Ordering Information:
Added CY2305CSXA-1 and CY2305CSXA-1T parts under Pb-free CY2305C.
*I
2901743
03/30/2010
VIVG
Added Ordering Code Definitions under Ordering Information.
Updated Package Diagrams.
*J
3080990
11/10/2010
BASH
Updated Pinouts:
Updated Figure 1 (Modified pin diagram).
Added Acronyms and Units of Measure.
Updated to new template.
*K
3160535
02/03/2011
BASH
Updated Electrical Characteristics:
Removed minimum value of VIL parameter and maximum value of VIH
parameter.
Updated Electrical Characteristics:
Removed minimum value of VIL parameter and maximum value of VIH
parameter.
Updated Ordering Information:
Removed Prune parts CY2305CSXA-1 and CY2305CSXA-1T.
*L
3822852
11/27/2012
PURU
Updated Functional Overview:
Updated Select Input Decoding (Added Figure 3 only, no edits).
Updated Zero Delay and Skew Control (Minor edits).
Updated Package Diagrams:
spec 51-85091 – Changed revision from *C to *D.
spec 51-85068 – Changed revision from *C to *E.
spec 51-85066 – Changed revision from *D to *E.
Document Number: 38-07672 Rev. *O
Description of Change
KVM / NSI / Changed status from Preliminary to Final.
AESA
Added CY2305C Automotive-A grade devices
Extended duty cycle specs to cover entire frequency range
Page 20 of 22
CY2305C
CY2309C
Document History Page (continued)
Document Title: CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer
Document Number: 38-07672
Rev.
ECN No.
Issue Date
Orig. of
Change
*M
4201564
11/25/2013
CINM
Updated Package Diagrams:
spec 51-85066 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*N
4578443
11/25/2014
TAVA
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams.
*O
5242528
04/15/2016
SDHK /
PSR
Updated Electrical Characteristics:
Updated details in “Test Conditions” column corresponding to VOL and VOH
parameters.
Updated Electrical Characteristics:
Updated details in “Test Conditions” column corresponding to VOL and VOH
parameters.
Added Thermal Resistance.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *F to *H.
Updated to new template.
Document Number: 38-07672 Rev. *O
Description of Change
Page 21 of 22
CY2305C
CY2309C
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 38-07672 Rev. *O
Revised April 26, 2016
Page 22 of 22