SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04 — 22 April 2010 Product data sheet 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs. The SSTUB32868 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). It further offers added features over the JEDEC standard register in that it can be configured for normal or high output drive strength, simply by tying input pin SELDR either HIGH or LOW as needed. This allows use in different module designs varying from low to high density designs by picking the appropriate drive strength to match net loading conditions. Furthermore, the SSTUB32868 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. The SSTUB32868 is packaged in a 176-ball, 8 × 22 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 6 mm × 15 mm of board space) allows for adequate signal routing and escape using conventional card technology. 2. Features and benefits 28-bit data register supporting DDR2 Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866) Parity checking function across 22 input data bits Parity out signal Controlled multi-impedance output impedance drivers enable optimal signal integrity and speed Meets or exceeds SSTUB32868 JEDEC standard speed performance Supports up to 450 MHz clock frequency of operation Programmable for normal or high output drive Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity Two additional chip select inputs allow optional flexible enabling and disabling Supports Stub Series Terminated Logic SSTL_18 data inputs Differential clock (CK and CK) inputs Supports Low Voltage Complementary Metal-Oxide Semiconductor (LVCMOS) switching levels on the control and RESET inputs Single 1.8 V supply operation (1.7 V to 2.0 V) Available in 176-ball 6 mm × 15 mm, 0.65 mm ball pitch TFBGA package 3. Applications 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality 4. Ordering information Table 1. Ordering information Type number Solder process Package Name Description Version SSTUB32868ET/G Pb-free (SnAgCu solder ball TFBGA176 plastic thin fine-pitch ball grid array package; SOT932-1 compound) 176 balls; body 6 × 15 × 0.7 mm SSTUB32868ET/S Pb-free (SnAgCu solder ball TFBGA176 plastic thin fine-pitch ball grid array package; SOT932-1 compound) 176 balls; body 6 × 15 × 0.7 mm 4.1 Ordering options Table 2. Ordering options Type number SSTUB32868_4 Product data sheet Temperature range SSTUB32868ET/G Tamb = 0 °C to +70 °C SSTUB32868ET/S Tamb = 0 °C to +85 °C All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 2 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 5. Functional diagram RESET SSTUB32868 CK CK VREF DCKE0, DCKE1 2 2 D CLK Q R DODT0, DODT1 2 2 D CLK Q 2 QCKE0B, QCKE1B 2 QODT0A, QODT1A 2 QODT0B, QODT1B QCS0A D CLK QCKE0A, QCKE1A 2 R DCS0 2 2 Q R QCS0B D QCS1A CSGEN DCS1 CLK Q QCS1B R DCS2 DCS3 one of 22 channels D1 D CE CLK Q1A Q R to 21 other channels(1) Q1B 002aac336 (1) Register A configuration (C = 0): D2 to D5, D7, D9 to D12, D17 to D28 Register B configuration (C = 1): D2 to D12, D17 to D20, D22, D24 to D28 Fig 1. SSTUB32868_4 Product data sheet Logic diagram of SSTUB32868 (positive logic) All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 3 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity RESET CK CK Dn(1) VREF 22 22 22 D CLK QnA(2) 22 Q 22 R CE QnB(3) 22 PAR_IN D CLK R Q CE PARITY GENERATOR AND ERROR CHECK DCS0 QERR D CLK QCS0A Q QCS0B R CSGEN DCS1 D CLK QCS1A Q QCS1B R DCS2 DCS3 002aac497 (1) Register A configuration (C = 0): D1 to D5, D7, D9 to D12, D17 to D28 Register B configuration (C = 1): D1 to D12, D17 to D20, D22, D24 to D28 (2) Register A configuration (C = 0): Q1A to Q5A, Q7A, Q9A to Q12A, Q17A to Q28A Register B configuration (C = 1): Q1A to Q12A, Q17A to Q20A, Q22A, Q24A to Q28A (3) Register A configuration (C = 0): Q1B to Q5B, Q7B, Q9B to Q12B, Q17B to Q28B Register B configuration (C = 1): Q1B to Q12B, Q17B to Q20B, Q22B, Q24B to Q28B Fig 2. SSTUB32868_4 Product data sheet Parity logic diagram (positive logic) All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 4 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 6. Pinning information 6.1 Pinning SSTUB32868ET/G SSTUB32868ET/S ball A1 index area 2 1 B D F H K M P T V 4 3 6 5 8 7 A C E G J L N R U W Y AA AB 002aac337 Transparent top view Fig 3. SSTUB32868_4 Product data sheet Pin configuration for TFBGA176 All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 1 2 3 4 5 6 7 8 A D2 D1 C GND VREF GND Q1A Q1B B D4 D3 VDD VDD VDD VDD Q2A Q2B C D6 (DCKE1) D5 GND GND GND GND Q3A Q3B D D8 (DCKE0) D7 VDD VDD VDD VDD Q4A Q4B E D9 Q6A (QCKE1A) GND GND GND GND Q5A Q5B F D10 Q8A (QCKE0A) VDD VDD VDD VDD Q7A Q6B (QCKE1B) G D11 Q10A GND GND GND GND Q9A Q7B H D12 Q12A VDD VDD VDD VDD Q11A Q8B (QCKE0B) J DCS1 (D13) QCS1A (Q13A) GND GND GND GND Q10B Q9B K DCS0 (D14) QCS0A (Q14A) DCS2 VDD VDD VDD Q12B Q11B L CK CSGEN PAR_IN GND GND GND Q14B (QCS0B) Q13B (QCS1B) M CK RESET QERR VDD VDD VDD Q15B (QODT0B) Q16B (QODT1B) N D15 (DODT0) Q15A (QODT0A) GND GND GND GND Q17B Q18B P D16 (DODT1) Q16A (QODT1A) DCS3 VDD VDD VDD Q19B Q20B R D17 Q17A GND GND GND GND Q18A Q21B T D18 Q19A VDD VDD VDD VDD Q20A Q22B U D19 Q21A GND GND GND GND Q22A Q23B V D20 Q23A VDD VDD VDD VDD Q24A Q24B W D21 D22 GND GND GND GND Q25A Q25B Y D23 D24 VDD VDD VDD VDD Q26A Q26B AA D25 D26 GND GND GND GND Q27A Q27B AB D27 D28 SELDR VDD VREF VDD Q28A Q28B 002aac498 176-ball, 8 × 22 grid; top view. Fig 4. SSTUB32868_4 Product data sheet Ball mapping (1 : 2 Register A; C = 0) All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 6 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 1 2 3 4 5 6 7 8 A D2 D1 C GND VREF GND Q1A Q1B B D4 D3 VDD VDD VDD VDD Q2A Q2B C D6 D5 GND GND GND GND Q3A Q3B D D8 D7 VDD VDD VDD VDD Q4A Q4B E D9 Q6A GND GND GND GND Q5A Q5B F D10 Q8A VDD VDD VDD VDD Q7A Q6B G D11 Q10A GND GND GND GND Q9A Q7B H D12 Q12A VDD VDD VDD VDD Q11A Q8B J D13 (DODT1) Q13A (QODT1A) GND GND GND GND Q10B Q9B K D14 (DODT0) Q14A (QODT0A) DCS2 VDD VDD VDD Q12B Q11B L CK CSGEN PAR_IN GND GND GND Q14B (QODT0B) Q13B (QODT1B) M CK RESET QERR VDD VDD VDD Q15B (QCS0B) Q16B (QCS1B) N D15 (DCS0) Q15A (QCS0A) GND GND GND GND Q17B Q18B P D16 (DCS1) Q16A (QCS1A) DCS3 VDD VDD VDD Q19B Q20B R D17 Q17A GND GND GND GND Q18A Q21B (QCKE0B) T D18 Q19A VDD VDD VDD VDD Q20A Q22B U D19 Q21A (QCKE0A) GND GND GND GND Q22A Q23B (QCKE1B) V D20 Q23A (QCKE1A) VDD VDD VDD VDD Q24A Q24B W D21 (DCKE0) D22 GND GND GND GND Q25A Q25B Y D23 (DCKE1) D24 VDD VDD VDD VDD Q26A Q26B AA D25 D26 GND GND GND GND Q27A Q27B AB D27 D28 SELDR VDD VREF VDD Q28A Q28B 002aac499 176-ball, 8 × 22 grid; top view. Fig 5. SSTUB32868_4 Product data sheet Ball mapping (1 : 2 Register B; C = 1) All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 7 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 6.2 Pin description Table 3. Pin description Symbol Pin 1 : 2 Register A (C = 0) Type Description SSTL_18 The outputs of this register will not be suspended by the DCS0 and DCS1 control. SSTL_18 The outputs of this register will not be suspended by the DCS0 and DCS1 control. A2, A1, B2, B1, C2, C1, D2, D1, E1, F1, G1, H1, J1, K1, N1, P1, R1, T1, U1, V1, W1, W2, Y1, Y2, AA1, AA2, AB1, AB2 SSTL_18 Data inputs, clocked in on the crossing of the rising edge of CD and the falling edge of CK. SSTL_18 Chip select inputs. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs (CSGEN = HIGH) only when at least one chip select input is LOW. If CSGEN, DCS0 and DCS1 inputs are HIGH, D1 to D28[1] inputs will be disabled. A3 LVCMOS input Configuration control inputs; Register A or Register B 1.8 V CMOS outputs Data outputs[2] that are suspended by the DCS0 and DCS1 control. 1.8 V CMOS outputs Data outputs that will not be suspended by the DCS0 and DCS1 control. 1.8 V CMOS outputs Data outputs that will not be suspended by the DCS0 and DCS1 control. 1 : 2 Register B (C = 1) Ungated inputs DCKE0 D1 W1 DCKE1 C1 Y1 DODT0 N1 K1 DODT1 P1 J1 Chip Select gated inputs D1 to D28 A2, A1, B2, B1, C2, C1, D2, D1, E1, F1, G1, H1, N1, P1, R1, T1, U1, V1, W1, W2, Y1, Y2, AA1, AA2, AB1, AB2 Chip Select inputs DCS0 K1 N1 DCS1 J1 P1 DCS2 K3 K3 DCS3 P3 P3 Configuration control inputs C A3 Re-driven outputs Q1A to Q28A A7, B7, C7, D7, E7, E2, F7, F2, G7, G2, H7, H2, N2, P2, R2, R7, T2, T7, U2, U7, V2, V7, W7, Y7, AA7, AB7 A7, B7, C7, D7, E7, E2, F7, F2, G7, G2, H7, H2, J2, K2, N2, P2, R2, R7, T2, T7, U2, U7, V2, V7, W7, Y7, AA7, AB7 Q1B to Q28B A8, B8, C8, D8, E8, F8, G8, H8, J8, J7, K8, K7, L8, L7, M7, M8, N7, N8, P7, P8, R8, T8, V8, U8, W8, Y8, AA8, AB8 A8, B8, C8, D8, E8, F8, G8, H8, J8, J7, K8, K7, L8, L7, M7, M8, N7, N8, P7, P8, R8, T8, U8, V8, W8, Y8, AA8, AB8 QCS0A K2 N2 QCS0B L7 M7 QCS1A J2 P2 QCS1B L8 M8 QCKE0A F2 U2 QCKE0B H8 R8 QCKE1A E2 V2 QCKE1B F8 U8 SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 8 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity Table 3. Pin description …continued Symbol Pin 1 : 2 Register A (C = 0) Type Description 1.8 V CMOS outputs Data outputs that will not be suspended by the DCS0 and DCS1 control. M3 open-drain output Output error bit; generated on clock cycle after the corresponding data output. L3 SSTL_18 Parity input. Arrives one clock cycle after the corresponding data input. L2 LVCMOS input Chip select gate enable. When HIGH, the D1 to D28[1] inputs will be latched only when at least one chip select input is LOW during the rising edge of the clock. When LOW, the D1 to D28[1] inputs will be latched and re-driven on every rising edge of the clock. 1 : 2 Register B (C = 1) QODT0A N2 K2 QODT0B M7 L7 QODT1A P2 J2 QODT1B M8 L8 Output error QERR M3 Parity input PAR_IN L3 Program inputs CSGEN L2 Clock inputs CK L1 L1 differential input Positive master clock input. CK M1 M1 differential input Negative master clock input. Miscellaneous inputs RESET M2 M2 LVCMOS input Asynchronous reset input. Resets registers and disables VREF data and clock differential-input receivers. VREF A5, AB5 A5, AB5 0.9 V nominal Input reference voltage. VDD B3, B4, B5, B6, D3, D4, D5, D6, F3, F4, F5, F6, H3, H4, H5, H6, K4, K5, K6, M4, M5, M6, P4, P5, P6, T3, T4, T5, T6, V3, V4, V5, V6, Y3, Y4, Y5, Y6, AB4, AB6 B3, B4, B5, B6, D3, D4, D5, D6, F3, F4, F5, F6, H3, H4, H5, H6, K4, K5, K6, M4, M5, M6, P4, P5, P6, T3, T4, T5, T6, V3, V4, V5, V6, Y3, Y4, Y5, Y6, AB4, AB6 1.8 V nominal Power supply voltage. GND A4, A6, C3, C4, C5, C6, E3, E4, E5, E6, G3, G4, G5, G6, J3, J4, J5, J6, L4, L5, L6, N3, N4, N5, N6, R3, R4, R5, R6, U3, U4, U5, U6, W3, W4, W5, W6, AA3, AA4, AA5, AA6 A4, A6, C3, C4, C5, C6, ground E3, E4, E5, E6, G3, G4, input G5, G6, J3, J4, J5, J6, L4, L5, L6, N3, N4, N5, N6, R3, R4, R5, R6, U3, U4, U5, U6, W3, W4, W5, W6, AA3, AA4, AA5, AA6 Ground. SELDR AB3 AB3 Selects output drive strength: ‘HIGH’ for normal drive; ‘LOW’ for high drive. This pin will default HIGH if left open-circuit (built-in weak pull-up resistor). SSTUB32868_4 Product data sheet LVCMOS input with weak pull-up All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 9 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity [1] Data inputs = D1 to D5, D7, D9 to D12, D17 to D28 when C = 0. Data inputs = D1 to D12, D17 to D20, D22, D24 to D28 when C = 1. [2] Data outputs = Q1x to Q5x, Q7x, Q9x to Q12x, Q17x to Q28x when C = 0. Data outputs = Q1x to Q12x, Q17x to Q20x, Q22x, Q24x to Q28x when C = 1. 7. Functional description 7.1 Function table Table 4. Function table (each flip-flop) Outputs[1] Inputs RESET DCS0[2] DCS1[2] CSGEN CK CK Dn, DODTn, DCKEn Qn H L L X ↑ ↓ L L L L L H L L X ↑ ↓ H H L L H H L L X L or H L or H X Q0 Q0 Q0 Q0 H L H X ↑ ↓ L L L H L H L H X ↑ ↓ H H L H H H L H X L or H L or H X Q0 Q0 Q0 Q0 H H L X ↑ ↓ L L H L L H H L X ↑ ↓ H H H L H H H L X L or H L or H X Q0 Q0 Q0 Q0 H H H L ↑ ↓ L L H H L QCS0x QCS1x QODTn, QCKEn H H H L ↑ ↓ H H H H H H H H L L or H L or H X Q0 Q0 Q0 Q0 H H H H ↑ ↓ L Q0 H H L H H H H ↑ ↓ H Q0 H H H H H H H L or H L or H X Q0 Q0 Q0 Q0 L X or floating X or floating X or floating X or floating X or floating X or floating L L L L [1] Q0 is the previous state of the associated output. [2] DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs. SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 10 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity Table 5. Parity and standby function table Inputs Output ∑ of inputs = H (D1 to D28) PAR_IN[2] QERR[3][4] ↓ even L H ↑ ↓ odd L L X ↑ ↓ even H L L X ↑ ↓ odd H H X L ↑ ↓ even L H X L ↑ ↓ odd L L X L ↑ ↓ even H L RESET DCS0[1] DCS1[1] CK CK H L X ↑ H L X H L H H H H H X L ↑ ↓ odd H H H H H ↑ ↓ X X QERR0[5] H X X L or H L or H X X QERR0 L X or floating X or floating X or floating X or floating X X or floating H [1] DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function. [2] PAR_IN arrives one clock cycle after the data to which it applies. [3] This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. [4] QERR0 is the previous state of output QERR. [5] If DCS0, DCS1, DCS2, DCS3 and CSGEN are driven HIGH, the device is placed in Low-Power Mode (LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus two clock cycles or until RESET is driven LOW. 7.2 Functional information The SSTUB32868 is a 28-bit 1 : 2 configurable registered buffer designed for 1.7 V to 1.9 V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset and all outputs are forced LOW except QERR. The LVCMOS RESET and C inputs always must be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register will be cleared and the data outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 11 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUB32868 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The SSTUB32868 includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device. The corresponding QERR output signal for the data inputs is generated two clock cycles after the data, to which the QERR signal applies, is registered. The SSTUB32868 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D inputs (D1 to D5, D7, D9 to D12, D17 to D28 when C = 0; or D1 to D12, D17 to D20, D22, D24 to D28 when C = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D inputs must be tied to a known logic state. If an error occurs and the QERR output is driven LOW, it stays latched LOW for a minimum of two clock cycles or until RESET is driven LOW. If two or more consecutive parity errors occur, the QERR output is driven LOW and latched LOW for a clock duration equal to the parity error duration or until RESET is driven LOW. If a parity error occurs on the clock cycle before the device enters the Low-Power Mode (LPM) and the QERR output is driven LOW, then it stays latched LOW for the LPM duration plus two clock cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0, DCS1, DCS2 and DCS3) are not included in the parity check computation. The C input controls the pinout configuration from Register A configuration (when LOW) to Register B configuration (when HIGH). The C input should not be switched during normal operation. It should be hard-wired to a valid LOW or HIGH level to configure the register in the desired mode. The device also supports low-power active operation by monitoring both system chip select (DCS0, DCS1, DCS2 and DCS3) and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN, DCS0 and DCS1 inputs are HIGH. If CSGEN or the DCSn inputs are LOW, the Qn outputs will function normally. Also, if all DCSn inputs are HIGH, the device will gate the QERR output from changing states. If any of the DCSn are LOW, the QERR output will function normally. The RESET input has priority over the DCSn control, and when driven LOW will force the Qn outputs LOW and the QERR output HIGH. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground (GND), in which case the setup time requirement for DCSn would be the same as for the other D data inputs. To control the Low-power mode with DCSn only, the CSGEN input should be pulled up to VDD through a pull-up resistor. The two VREF pins (A5 and AB5) are connected together internally by approximately 150 Ω. However, it is necessary to connect only one of the two VREF pins to the external Vref power supply. An unused VREF pin should be terminated with a Vref coupling capacitor. The SSTUB32868 is available in a TFGBA176 package. SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 12 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 7.3 Register timing RESET CSGEN DCSn m m+1 m+2 m+3 m+4 CK CK tACT tsu th Dn, DODTn, DCKEn(1) tPDM, tPDMSS CK to Q Qn, QODTn, QCKEn tsu th PAR_IN(1) tPHL tPHL, tPLH CK to QERR CK to QERR QERR(2) data to QERR latency HIGH, LOW, or Don't care HIGH or LOW 002aab899 (1) After RESET is switched from LOW to HIGH, all data and PAR_IN input signals must be set and held LOW for a minimum time of tACT(max) to avoid false error. (2) If the data is clocked on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be produced on the m + 2 clock pulse and it will be valid on the m + 3 clock pulse. Fig 6. Timing diagram during start-up (RESET switches from LOW to HIGH) SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 13 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity RESET CSGEN DCSn m+1 m m+2 m+3 m+4 CK CK tsu th Dn, DODTn, DCKEn tPDM, tPDMSS CK to Q Qn, QODTn, QCKEn tsu th PAR_IN tPHL, tPLH CK to QERR QERR(1) data to QERR latency unknown input event output signal is dependent on the prior unknown event HIGH or LOW 002aab900 (1) If the data is clocked in on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be generated on the m + 2 clock pulse and it will be valid on the m + 3 clock pulse. If an error occurs and the QERR output is driven LOW, it stays LOW for a minimum of two clock cycles or until RESET is driven LOW. Fig 7. Timing diagram during normal operation (RESET = HIGH) SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 14 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity RESET tINACT CSGEN(1) DCSn(1) CK(1) CK(1) Dn, DODTn, DCKEn(1) tPHL RESET to Q Qn, QODTn, QCKEn PAR_IN(1) tPLH RESET to QERR QERR HIGH, LOW, or Don't care HIGH or LOW 002aac511 (1) After RESET is switched from HIGH to LOW, all data and clock input signals must be held at valid logic levels (not floating) for a minimum time of tINACT(max). Fig 8. Timing diagram during shutdown (RESET switches from HIGH to LOW) SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 15 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions Min Max Unit V −0.5 +2.5 −0.5 +2.5 V −0.5 VDD + 0.5 V VI input voltage receiver [1][2] VO output voltage driver [1][2] IIK input clamping current VI < 0 V or VI > VDD - ±50 mA IOK output clamping current VO < 0 V or VO > VDD - ±50 mA IO output current continuous; 0 V < VO < VDD - ±50 mA ICCC continuous current through each VDD or GND pin - ±100 mA Tstg storage temperature −65 +150 °C VESD electrostatic discharge voltage Human Body Model (HBM); 1.5 kΩ; 100 pF 2 - kV Machine Model (MM); 0 Ω; 200 pF 200 - V [1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. [2] This value is limited to 2.5 V maximum. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VDD supply voltage 1.7 - 2.0 V Vref reference voltage 0.49 × VDD 0.50 × VDD 0.51 × VDD V VT termination voltage Vref − 0.040 Vref Vref + 0.040 V VI input voltage 0 VDD V V Conditions Min Typ - Max Unit VIH(AC) AC HIGH-level input voltage Dn, CSR and PAR_IN inputs [1] Vref + 0.250 - - VIL(AC) AC LOW-level input voltage Dn, CSR and PAR_IN inputs [1] - Vref − 0.250 V VIH(DC) DC HIGH-level input voltage Dn, CSR and PAR_IN inputs [1] Vref + 0.125 - - DC LOW-level input voltage Dn, CSR and PAR_IN inputs [1] - - Vref − 0.125 V 0.65 × VDD - - V - - 0.35 × VDD V 0.675 - 1.125 V VIL(DC) - V VIH HIGH-level input voltage RESET, CSGEN [2] VIL LOW-level input voltage RESET, CSGEN [2] VICR common mode input voltage CK, CK range VID differential input voltage CK, CK 600 - - mV IOH HIGH-level output current SELDR either HIGH or LOW - - −8 mA IOL LOW-level output current SELDR either HIGH or LOW - - 8 mA Tamb ambient temperature operating in free air SSTUB32868ET/G 0 - 70 °C SSTUB32868ET/S 0 - 85 °C [1] The differential inputs must not be floating, unless RESET is LOW. [2] The RESET input of the device must be held at valid logic levels (not floating) to ensure proper device operation. SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 16 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 10. Characteristics Table 8. Characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter VOH Min Typ Max Unit HIGH-level output voltage IOH = −6 mA; VDD = 1.7 V 1.2 - - V VOL LOW-level output voltage IOL = 6 mA; VDD = 1.7 V - - 0.5 V II input current all inputs; VI = VDD or GND; VDD = 1.9 V - - ±5 μA IDD supply current static standby; RESET = GND; VDD = 1.9 V; IO = 0 mA - - 2 mA static operating; RESET = VDD; VDD = 1.9 V; IO = 0 mA; VI = VIH(AC) or VIL(AC) - - 80 mA - 16 - μA per each data input (1 : 1 mode); RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle; IO = 0 mA; VDD = 1.8 V - 19 - μA per each data input (1 : 2 mode); RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle; IO = 0 mA; VDD = 1.8 V - 19 - μA Dn, CSGEN, PAR_IN inputs; VI = Vref ± 250 mV; VDD = 1.8 V 2.5 - 4 pF DCSn; VICR = 0.9 V; VID = 600 mV; VDD = 1.8 V 2.5 - 4 pF CK and CK; VICR = 0.9 V; VID = 600 mV; VDD = 1.8 V 2 - 3 pF 3 - 5 pF - 15 - Ω - 53 - Ω - 7 - Ω - 53 - Ω - +0.3VDD V IDDD dynamic operating current clock only; RESET = VDD; per MHz VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. IO = 0 mA; VDD = 1.8 V input capacitance Ci Conditions RESET; VI = VDD or GND; VDD = 1.8 V output impedance Zo normal drive; instantaneous [1] normal drive; steady-state high drive; instantaneous high drive; steady-state [1] Input RESET VIL LOW-level input voltage −0.5 VIH HIGH-level input voltage 0.7VDD - 2.5 V II input current VI = VDD −5 - +5 μA IL leakage current VI = VSS −100 −25 −10 μA [1] Instantaneous is defined as within < 2 ns following the output data transition edge. SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 17 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity Table 9. Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol Parameter fclk clock frequency tW pulse width Min Typ Max Unit - - 450 MHz 1 - - ns differential inputs active time [1][2] - - 10 ns tINACT differential inputs inactive time [1][3] - - 15 ns tsu set-up time DCSn before CK↑, CK↓, CSR HIGH; CSR before CK↑, CK↓, DCSn HIGH 0.6 - - ns DCSn before CK↑, CK↓, CSR LOW 0.5 - - ns DODTn, DCKEn ad Dn before CK↑, CK↓ 0.5 - - ns PAR_IN before CK↑, CK↓ 0.5 - - ns DCSn, DODTn, DCKEn and Dn after CK↑, CK↓ 0.4 - - ns PAR_IN after CK↑, CK↓ 0.4 - - ns tACT hold time th Conditions CK, CK HIGH or LOW [1] This parameter is not necessarily production tested. [2] VREF must be held at a valid input voltage level, and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken HIGH. [3] VREF, data and clock inputs must be held at valid voltage levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW. Table 10. Switching characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit fclk(max) maximum clock frequency input tPDM peak propagation delay single bit switching; from CK↑ and CK↓ to Qn 450 - - MHz 1.1 - 1.5 ns tPLH LOW to HIGH propagation delay from CK↑ and CK↓ to QERR 1.2 - 3 ns tPHL HIGH to LOW propagation delay from RESET↑ to QERR↓ - - 3 ns from CK↑ and CK↓ to QERR 1 - 2.4 ns - - 3 ns - - 1.6 ns [1] from RESET↑ to Qn↓ tPDMSS [1] simultaneous switching peak propagation delay from CK↑ and CK↓ to Qn [1] Includes 350 ps of test-load transmission line delay. Table 11. Output edge rates Over recommended operating conditions, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit dV/dt_r rising edge slew rate from 20 % to 80 % 1 - 4 V/ns dV/dt_f falling edge slew rate from 80 % to 20 % 1 - 4 V/ns dV/dt_Δ absolute difference between dV/dt_r (from 20 % to 80 %) or and dV/dt_f (from 80 % to 20 %) - - 1 V/ns SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 18 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 11. Test information 11.1 Parameter measurement information for data output load circuit VDD = 1.8 V ± 0.1 V. All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified. The outputs are measured one at a time with one transition per measurement. VDD DUT CK CK CK inputs RL = 1000 Ω delay = 350 ps Zo = 50 Ω 50 Ω OUT CL = 30 pF(1) RL = 1000 Ω test point RL = 100 Ω test point 002aab902 (1) CL includes probe and jig capacitance. Fig 9. Load circuit, data output measurements LVCMOS VDD 0.5VDD 0.5VDD RESET 0V tINACT IDD(1) tACT 90 % 10 % 002aaa372 (1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. Fig 10. Voltage and current waveforms; inputs active and inactive times tW VIH input VICR VICR VID VIL 002aaa373 VID = 600 mV. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs. Fig 11. Voltage waveforms; pulse duration SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 19 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity CK VICR VID CK tsu th VIH input Vref Vref VIL 002aaa374 VID = 600 mV. Vref = 0.5VDD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs. Fig 12. Voltage waveforms; setup and hold times CK VICR VICR tPLH tPHL Vi(p-p) CK VOH VT output VOL 002aaa375 tPLH and tPHL are the same as tPD. Fig 13. Voltage waveforms; propagation delay times (clock to output) LVCMOS VIH RESET 0.5VDD VIL tPHL VOH output VT VOL 002aaa376 tPLH and tPHL are the same as tPD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs. Fig 14. Voltage waveforms; propagation delay times (reset to output) SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 20 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 11.2 Data output slew rate measurement VDD = 1.8 V ± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified. VDD DUT RL = 50 Ω OUT test point CL = 10 pF(1) 002aaa377 (1) CL includes probe and jig capacitance. Fig 15. Load circuit, HIGH-to-LOW slew measurement output VOH 80 % dv_f 20 % dt_f 002aaa378 VOL Fig 16. Voltage waveforms, HIGH-to-LOW slew rate measurement DUT OUT test point CL = 10 pF(1) RL = 50 Ω 002aaa379 (1) CL includes probe and jig capacitance. Fig 17. Load circuit, LOW-to-HIGH slew measurement dt_r VOH 80 % dv_r 20 % output 002aaa380 VOL Fig 18. Voltage waveforms, LOW-to-HIGH slew rate measurement SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 21 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 11.3 Error output load circuit and voltage measurement VDD = 1.8 V ± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified. VDD DUT RL = 1 kΩ OUT test point CL = 10 pF(1) 002aaa500 (1) CL includes probe and jig capacitance. Fig 19. Load circuit, error output measurements LVCMOS RESET VDD 0.5VDD 0V tPLH VOH output waveform 2 0.15 V 002aab903 0V Fig 20. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET input timing inputs VICR Vi(p-p) VICR tPHL VDD output waveform 1 0.5VDD VOL 002aab904 Fig 21. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 22 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity timing inputs VICR Vi(p-p) VICR tPLH VOH output waveform 2 0.15 V 002aab907 0V Fig 22. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 23 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 12. Package outline TFBGA176: plastic thin fine-pitch ball grid array package; 176 balls; body 6 x 15 x 0.7 mm B D SOT932-1 A ball A1 index area A2 A E A1 detail X e1 1/2 e C e ∅v ∅w b AB AA Y W V U T R P N M L K J H G F E D C B A ball A1 index area M y y1 C C A B C M e e2 1/2 e 1 2 3 4 5 6 7 8 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.15 0.35 0.25 0.80 0.65 0.45 0.35 6.1 5.9 15.1 14.9 0.65 4.55 13.65 0.15 0.08 0.1 0.1 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT932-1 --- MO-246 --- EUROPEAN PROJECTION ISSUE DATE 06-01-11 06-01-16 Fig 23. Package outline SOT932-1 (TFBGA176) SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 24 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 25 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 13. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24. SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 26 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 14. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DDR2 Double Data Rate 2 DIMM Dual In-line Memory Module DRAM Dynamic Random Access Memory LVCMOS Low Voltage Complementary Metal-Oxide Semiconductor RDIMM Registered Dual In-line Memory Module SSTL Stub Series Terminated Logic 15. Revision history Table 15. Revision history Document ID Release date Data sheet status SSTUB32868_4 20100422 Product data sheet Modifications: SSTUB32868_3 • • Change notice Supersedes SSTUB32868_3 Section 2 “Features and benefits”: deleted (old) second bullet item Table 8 “Characteristics”: added sub-section “Input RESET” 20070307 Product data sheet - SSTUB32868_2 SSTUB32868_2 20060912 Product data sheet - SSTUB32868_1 SSTUB32868_1 20060825 Product data sheet - - SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 27 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 28 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] SSTUB32868_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 22 April 2010 © NXP B.V. 2010. All rights reserved. 29 of 30 SSTUB32868 NXP Semiconductors 1.8 V DDR2-800 configurable registered buffer with parity 18. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 8 9 10 11 11.1 11.2 11.3 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 10 Function table . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional information . . . . . . . . . . . . . . . . . . 11 Register timing . . . . . . . . . . . . . . . . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Recommended operating conditions. . . . . . . 16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 19 Parameter measurement information for data output load circuit . . . . . . . . . . . . . . . . . . 19 Data output slew rate measurement. . . . . . . . 21 Error output load circuit and voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 Soldering of SMD packages . . . . . . . . . . . . . . 25 Introduction to soldering . . . . . . . . . . . . . . . . . 25 Wave and reflow soldering . . . . . . . . . . . . . . . 25 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Contact information. . . . . . . . . . . . . . . . . . . . . 29 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 April 2010 Document identifier: SSTUB32868_4