D2 PA K PSMN017-30BL N-channel 30 V 17 mΩ logic level MOSFET in D2PAK Rev. 2 — 3 April 2012 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in D2PAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for logic level gate drive sources 1.3 Applications DC-to-DC converters Motor control Load switching Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 32 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 47 W Tj junction temperature -55 - 175 °C VGS = 4.5 V; ID = 10 A; Tj = 25 °C; see Figure 13 - 18.6 23.3 mΩ VGS = 10 V; ID = 10 A; Tj = 25 °C; see Figure 13 - 13.3 17 mΩ VGS = 4.5 V; ID = 10 A; VDS = 15 V; see Figure 14; see Figure 15 - 1.94 - nC - 5.1 - nC VGS = 10 V; Tj(init) = 25 °C; ID = 32 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped - - 13 mJ [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy Continuous current is limited by package. PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain Simplified outline Graphic symbol mb 3 S source mb D mounting base; connected to drain D G mbb076 S 2 1 3 SOT404 (D2PAK) 3. Ordering information Table 3. Ordering information Type number Package PSMN017-30BL Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped) 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 30 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 [1] - 25.5 A VGS = 10 V; Tmb = 25 °C; see Figure 1 [1] - 32 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 - 154 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 47 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 32 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 154 A VGS = 10 V; Tj(init) = 25 °C; ID = 32 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped - 13 mJ Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy Continuous current is limited by package. PSMN017-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 2 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 003aaj442 40 03aa16 120 ID (A) Pder (%) (1) 30 80 20 40 10 0 0 0 50 100 150 200 Tmb (°C) 0 50 100 150 200 Tmb (°C) (1) Capped at 32A due to package Fig 1. Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aaj594 103 ID (A) 102 Limit RDSon= VDS / ID tp =10 μ s 100 μ s 10 1 ms DC 1 10 ms 100 ms 10-1 10-1 Fig 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN017-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 3 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 3.18 3.2 K/W Rth(j-a) thermal resistance from junction to ambient - 50 - K/W 003aaj593 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 0.05 δ= P 10-1 0.02 tp T t tp single shot T 10-2 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN017-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 4 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit - - V Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 10; see Figure 11 1.3 1.7 2.15 V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 11 0.5 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 11 - - 2.45 V - 0.3 1 µA IDSS drain leakage current VDS = 30 V; VGS = 0 V; Tj = 25 °C VDS = 30 V; VGS = 0 V; Tj = 125 °C - - 50 µA IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 4.5 V; ID = 10 A; Tj = 175 °C; see Figure 12 - - 43 mΩ VGS = 4.5 V; ID = 10 A; Tj = 25 °C; see Figure 13 - 18.6 23.3 mΩ VGS = 10 V; ID = 10 A; Tj = 175 °C; see Figure 12 - 24 31.5 mΩ VGS = 10 V; ID = 10 A; Tj = 100 °C; see Figure 12 - - 23.5 mΩ VGS = 10 V; ID = 10 A; Tj = 25 °C; see Figure 13 - 13.3 17 mΩ f = 1 MHz - 2.03 - Ω ID = 10 A; VDS = 15 V; VGS = 10 V; see Figure 14; see Figure 15 - 10.7 - nC ID = 0 A; VDS = 0 V; VGS = 10 V; see Figure 14; see Figure 15 - 9.55 - nC ID = 10 A; VDS = 15 V; VGS = 4.5 V; see Figure 14; see Figure 15 - 5.1 - nC RDSon RG drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge - 1.52 - nC QGS(th) pre-threshold gate-source charge - 1 - nC QGS(th-pl) post-threshold gate-source charge - 0.5 - nC QGD gate-drain charge - 1.94 - nC VGS(pl) gate-source plateau voltage ID = 10 A; VDS = 15 V; see Figure 14; see Figure 15 - 2.86 - V Ciss input capacitance Coss output capacitance VDS = 15 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 Crss reverse transfer capacitance PSMN017-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 - 552 - pF - 127 - pF - 64 - pF © NXP B.V. 2012. All rights reserved. 5 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit td(on) turn-on delay time - 10.7 - ns tr rise time VDS = 15 V; RL = 1.5 Ω; VGS = 4.5 V; RG(ext) = 5 Ω - 9.2 - ns td(off) turn-off delay time - 11.4 - ns tf fall time - 5.1 - ns 1.2 V Source-drain diode VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; see Figure 17 - 0.89 trr reverse recovery time 17.3 - ns recovered charge IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 15 V - Qr - 6.5 - nC 003aaj415 30 10 003aaj418 30 4.5 ID (A) ID (A) 3.5 20 20 3 10 10 2.8 Tj = 175 °C VGS (V) = 2.4 0 0 1 2 3 VDS(V) Tj = 25 °C 0 4 0 1 2 3 VGS (V) 4 Tj = 25 °C Fig 5. Output characteristics; drain current as a function of drain-source voltage; typical values PSMN017-30BL Product data sheet Fig 6. Transfer characteristics; drain current as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 6 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 003aaj532 1000 C (pF) 003aaj417 30 Ciss gfs (S) 800 20 600 400 10 Crss 200 0 0 0 Fig 7. 3 6 9 VGS (V) 12 0 Input and reverse transfer capacitances as a function of gate-source voltage; typical values 003aaj458 40 Fig 8. 10 20 ID (A) 30 Forward transconductance as a function of drain current; typical values 003aab271 10-1 ID (A) 10-2 RDSon (mΩ) 30 min typ 1 2 max 10-3 10-4 20 10-5 10-6 10 0 Fig 9. 4 8 12 VGS (V) 0 16 Drain-source on-state resistance as a function of gate-source voltage; typical values PSMN017-30BL Product data sheet VGS (V) 3 Fig 10. Sub-threshold drain current as a function of gate-source voltage All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 7 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 003a a c982 3 03aa27 2 a VGS (th) (V) max 1.5 2 typ 1 min 1 0.5 0 -60 0 60 120 Tj (°C) 180 Fig 11. Gate-source threshold voltage as a function of junction temperature 0 −60 0 60 120 Tj (°C) 180 Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature 003aaj421 60 3 VDS 3.5 RDSon (mΩ) ID 40 VGS(pl) VGS(th) VGS 20 QGS1 4.5 QGS2 QGS VGS (V) = 10 QGD QG(tot) 003aaa508 0 5 10 15 20 25 ID (A) 30 Tj = 25 °C Fig 13. Drain-source on-state resistance as a function of drain current; typical values PSMN017-30BL Product data sheet Fig 14. Gate charge waveform definitions All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 8 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 003aaj423 10 003aaj424 103 VGS (V) Ciss 6V 8 6 C (pF) 24 V Coss 102 VDS = 15V 4 Crss 2 0 0 4 8 QG (nC) 10 10-1 12 Fig 15. Gate-source voltage as a function of gate charge; typical values 1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aaj425 40 IS (A) 30 20 10 Tj = 25 °C Tj = 175°C 0 0 0.4 0.8 VSD (V) 1.2 Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN017-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 9 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 7. Package outline SOT404 Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-03-16 SOT404 Fig 18. Package outline SOT404 (D2PAK) PSMN017-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 10 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN017-30BL v.2 20120403 Product data sheet - PSMN017-30BL v.1 - - Modifications: PSMN017-30BL v.1 PSMN017-30BL Product data sheet • • Status changed from objective to product. Various changes to content. 20120228 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 11 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK 9. Legal information 9.1 Data sheet status Document status[1] [2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 12 of 14 PSMN017-30BL NXP Semiconductors N-channel 30 V 17 mΩ logic level MOSFET in D2PAK Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 April 2012 Document identifier: PSMN017-30BL