ATMEL ATTINY45V-10SU

Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)
Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)
Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny25/45/85)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Programmable Dead Time Generator
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
4 Single Ended Channels
2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC and 20-pad QFN/MLF
Operating Voltage
– 1.8 - 5.5V for ATtiny25/45/85V
– 2.7 - 5.5V for ATtiny25/45/85
Speed Grade
– ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 300 μA
– Power-down Mode:
0.1μA at 1.8V
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25/V*
ATtiny45/V
ATtiny85/V*
Summary
*Preliminary
2586JS–AVR–12/06
1. Pin Configurations
Figure 1-1.
Pinout ATtiny25/45/85
PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
15
14
13
12
11
6
7
8
9
10
1
2
3
4
5
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
DNC
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
DNC
DNC
GND
DNC
DNC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
DNC
DNC
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
20
19
18
17
16
DNC
DNC
DNC
DNC
DNC
QFN/MLF
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
2
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
8-BIT DATABUS
CALIBRATED
INTERNAL
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
WATCHDOG
TIMER
TIMING AND
CONTROL
VCC
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
GND
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
GENERAL
PURPOSE
REGISTERS
TIMER/
COUNTER0
X
Y
Z
TIMER/
COUNTER1
ALU
UNIVERSAL
SERIAL
INTERFACE
STATUS
REGISTER
INTERRUPT
UNIT
PROGRAMMING
LOGIC
DATA
EEPROM
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
OSCILLATORS
ADC /
ANALOG COMPARATOR
PORT B DRIVERS
RESET
PB0-PB5
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
3
2586JS–AVR–12/06
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
2.2
2.2.1
Pin Descriptions
VCC
Supply voltage.
2.2.2
GND
Ground.
2.2.3
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on
page 61.
On the ATtiny25 device the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged
in the ATtiny15 compatibility mode for supporting the backward compatibility with ATtiny15.
2.2.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 23-3 on page
170. Shorter pulses are not guaranteed to generate a reset.
4
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
5
2586JS–AVR–12/06
4. Register Summary
Address
6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x3F
SREG
Name
I
T
H
S
V
N
Z
C
Page
page 7
0x3E
SPH
–
–
–
–
–
–
SP9
SP8
page 10
0x3D
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
page 10
0x3C
Reserved
0x3B
GIMSK
–
INT0
PCIE
–
–
–
–
–
page 51
0x3A
GIFR
–
INTF0
PCIF
–
–
–
–
–
page 52
0x39
TIMSK
–
OCIE1A
OCIE1B
OCIE0A
OCIE0B
TOIE1
TOIE0
–
page 84/page 106
0x38
TIFR
–
OCF1A
OCF1B
OCF0A
OCF0B
TOV1
TOV0
–
page 84
0x37
SPMCSR
–
–
–
CTPB
RFLB
PGWRT
PGERS
SPMEN
page 148
0x36
Reserved
0x35
MCUCR
BODS
PUD
SE
SM1
SM0
BODSE
ISC01
ISC00
page 37,page 51, page 65,
0x34
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
page 44,
0x33
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
page 82
0x32
TCNT0
0x31
OSCCAL
0x30
TCCR1
–
–
Timer/Counter0
page 83
Oscillator Calibration Register
CTC1
PWM1A
COM1A1
COM1A0
CS13
page 31
CS12
CS11
CS10
page 92, page 103
0x2F
TCNT1
Timer/Counter1
page 94, page 105
0x2E
OCR1A
Timer/Counter1 Output Compare Register A
page 94, page 105
0x2D
OCR1C
Timer/Counter1 Output Compare Register C
0x2C
GTCCR
0x2B
OCR1B
0x2A
TCCR0A
0x29
OCR0A
TSM
PWM1B
COM1B1
COM0A1
COM0A0
COM0B1
COM1B0
FOC1B
FOC1A
PSR1
PSR0
WGM01
WGM00
Timer/Counter1 Output Compare Register B
COM0B0
page 95
–
Timer/Counter0 – Output Compare Register A
0x28
OCR0B
0x27
PLLCSR
LSM
0x26
CLKPR
CLKPCE
–
0x25
DT1A
DT1AH3
DT1AH2
DT1BH3
DT1BH2
-
-
–
page 79
page 83
Timer/Counter0 – Output Compare Register B
–
page 95, page 106
page 79, page 93, page
page 84
–
–
PCKE
PLLE
PLOCK
page 97, page 107
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 32
DT1AH1
DT1AH0
DT1AL3
DT1AL2
DT1AL1
DT1AL0
page 109
DT1BH1
DT1BH0
DT1BL3
DT1BL2
DT1BL1
DT1BL0
page 110
-
-
-
-
DTPS11
DTPS10
page 109
WDE
WDP2
WDP1
WDP0
page 44
PRTIM1
PRTIM0
PRUSI
PRADC
page 36
EEAR8
page 19
0x24
DT1B
0x23
DTPS1
0x22
DWDR
0x21
WDTCR
0x20
PRR
0x1F
EEARH
0x1E
EEARL
0x1D
EEDR
0x1C
EECR
0x1B
Reserved
–
0x1A
Reserved
–
0x19
Reserved
0x18
PORTB
–
–
PORTB5
0x17
DDRB
–
–
0x16
PINB
–
0x15
PCMSK
0x14
DIDR0
0x13
GPIOR2
General Purpose I/O Register 2
page 9
0x12
GPIOR1
General Purpose I/O Register 1
page 9
0x11
GPIOR0
General Purpose I/O Register 0
page 9
0x10
USIBR
USI Buffer Register
page 119
DWDR[7:0]
WDIF
WDIE
WDP3
WDCE
–
EEAR7
EEAR6
EEAR5
EEAR4
page 145
EEAR3
EEAR2
EEAR1
EEAR0
page 19
EERIE
EEMPE
EEPE
EERE
page 20
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
page 65
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
page 65
–
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 65
–
–
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
page 52
–
–
ADC0D
ADC2D
ADC3D
ADC1D
AIN1D
AIN0D
page 125, page 143
EEPROM Data Register
–
–
EEPM1
EEPM0
page 19
–
0x0F
USIDR
0x0E
USISR
USISIF
USIOIF
USIPF
USIDC
USI Data Register
USICNT3
USICNT2
USICNT1
USICNT0
page 118
page 119
0x0D
USICR
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
page 120
0x0C
Reserved
–
0x0B
Reserved
–
0x0A
Reserved
–
0x09
Reserved
0x08
ACSR
0x07
–
ACD
ACBG
ACO
ACI
ACIE
–
ACIS1
ACIS0
page 124
ADMUX
REFS1
REFS0
ADLAR
REFS2
MUX3
MUX2
MUX1
MUX0
page 138
0x06
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
page 140
0x05
ADCH
ADC Data Register High Byte
0x04
ADCL
ADC Data Register Low Byte
0x03
ADCSRB
0x02
Reserved
–
0x01
Reserved
–
0x00
Reserved
–
BIN
ACME
IPR
–
–
page 141
page 141
ADTS2
ADTS1
ADTS0
page 124, page 142
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
7
2586JS–AVR–12/06
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
2
BRANCH INSTRUCTIONS
RJMP
k
IJMP
RCALL
k
Relative Jump
PC ← PC + k + 1
None
Indirect Jump to (Z)
PC ← Z
None
2
Relative Subroutine Call
PC ← PC + k + 1
None
3
3
ICALL
Indirect Call to (Z)
PC ← Z
None
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
8
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
1
None
1
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd ← K
None
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(z) ← R1:R0
None
IN
Rd, P
In Port
Rd ← P
None
OUT
P, Rr
Out Port
P ← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
SPM
1
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/Timer)
For On-chip Debug Only
None
None
1
N/A
9
2586JS–AVR–12/06
6. Ordering Information
6.1
ATtiny25
Speed (MHz)(3)
10
20
Notes:
Power Supply
Ordering Code(2)
Package(1)
1.8 - 5.5V
ATtiny25V-10PU
ATtiny25V-10SU
ATtiny25V-10MU
8P3
8S2
20M1
Industrial
(-40°C to 85°C)
2.7 - 5.5V
ATtiny25-20PU
ATtiny25-20SU
ATtiny25-20MU
8P3
8S2
20M1
Industrial
(-40°C to 85°C)
Operational Range
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 168
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20M1
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
10
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
6.2
ATtiny45
Speed (MHz)(3)
Power Supply
Ordering Code(2)
Package(1)
10
1.8 - 5.5V
ATtiny45V-10PU
ATtiny45V-10SU
ATtiny45V-10MU
8P3
8S2
20M1
Industrial
(-40°C to 85°C)
20
2.7 - 5.5V
ATtiny45-20PU
ATtiny45-20SU
ATtiny45-20MU
8P3
8S2
20M1
Industrial
(-40°C to 85°C)
Notes:
Operational Range
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 168
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20M1
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
11
2586JS–AVR–12/06
6.3
ATtiny85
Speed (MHz)(3)
Power Supply
Ordering Code(2)
Package(1)
10
1.8 - 5.5V
ATtiny85V-10PU
ATtiny85V-10SU
ATtiny85V-10MU
8P3
8S2
20M1
Industrial
(-40°C to 85°C)
20
2.7 - 5.5V
ATtiny85-20PU
ATtiny85-20SU
ATtiny85-20MU
8P3
8S2
20M1
Industrial
(-40°C to 85°C)
Notes:
Operational Range
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 168
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20M1
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
12
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
7. Packaging Information
7.1
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
MIN
NOM
A
b2
b3
b
4 PLCS
Side View
L
0.210
NOTE
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
0.100 BSC
eA
0.300 BSC
0.115
3
3
e
L
Notes:
MAX
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
13
2586JS–AVR–12/06
7.2
8S2
C
1
E
E1
L
N
θ
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
SIDE VIEW
NOM
MAX
NOTE
A
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
θ
0°
8°
e
Notes: 1.
2.
3.
4.
5.
MIN
2, 3
1.27 BSC
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/7/06
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
D
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
7.3
20M1
D
1
Pin 1 ID
2
SIDE VIEW
E
3
TOP VIEW
A2
D2
A1
A
0.08
1
2
Pin #1
Notch
(0.20 R)
3
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
b
L
e
BOTTOM VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
–
0.01
0.05
A2
b
0.18
D
D2
E2
L
0.23
0.30
4.00 BSC
2.45
2.60
2.75
4.00 BSC
2.45
e
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
NOTE
0.20 REF
E
Note:
C
2.60
2.75
0.50 BSC
0.35
0.40
0.55
10/27/04
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
20M1
REV.
A
15
2586JS–AVR–12/06
8. Errata
8.1
Errata ATtiny25
The revision letter in this section refers to the revision of the ATtiny25 device.
8.1.1
Rev C
No known errata
8.1.2
Rev B
• Reading EEPROM at low frequency may not work for frequencies below 900 kHz
1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
8.1.3
Rev A
Not sampled.
16
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
8.2
Errata ATtiny45
The revision letter in this section refers to the revision of the ATtiny45 device.
8.2.1
Rev E
No known errata
8.2.2
Rev D
• Reading EEPROM at low frequency may not work for frequencies below 900 kHz
1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
8.2.3
Rev B and C
•
•
•
•
PLL not locking
EEPROM read from application code does not work in Lock Bit Mode 3
Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly
1. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
2. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
3. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly
Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when
the control bits, COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0,
respectively, the OC1B-XOC1B output works correctly.
Problem Fix/Work around
The only workaround is to use same control setting on COM1A(1:0) and COM1B(1:0) control bits, see table 14-4 in the data sheet. The problem has been fixed for Tiny45 rev D.
17
2586JS–AVR–12/06
8.2.4
Rev A
•
•
•
•
•
Too high power down power consumption
DebugWIRE looses communication when single stepping into interrupts
PLL not locking
EEPROM read from application code does not work in Lock Bit Mode 3
Reading EEPROM at low frequency may not work for frequencies below 900 kHz
1. Too high power down power consumption
Three situations will lead to a too high power down power consumption. These are:
– An external clock is selected by fuses, but the I/O PORT is still enabled as an output.
– The EEPROM is read before entering power down.
– VCC is 4.5 volts or higher.
Problem fix / Workaround
– When using external clock, avoid setting the clock pin as Output.
– Do not read the EEPROM if power down power consumption is important.
– Use VCC lower than 4.5 Volts.
2. DebugWIRE looses communication when single stepping into interrupts
When receiving an interrupt during single stepping, debugwire will loose
communication.
Problem fix / Workaround
– When singlestepping, disable interrupts.
– When debugging interrupts, use breakpoints within the interrupt routine, and run into
the interrupt.
3. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
4. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
5. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
18
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
8.3
Errata ATtiny85
The revision letter in this section refers to the revision of the ATtiny85 device.
8.3.1
Rev B
No known errata.
8.3.2
Rev A
• Reading EEPROM at low frequency may not work for frequencies below 900 kHz
1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
19
2586JS–AVR–12/06
9. Datasheet Revision History
9.1
Rev. 2586J-12/06
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
20
Updated ”Low Power Consumption” on page 1.
Updated description of instruction length in “Architectural Overview” ,
starting on page 6.
Updated Flash size in ”In-System Re-programmable Flash Program
Memory” on page 14.
Updated cross-references in sections “Atomic Byte Programming” ,
“Erase” and “Write” , starting on page 16.
Updated ”Atomic Byte Programming” on page 16.
Updated ”Internal PLL for Fast Peripheral Clock Generation - clkPCK”
on page 23.
Replaced single clocking system figure with two: Figure 7-2 and Figure
7-3 on page 23.
Updated Table 7-1 on page 24, Table 7-4 on page 26 and Table 7-6 on
page 28.
Updated ”Calibrated Internal RC Oscillator” on page 27.
Updated Table 7-11 on page 29.
Updated ”OSCCAL – Oscillator Calibration Register” on page 31.
Updated ”CLKPR – Clock Prescale Register” on page 32.
Updated ”Power-down Mode” on page 35.
Updated “Bit 0” in ”PRR – Power Reduction Register” on page 38.
Added footnote to Table 9-3 on page 46.
Updated Table 12-5 on page 64.
Deleted “Bits 7, 2” in ”MCUCR – MCU Control Register” on page 65.
Updated and moved section “Timer/Counter0 Prescaler and Clock
Sources”, now located on page 67.
Updated ”Timer/Counter1 Initialization for Asynchronous Mode” on
page 89.
Updated bit description in ”PLLCSR – PLL Control and Status Register”
on page 97 and ”PLLCSR – PLL Control and Status Register” on page
107.
Added recommended maximum frequency in”Prescaling and Conversion Timing” on page 129.
Updated Figure 19-8 on page 134 .
Updated ”Temperature Measurement” on page 138.
Updated Table 19-3 on page 139.
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
9.2
Updated bit R/W descriptions in:
”TIMSK – Timer/Counter Interrupt Mask Register” on page 84,
”TIFR – Timer/Counter Interrupt Flag Register” on page 84,
”TIMSK – Timer/Counter Interrupt Mask Register” on page 95,
”TIFR – Timer/Counter Interrupt Flag Register” on page 96,
”PLLCSR – PLL Control and Status Register” on page 97,
”TIMSK – Timer/Counter Interrupt Mask Register” on page 106,
”TIFR – Timer/Counter Interrupt Flag Register” on page 106,
”PLLCSR – PLL Control and Status Register” on page 107 and
”DIDR0 – Digital Input Disable Register 0” on page 143.
Added limitation to ”Limitations of debugWIRE” on page 145.
Updated ”DC Characteristics” on page 166.
Updated Table 23-4 on page 170.
Updated Figure 23-6 on page 173.
Updated Table 23-7 on page 173.
Updated Table 24-1 on page 179.
Updated Table 24-2 on page 179.
Updated Table 24-26, Table 24-27 and Table 24-28, starting on page 188.
Updated Table 24-29, Table 24-30 and Table 24-31, starting on page 189.
Updated Table 24-33 on page 191.
Updated Table 24-40, Table 24-41, Table 24-42 and Table 24-43, starting
on page 195.
Rev. 2586I-09/06
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
All Characterization data moved to ”Electrical Characteristics” on page
166.
All Register Descriptions are gathered up in seperate sections in the
end of each chapter.
Updated Table 13-3 on page 80, Table 13-6 on page 81, Table 13-8 on
page 82 and Table 22-4 on page 152.
Updated ”Calibrated Internal RC Oscillator” on page 27.
Updated Note in Table 8-1 on page 34.
Updated ”System Control and Reset” on page 39.
Updated Register Description in ”I/O Ports” on page 53.
Updated Features in ”USI – Universal Serial Interface” on page 111.
Updated Code Example in ”SPI Master Operation Example” on page 113
and ”SPI Slave Operation Example” on page 115.
Updated ”Analog Comparator Multiplexed Input” on page 123.
Updated Figure 19-1 on page 127.
Updated ”Signature Bytes” on page 153.
Updated ”Electrical Characteristics” on page 166.
21
2586JS–AVR–12/06
9.3
Rev. 2586H-06/06
1.
2.
3.
9.4
Rev. 2586G-05/06
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
9.5
Updated Features in ”Analog to Digital Converter” on page 126.
Updated Operation in ”Analog to Digital Converter” on page 126.
Updated Table 19-3 on page 139.
Updated Table 19-2 on page 138.
Updated ”Errata” on page 209.
Rev. 2586D-02/06
1.
2.
3.
22
Updated ”Digital Input Enable and Sleep Modes” on page 57.
Updated Table 22-15 on page 163.
Updated ”Ordering Information” on page 203.
Rev. 2586E-03/06
1.
2.
3.
4.
5.
9.7
Updated ”Internal PLL for Fast Peripheral Clock Generation - clkPCK”
on page 23.
Updated ”Default Clock Source” on page 25.
Updated ”Low-frequency Crystal Oscillator” on page 27.
Updated ”Calibrated Internal RC Oscillator” on page 27.
Updated ”Clock Output Buffer” on page 30.
Updated ”Power Management and Sleep Modes” on page 34.
Added ”BOD Disable” on page 34.
Updated Figure 18-1 on page 123.
Updated ”Bit 6 – ACBG: Analog Comparator Bandgap Select” on page
124.
Added note for Table 19-2 on page 129.
Updated ”Register Summary” on page 199.
Rev. 2586F-04/06
1.
2.
3.
9.6
Updated ”Calibrated Internal RC Oscillator” on page 27.
Updated Table 7.12.1 on page 31.
Added Table 23-1 on page 169.
Updated Table 7-4 on page 26, Table 7-5 on page 27, Table 7-9 on page
29, Table 7-12 on page 30, Table 7-11 on page 29, Table 10-1 on page
48,Table 19-4 on page 139, Table 22-15 on page 163, Table 23-5 on page
171.
Updated ”Timer/Counter1 in PWM Mode” on page 89.
Updated text ”Bit 2 - TOV1: Timer/Counter1 Overflow Flag” on page 96.
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
4.
5.
6.
7.
8.
9.
9.8
Rev. 2586C-06/05
1.
2.
3.
4.
5.
6.
9.9
Updated ”Features” on page 1.
Updated Figure 1-1 on page 2.
Updated Code Examples on page 17 and page 18.
Moved “Temperature Measurement” to Section 19.9 page 138.
Updated ”Register Summary” on page 199.
Updated ”Ordering Information” on page 203.
Rev. 2586B-05/05
1.
2.
3.
4.
5.
6.
7.
8.
9.
9.10
Updated values in ”DC Characteristics” on page 166.
Updated ”Register Summary” on page 199.
Updated ”Ordering Information” on page 203.
Updated Rev B and C in ”Errata ATtiny45” on page 210.
All references to power-save mode are removed.
Updated Register Adresses.
CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE,
removed some TBD.
Removed “Preliminary Description” from ”Temperature Measurement”
on page 138.
Updated ”Features” on page 1.
Updated Figure 1-1 on page 2 and Figure 9-1 on page 39.
Updated Table 8-2 on page 38, Table 12-4 on page 64, Table 12-5 on
page 64
Updated ”Serial Programming Instruction set” on page 157.
Updated SPH register in ”Instruction Set Summary” on page 201.
Updated ”DC Characteristics” on page 166.
Updated ”Ordering Information” on page 203.
Updated ”Errata” on page 209.
Rev. 2586A-02/05
1.
Initial revision.
23
2586JS–AVR–12/06
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
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