Features • • • • • • • • • • Compatible with MCS-51™ Products 8K Bytes of Factory Programmable QuickFlash™ Memory Fully Static Operation: 0 Hz to 20 MHz Three-Level Program Memory Lock 256 x 8-Bit Internal RAM 32 Programmable I/O Lines Three 16-Bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes Description The AT80F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of QuickFlash memory. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout. The on-chip QuickFlash allows custom codes to be quickly programmed in the factory. By combining a versatile 8-bit CPU with QuickFlash on a monolithic chip, the Atmel AT80F52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. (continued) Pin Configurations 13 15 17 19 21 12 14 16 18 20 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) INDEX CORNER (RXD) (TXD) (INT0) (INT1) (T0) (T1) P1.5 P1.6 P1.7 RST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5 (AD0) (AD1) (AD2) (AD3) (T2 EX) (T2) PLCC P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3 (TXD) (INT0) (INT1) (T0) (T1) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA NC ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) (WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 (RXD) 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 (T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND 6 4 2 44 42 40 1 5 3 4 3 4 13 9 7 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 1 7 1 9 2 1 2 3 2 5 2 72 9 18 20 22 24 26 28 (WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 (AD0) (AD1) (AD2) (AD3) (T2 EX) (T2) P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3 44 42 40 38 36 34 43 41 39 37 35 P1.5 P1.6 P1.7 RST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5 AT80F52 PDIP TQFP INDEX CORNER 8-Bit Microcontroller with 8K Bytes QuickFlash™ Memory P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA NC ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) 0980A-A–12/97 3-15 Block Diagram P0.0 - P0.7 P2.0 - P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC GND RAM ADDR. REGISTER B REGISTER PORT 0 LATCH RAM PORT 2 LATCH QUICK FLASH STACK POINTER ACC BUFFER TMP1 TMP2 PROGRAM ADDRESS REGISTER PC INCREMENTER ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PROGRAM COUNTER PSW PSEN ALE EA TIMING AND CONTROL INSTRUCTION REGISTER DPTR RST PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS OSC P1.0 - P1.7 3-16 AT80F52 P3.0 - P3.7 AT80F52 The AT80F52 provides the following standard features: 8K bytes of QuickFlash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT80F52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset. Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during QuickFlash verification. Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during QuickFlash verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for QuickFlash verification. Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe) RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. 3-17 If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. PSEN Program Store Enable is the read strobe to external program memory. When the AT80F52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. XTAL2 Output from the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. EA External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Table 1. AT80F52 SFR Map and Reset Values 0F8H 0F0H 0FFH B 00000000 0F7H 0E8H 0E0H 0EFH ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 00000000 0C8H T2CON 00000000 0D7H T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 0CFH 0C0H 0C7H 0B8H IP XX000000 0BFH 0B0H P3 11111111 0B7H 0A8H IE 0X000000 0AFH 0A0H P2 11111111 0A7H 98H SCON 00000000 90H P1 11111111 88H TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 80H P0 11111111 SP 00000111 DPL 00000000 DPH 00000000 3-18 SBUF XXXXXXXX 9FH 97H AT80F52 TH0 00000000 TH1 00000000 8FH PCON 0XXX0000 87H AT80F52 Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. Table 2. T2CON—Timer/Counter 2 Control Register T2CON Address = 0C8H Reset Value = 0000 0000B Bit Addressable Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 7 6 5 4 3 2 1 0 Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered). CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Data Memory The AT80F52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. 3-19 Timer 0 and 1 Timer 0 and Timer 1 in the AT80F52 operate the same way as Timer 0 and Timer 1 in the AT89C51. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. Capture Mode RCLK +TCLK CP/RL2 TR2 0 0 1 16-Bit Auto-Reload In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 1. 0 1 1 16-Bit Capture Auto-Reload (Up or Down Counter) 1 X 1 Baud Rate Generator X X 0 (Off) Table 3. Timer 2 Operating Modes MODE In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Figure 1. Timer in Capture Mode ÷12 OSC C/T2 = 0 TH2 TL2 OVERFLOW CONTROL C/T2 = 1 TF2 TR2 CAPTURE T2 PIN RCAP2H RCAP2L TRANSITION DETECTOR TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 3-20 AT80F52 AT80F52 Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. Figure 2. Timer 2 Auto Reload Mode (DCEN = 0) ÷12 OSC C/T2 = 0 TH2 TL2 OVERFLOW CONTROL TR2 C/T2 = 1 RELOAD TIMER 2 INTERRUPT T2 PIN RCAP2H RCAP2L TF2 TRANSITION DETECTOR EXF2 T2EX PIN CONTROL EXEN2 Table 4. T2MOD—Timer 2 Mode Control Register T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable Bit — — — — — — T2OE DCEN 7 6 5 4 3 2 1 0 Symbol Function — Not implemented, reserved for future T2OE Timer 2 Output Enable bit. DCEN When set, this bit allows Timer 2 to be configured as an up/down counter. 3-21 Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) (DOWN COUNTING RELOAD VALUE) 0FFH ÷12 OSC TOGGLE 0FFH EXF2 OVERFLOW C/T2 = 0 TH2 TL2 TF2 CONTROL TR2 C/T2 = 1 TIMER 2 INTERRUPT T2 PIN RCAP2H RCAP2L COUNT DIRECTION 1=UP 0=DOWN (UP COUNTING RELOAD VALUE) T2EX PIN Figure 4. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW ÷2 "0" "1" NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 SMOD1 OSC ÷2 C/T2 = 0 "1" TH2 "0" TL2 RCLK CONTROL TR2 ÷ 16 Rx CLOCK C/T2 = 1 "1" "0" T2 PIN TCLK RCAP2H RCAP2L TRANSITION DETECTOR ÷ 16 T2EX PIN EXF2 CONTROL EXEN2 3-22 AT80F52 TIMER 2 INTERRUPT Tx CLOCK AT80F52 Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation. Timer 2 Overflow Rate Modes 1 and 3 Baud Rates = -----------------------------------------------------------16 The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below. Oscillator Frequency Modes 1 and 3 --------------------------------------- = --------------------------------------------------------------------------------------------32 × [ 65536 – (RCAP2H,RCAP2L) ] Baud Rate where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Figure 5. Timer 2 in Clock-Out Mode OSC ÷2 TL2 (8-BITS) TH2 (8-BITS) RCAP2L RCAP2H TR2 C/T2 BIT P1.0 (T2) ÷2 T2OE (T2MOD.1) TRANSITION DETECTOR P1.1 (T2EX) EXF2 TIMER 2 INTERRUPT EXEN2 3-23 Programmable Clock Out A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation. Oscillator Fequency Clock-Out Frequency = -----------------------------------------------------------------------------------------4 × [ 65536 – (RCAP2H,RCAP2L) ] In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. UART The UART in the AT80F52 operates the same way as the UART in the AT89C52. Table 5. Interrupt Enable (IE) Register (MSB) EA (LSB) — ET2 ES ET1 EX1 Enable Bit = 0 disables the interrupt. Symbol Position Function EA IE.7 Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. — IE.6 Reserved. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. User software should never write 1s to unimplemented bits, because they may be used in future AT89 products. Interrupts 3-24 AT80F52 EX0 Enable Bit = 1 enables the interrupt. Figure 6. Interrupt Sources The AT80F52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows. ET0 0 INT0 IE0 1 TF0 0 INT1 IE1 1 TF1 TI RI TF2 EXF2 AT80F52 Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 8. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Figure 7. Oscillator Connections C2 XTAL2 C1 XTAL1 Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. GND Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators Figure 8. External Clock Drive Configuration Power Down Mode NC XTAL2 EXTERNAL OSCILLATOR SIGNAL XTAL1 In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is GND Status of External Pins During Idle and Power Down Modes Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data 3-25 Program Memory Lock Bits The AT80F52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 Protection Type 1 U U U No program lock features. 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the QuickFlash memory is disabled. 3 P P U Same as mode 2, but verify is also disabled. 4 P P P Same as mode 3, but external execution is also disabled. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. Programming/Verifying the QuickFlash The AT80F52 can only be programmed by Atmel. Customer codes should be submitted in duplicate on a floppy disk or uploaded to Atmel’s bulletin board or Web site. The code should be in the Intel Hex format. The desired states of the Lock Bits should be specified. Once programmed, the code memory and Lock Bits cannot be erased or reprogrammed. Please consult the factory or Atmel’s representatives for details on submitting custom codes. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 80H indicates QuickFlash (032H) = 02H indicates AT80F52 QuickFlash Verification Modes RST PSEN ALE EA P2.6 P2.7 P3.6 P3.7 Read Code Data H L H H L L H H Read Signature Byte H L H H L L L L Mode 3-26 AT80F52 AT80F52 Figure 9. Verifying the QuickFlash Memory +5V AT80F52 A0 - A7 ADDR. OOOOH/1FFFH A8 - A12 P1 VCC P2.0 - P2.4 P0 PGM DATA (USE 10K PULLUPS) P2.6 P2.7 SEE QUICK FLASH VERIFICATION MODES TABLE ALE P3.6 VIH P3.7 XTAL 2 EA XTAL1 RST 3-20 MHz GND VIH PSEN QuickFlash Verification Characteristics TA = 0°C to 70°C, VCC = 5.0 ± 10% Min Max Units 3 20 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tAVQV Address to Data Valid 48tCLCL tELQV ENABLE Low to Data Valid 48tCLCL tEHQZ Data Float After ENABLE 0 48tCLCL QuickFlash Verification Waveforms VERIFICATION ADDRESS P1.0 - P1.7 P2.0 - P2.4 tAVQV DATA OUT PORT 0 ALE LOGIC 1 LOGIC 0 EA LOGIC 1 LOGIC 0 P2.7 (ENABLE) tELQV tEHQZ 3-27 Absolute Maximum Ratings* Operating Temperature .................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage............................................. 6.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current...................................................... 15.0 mA DC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted. Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA) -0.5 0.2 VCC-0.1 V VIL1 Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V VIH Input High Voltage 0.2 VCC+0.9 VCC+0.5 V VIH1 Input High Voltage 0.7 VCC VCC+0.5 V IOL = 1.6 mA 0.45 V 0.45 V VOL (Except XTAL1, RST) (XTAL1, RST) Output Low Voltage (1) (Ports 1,2,3) Voltage(1) VOL1 Output Low (Port 0, ALE, PSEN) IOL = 3.2 mA VOH Output High Voltage (Ports 1,2,3, ALE, PSEN) IOH = -60 µA, VCC = 5V ± 10% VOH1 Output High Voltage (Port 0 in External Bus Mode) 2.4 V IOH = -25 µA 0.75 VCC V IOH = -10 µA 0.9 VCC V 2.4 V IOH = -300 µA 0.75 VCC V IOH = -80 µA 0.9 VCC V IOH = -800 µA, VCC = 5V ± 10% IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA ITL Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pulldown Resistor 300 KΩ CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF ICC Power Supply Current Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA VCC = 6V 100 µA VCC = 3V 40 µA Power Down Mode Notes: (1) 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V. 3-28 50 AT80F52 AT80F52 AC Characteristics Under operating conditions, load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics Symbol Parameter 12 MHz Oscillator Variable Oscillator Min Min Max 0 20 Max Units 1/tCLCL Oscillator Frequency tLHLL ALE Pulse Width 127 2tCLCL-40 ns tAVLL Address Valid to ALE Low 43 tCLCL-13 ns tLLAX Address Hold After ALE Low 48 tCLCL-20 ns tLLIV ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns tPLPH PSEN Pulse Width 205 3tCLCL-20 ns tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold After PSEN tPXIZ Input Instruction Float After PSEN tPXAV PSEN to Address Valid tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6tCLCL-100 ns tWLWH WR Pulse Width 400 6tCLCL-100 ns tRLDV RD Low to Valid Data In tRHDX Data Hold After RD tRHDZ Data Float After RD 97 2tCLCL-28 ns tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns tAVDV Address to Valid Data In 585 9tCLCL-165 ns tLLWL ALE Low to RD or WR Low 200 3tCLCL+50 ns tAVWL Address to RD or WR Low 203 4tCLCL-75 ns tQVWX Data Valid to WR Transition 23 tCLCL-20 ns tQVWH Data Valid to WR High 433 7tCLCL-120 ns tWHQX Data Hold After WR 33 tCLCL-20 ns tRLAZ RD Low to Address Float tWHLH RD or WR High to ALE High 233 4tCLCL-65 145 0 3tCLCL-45 0 59 75 tCLCL-8 0 5tCLCL-90 3tCLCL-50 0 43 123 tCLCL-20 ns ns ns 0 300 ns ns tCLCL-10 252 MHz ns ns 0 ns tCLCL+25 ns 3-29 External Program Memory Read Cycle tLHLL ALE tAVLL tLLIV tLLPL tPLIV PSEN tPXAV tPLAZ tPXIZ tLLAX tPXIX A0 - A7 PORT 0 tPLPH INSTR IN A0 - A7 tAVIV A8 - A15 PORT 2 A8 - A15 External Data Memory Read Cycle tLHLL ALE tWHLH PSEN tLLDV tRLRH tLLWL RD tLLAX tAVLL PORT 0 tRLDV tRLAZ A0 - A7 FROM RI OR DPL tRHDZ tRHDX DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 3-30 P2.0 - P2.7 OR A8 - A15 FROM DPH AT80F52 A8 - A15 FROM PCH AT80F52 External Data Memory Write Cycle tLHLL ALE tWHLH PSEN tLLWL WR tAVLL tLLAX tQVWX A0 - A7 FROM RI OR DPL PORT 0 tWLWH tQVWH DATA OUT tWHQX A0 - A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH External Clock Drive Waveforms tCHCX VCC - 0.5V tCHCX tCLCH tCHCL 0.7 VCC 0.2 VCC - 0.1V 0.45V tCLCX tCLCL External Clock Drive Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period tCHCX Min Max Units 0 20 MHz 41.6 ns High Time 15 ns tCLCX Low Time 15 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns 3-31 Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF. Symbol Parameter 12 MHz Osc Min Variable Oscillator Max Min Units Max tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-117 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns Shift Register Mode Timing Waveforms INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH WRITE TO SBUF tXHQX 0 1 tXHDV OUTPUT DATA CLEAR RI VALID 2 3 4 5 6 tXHDX VALID SET TI VALID VALID VALID VALID VALID AC Testing Input/Output Waveforms(1) Note: 3-32 1. Float Waveforms(1) V LOAD+ 0.2 VCC + 0.9V TEST POINTS 0.45V VALID SET RI INPUT DATA VCC - 0.5V 7 AT80F52 V LOAD - Note: 1. V OL - 0.1V V OL + 0.1V Timing Reference Points V LOAD 0.2 VCC - 0.1V AC Inputs during testing are driven at V CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0. 0.1V 0.1V For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs. AT80F52 Ordering Information Speed (MHz) Power Supply 12 5V ± 20% 16 20 5V ± 20% 5V ± 20% Ordering Code Package Operation Range AT80F52-12AC AT80F52-12JC AT80F52-12PC 44A 44J 40P6 Commercial (0°C to 70°C) AT80F52-12AI AT80F52-12JI AT80F52-12PI 44A 44J 40P6 Industrial (-40°C to 85°C) AT80F52-16AC AT80F52-16JC AT80F52-16PC 44A 44J 40P6 Commercial (0°C to 70°C) AT80F52-16AI AT80F52-16JI AT80F52-16PI 44A 44J 40P6 Industrial (-40°C to 85°C) AT80F52-20AC AT80F52-20JC AT80F52-20PC 44A 44J 40P6 Commercial (0°C to 70°C) AT80F52-20AI AT80F52-20JI AT80F52-20PI 44A 44J 40P6 Industrial (-40°C to 85°C) Package Type 44A 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 3-33