29C516E
16–Bit Flow–Through EDAC
Error Detection And Correction unit
1. Introduction
The 29C516E Atmel EDAC is a very low power
flow–through 16–bit Error Detection And Correction unit
(EDAC) with two user data buses. The EDAC is used in
a high integrity system for monitoring and correction of
data values coming from the memory space. During a
processor write cycle, at each memory location (16–bit
width), EDAC calculated checkword (6 or 8–bit width) is
added. When performing a read operation from memory,
the 29C516E verifies the entire checkword and data
combination. It detects and can correct 100% of all the
single–bit errors and it detects all double–bit errors.
When the 29C516E uses 6–checkbit, it can detect any
error on any single 4–bit memory chip. The 8–check–bit
option gives the additional capability to detect all errors
on any single 8–bit memory chip. All the errors are
signaled to the master system (via 2 error Flags) in order
to allow the processor to make the required action.
The 29C516E operates in two possible modes: corrected
or detected mode. In the corrected mode, the single–bit in
error is complemented (corrected). Then, the available
entire data is placed on the output port and the Correctable
Error Flag is set. In case of double–bit errors (or more),
the corrupted data is placed on the output port and the
Uncorrectable Error Flag is set. Note that when there is
more than two errors, then some bit patterns may appear
as possible correctable errors. Therefore, if the
environment produces this type of error, the EDAC must
be used in detect and provide no automatic correction.
Data and syndrome analysis must be done.
The 29C516E acts as a data buffer for µP–memory
interfacing. A flow–through EDAC is placed in the data
bus path, between the processor and the memory to be
protected. This component is able to serve two different
users of one memory space. So, it forms the interface
between the 22/24–bit (16+6/16+8) memory data bus and
the two 16–bit processor data busses with a high drive
capability (–12.8 mA). The two data ports can be used to
create a dual port bus in front of memory space. The
User–1(2) can transfer data from/to the memory or
from/to the User–2(1), by–passing the memory. During
read or write memory cycles processed by the User–1(2),
the User–2(1) have the possibility to listen the
transferred data.
2. Features
Very Low Power CMOS
16–Bit operation with 6 or 8 Check Bits
Fast Error Detection : 31 ns (max.)
Fast Error Correction : 32 ns (max.)
Corrects all Single–Bit Errors
Detects all Double–Bit Errors
Detects some Multi–Bit Errors
Detects Chip Errors (x1, x4 & x8 RAM Format)
Atmel Corporation
Rev. D (09 Dec. 97)
Correctable and Uncorrectable Error Flags
Two User Data Buses
User to User Transfer and Listening operation
High Drive Capability on Buses : –12.8 mA
TTL Compatible
Single 5V ±10% Power Supply
100 Pin Multilayer Quad Flat Pack
(Flat leaded or L leaded).
1
29C516E
3. Interface
3.1. Functional Diagram
Figure 1.Functional Diagram
CHECK BIT
GENERATOR
CORRECT
SYNCHK
8
I/O
BUFFER
8
MC[0..7]
16
MEM1
EN1
RD/WR1
8
U1D[0..15]
16
16
I/O
BUFFER 16
U2/U1
TRANS
U2D[0..15]
CONTROLLER
16
29C516E
16
I/O
BUFFER 16
RD/WR2
EN2
MEM2
16
16
CERR
NCERR
I/O
BUFFER
16
SYNDROME
DECODER
8
N22
16
MD[0..15]
SYNDROME
GENERATOR
3.2. Block Diagram
Figure 2.Block Diagram
VCC
CORRECT
SYNCHK
N22
U1/U2
TRANS
29C516E
U1D[0..15] MC[0..7]
EN1
MEM1
RD/WR1 MD[0..15]
U2D[0..15]
EN2
MEM2
RD/WR2
CERR
NCERR
GND
2
Rev. D (09 Dec. 97)
29C516E
3.3. Pin Configuration for multilayer quad Flat–pack (flat or L leaded)
Vcc
RD/WR2
CORRECT
SYNCHK
TRANS
U2/U1
EN2
Gnd
Gnd
MC[7]
MC[6]
MC[5]
MC[4]
Vcc
MC[3]
MC[2]
MC[1]
MC[0]
nc
nc
Figure 3.Pin Configuration
MQFPF100
or
MQFPL100
(Top view)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
nc
nc
Gnd
MD[15]
MD[14]
MD[13]
MD[12]
Vcc
MD[11]
MD[10]
MD[9]
MD[8]
Gnd
MD[7]
MD[6]
MD[5]
MD[4]
Vcc
MD[3]
MD[2]
MD[1]
MD[0]
Gnd
MEM1
EN1
RD/WR1
Vcc
U1D[0]
nc
nc
nc
Vcc
U1D[14]
U1D[13]
U1D[12]
Gnd
U1D[11]
U1D[10]
U1D[9]
U1D[8]
Vcc
U1D[7]
U1D[6]
U1D[5]
U1D[4]
Gnd
U1D[3]
U1D[2]
U1D[1]
nc
nc
nc
MEM2
Gnd
U2D[15]
U2D[14]
U2D[13]
U2D[12]
Vcc
U2D[11]
U2D[10]
U2D[9]
U2D[8]
Gnd
U2D[7]
U2D[6]
U2D[5]
U2D[4]
Vcc
U2D[3]
U2D[2]
U2D[1]
U2D[0]
Gnd
NCERR
CERR
N22
U1D[15]
nc
nc
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
index corner
3
Rev. D (09 Dec. 97)
29C516E
3.4. Pin Description
Table 1:
Name
Pin Description
I/O
Active
Description
U1D[0..15]
53,49..47,45..42,40..37,35..33,28
I/O*
High
User 1 Data Bus
U2D[0..15]
23..20,18..15,13..10,8..5
I/O*
High
User 2 Data Bus
ΜD[0..15]
59..62,64..67,69..72,74..77
I/O*
High
Memory Data Bus
ΜC[0..7]
83..86,88..91
I/O*
High
Memory Check–bit Bus
CERR
26
O
Low
Correctable Error
NCERR
25
O
Low
Uncorrectable Error
Buses
Error Flags
General Control Signals
CORRECT
98
I*
High
When active, the EDAC is in CORRECT mode. If low,
the EDAC is in DETECT mode.
SYNCHK
97
I*
Low
Selects the Syndrome bits (high byte) and the Check–bits
(low byte) to be driven on the selected User Data Bus.
N22
27
I*
High
When active, the EDAC uses 6 check–bits. If low, the
EDAC uses 8 check–bits in memory read.
TRANS
96
I*
H/L
Selects the Data path to be used. If high, the EDAC
access the memory, if low, the EDAC access the transfer
buffer.
U2/U1
95
I*
H/L
Selects who is the master of User 1 and User 2. The
master is responsible for applying RD/WRx, MEMx, and
ENx signals in a correct way.
User 1 Control Signals
RD/WRT
55
I*
H/L
User 1 Read/Write signal
EN1
56
I*
Low
User 1 Output Enable
MEM1
57
I*
Low
User 1 Memory Select
User 1 Control Signals
RD/WR2
99
I*
H/L
User 2 Read/Write signal
EN2
94
I*
Low
User 2 Output Enable
MEM2
3
I*
Low
User 2 Memory Select
VCCB
9,19,32,41,54,63,73,87
I
–
Buffers supply (5 V nominal)
GNDB
4,14,24,36,46,58,68,78,92
I
–
Buffers 0 V nominal reference
VCCC
100
I
–
Core supply (5 V nominal)
GNDC
93
I
–
Core 0 V reference
Power (Buffers)
Power (Core)
* Pull–up buffers
4
Rev. D (09 Dec. 97)
29C516E
4. Check–Bit Generation
The Check–bit Generator produces 8 check–bits
(whatever N22 value) from the incoming User Data Word
UxD[0..15] according the Table 2.
Example: to create check–bit 0, bit 13, 12, 8, 7, 6, 5, 4 and
0 of the Data Word are XORed together.
If memory devices 8–bit wide are used, 24 bits
(MD[0..15] & MC[0..7]) are stored to give error
detection. But if memory devices 1–bit or 4–bit wide are
used, 22 bits (MD[0..15] & MC[0..5]) are stored to give
error detection.
Table 2: Check Bit Generation (indicates a bit of UxD bus used in the XOR/NXOR)
MC[..]
PARITY
UxD[..]
15
0
14
13
12
x
x
Even(XOR)
1
Even(XOR)
2
Odd(NXOR)
3
Odd(NXOR)
4
Even(XOR)
x
5
Even(XOR)
x
6
Even(XOR)
7
Odd(NXOR)
11
x
10
x
x
9
x
x
x
x
x
x
x
7
6
5
4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
1
x
x
x
2
x
x
x
x
3
x
x
x
x
8
x
x
x
x
x
x
x
x
x
x
x
x
x
5. Syndrome Generation
The syndrome Generator produces 8 syndrome–bits
(whatever N22 value) from the incoming Memory Data
Word MD[0..15] and the associated Check–bits MC[0..7]
(or MC[0..5]) according the Table 3.
Syndrome–bit SY[x] is the XOR of the generated
Check–bit MC[x] with the generation of Chek–bit on
MD[..].
Example: to create syndrome–bit 3, first the bit 14,
13, 10, 4, 3, 2, 1 and 0 of the Data Word
(MD[14,13,10,4,3,2,1,0]) are NXORed. Then, the result
is XORed with the associated Check–bit (MC[3]) of the
Check–byte read in the same time as Data Word is
checked.
If the memory uses x8 devices, then the bits should be
physically divided as follows: MC[0..7], MD[0..7] and
MD[8..15] . For x4 organization, the bits should be
divided MC[0..2]+MC[6], MC[3..5]+MC[7], MD[0..3],
MD[4..7], MD[8..11] and MD[12..15].
Table 3: Syndrome Bit Generation (indicates a bit of MD and MC buses used in the XOR/NXOR)
SY[..]
PARITY
MD[..]
15
0
14
EVEN(XOR)
1
EVEN(XOR)
2
ODD(NXOR)
3
ODD(NXOR)
4
EVEN(XOR)
x
5
EVEN(XOR)
x
6
EVEN(XOR)
7
ODD(NXOR)
13
12
x
x
x
x
x
10
x
x
x
x
x
x
x
MC[..]
8
7
6
5
4
x
x
x
x
x
x
x
x
x
x
9
x
x
x
x
x
x
x
x
x
x
x
x
x
3
2
1
0
7
3
6
2
1
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
4
x
x
x
x
x
5
x
x
x
x
x
x
11
x
x
x
x
x
x
x
5
Rev. D (09 Dec. 97)
29C516E
6. Syndrome Decoding
The syndrome decoder generates the error flags CERR
(Correctable ERRor) and NCERR (Non–Correctable
ERRor). If a correctable error occurs, the 29C516E
EDAC provides corrected data to the user. The inputs are
the 8 syndrome bits from the syndrome generator, the 16
data bits from the memory and the control signal N22.
N22 signal controls if 22 or 24 bits shall be decode from
the entire memory word.
Table 4: 6–Bit Syndrome Word to Bit–In–Error (N22=”1”)
Syndrome Bit SY[..]
Hex
0
1
2
3
5
0
0
1
1
4
0
1
0
1
Hex
3
2
1
0
0
0
0
0
0
N.E.D
MC4
MC5
D
1
0
0
0
1
MC0
D
D
MD7
2
0
0
1
0
MC1
D
D
MD11
3
0
0
1
1
D
MD8
MD6
D
4
0
1
0
0
MC2
D
D
MD15
5
0
1
0
1
D
MD5
MD12
D
6
0
1
1
0
D
MD9
M
D
7
0
1
1
1
M
D
D
M
8
1
0
0
0
MC3
D
D
M
D
9
1
0
0
1
D
M
MD13
A
1
0
1
0
D
MD10
MD14
D
B
1
0
1
1
MD4
D
D
M
C
1
1
0
0
D
MD2
MD3
D
D
1
1
0
1
MD0
D
D
M
E
1
1
1
0
MD1
D
D
M
F
1
1
1
1
D
M
M
D
Note :
N.E.D = No Errors Detected
MDx = Memory Data Bit–In–Error
MCx = Memory Check Bit–In–Error
D = Double–Bit–In–Error Detected
M = Multi–Bit–In–Error Detected
6
Rev. D (09 Dec. 97)
29C516E
Table 5: 8–Bit Syndrome Word to Bit–In–Error (N22 = ”0”)
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Syndrome Bit
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SY [..]
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D
Hex
3
2
1
0
0
0
0
0
0
N.E.D
MC4
MC5
D
MC6
D
D
D
MC7
D
D
D
D
M
M
1
0
0
0
1
MC0
D
D
D
D
D
D
MD7
D
M
D
M
M
D
D
D
2
0
0
1
0
MC1
D
D
M
D
D
D
D
D
M
D
D
M
D
D
MD11
3
0
0
1
1
D
D
MD6
D
D
MD8
D
D
D
M
D
D
D
D
M
D
4
0
1
0
0
MC2
D
D
D
D
M
M
M
D
D
D
MD15
M
D
D
D
5
0
1
0
1
D
M
D
D
D
D
M
M
D
D
MD12
D
D
MD5
D
D
6
0
1
1
0
D
MD9
M
D
D
D
M
M
D
D
M
D
D
M
M
D
7
0
1
1
1
M
D
D
M
M
D
D
D
M
D
D
M
M
D
D
M
8
1
0
0
0
MC3
D
D
M
D
M
D
D
D
D
D
M
M
D
D
M
9
1
0
0
1
D
M
M
D
D
M
D
D
M
M
D
D
D
M
MD13
D
A
1
0
1
0
D
MD10
MD14
D
D
D
D
D
M
D
D
D
D
M
M
D
B
1
0
1
1
D
D
D
M
MD4
D
D
D
M
M
M
M
D
M
D
M
C
1
1
0
0
D
M
D
D
D
D
M
M
D
D
MD3
D
D
MD2
D
D
D
1
1
0
1
MD0
D
D
M
D
D
M
M
D
D
D
M
M
D
D
M
E
1
1
1
0
M
D
D
M
D
D
M
M
D
D
D
M
MD1
D
D
M
F
1
1
1
1
D
M
M
D
D
M
M
M
D
M
M
D
D
M
M
D
Note :
N.E.D = No Errors Detected
MDx = Memory Data Bit–In–Error
MCx = Memory Check Bit–In–Error
D = Double–Bit–In–Error Detected
M = Multi–Bit–In–Error Detected
7. The 6–Bit Syndrome Word
This feature is available when the N22 pin is driven at a
high level.
7.1. No Errors
If there are no errors in the read Data or Check–Bit, all the
syndrome byte is ”00”. The EDAC flags are inactive.
No Error : SY=00
7.2. Single Bit–Error
A single bit–error in a Memory Data word read (MD[..])
causes three syndrome bits to be set to one. The code
formed indicates which bit of the Memory Data word is
incorrect.
For example, if MD[2] were incorrect, the syndrome byte
would have bits 2, 3 and 4 set to one. The syndrome
decoder of 29C516E EDAC decodes the information in
the syndrome byte and only sets low the error flag CERR.
In correct mode (CORRECT pin active), it inverts (and
hence corrects) the relevant bit in error of the Memory
Data word and provides the expected Data word for the
EDAC controller.
If there is an error in the Memory Check–bit (MC[..]),
only one bit of the syndrome is set to one.
In this case, the syndrome decoder sets low the
correctable error flag CERR, but NCERR does not
change. It does not correct the Check–bit because these
bits are not used by the system.
7
Rev. D (09 Dec. 97)
29C516E
Table 6: Single Bit–Error
MD[..]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
SY(hexa)
34h
2Ah
29h
25h
32h
1Ah
16h
13h
31h
23h
15h
0Bh
2Ch
1Ch
0Eh
0Dh
MC[..]
[–]
[–]
[5]
[4]
[3]
[2]
[1]
[0]
SY(hexa)
––h
––h
20h
10h
08h
04h
02h
01h
7.3. Double–Bit Error
If two errors occurs, there will be either 2, 4 or 6 bits set
to one in the syndrome byte. The syndrome value
generated by a double–bit error does not take place of a
syndrome value generated by a single–bit error. Then,
only the non correctable error flag NCERR will be
activated to indicate that errors are present but cannot
be corrected.
Example: If MD[4] and MC[2] are incorrect, syndrome
bits [0], [1], [2] and [3] are set to one (SY=0Fh ), NCERR
is set low and CERR remains at high level.
7.4. Triple–Bit Error
Triple–Bit Error When three errors are detected, an error
flag is set low as warning to the system. But the generated
syndrome can have the listed value of single–bit error.
The device must be in detect mode to prevent false
correction occurring.
Example: If MD[0], MD[14] and MC[1] are corrupted,
the syndrome value is ”25h ”. This is decoded by the
29C516E EDAC as being a correctable error on MD[12].
The CERR flag is set low and correction would take
place if the device is in correct mode. This would cause
more errors.
7.5. 4–bit Wide Memory Error
The 6 check–bit code can be used to provide error
detection for up to 4 errors occurring in the following
groups: MD[15..12], MD[11..8], MD[7..4], MD[3..0],
MC[5..3] and MC[2..0]. The 29C516E EDAC can flag
any number of errors in 4–bit wide memory chip. A
special attention must be taken, multi–bit error ( 3)
located into the defined groups can provide the syndrome
byte of a single–bit error.
Example: If MD[3], MD[2], MD[1] and MD[0] are in
error, the syndrome code is ”33 h ”;
8. The 8–Bit Syndrome Word
This feature is available when the N22 pin is driven at a
low level.
8.1. No Errors
If there are no errors in the read Data or Check–Bit, all the
syndrome byte is ”00”. The EDAC flags are inactive.
No Error : SY=00
8.2. Single Bit–Error
Single Bit–Error A single bit–error in a Memory Data
word read (MD[..]) causes three syndrome bits to be set
to one. The code formed indicates which bit of the
Memory Data word is incorrect.
For example, if MD[10] were incorrect, the syndrome
byte would have bits 1, 3 and 4 set to one. The syndrome
decoder of 29C516E EDAC decodes the information in
the syndrome byte and only sets low the error flag CERR.
In correct mode (CORRECT pin active), it inverts (and
hence corrects) the relevant bit in error of the Memory
Data word and provides the expected Data word for the
EDAC controller.
If there is an error in the Memory Check–bit (MC[..]),
only one bit of the syndrome is set to one.
In this case, the syndrome decoder sets low the
correctable error flag CERR, but NCERR does not
change. It does not correct the Check–bit because these
bits are not used by the system.
8
Rev. D (09 Dec. 97)
29C516E
Table 7: Single Bit Error
MD[..]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
SY(hexa)
34h
2Ah
29h
25h
32h
1Ah
16h
13h
31h
23h
15h
0Bh
2Ch
1Ch
0Eh
0Dh
MC[..]
[–]
[–]
[5]
[4]
[3]
[2]
[1]
[0]
SY(hexa)
––h
––h
20h
10h
08h
04h
02h
01h
8.3. Double–Bit Error
If two errors occur, there will be 2, 3, 4, 5, 6 or 8 bits set
to one in the syndrome byte. The syndrome value
generated by a double–bit error does not take place of a
syndrome value generated by a single–bit error. Then,
only the non correctable error flag NCERR will be
activated to indicate that errors are present but cannot be
corrected.
Example: If MD[5] and MC[7] are incorrect, syndrome
bits [0], [2], [4] and [6] are set to one (SY=55h ), NCERR
is set low and CERR remains at high level.
8.4. Triple–Bit Error
When three errors are detected, an error flag is set low as
warning to the system. But the generated syndrome can
have the listed value of single–bit error. The device must
be in detect mode to prevent false correction occurrence.
Example: If MD[0], MD[9] and MC[0] are corrupted, the
syndrome value is ”1Ah ”.
This is decoded by the 29C516E EDAC as being a
correctable error on MD[10]. The CERR flag is set low
and correction would take place if the device is in correct
mode. This would cause more errors.
8.5. 4–bit Wide Memory Error
The 8 check–bit code can be used to provide error
detection for up to 4 errors occur in the following groups:
MD[15..12], MD[11..8], MD[7..4], MD[3..0], MC[7..4]
and MC[3..0]. The 29C516E EDAC can flag any number
of errors in 4–bit wide memory chip.
A special attention must be taken, multi–bit error ( 3)
located into the defined groups can provide the syndrome
byte of a single–bit error.
Example: If MD[11], MD[10], MD[9] and MD[8] are in
error, the syndrome code is ”AD h ”.
8.6. 8–bit Wide Memory Error
The 8 check–bit code can be used to provide error
detection for up to 8 errors occurring in the following
groups: MD[15..8], MD[7..0] and MC[7..0].
The 29C516E EDAC can flag any number of errors in
8–bit wide memory chip. A special attention must be
taken, multi–bit error ( 3) located into the defined groups
can provide the syndrome byte of a single–bit error.
Example: If MD[13], MD[12], MD[10] and MD[9] are in
error, the syndrome code is ”40h ”. (In 6 check–bit
coding, the syndrome code should have been ”00h ”, the
”No Error Detected” value.) Note that the syndrome code
”40 h ” is also the code for MC[6] in error.
9. Transactions
Transactions Three types of transactions may be done:
9.1. Memory Read
The TRANS pin is driven at a high level to select the
access to the memory. The external arbiter drives the
U2/U1 pin and dispatches the commands RD/WRx,
MEMx and ENx. All transaction managed by the master
user can be listened by the second user.
9
Rev. D (09 Dec. 97)
29C516E
1
0
RD/WR1
EN1
MEM1
RD/WR2
EN2
MEM2
1
1
0
0
x
x
x
0
1
x
0
1
1
x
x
1
1
1
1
1
0
1
x
0
x
x
x
0
0
1
x
x
1
x
x
x
x
x
1
1
UD1[0..15] = MD[0..15]
0
1
UD1[0..15] = {corrected MD[0..15]}
x
0
UD1[0..15] = {corrupted MD[0..15]}
Function
UD1[0..15] = MD[0..15]
x
x
x
x
x
x
x
x
x
x
1
0
0
x
x
UD2[0..15] = {expected UD1[0..15]} (User 2 listening)
1
1
UD2[0..15] = MD[0..15]
0
1
UD2[0..15] = {corrected MD[0..15]}
x
0
UD2[0..15] = {corrupted MD[0..15]}
x
1
x
NCERR
SYNCHK
1
CERR
CORRECT
U2/U1
TRANS
Table 8:
0
1
x
x
x
1
1
0
0
1
x
0
0
0
x
1
x
x
x
1
x
x
x
x
x
UD1[0..15] = {MC[0..7] Syndrome}
UD1[0..15] = H.Z
UD2[0..15] = MD[0..15]
UD2[0..15] = {MC[0..7] Syndrome}
UD2[0..15] = H.Z
UD1[0..15] = {expected UD2[0..15]} (User 1 listening)
x : don’t care
9.2. Memory Write
The TRANS pin is driven at a high level to select the
access to the memory. The external arbiter drives the
U2/U1 pin and dispatches the commands RD/WRx,
MEMx and ENx. All transaction managed by the master
user can be listened by the second user.
EN2
MEM2
EN1
RD/WR2
1
MEM1
1
0
RD/WR1
1
U2/U1
TRANS
Table 9:
0
0
0
x
x
x
1
x
x
1
x
x
x
0
x
x
1
0
0
UD2[0..15] = UD1[0..15] (User 2 listening)
x
x
x
0
0
0
MD[0..15] = UD2[0..15]
MC[0..7] = {check–bits generated from UD2[0..15]}
1
x
x
x
x
0
MD[0..15] = H.Z
x
1
MC[0..7] = H.Z
1
0
0
0
x
x
UD1[0..15] = UD2[0..15] (User 1 listening)
0
Function
MD[0..15] = UD1[0..15]
MC[0..7] = {check–bits generated from UD1[0..15]}
MD[0..15] = H.Z
MC[0..7] = H.Z
x : don’t care
CERR and NCERR are not valid
CORRECT and SYNCHK are not active
10
Rev. D (09 Dec. 97)
29C516E
9.3. User to User Transfer
The TRANS pin is driven at a low level to select this
mode. The external arbiter drives the U2/U1 pin and
dispatches the unidirectional commands RD/WRx,
MEMx and ENx.
MEM2
0
EN2
0
RD/WR2
0
MEM1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
0
1
UD2[0..15] = UD1[0..15]
1
x
UD2[0..15] = Η.Ζ
x
0
0
1
UD1[0..15] = UD2[0..15]
1
x
UD1[0..15] = H.Z
x
0
EN1
RD/WR1
U2/U1
TRANS
Table 10:
0
1
x
x
0
0
1
1
x
x
0
1
0
1
x
x
x
0
Function
UD1[0..15] = UD2[0..15]
UD1[0..15] = H.Z
UD2[0..15] = UD1[0..15]
UD2[0..15] = H.Z
x : don’t care
CERR and NCERR are not valid
CORRECT and SYNCHK are not active
11
Rev. D (09 Dec. 97)
29C516E
10. Signal Timing
10.1. Memory Write
Figure 4.Memory Write Timing Diagram
U2/U1
N22
t13
t20
t22
t22
t22
t20
t19
t23
t23
t23
t2
MD[0..15]
Memory Data Word
t14
t20
t22
t22
t22
t20
1.5
t21
t23
t23
t23
1.5
t3
2.5
Generated
Check–bits
MC[0..7]
UD2[0..15]
1.5TRANS
RD/WR2
EN2
MEM2
Propagation Delays
Output Enable /
Disable Times
t2 *
t3 *
13 ns
26 ns
t19 *
23 ns
t20 *
22 ns
t13 *
18 ns
t14 *
( * : Max Value )
30 ns
t21 *
22 ns
t22 *
( * : Max Value )
19 ns
Figure 5.Transfer Write Timing Diagram
U2/U1
t13
t20
t12
t22
t22
t22
t18
t21
t23
t23
t23
t19
t1
UD2[0..15]
UD1[0..15]
TRANS
RD/WR1
EN1
MEM1
Propagation Delays
t1 *
14 ns
Output Enable /
Disable Times
t18 *
23 ns
t12 *
20 ns
t19 *
23 ns
t13 *
( * : Max Value )
18 ns
t20 *
22 ns
t21 *
22 ns
t22 *
19 ns
t23 *
( * : Max Value )
19 ns
12
Rev. D (09 Dec. 97)
29C516E
10.2. Memory Read
Figure 6.Memory Read Timing Diagram
t8
t5
t16
CERR
Valid Error Flag
t9
t6
t17
NCERR
Valid Error Flag
N22
MD[0..15]
Memory Data Word
MC[0..7]
Memory Check–bits
CORRECT
t15
t4
t7
t10
t22
t22
t22
t18
2.5
2.5
UD1[0..15]
Corrected Data
TRANS
RD/WR2
EN2
MEM2
Propagation Delays
Output Enable /
Disable Times
t4 *
t5 *
t6 *
t7 *
t8 *
34 ns
33 ns
34 ns
32 ns
31 ns
t9 *
t10 *
t15 *
t16 *
t17 *
32 ns
19 ns
24 ns
24 ns
24 ns
t18 *
t22 *
23 ns
19 ns
( * : Max Value )
( * : Max Value )
( * : Max Value )
13
Rev. D (09 Dec. 97)
29C516E
10.3. Transfer Read
Figure 7.Transfer Read Timing Diagram
U2/U1
t13
t20
t12
t22
t22
t22
t18
t21
t23
t23
t23
t19
t1
UD2[0..15]
UD1[0..15]
TRANS
RD/WR2
EN2
MEM2
Propagation Delays
t1 *
14 ns
Output Enable /
Disable Times
t12 *
20 ns
t18 *
23 ns
t19 *
23 ns
t13 *
( * : Max Value )
18 ns
t20 *
22 ns
t21 *
22 ns
t22 *
19 ns
t23 *
( * : Max Value )
19 ns
11. Electrical Characteristics
11.1. Absolute Maximum Ratings
Table 11:
Parameter
Value
Supply voltage, Vcc
– 0.5 to 7V
Input voltage range
– 0.5 to Vcc + 0.5 V
Input current per power pin
+/– 50 mA
Input current per signal pin
+/– 10 mA
Continuous output current, one pin
+/– 30 mA
Soldering lead temperature 1.6 mm from case for max 10 s
+ 300 C
Storage temperature
– 65 C to + 150 C
Maximum package power dissipation
1.0 W
14
Rev. D (09 Dec. 97)
29C516E
11.2. Operating Conditions
Table 12:
Parameter
Min..
Typ
Max
Unit
Supply voltage, Vcc
4.5
5.0
5.5
Volt
Operating temperature range
– 55
125
C
11.3. Static Electrical Characteristics
Table 13:
Parameter
Condition
VIH
High level input voltage
VIL
Low level input voltage
Min.
Typ
Max
2,2
Unit
V
0,8
V
VOH1
High level output voltage
IOH = – 20 ,µΑ
VOL1
Low level output voltage
IOL = + 20 ,µΑ
VOH2
High level output voltage
IOH = – 12.8 mΑ
VOL2
Low level output voltage
IOL = + 12.8 mΑ
IIL
Low level input current
Vin = Gnd
– 10
–1
µΑ
IILP
Low level input current, (Pull–up Input)
Vin = Gnd
– 100
– 40
µΑ
IIH
High level input current
Vin = Vcc
+1
+ 10
µΑ
IIHP
High level input current, (Pull–down Input)
Vin = Vcc
+ 40
+ 100
µΑ
+ 10
µΑ
IOZ
Output leakage current
IOZHP
Output leakage current, (Pull–down Input)
Outputs disable,
(Vout=Vcc)
CI
Input pin capacitance
+40
+ 10
V
µΑ
– 40
I/O pin capacitance
Standby supply current
V
V
0,4
– 100
Outputs disable,
(Vout=Gnd)
ICCSB
3,7
– 10
Output leakage current, (Pull–up Input)
V
0,1
Outputs disable,
(Gnd<Vout<Vcc)
IOZLP
CIO
Vcc–0.1
+ 100
µΑ
8
pF
12
pF
+ 20
µΑ
15
Rev. D (09 Dec. 97)
29C516E
12. Ordering information
Temperature Range
S
Package
M
FR
Device
–
29C516E
–
Speed
Flow
31
SB
31ns
EDAC16 rad
tolerant
M: 5V
version
M: Military
S: Space
KR: MQFPF100
FR: MQFPL100
Blank: Atmel Military flow
/883: Mil STD 883 class B or S
SB: ESA/SCC 9000 level B
SC: ESA/SCC 9000 level C
P883: MIL–STD–883 + PIND Test
Hxxx: Customer specification
The information contained herein is subject to change without notice. No responsibility is assumed by Atmel for using this publication and/or circuits
described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
16
Rev. D (09 Dec. 97)