ATMEL 5962-02A0201QXC

TS80C51U2
TS83C51U2
TS87C51U2
Double UART 8-bit CMOS Microcontroller
1. Description
TS80C51U2 is high performance CMOS ROM, OTP
and EPROM versions of the 80C51 CMOS single chip
8-bit microcontroller.
The TS80C51U2 retains all features of the 80C51 with
extended ROM/EPROM capacity (16 Kbytes), 256 bytes
of internal RAM, a 7-source , 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C51U2 has a second UART,
enhanced functions on both UART, enhanced timer 2,
a hardware watchdog timer, a dual data pointer, a baud
rate generator and a X2 speed improvement mechanism.
The fully static design of the TS80C51U2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C51U2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
●
80C52 Compatible
●
Asynchronous port reset
• 8051 pin and instruction compatible
●
Interrupt Structure with
• Four 8-bit I/O ports
• 7 Interrupt sources
• Three 16-bit timer/counters
• 4 level priority interrupt system
• 256 bytes scratchpad RAM
●
●
Full duplex Enhanced UARTs
High-Speed Architecture
• Framing error detection
• 40 MHz @ 5V, 30MHz @ 3V
• Automatic address recognition
• X2 Speed Improvement capability (6 clocks/
machine cycle)
●
Low EMI (inhibit ALE)
●
Power Control modes
• Idle mode
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
●
Second UART
●
Baud Rate Generator
●
Dual Data Pointer
●
On-chip ROM/EPROM (16K-bytes)
●
Programmable Clock Out and Up/Down Timer/
Counter 2
●
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
• Power-down mode
• Power-off Flag
●
Once mode (On-chip Emulation)
●
Power supply: 4.5-5.5V, 2.7-5.5V
●
Temperature ranges: Commercial (0 to 70oC) and
Industrial (-40 to 85oC)
●
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44
(window), CDIL40 (window)
3. The second UART
In this document, UART_0 will make reference to the
first UART (present in all Atmel Wireless &
Microcontrollers C51 derivatives) and UART_1 will
make reference to the second UART, only present in
the TS80C51U2 part.
Rev. D - 15 January, 2001
The second UART (UART_1) can be seen as an alternate
function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or
P1.7 for TXD1) or can be connected to (pin6 or pin12)
and (pin28 or pin34) of 44-pin package (see Pin
1
TS80C51U2
TS83C51U2
TS87C51U2
configuration). UART_1 is fully compliant with the first one allowing an internal baud rate generator to be the
clock source. This common internal baud rate generator can be used independently by each UART or both as clock
source allowing to program various speeds.
The TS80C51U2 provides 7 sources of interrupt with four priority levels. UART_1 has a lower priority than Timer
2. The Serial Ports are full duplex meaning they can transmit and receive simultaneously. They are also receive
buffered, meaning they can start reception of a second byte before a previously received byte has been read from
the receive register. The Serial Port receive and transmit registers of UART_1 are both accessed at Special Function
Register SBUF_1. Writing to SBUF_1 loads the transmit register and reading SBUF_1 accesses a physical separate
receive register.
The UART_1 port control and status is the Special Function Register SCON_1. This register contains not only the
mode selection bit but also the 9th bit for transmit and receive (TB8_1 and RB8_1) and the serial port interrupt
bits (TI_1 and RI_1). The automatic address recognition feature is enabled when multiprocessor communication
is enabled. Implemented in hardware, automatic address recognition enhances the multiprocessor communication
feature by allowing the Serial Port to examine address of each incoming frame and provides filtering capability.
The UART_1 also comes with Frame error detection, similar to the UART_0.
2
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 1. Memory size
PDIL40
PLCC44
VQFP44 1.4
ROM (bytes)
EPROM (bytes)
TS80C51U2
TS83C51U2
TS87C51U2
0
16k
0
0
0
16k
(2) (2)
(1)
XTAL1
ALE/ PROG
C51
CORE
PSEN
ROM
/EPROM
16Kx8
RAM
256x8
UART_0
XTAL2
(1)
Timer2
(3)
TxD1
RxD1
T2
T2EX
Vss
Vcc
TxD
RxD
4. Block Diagram
(3)
UART_1
IB-bus
CPU
EA/VPP
Timer 0
Timer 1
(2)
Parallel I/O Ports
INT
Ctrl
WatchDog
P3
P2
P1
P0
INT1
(2) (2)
T1
(2) (2)
INT0
Port 0 Port 1 Port 2 Port 3
RESET
WR
(2)
T0
RD
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(3): See pin description
Rev. D - 15 January, 2001
3
TS80C51U2
TS83C51U2
TS87C51U2
5. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51U2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
• Serial I/O port registers for UART_0: SADDR_0, SADEN_0, SBUF_0, SCON_0
• Serial I/O port registers for UART_1: SADDR_1, SADEN_1, SBUF_1, SCON_1
• Baud Rate Generator registers: BRL, BDRCON, BDRCON_1
• Power and clock control registers: PCON
• HDW Watchdog Timer Reset: WDTRST, WDTPRG
• Interrupt system registers: IE, IP, IPH
• Others: AUXR, CKCON
Table 2. All SFRs with their address and their reset value
Bit
addressable
0/8
Non Bit addressable
1/9
2/A
3/B
4/C
5/D
6/E
7/F
F8h
F0h
FFh
B
0000 0000
F7h
E8h
E0h
EFh
ACC
0000 0000
E7h
D8h
DFh
D0h
PSW
0000 0000
C8h
T2CON
0000 0000
T2MOD
XXXX XX00
C0h
SCON_1
0000 0000
SBUF_1
XXXX XXXX
B8h
IP
X000 0000
SADEN_0
0000 0000
B0h
P3
1111 1111
A8h
IE
0X00 0000
A0h
P2
1111 1111
98h
SCON_0
0000 0000
90h
P1
1111 1111
88h
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
80h
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
0/8
1/9
2/A
3/B
D7h
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
CFh
C7h
SADEN_1
0000 0000
BFh
IPH
X000 0000
SADDR_0
0000 0000
SADDR_1
0000 0000
AFh
AUXR1
XXXX XXX0
SBUF_0
XXXX XXXX
BRL
0000 0000
B7h
WDTRST
XXXX XXXX
BDRCON
0XXX 0000
WDTPRG
XXXX X000
BDRCON_1
0X00 00XX
A7h
9Fh
97h
TH0
0000 0000
4/C
TH1
0000 0000
5/D
AUXR
00XX XXX0
6/E
CKCON
XXXX XXX0
8Fh
PCON
00X1 0000
87h
7/F
reserved
4
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
6. Pin Configuration
P0.2/AD2
P0.3/AD3
1 44 43 42 41 40
P0.1/AD1
2
P0.0/AD0
3
VCC
4
39
38
P0.4/AD4
P1.6/RxD_1
P0.6 / A6
P1.7/TxD_1
9
37
P0.6/AD6
32
P0.7 / A7
RST
10
36
P0.7/AD7
31
30
EA/VPP
ALE/PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P3.0/RxD_0
35
34
33
EA/VPP
P3.1/TxD_0
11
12
13
P3.2/INT0
P3.3/INT1
14
15
32
31
PSEN
P3.4/T0
P3.5/T1
16
30
P2.6/A14
17
29
P2.5/A13
24
23
22
21
P0.5/AD5
TxD_1
ALE/PROG
P2.7/A15
18 19 20 21 22 23 24 25 26 27 28
P2.2 / A10
P2.1 / A9
P2.0 / A8
P2.3/A11
P2.4/A12
17
18
19
20
P2.4 / A12
P2.3 / A11
P2.2/A10
25
P2.1/A9
16
NIC*
P2.0/A8
26
VSS
14
15
PLCC/CQPJ 44
XTAL1
29
28
27
RxD_1
XTAL2
CDIL40
5
P3.7/RD
PDIL/
6
7
8
P3.6/WR
11
12
13
VSS1/NIC*
10
P1.0/T2
9
P1.1/T2EX
P0.5 / A5
P1.2/RxD_1
P1.5
P1.3/TxD_1
P0.3 / A3
P0.4 / A4
P1.4
VSS
36
35
34
33
P0.3/AD3
XTAL1
6
7
8
5
P0.2/AD2
P3.7/RD
XTAL2
P0.1 / A1
P0.2 / A2
P0.1/AD1
P3.5/T1
P3.6/WR
37
P0.0/AD0
P3.4/T0
P0.0 / A0
VCC
P3.2/INT0
P3.3/INT1
39
38
VSS1/NIC*
P3.0/RxD_0
P3.1/TxD_0
2
3
4
P1.0/T2
P1.7/TxD_1
RST
VCC
P1.1/T2EX
P1.6/RxD_1
40
P1.3/TxD_1
P1.2/RxD_1
P1.1 / T2EX
P1.2/RxD_1
P1.3/TxD_1
P1.4
P1.5
1
P1.4
s
P1.0 / T2
44 43 42 41 40 39 38 37 36 35 34
P1.5
1
P1.6/RxD_1
P1.7/TxD_1
RST
P3.0/RxD_0
RxD_1
P3.1/TxD_0
2
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
3
4
5
VQFP44 1.4
6
7
8
33
32
P0.4/AD4
31
P0.6/AD6
30
P0.7/AD7
29
28
27
EA/VPP
9
26
25
10
24
23
11
P0.5/AD5
TxD_1
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.3/A11
P2.4/A12
P2.2/A10
P2.1/A9
NIC*
P2.0/A8
VSS
XTAL1
XTAL2
P3.7/RD
*NIC: No Internal Connection
P3.6/WR
12 13 14 15 16 17 18 19 20 21 22
See “Alternate function on Port 1” on page 32 for accurate RxD_1 and TxD_1 pin location, depending on AUXR
register configuration.
Rev. D - 15 January, 2001
5
TS80C51U2
TS83C51U2
TS87C51U2
Table 3. Pin Description for 40/44 pin packages
PIN NUMBER
TYPE
NAME AND FUNCTION
16
39
I
I
44
38
I
39-32
43-36
37-30
I/O
1-8
2-9
40-44
1-3
I/O
1
2
2
3
40
41
I/O
I
3
4
4
5
42
43
I
O
7
8
8
9
2
3
I
O
P2.0-P2.7
21-28
24-31
18-25
I/O
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
Ground: 0V reference
Optional Ground: Contact the Sales Office for ground connection.
Power Supply: This is the power supply voltage for normal, idle and powerdown operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups. Port 1 also receives the low-order
address byte during memory programming and verification.
Alternate functions for TSC8x54/58 Port 1 include:
T2 (P1.0): Timer/Counter 2 external count input/Clockout
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
Depending on values of (M1UA_1, M0UA_1) bits located into AUXR register,
the UART_1 pins are alternate functins of P1 with two possible locations.
First location:
P1.2: RxD_1, serial input port for UART_1
P1.3: TxD_1, serial output port for UART_1
Second location:
P1.6: RxD_1, serial input port for UART_1
P1.7: TxD_1, serial output port for UART_1
See “Alternate function on Port 1” on page 32
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming
and verification: P2.0 to P2.5
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.
RxD_0 (P3.0): Serial input port for UART_0
TxD_0 (P3.1): Serial output port for UART_0
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
MNEMONIC
DIL
LCC
VQFP 1.4
VSS
Vss1
20
22
1
VCC
40
P0.0-P0.7
P1.0-P1.7
6
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 3. Pin Description for 40/44 pin packages
PIN NUMBER
TYPE
NAME AND FUNCTION
4
I
33
27
O (I)
29
32
26
O
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC. If the hardware watchdog reaches its
time-out, the reset pin becomes an output during the time the internal reset is
activated.
Address Latch Enable/Program Pulse: Output pulse for latching the low byte
of the address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program
pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal
fetches.
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
EA/VPP
31
35
29
I
External Access Enable/Programming Supply Voltage: EA must be externally
held low to enable the device to fetch code from external program memory
locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is
held high, the device executes from internal program memory unless the program
counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must
be held low for ROMless devices. This pin also receives the 12.75V programming
supply voltage (VPP) during EPROM programming. If security level 1 is
programmed, EA will be internally latched on Reset.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
XTAL2
RxD_1
18
-
20
12
14
6
O
I
TxD_1
-
34
28
O
Crystal 2: Output from the inverting oscillator amplifier
Serial Input for UART_1. For 44-pin package only.
Serial Ouput for UART_1. This pin is pulled up by a 100K resistor when not
selected. For 44-pin package only.
MNEMONIC
DIL
LCC
VQFP 1.4
Reset
9
10
ALE/PROG
30
PSEN
Rev. D - 15 January, 2001
7
TS87C51U2
7. TS80C51U2 Enhanced Features
In comparison to the original 80C52, the TS80C51U2 implements some new features, which are:
•
•
•
•
•
•
•
•
•
•
The X2 option.
The second full duplex enhanced UART.
The Baud Rate generator.
The Dual Data Pointer.
The Watchdog.
The 4 level interrupt priority system.
The power-off flag.
The ONCE mode.
The ALE disabling.
Some enhanced features are also located in the UARTs and the timer 2.
7.1 X2 Feature
The TS80C51U2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:
●
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
●
Save power consumption while keeping same CPU power (oscillator power saving).
●
Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
●
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
7.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
2
XTAL1
FXTAL
XTAL1:2
0
1
state machine: 6 clock cycles.
CPU control
FOSC
X2
CKCON reg
Figure 1. Clock Generation Diagram
8
Rev. D - 06 december, 2000
TS87C51U2
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
Figure 2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UARTs, timers) will have their time reference divided by two. For example
a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with
4800 baud rate will have 9600 baud rate.
Rev. D - 06 december, 2000
9
TS87C51U2
Table 4. CKCON Register
CKCON - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
X2
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
X2
Description
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2).
Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL).
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com)
10
Rev. D - 06 december, 2000
TS80C51U2
TS83C51U2
TS87C51U2
7.2 Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3).
External Data Memory
7
0
DPS
AUXR1(A2H)
DPTR1
DPTR0
DPH(83H) DPL(82H)
Figure 3. Use of Dual Pointer
Rev. D - 15 January, 2001
11
TS80C51U2
TS83C51U2
TS87C51U2
Table 5. AUXR1: Auxiliary Register 1
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
DPS
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
DPS
Description
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XXX0
Not bit addressable
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.
12
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE
0003 05A2 INC AUXR1
0005 90A000 MOV DPTR,#DEST
0008
LOOP:
0008 05A2 INC AUXR1
000A E0
MOVX A,@DPTR
000B A3
INC DPTR
000C 05A2 INC AUXR1
000E F0
MOVX @DPTR,A
000F A3
INC DPTR
0010 70F6 JNZ LOOP
0012 05A2 INC AUXR1
; address of SOURCE
; switch data pointers
; address of DEST
; switch data pointers
; get a byte from SOURCE
; increment SOURCE address
; switch data pointers
; write the byte to DEST
; increment DEST address
; check for 0 terminator
; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.
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7.3 Timer 2
The timer 2 in the TS80C51U2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in
cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation
is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation)
as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the
combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8bit Microcontroller Hardware description.
Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of
Capture and Baud Rate Generator Modes.
In TS80C51U2 Timer 2 includes the following enhancements:
●
Auto-reload mode with up or down counter
●
Programmable clock-output
7.3.1 Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit
in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit
Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in
Figure 4. In this mode the T2EX pin controls the direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded
into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh
into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2
does not generate any interrupt. This bit can be used to provide 17-bit resolution.
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(:6 in X2 mode)
XTAL1
FXTAL
:12
FOSC
0
1
T2
C/T2
T2CONreg
TR2
T2CONreg
(DOWN COUNTING RELOAD VALUE)
FFh
FFh
(8-bit)
(8-bit)
T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up counting
TOGGLE
T2CONreg
EXF2
TL2
TH2
(8-bit)
(8-bit)
TF2
TIMER 2
INTERRUPT
T2CONreg
RCAP2L
(8-bit)
RCAP2H
(8-bit)
(UP COUNTING RELOAD VALUE)
Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1)
7.3.2 Programmable Clock-Output
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The
input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value.
At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer
2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system
oscillator frequency and the value in the RCAP2H and RCAP2L registers:
F
osc
Clock – OutFrequency = -------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L )
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
(FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
●
Set T2OE bit in T2MOD register.
●
Clear C/T2 bit in T2CON register.
●
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
●
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different
one depending on the application.
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●
To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration,
the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and
RCAP2L registers.
XTAL1
:2
(:1 in X2 mode)
TR2
T2CON reg
TL2
(8-bit)
TH2
(8-bit)
OVERFLOW
RCAP2L RCAP2H
(8-bit) (8-bit)
Toggle
T2
Q
D
T2OE
T2MOD reg
T2EX
EXF2
EXEN2
T2CON reg
TIMER 2
INTERRUPT
T2CON reg
Figure 5. Clock-Out Mode C/T2 = 0
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Table 6. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
Mnemonic
7
TF2
6
EXF2
5
RCLK_0
Receive Clock bit for UART_0
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK_0
Transmit Clock bit for UART_0
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.
2
TR2
1
C/T2#
0
CP/RL2#
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: FOSC).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
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Table 7. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
T2OE
DCEN
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
T2OE
Timer 2 Output Enable bit
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0
DCEN
Down Counter Enable bit
Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.
Description
Reset Value = XXXX XX00b
Not bit addressable
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7.4 TS80C51U2 Serial I/O Ports enhancements
The serial I/O ports in the TS80C51U2 are compatible with the serial I/O port in the 80C52.
They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O ports include the following enhancements:
●
Framing error detection
●
Automatic address recognition
As these improvements apply to both UART, most of the time in the following lines, there won’t be any reference
to UART_0 or UART_1, but only to UART, generally speaking. Idem for the bits in registers.
7.4.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
SCON_0 for UART_0 (98h)
(SCON_1 for UART_1 (C0h))
Set FE bit if stop bit is 0 (framing error) (SMOD0_0 = 1 for UART_0)
SM0 to UART mode control (SMOD0_0 = 0 for UART_0)
SMOD1_0 SMOD0_0
-
POF
GF1
GF0
PD
To UART framing error control
IDL
PCON for UART_0 (87h)
(SMOD bits for UART_1 are
located in BDRCON_1)
Figure 6. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.
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Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 7. and Figure 8.).
RXD
D0
D1
D2
Start
bit
D3
D4
D5
D6
D7
Data byte
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
Figure 7. UART Timings in Mode 1
RXD
D0
Start
bit
D1
D2
D3
D4
D5
D6
Data byte
D7
D8
Ninth Stop
bit bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Figure 8. UART Timings in Modes 2 and 3
7.4.2 Automatic Address Recognition
The automatic address recognition feature is enabled for each UART when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
7.4.3 Given Address
Each UART has an individual address that is specified in SADDR_0 or SADDR_1 register; the SADEN_0 or
SADEN_1 register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example
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illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR
SADEN
Given
0101 0110b
1111 1100b
0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:
SADDR
SADEN
Given
1111 0001b
1111 1010b
1111 0X0Xb
Slave B:
SADDR
SADEN
Given
1111 0011b
1111 1001b
1111 0XX1b
Slave C:
SADDR
SADEN
Given
1111 0010b
1111 1101b
1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A
only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but
not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2
clear (e.g. 1111 0001b).
7.4.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as
don’t-care bits, e.g.:
SADDR
SADEN
Broadcast =SADDR OR SADEN
0101 0110b
1111 1100b
1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a
broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:
SADDR
1111 0001b
SADEN
1111 1010b
Broadcast 1111 1X11b,
Slave B:
SADDR
1111 0011b
SADEN
1111 1001b
Broadcast 1111 1X11B,
Slave C:
SADDR=
1111 0010b
SADEN
1111 1101b
Broadcast 1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the
master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send
and address FBh.
7.4.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX
XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
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7.4.6 Baud Rate Selection for UART0_0 for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON
registers.
TIMER1_BRG
TIMER2_BRG
0
1
TIMER_BRG
0
1
TIMER_BRG
0
1
/ 16
0
1
/ 16
Rx_0 Clock
RCLK_0
INT_BRG_0
RBCK_0
TIMER1_BRG
TIMER2_BRG
Tx_0 Clock
TCLK_0
INT_BRG_0
TBCK_0
Figure 9. Baud Rate selection
7.4.7 Baud Rate Selection for UART1_1 for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the BDRCON_1 register.
TIMER1_BRG
TIMER2_BRG
0
1
TIMER_BRG
0
1
TIMER_BRG
0
1
/ 16
0
1
/ 16
Rx_1 Clock
RCLK_1
INT_BRG_1
RBCK_1
TIMER1_BRG
TIMER2_BRG
Tx_1 Clock
TCLK_1
INT_BRG_1
TBCK_1
Figure 10. Baud Rate selection
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7.4.8 Baud Rate selection table for UART_0
TCLK_0
RCLK_0
TBCK_0
RBCK_0
Clock Source for
UART_0 Tx
Clock Source
UART_0 Rx
0
0
0
0
Timer 1
Timer 1
1
0
0
0
Timer 2
Timer 1
0
1
0
0
Timer 1
Timer 2
1
1
0
0
Timer 2
Timer 2
X
0
1
0
INT_BRG_0
Timer 1
X
1
1
0
INT_BRG_0
Timer 2
0
X
0
1
Timer 1
INT_BRG_0
1
X
0
1
Timer 2
INT_BRG_0
X
X
1
1
INT_BRG_0
INT_BRG_0
7.4.9 Baud Rate selection table for UART_1
TCLK_1
RCLK_1
TBCK_1
RBCK_1
Clock Source for
UART_1 Tx
Clock Source
UART_1 Rx
0
0
0
0
Timer 1
Timer 1
1
0
0
0
Timer 2
Timer 1
0
1
0
0
Timer 1
Timer 2
1
1
0
0
Timer 2
Timer 2
X
0
1
0
INT_BRG_1
Timer 1
X
1
1
0
INT_BRG_1
Timer 2
0
X
0
1
Timer 1
INT_BRG_1
1
X
0
1
Timer 2
INT_BRG_1
X
X
1
1
INT_BRG_1
INT_BRG_1
7.4.10 Internal Baud Rate Generator (BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the
BRL reload value, the X2 bit in CKON register, the value of SPD bit (Speed Mode) in BDRCON register and the value
of the SMOD1_0 bit in PCON register (for UART_0) or SMOD1_1 in BDRCON_1 register (for UART_1). The Internal
Baud Rate Generator is common to both UARTs:
SMOD1_0
/2
XTAL1
/2
FXTAL
X2
SPD
BRR
0
1
/6
0
1
auto reload counter
BRG
overflow
BRL
0
1
INT_BRG_0
0
1
INT_BRG_1
/2
SMOD1_1
Figure 11. Internal Baud Rate
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●
for UART_1
Baud_Rate =
(BRL) = 256 ●
2SMOD1_1 x 2X2 x FXTAL
2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)]
2SMOD1_1 x 2X2 x FXTAL
2 x 2 x 6(1-SPD) x 16 x Baud_Rate
for UART_0
Baud_Rate =
(BRL) = 256 -
2SMOD1_0 x 2X2 x FXTAL
2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)]
2SMOD1_0 x 2X2 x FXTAL
2 x 2 x 6(1-SPD) x 16 x Baud_Rate
Example of computed value when X2=1, SMOD1=1, SPD=1
FXTAL = 16.384 MHz
Baud Rates
FXTAL = 24MHz
BRL
Error (%)
BRL
Error (%)
115200
247
1.23
243
0.16
57600
238
1.23
230
0.16
38400
229
1.23
217
0.16
28800
220
1.23
204
0.16
19200
203
0.63
178
0.16
9600
149
0.31
100
0.16
4800
43
1.23
-
-
Example of computed value when X2=0, SMOD1=0, SPD=0
FOSC = 16.384 MHz
Baud Rates
FOSC = 24MHz
BRL
Error (%)
BRL
Error (%)
4800
247
1.23
243
0.16
2400
238
1.23
230
0.16
1200
220
1.23
202
3.55
600
185
0.16
152
0.16
The baud rate generator can be used for mode 1 or 3 (refer to figures 9 and 10), but also for mode 0 for both
UARTs, thanks to the bit SRC located in BDRCON register (Table 12)
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7.5 UARTs registers
SADEN_0 - Slave Address Mask Register for UART_0 (B9h)
7
6
5
4
3
2
1
0
3
2
1
0
3
2
1
0
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
Reset Value = 0000 0000b
SADEN_1 - Slave Address Mask Register for UART_1 (BAh)
7
6
5
4
Reset Value = 0000 0000b
SADDR_0 - Slave Address Register for UART_0 (A9h)
7
6
5
4
Reset Value = 0000 0000b
SADDR_1 - Slave Address Register for UART_1 (AAh)
7
6
5
Reset Value = 0000 0000b
SBUF_0 - Serial Buffer Register for UART_0 (99h)
7
6
5
Reset Value = XXXX XXXXb
SBUF_1 - Serial Buffer Register for UART_1 (C1h)
7
6
5
Reset Value = XXXX XXXXb
BRL - Baud Rate Reload Register for the internal baud rate generator, UART_0 and UART_1 (9Ah)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
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Table 8. SCON Register
SCON_0 - Serial Control Register for UART_0 (98h)
7
6
5
4
3
2
1
0
FE_0/
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
Bit
Number
7
Bit
Mnemonic
FE_0
SM0_0
Description
Framing Error bit (SMOD0_0=1) for UART_0
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0_0 must be set to enable access to the FE bit
Serial port Mode bit 0 (SMOD0_0=0) for UART_0
Refer to SM1 for serial port mode selection.
SMOD0_0 must be cleared to enable access to the SM0_0 bit
Serial port Mode bit 1 for UART_0
SM0_0 SM1_0 Mode
Description
0
0
1
1
0
1
0
1
0
1
2
3
Shift Register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
FXTAL/12 (FXTAL/6 X2 mode)
Variable
FXTAL/64 or FXTAL/32 (FXTAL/32 or FXTAL/16 X2 mode)
Variable
6
SM1_0
5
SM2_0
4
REN_0
Reception Enable bit for UART_0
Clear to disable serial reception.
Set to enable serial reception.
3
TB8_0
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_0.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2
RB8_0
Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART_0
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART_0
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
TI_0
Transmit Interrupt flag for UART_0
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
0
RI_0
Receive Interrupt flag for UART_0
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.
Reset Value = 0000 0000b
Bit addressable
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Table 9. SCON Register
SCON_1 - Serial Control Register for UART_1 (C0h)
7
6
5
4
3
2
1
0
FE_1/
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
Bit
Number
7
Bit
Mnemonic
Description
FE_1
Framing Error bit (SMOD0_1=1) for UART_1
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0_1 must be set to enable access to the FE bit
SM0_1
Serial port Mode bit 0 (SMOD0_1=0) for UART_1
Refer to SM1 for serial port mode selection.
SMOD0_1 must be cleared to enable access to the SM0_1 bit
Serial port Mode bit 1 for UART_1
SM0_1 SM1_1 Mode
Description
0
0
1
1
0
1
0
1
0
1
2
3
Shift Register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
FXTAL/12 (FXTAL/6 X2 mode)
Variable
FXTAL/64 or FXTAL/32 (FXTAL/32 or FXTAL/16 X2 mode)
Variable
6
SM1_1
5
SM2_1
4
REN_1
Reception Enable bit for UART_1
Clear to disable serial reception.
Set to enable serial reception.
3
TB8_1
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_1.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2
RB8_1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART_1
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART_1
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
TI_1
Transmit Interrupt flag for UART_1
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
0
RI_1
Receive Interrupt flag for UART_1
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.
Reset Value = 0000 0000b
Bit addressable
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Table 10. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
Mnemonic
7
TF2
6
EXF2
5
RCLK_0
Receive Clock bit for UART_0
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK_0
Transmit Clock bit for UART_0
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.
2
TR2
1
C/T2#
0
CP/RL2#
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: FOSC).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
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Table 11. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1_0
SMOD0_0
-
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
7
SMOD1_0
Serial port Mode bit 1 for UART_0
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0_0
Serial port Mode bit 0 for UART_0
Clear to select SM0_0 bit in SCON_0 register.
Set to to select FE_0 bit in SCON_0 register.
5
-
4
POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.
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Table 12. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
6
5
4
3
2
1
0
-
-
-
BRR
TBCK_0
RBCK_0
SPD
SRC
Bit
Number
Bit Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
BRR
3
TBCK_0
Transmission Baud rate Generator Selection bit for UART_0
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2
RBCK_0
Reception Baud Rate Generator Selection bit for UART_0
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1
SPD
Baud Rate Speed Control bit for UART_0
Clear to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0
SRC
Baud Rate Source select bit in Mode 0 for UART_0 and UART_1
Clear to select FOSC/12 as the Baud Rate Generator (FOSC/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0..
Description
Baud Rate Run Control bit
Clear to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
Reset Value = XXX0 0000b
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Table 13. BDRCON_1 Register
BDRCON_1 - Baud Rate Control Register for UART_1 (9Ch)
7
6
5
4
3
2
1
0
SMOD1_1
SMOD0_1
RCLK_1
TCLK_1
TBCK_1
RBCK_1
-
-
Bit
Number
Bit Mnemonic
7
SMOD1_1
Serial port Mode bit 1 for UART_1
Set to select double baud rate, in mode 1, 2 and 3.
6
SMOD0_1
SCON Select bit for UART_1
Clear to select SM0_1 bit in SCON_1 register..
Set to to select FE_1 bit in SCON_1 register.
5
RCLK_1
Receive Clock bit for UART_1
Clear to select Timer 1 as Receive Baud Rate Generator for the UART_1
Set to Select Timer 2 as the Receive Baud Rate Generator for the UART_1
4
TCLK_1
Transmit Clock bit for UART_1
Clear to select Timer 1 as Transmit Baud Rate Generator for the UART_1
Set to Select Timer 2 as the Transmit Baud Rate Generator for the UART_1.
3
TBCK_1
Transmission Baud rate Generator Selection bit for UART_1
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator, for Tx.
Set to select internal Baud Rate Generator for Tx.
2
RBCK_1
Reception Baud Rate Generator Selection bit for UART_1
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator for Rx.
Set to select internal Baud Rate Generator for Rx.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Description
Reset Value = 0000 00XXb
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7.6 Alternate function on Port 1
The M1UA_1 and M0UA_1 bits located into AUXR register at bit location 7 and 6 permit to validate alternate functions
located on Port 1. Following the combination of these two bits, the TxD_1 output and RxD_1 input of UART_1 take
place on Port 1 pins (two different locations are possible) and the other locations of TxD_1 and RxD_1 available only
for 44-pin package are no more valid.
Table 14. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
M1UA_1
M0UA_1
-
-
-
-
-
AO
Bit
Number
Bit Mnemonic
7
M1UA_1
Multiplex I/Os of UART_1 bit 1
This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins.
6
M0UA_1
Multiplex I/Os of UART_1 bit 0
This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins.
M1UA_1M0UA_1Result
0 0
UART_1 pins are disabled.
0 1
UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only.
1 0
UART_1 pins are alternate functions of P1 located at P1.2 and P1.3.
1 1
UART_1 pins are alternate functions of P1 located at P1.6 and P1.7.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
AO
Description
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
Reset Value = 00XX XXX0b
Not bit addressable
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7.7 Interrupt System
The TS80C51U2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts
(timers 0, 1 and 2) and the two serial port interrupts. These interrupts are shown in Figure 12.
High priority
interrupt
IPH, IP
3
IE0
INT0
0
3
TF0
0
3
IE1
INT1
0
3
TF1
Interrupt
polling
sequence, decreasing
from high to low priority
0
RI_0
TI_0
3
TF2
3
EXF2
0
0
RI_1
TI_1
Individual Enable
Global Disable
Low priority
interrupt
Figure 12. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 16.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 17.) and in the Interrupt Priority High register (See Table 18.).
shows the bit values and priority levels associated with each combination.
The second UART interrupt vector is located at address 0033H. All other vector addresses are the same as standard
C52 devices.
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Table 15. Priority Level Bit Values
IPH.x
IP.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 16. IE Register
IE - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
ES_1
ET2
ES_0
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
7
EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
6
ES_1
Serial port Enable bit for UART_1
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
5
ET2
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4
ES_0
Serial port Enable bit for UART_0
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
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Table 17. IP Register
IP - Interrupt Priority Register (B8h)
7
6
5
4
3
2
1
0
-
PS_1
PT2
PS_0
PT1
PX1
PT0
PX0
Bit
Number
Bit
Mnemonic
7
-
6
PS_1
Serial port Priority bit for UART_1
Refer to PSH for priority level.
5
PT2
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4
PS_0
Serial port Priority bit for UART_0
Refer to PSH for priority level.
3
PT1
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2
PX1
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1
PT0
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0
PX0
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = X000 0000b
Bit addressable
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Table 18. IPH Register
IPH - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
PSH_1
PT2H
PSH_0
PT1H
PX1H
PT0H
PX0H
Bit
Number
Bit
Mnemonic
7
-
6
5
4
3
2
1
0
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PSH_1
Serial port Priority High bit for UART_1
PSH_1
PS_1
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT2H
Timer 2 overflow interrupt Priority High bit
PT2H
PT2
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PSH_0
Serial port Priority High bit for UART_0
PSH_0
PS_0
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT1H
Timer 1 overflow interrupt Priority High bit
PT1H
PT1
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX1H
External interrupt 1 Priority High bit
PX1H
PX1
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT0H
Timer 0 overflow interrupt Priority High bit
PT0H
PT0
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX0H
External interrupt 0 Priority High bit
PX0H
PX0
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = X000 0000b
Not bit addressable
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7.8 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or
during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running,
the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
7.9 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to 7.4.6, PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last
instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before VCC
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 13.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C51U2 into power-down mode.
INT0
INT1
XTAL1
Active phase
Power-down phase
Oscillator restart phase
Active phase
Figure 13. Power-Down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt,
PD and IDL bits are cleared and idle mode is not entered.
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Table 19. The state of ports during idle and power-down modes
Mode
Program
Memory
ALE
PSEN
PORT0
Idle
Idle
Power Down
Power Down
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Port Data*
Floating
Port Data*
Floating
PORT1
PORT2
PORT3
Port
Port
Port
Port
Port Data
Address
Port Data
Port Data
Port
Port
Port
Port
Data
Data
Data
Data
Data
Data
Data
Data
* Port 0 can force a "zero" level. A "one" Level will leave port floating.
38
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7.10 Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The
WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default
disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,
SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
7.10.1 Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.
The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled,
it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at
least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST
is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make
the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within
the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from
16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 21. (SFR0A7h).
Table 20. WDTRST Register
WDTRST Address (0A6h)
Reset value
7
6
5
4
3
2
1
X
X
X
X
X
X
X
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
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Table 21. WDTPRG Register
WDTPRG Address (0A7h)
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Bit
Number
Bit
Mnemonic
7
T4
6
T3
5
T2
4
T1
3
T0
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
Description
Reserved
Do not try to set or clear this bit.
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Selected Time-out
(214 - 1) machine cycles, 16.3 ms @ 12 MHz
(215 - 1) machine cycles, 32.7 ms @ 12 MHz
(216 - 1) machine cycles, 65.5 ms @ 12 MHz
(217 - 1) machine cycles, 131 ms @ 12 MHz
(218 - 1) machine cycles, 262 ms @ 12 MHz
(219 - 1) machine cycles, 542 ms @ 12 MHz
(220 - 1) machine cycles, 1.05 s @ 12 MHz
(221 - 1) machine cycles, 2.09 s @ 12 MHz
Reset value XXXX X000
7.10.2 WDT during Power Down and Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51U2
is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51U2 while in
Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter
Idle mode.
40
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
7.11 ONCETM Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C51U2 without removing the circuit from
the board. The ONCE mode is invoked by driving certain pins of the TS80C51U2; the following sequence must
be exercised:
●
Pull ALE low while the device is in reset (RST high) and PSEN is high.
●
Hold ALE low as RST is deactivated.
While the TS80C51U2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26.
shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 22. External Pin Status during ONCE Mode
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
XTAL1/2
Weak pull-up
Weak pull-up
Float
Weak pull-up
Weak pull-up
Weak pull-up
Active
Rev. D - 15 January, 2001
41
TS80C51U2
TS83C51U2
TS87C51U2
7.12 Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to
the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 23.). POF is set by hardware when VCC rises
from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type
of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will
return indeterminate value.
Table 23. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1_0
SMOD0_0
-
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
7
SMOD1_0
Serial port Mode bit 1 for UART_0
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0_0
Serial port Mode bit 0 for UART_0
Clear to select SM0_0 bit in SCON_0 register.
Set to to select FE_0 bit in SCON_0 register.
5
-
4
POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X1 0000b
Not bit addressable
42
Rev. D - 15 January, 2001
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7.13 Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but
remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is
weakly pulled high.
Table 24. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
M1UA_1
M0UA_1
-
-
-
-
-
AO
Bit
Number
Bit Mnemonic
7
M1UA_1
Multiplex I/Os of UART_1 bit 1
This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins.
6
M0UA_1
Multiplex I/Os of UART_1 bit 0
This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins.
M1UA_1M0UA_1Result
0 0
UART_1 pins are disabled.
0 1
UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only.
1 0
UART_1 pins are alternate functions of P1 located at P1.2 and P1.3.
1 1
UART_1 pins are alternate functions of P1 located at P1.6 and P1.7.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
AO
Description
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
Reset Value = 00XX XXX0b
Not bit addressable
Rev. D - 15 January, 2001
43
TS80C51U2
TS83C51U2
TS87C51U2
8. TS80C51U2 ROM
8.1 ROM Structure
The TS83C51U2 ROM memory is divided in three different arrays:
●
the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes.
●
the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.
●
the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.
8.2 ROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
8.2.1 Encryption Array
Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a
byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.
8.2.2 Program Lock Bits
The lock bits when programmed according to Table 25. will provide different level of protection for the on-chip
code and data.
Table 25. Program Lock bits
Program Lock Bits
Protection description
Security level
LB1
LB2
LB3
1
U
U
U
No program lock features enabled. Code verify will still be encrypted by the encryption
array if programmed. MOVC instruction executed from external program memory returns
non encrypted data.
2
P
U
U
MOVC instruction executed from external program memory are disabled from fetching
code bytes from internal memory, EA is sampled and latched on reset.
U: unprogrammed
P: programmed
8.2.3 Signature bytes
The TS83C51U2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described
in section 10.
8.2.4 Verify Algorithm
Refer to 9.3.4
44
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
9. TS87C51U2 EPROM
9.1 EPROM Structure
The TS87C51U2 EPROM is divided in two different arrays:
●
the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes.
●
the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.
In addition a third non programmable array is implemented:
●
the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.
9.2 EPROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
9.2.1 Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time
a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.
9.2.2 Program Lock Bits
The three lock bits, when programmed according to Table 26., will provide different level of protection for the
on-chip code and data.
Table 26. Program Lock bits
Program Lock Bits
Protection description
Security
level
LB1
LB2
LB3
1
U
U
U
No program lock features enabled. Code verify will still be encrypted by the encryption
array if programmed. MOVC instruction executed from external program memory
returns non encrypted data.
2
P
U
U
MOVC instruction executed from external program memory are disabled from fetching
code bytes from internal memory, EA is sampled and latched on reset, and further
programming of the EPROM is disabled.
3
U
P
U
Same as 2, also verify is disabled.
4
U
U
P
Same as 3, also external execution is disabled.
U: unprogrammed,
P: programmed
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification.
Rev. D - 15 January, 2001
45
TS80C51U2
TS83C51U2
TS87C51U2
9.2.3 Signature bytes
The TS87C51U2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described
in section 10.
9.3 EPROM Programming
9.3.1 Set-up modes
In order to program and verify the EPROM or to read the signature bytes, the TS87C51U2 is placed in specific
set-up modes (See Figure 14.).
Control and program signals must be held at the levels indicated in Table 27.
9.3.2 Definition of terms
Address Lines:P1.0-P1.7, P2.0-P2.5 respectively for A0-A13.
Data Lines:P0.0-P0.7 for D0-D7
Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.
Program Signals:ALE/PROG, EA/VPP.
Table 27. EPROM Set-Up Modes
Mode
EA/
VPP
P2.6
P2.7
P3.3
P3.6
P3.7
12.75V
0
1
1
1
1
1
0
0
1
1
12.75V
0
1
0
1
1
0
0
0
0
0
12.75V
1
1
1
1
1
1
0
12.75V
1
1
1
0
0
1
0
12.75V
1
0
1
1
0
RST
PSEN
Program Code data
1
0
Verify Code data
1
0
Program Encryption Array
Address 0-3Fh
1
0
Read Signature Bytes
1
0
Program Lock bit 1
1
Program Lock bit 2
Program Lock bit 3
46
ALE/
PROG
1
1
1
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
+5V
EA/VPP
PROGRAM
SIGNALS*
VCC
ALE/PROG
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
CONTROL
SIGNALS*
4 to 6 MHz
P0.0-P0.7
D0-D7
P1.0-P1.7
A0-A7
P2.0-P2.5
A8-A13
XTAL1
VSS
GND
* See Table 31. for proper value on these inputs
Figure 14. Set-Up Modes Configuration
9.3.3 Programming Algorithm
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses
applied during byte programming from 25 to 1.
To program the TS87C51U2 the following sequence must be exercised:
●
Step 1: Activate the combination of control signals.
●
Step 2: Input the valid address on the address lines.
●
Step 3: Input the appropriate data on the data lines.
●
Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
●
Step 5: Pulse ALE/PROG once.
●
Step 6: Lower EA/VPP from VPP to VCC
Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is
reached (See Figure 15.).
9.3.4 Verify algorithm
Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify
of the programmed array will ensure reliable programming of the TS87C51U2.
P 2.7 is used to enable data output.
To verify the TS87C51U2 code the following sequence must be exercised:
●
Step 1: Activate the combination of program and control signals.
●
Step 2: Input the valid address on the address lines.
●
Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 15.)
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the
code array is well encrypted.
Rev. D - 15 January, 2001
47
TS80C51U2
TS83C51U2
TS87C51U2
Programming Cycle
Read/Verify Cycle
A0-A12
Data In
D0-D7
Data Out
100µs
ALE/PROG
EA/VPP
12.75V
5V
0V
Control signals
Figure 15. Programming and Verification Signal’s Waveform
9.4 EPROM Erasure (Windowed Packages Only)
Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full
functionality.
Erasure leaves all the EPROM cells in a 1’s state (FF).
9.4.1 Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15
W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2 rating for 30 minutes, at a distance
of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers.
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately
4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources
over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause
inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque
label be placed over the window.
48
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
10. Signature Bytes
The TS83/87C51U2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the
procedure for EPROM verify but activate the control lines provided in Table 27. for Read Signature Bytes. Table
28. shows the content of the signature byte for the TS83/87C51U2.
Table 28. Signature Bytes Content
Location
Contents
30h
58h
Manufacturer Code: Atmel Wireless & Microcontrollers
31h
57h
Family Code: C51 X2
60h
2Bh
Product name: TS83C51U2
60h
ABh
Product name: TS87C51U2
61h
FFh
Product revision number
Rev. D - 15 January, 2001
Comment
49
TS80C51U2
TS83C51U2
TS87C51U2
11. Electrical Characteristics
11.1 Absolute Maximum Ratings (1)
Ambiant Temperature Under Bias:
C = commercial
I = industrial
Storage Temperature
Voltage on VCC to VSS
Voltage on VPP to VSS
Voltage on Any Pin to VSS
Power Dissipation
0°C to 70°C
-40°C to 85°C
-65°C to + 150°C
-0.5 V to + 7 V
-0.5 V to + 13 V
-0.5 V to VCC + 0.5 V
1 W(2)
NOTES
1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
11.2 Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset,
which made sense for the designs were the CPU was running under reset. In Atmel Wireless & Microcontrollers
new devices, the CPU is no more active during reset, so the power consumption is very low but is not really
representative of what will happen in the customer system. That’s why, while keeping measurements under Reset,
Atmel Wireless & Microcontrollers presents a new way to measure the operating Icc:
Using an internal test ROM, the following code is executed:
Label:
SJMP Label (80 FE)
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1
is driven by the clock.
This is much more representative of the real operating Icc.
50
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
11.3 DC Parameters for Standard Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
Table 29. DC Parameters in Standard Voltage
Symbol
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
Output Low Voltage, ports 1, 2, 3 (6)
VOL1
VOL2
VOH
Min
Typ
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.3
0.45
1.0
V
V
V
IOL = 100 µA(4)
0.3
0.45
1.0
V
V
V
IOL = 200 µA(4)
0.3
0.45
1.0
V
V
V
IOL = 100 µA(4)
Output Low Voltage, port 0 (6)
Output Low Voltage, ALE, PSEN
Output High Voltage, ports 1, 2, 3
VCC - 0.3
V
V
V
VCC - 0.7
VCC - 1.5
VOH1
Output High Voltage, port 0
VCC - 0.3
V
V
V
VCC - 1.5
Output High Voltage,ALE, PSEN
VCC - 0.3
V
V
V
VCC - 1.5
RST Pulldown Resistor
50
IOL = 3.5 mA(4)
IOL = 3.2 mA(4)
IOL = 7.0 mA(4)
IOL = 1.6 mA(4)
IOL = 3.5 mA(4)
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
VCC = 5 V ± 10%
VCC - 0.7
RRST
IOL = 1.6 mA(4)
VCC = 5 V ± 10%
VCC - 0.7
VOH2
Test Conditions
IOH = -100 µA
IOH = -1.6 mA
IOH = -3.5 mA
VCC = 5 V ± 10%
90 (5)
200
kΩ
IIL
Logical 0 Input Current ports 1, 2 and 3
-50
µA
Vin = 0.45 V
ILI
Input Leakage Current
±10
µA
0.45 V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
-650
µA
Vin = 2.0 V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
TA = 25°C
IPD
Power Down Current
50
µA
2.0 V < VCC < 5.5 V(3)
ICC
Power Supply Current Maximum values, X1
mode: (7)
under
RESET
Rev. D - 15 January, 2001
20 (5)
1 + 0.4 Freq
(MHz)
@12MHz 5.8
@16MHz 7.4
VCC = 5.5 V(1)
mA
51
TS80C51U2
TS83C51U2
TS87C51U2
Symbol
Parameter
ICC
Power Supply Current Maximum values, X1
mode: (7)
operating
ICC
idle
Min
Typ
Max
Unit
3 + 0.6 Freq
(MHz)
mA
VCC = 5.5 V(8)
mA
VCC = 5.5 V(2)
@12MHz 10.2
@16MHz 12.6
Power Supply Current Maximum values, X1
mode: (7)
0.25+0.3Freq
(MHz)
@12MHz 3.9
@16MHz 5.1
Test Conditions
11.4 DC Parameters for Low Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ; F = 0 to 30 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ; F = 0 to 30 MHz.
Table 30. DC Parameters for Low Voltage
Symbol
Parameter
Min
Typ
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
Output Low Voltage, ports 1, 2, 3 (6)
0.45
V
IOL = 0.8 mA(4)
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
0.45
V
IOL = 1.6 mA(4)
VOH
Output High Voltage, ports 1, 2, 3
0.9 VCC
V
IOH = -10 µA
VOH1
Output High Voltage, port 0, ALE, PSEN
0.9 VCC
V
IOH = -40 µA
IIL
Logical 0 Input Current ports 1, 2 and 3
-50
µA
Vin = 0.45 V
ILI
Input Leakage Current
±10
µA
0.45 V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
-650
µA
Vin = 2.0 V
200
kΩ
10
pF
Fc = 1 MHz
TA = 25°C
µA
VCC = 2.0 V to 5.5 V(3)
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
IPD
Power Down Current
50
90 (5)
20 (5)
10
ICC
under
RESET
ICC
operating
52
Test Conditions
Power Supply Current Maximum values, X1
mode: (7)
Power Supply Current Maximum values, X1
mode: (7)
(5)
50
30
1 + 0.2 Freq
(MHz)
@12MHz 3.4
@16MHz 4.2
1 + 0.3 Freq
(MHz)
@12MHz 4.6
@16MHz 5.8
VCC = 2.0 V to 3.3 V(3)
VCC = 3.3 V(1)
mA
VCC = 3.3 V(8)
mA
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Symbol
ICC
idle
Parameter
Min
Typ
Power Supply Current Maximum values, X1
mode: (7)
Max
0.15 Freq
(MHz) + 0.2
@12MHz 2
@16MHz 2.6
Unit
mA
Test Conditions
VCC = 3.3 V(2)
NOTES
1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 20.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2
N.C; Port 0 = VCC; EA = RST = VSS (see Figure 18.).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 19.).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 20.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly
higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case.
VCC
ICC
VCC
P0
VCC
RST
(NC)
CLOCK
SIGNAL
VCC
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 16. ICC Test Condition, under reset
Rev. D - 15 January, 2001
53
TS80C51U2
TS83C51U2
TS87C51U2
VCC
ICC
VCC
VCC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
EA
XTAL2
XTAL1
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
VSS
Figure 17. Operating ICC Test Condition
VCC
ICC
VCC
VCC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
EA
XTAL2
XTAL1
VSS
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
Figure 18. ICC Test Condition, Idle Mode
VCC
ICC
VCC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
(NC)
VCC
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 19. ICC Test Condition, Power-Down Mode
VCC-0.5V
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
0.7VCC
0.2VCC-0.1
Figure 20. Clock Signal Waveform for ICC Tests in Active and Idle Modes
54
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
11.5 AC Parameters
11.5.1 Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA
TA
TA
TA
=
=
=
=
0 to +70°C (commercial temperature range); VSS =
-40°C to +85°C (industrial temperature range); VSS
0 to +70°C (commercial temperature range); VSS =
-40°C to +85°C (industrial temperature range); VSS
0 V; VCC = 5 V ± 10%; -M and -V ranges.
= 0 V; VCC = 5 V ± 10%; -M and -V ranges.
0 V; 2.7 V < VCC < 5.5 V; -L range.
= 0 V; 2.7 V < VCC < 5.5 V; -L range.
Table 31. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals.
Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings
will then be degraded.
Table 31. Load Capacitance versus speed range, in pF
-M
100
80
100
Port 0
Port 1, 2, 3
ALE / PSEN
-V
50
50
30
-L
100
80
100
Table 33., Table 36. and Table 39. give the description of each AC symbols.
Table 34., Table 37. and Table 40. give for each range the AC parameter.
Table 35., Table 38. and Table 41. give the frequency derating formula of the AC parameter. To calculate each
AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value
in the formula. Values of the frequency must be limited to the corresponding speed grade:
Table 32. Max frequency for derating formula regarding the speed grade
Freq (MHz)
T (ns)
-M X1 mode
40
25
-M X2 mode
20
50
-V X1 mode
40
25
-V X2 mode
30
33.3
-L X1 mode
30
33.3
-L X2 mode
20
50
Example:
TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns):
x= 22 (Table 35.)
T= 50ns
TLLIV= 2T - x = 2 x 50 - 22 = 78ns
Rev. D - 15 January, 2001
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TS80C51U2
TS83C51U2
TS87C51U2
11.5.2 External Program Memory Characteristics
Table 33. Symbol Description
Symbol
T
Parameter
Oscillator clock period
TLHLL
ALE pulse width
TAVLL
Address Valid to ALE
TLLAX
Address Hold After ALE
TLLIV
ALE to Valid Instruction In
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction FloatAfter PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
Table 34. AC Parameters for Fix Clock
Speed
-M
40 MHz
Min
Min
33
25
50
33
ns
TLHLL
40
25
42
35
52
ns
TAVLL
10
4
12
5
13
ns
TLLAX
10
4
12
5
13
ns
78
Max
Min
Units
25
45
Max
-L
standard mode
30 MHz
T
70
Max
-L
X2 mode
20 MHz
40 MHz equiv.
Min
65
Max
98
ns
TLLPL
15
9
17
10
18
ns
TPLPH
55
35
60
50
75
ns
TPLIV
TPXIX
56
Min
-V
standard mode
40 MHz
Symbol
TLLIV
Max
-V
X2 mode
30 MHz
60 MHz equiv.
35
0
25
0
50
0
30
0
55
0
ns
ns
TPXIZ
18
12
20
10
18
ns
TAVIV
85
53
95
80
122
ns
TPLAZ
10
10
10
10
10
ns
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 35. AC Parameters for a Variable Clock: derating formula
Symbol
Type
Standard
Clock
X2 Clock
-M
-V
-L
Units
TLHLL
Min
2T-x
T-x
10
8
15
ns
TAVLL
Min
T-x
0.5 T - x
15
13
20
ns
TLLAX
Min
T-x
0.5 T - x
15
13
20
ns
TLLIV
Max
4T-x
2T-x
30
22
35
ns
TLLPL
Min
T-x
0.5 T - x
10
8
15
ns
TPLPH
Min
3T-x
1.5 T - x
20
15
25
ns
TPLIV
Max
3T-x
1.5 T - x
40
25
45
ns
TPXIX
Min
x
x
0
0
0
ns
TPXIZ
Max
T-x
0.5 T - x
7
5
15
ns
TAVIV
Max
5T-x
2.5 T - x
40
30
45
ns
TPLAZ
Max
x
x
10
10
10
ns
11.5.3 External Program Memory Read Cycle
12 TCLCL
TLHLL
TLLIV
ALE
TLLPL
TPLPH
PSEN
TLLAX
TAVLL
PORT 0
INSTR IN
TPLIV
TPLAZ
A0-A7
TPXAV
TPXIZ
TPXIX
INSTR IN
A0-A7
INSTR IN
TAVIV
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A8-A15
ADDRESS A8-A15
Figure 21. External Program Memory Read Cycle
Rev. D - 15 January, 2001
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TS80C51U2
TS83C51U2
TS87C51U2
11.5.4 External Data Memory Characteristics
Table 36. Symbol Description
Symbol
58
Parameter
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data set-up to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE high
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 37. AC Parameters for a Fix Clock
Speed
-M
40 MHz
85
135
125
175
ns
TWLWH
130
85
135
125
175
ns
60
0
Max
Min
102
0
Max
Min
Units
130
0
Min
-L
standard mode
30 MHz
TRLRH
100
Max
-L
X2 mode
20 MHz
40 MHz equiv.
Min
TRHDX
Min
-V
standard mode
40 MHz
Symbol
TRLDV
Max
-V
X2 mode
30 MHz
60 MHz equiv.
95
0
Max
137
0
ns
ns
TRHDZ
30
18
35
25
42
ns
TLLDV
160
98
165
155
222
ns
TAVDV
165
100
175
160
235
ns
130
ns
TLLWL
50
TAVWL
75
47
80
70
103
ns
TQVWX
10
7
15
5
13
ns
TQVWH
160
107
165
155
213
ns
TWHQX
15
9
17
10
18
ns
TRLAZ
TWHLH
100
30
0
10
Rev. D - 15 January, 2001
40
70
55
0
7
27
95
45
0
15
35
105
70
0
5
45
13
0
ns
53
ns
59
TS80C51U2
TS83C51U2
TS87C51U2
Table 38. AC Parameters for a Variable Clock: derating formula
Symbol
Type
Standard
Clock
X2 Clock
-M
-V
-L
Units
TRLRH
Min
6T-x
3T-x
20
15
25
ns
TWLWH
Min
6T-x
3T-x
20
15
25
ns
TRLDV
Max
5T-x
2.5 T - x
25
23
30
ns
TRHDX
Min
x
x
0
0
0
ns
TRHDZ
Max
2T-x
T-x
20
15
25
ns
TLLDV
Max
8T-x
4T -x
40
35
45
ns
TAVDV
Max
9T-x
4.5 T - x
60
50
65
ns
TLLWL
Min
3T-x
1.5 T - x
25
20
30
ns
TLLWL
Max
3T+x
1.5 T + x
25
20
30
ns
TAVWL
Min
4T-x
2T-x
25
20
30
ns
TQVWX
Min
T-x
0.5 T - x
15
10
20
ns
TQVWH
Min
7T-x
3.5 T - x
15
10
20
ns
TWHQX
Min
T-x
0.5 T - x
10
8
15
ns
TRLAZ
Max
x
x
0
0
0
ns
TWHLH
Min
T-x
0.5 T - x
15
10
20
ns
TWHLH
Max
T+x
0.5 T + x
15
10
20
ns
11.5.5 External Data Memory Write Cycle
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TLLAX
PORT 0
A0-A7
TQVWX
TWHQX
TQVWH
DATA OUT
TAVWL
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
Figure 22. External Data Memory Write Cycle
60
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
11.5.6 External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
TLLWL
TRLRH
TRLDV
RD
TLLAX
PORT 0
TRHDZ
TAVDV
TRHDX
A0-A7
DATA IN
TRLAZ
TAVWL
ADDRESS
OR SFR-P2
PORT 2
ADDRESS A8-A15 OR SFR P2
Figure 23. External Data Memory Read Cycle
11.5.7 Serial Port Timing - Shift Register Mode
Table 39. Symbol Description
Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output data set-up to clock rising edge
TXHQX
Output data hold after clock rising edge
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
Table 40. AC Parameters for a Fix Clock
Speed
-M
40 MHz
Max
200
300
300
400
ns
TQVHX
200
117
200
200
283
ns
TXHQX
30
13
30
30
47
ns
TXHDX
0
0
0
0
0
ns
117
Min
Max
117
Min
Units
300
34
Min
-L
standard mode
30 MHz
TXLXL
Rev. D - 15 January, 2001
Max
-L
X2 mode
20 MHz
40 MHz equiv.
Min
117
Min
-V
standard mode
40 MHz
Symbol
TXHDV
Max
-V
X2 mode
30 MHz
60 MHz equiv.
Max
200
ns
61
TS80C51U2
TS83C51U2
TS87C51U2
Table 41. AC Parameters for a Variable Clock: derating formula
-M
-V
Units
Symbol
Type
Standard
Clock
X2 Clock
-L
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
50
50
ns
TXHQX
Min
2T-x
T-x
20
20
20
ns
TXHDX
Min
x
x
0
0
0
ns
TXHDV
Max
10 T - x
5 T- x
133
133
133
ns
ns
11.5.8 Shift Register Timing Waveforms
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
0
WRITE to SBUF
TXHDV
INPUT DATA
1
2
3
4
5
6
7
TXHDX
VALID
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
Figure 24. Shift Register Timing Waveforms
62
Rev. D - 15 January, 2001
TS80C51U2
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TS87C51U2
11.5.9 EPROM Programming and Verification Characteristics
TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming. VCC = operating range while verifying
Table 42. EPROM Programming Parameters
Parameter
Symbol
VPP
Programming Supply Voltage
IPP
Programming Supply Current
1/TCLCL
Min
Max
Units
12.5
13
V
75
mA
6
MHz
Oscillator Frquency
4
TAVGL
Address Setup to PROG Low
48 TCLCL
TGHAX
Adress Hold after PROG
48 TCLCL
TDVGL
Data Setup to PROG Low
48 TCLCL
TGHDX
Data Hold after PROG
48 TCLCL
TEHSH
(Enable) High to VPP
48 TCLCL
TSHGL
VPP Setup to PROG Low
10
µs
TGHSL
VPP Hold after PROG
10
µs
TGLGH
PROG Width
90
TAVQV
Address to Valid Data
48 TCLCL
TELQV
ENABLE Low to Data Valid
48 TCLCL
TEHQZ
Data Float after ENABLE
0
µs
110
48 TCLCL
11.5.10 EPROM Programming and Verification Waveforms
PROGRAMMING
VERIFICATION
ADDRESS
ADDRESS
P1.0-P1.7
P2.0-P2.5
P3.4-P3.5*
TAVQV
P0
DATA OUT
DATA IN
TGHDX
TGHAX
TDVGL
TAVGL
ALE/PROG
TSHGL
TGLGH
EA/VPP
TGHSL
VPP
VCC
TEHSH
CONTROL
SIGNALS
(ENABLE)
VCC
TELQV
TEHQZ
* 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5
Figure 25. EPROM Programming and Verification Waveforms
Rev. D - 15 January, 2001
63
TS80C51U2
TS83C51U2
TS87C51U2
11.5.11 External Clock Drive Characteristics (XTAL1)
Table 43. AC Parameters
Symbol
Parameter
Min
Max
Units
TCLCL
Oscillator Period
25
ns
TCHCX
High Time
5
ns
TCLCX
Low Time
5
ns
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
60
%
TCHCX/TCLCX
Cyclic ratio in X2 mode
40
11.5.12 External Clock Drive Waveforms
VCC-0.5 V
0.7VCC
0.2VCC-0.1 V
TCHCL
0.45 V
TCHCX
TCLCH
TCLCX
TCLCL
Figure 26. External Clock Drive Waveforms
11.5.13 AC Testing Input/Output Waveforms
VCC-0.5 V
INPUT/OUTPUT
0.2VCC+0.9
0.2VCC-0.1
0.45 V
Figure 27. AC Testing Input/Output Waveforms
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement
are made at VIH min for a logic “1” and VIL max for a logic “0”.
11.5.14 Float Waveforms
FLOAT
VOH-0.1 V VLOAD
VOL+0.1 V
VLOAD+0.1 V
VLOAD-0.1 V
Figure 28. Float Waveforms
64
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA.
11.5.15 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
STATE4
INTERNAL
CLOCK
P1
P2
STATE5
STATE6
STATE1
STATE2
P1
P1
P1
P1
P2
P2
P2
P2
STATE3
P1
P2
STATE4
P1
P2
STATE5
P1
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
SAMPLED
PCL OUT
DATA
SAMPLED
FLOAT
P2 (EXT)
PCL OUT
DATA
SAMPLED
PCL OUT
FLOAT
FLOAT
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
FLOAT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
P0
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DPL OR Rt OUT
DATA OUT
P2
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
OLD DATA
P0 PINS SAMPLED
NEW DATA
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
P1, P2, P3 PINS SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
Figure 29. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
Rev. D - 15 January, 2001
65
TS80C51U2
TS83C51U2
TS87C51U2
12. Ordering Information
TS
-V
87C51U2
-V:
-L:
-E :
R
B
I
VCC: 5V +/- 10%
40 MHz, X1 mode
30 MHz, X2 mode
VCC: 2.7 to 5.5 V
30 MHz, X1 mode
20 MHz, X2 mode
Samples
Packages:
A: PDIL 40
B: PLCC 44
E: VQFP 44 (1.4mm)
J: Window CDIL 40*
K: Window CQPJ 44*
Conditioning
R: Tape & Reel
D: Dry Pack
B: Tape & Reel and
Dry Pack
Part Number
TS80C51U2:
ROMless
TS83C51U2zzz: 16k ROM, zzz is the customer code
TS87C51U2:
16k OTP EPROM
Temperature Range
I: Commercial and Industrial -40 to 85oC
(*) Check with Atmel Wireless & Microcontrollers Sales Office for availability - Ceramic parts only for OTP (TS87C51U2)
Ceramic packages (J, K) are available for prototyping, not for volume production.
Table 44. Maximum Clock Frequency
Code
-M
-V
-L
Standard Mode, oscillator frequency
Standard Mode, internal frequency
X2 Mode, oscillator frequency
X2 Mode, internal equivalent frequency
40
40
20
40
40
40
30
60
30
30
20
40
66
Unit
MHz
MHz
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 45. Possible Ordering Entries
TS80C51U2 ROMless
TS83C51U2zzz 16K ROM
TS87C51U2 16K OTP
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-VIA
-VIB
-VIE
-LIA
-LIB
-LIE
-EA
-EB
-EE
-EJ
-EK
●
-Ex for samples
●
Tape and Reel available for B and E packages
●
Dry pack mandatory for E packages
Rev. D - 15 January, 2001
67