MB91F465KA
MB91F465KB
FR60, MB91460K Series,
32-bit Microcontroller Datasheet
MB91460K series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require
high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which
is compatible with the FR family of CPUs.
This series contains the LIN-USART and CAN controllers.
Features
FR60 CPU core
■
32-bit RISC, load/store architecture, five-stage pipeline
■
16-bit fixed-length instructions (basic instructions)
■
Instruction execution speed: 1 instruction per cycle
■
Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for
embedded applications
■
Function entry/exit instructions and register data multi-load
store instructions : Instructions supporting C language
■
Register interlock function: Facilitating assembly-language
coding
■
Built-in multiplier with instruction-level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
■
Interrupts (save PC/PS): 6 cycles (16 priority levels)
■
Harvard architecture enabling program access and data
access to be performed simultaneously
■
Instructions compatible with the FR family
Internal peripheral resources
■
General-purpose ports: Maximum 73 ports
■
Sync-break detection
■
DMAC (DMA Controller)
■
Internal dedicated baud rate generator
■
Maximum of 5 channels able to operate simultaneously.
■
I2C bus interface (supports 400 kbps): 1 channel
■
2 transfer sources (internal peripheral/software)
■
Master/slave transmission and reception
■
Activation source can be selected using software.
■
Arbitration function, clock synchronisation function
■
Addressing mode specifies full 32-bit addresses
(increment/decrement/fixed)
■
CAN controller (C-CAN): 1 channel
Transfer mode (demand transfer/burst transfer/step
transfer/block transfer)
■
Maximum transfer speed: 1 Mbps
■
■
32 transmission/reception message buffers
■
Transfer data size selectable from 8/16/32-bit
■
16-bit PPG timer: 12 channels
■
Multi-byte transfer enabled (by software)
■
16-bit reload timer: 8 channels
■
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
■
■
A/D converter (successive approximation type)
16-bit free-run timer: 8 channels (1 channel each for ICU and
OCU)
10-bit resolution: 26 channels
■
■
Input capture: 8 channels (operates in conjunction with the
free-run timer)
■
Conversion time: minimum 1 s
■
■
External interrupt inputs: 10 channels
Output compare: 8 channels (operates in conjunction with the
free-run timer)
■
Shares the CAN RX pin and the I2C SDA pin
■
Watchdog timer
■
Bit search module (for REALOS)
■
Real-time clock
■
Function to search from the MSB (most significant bit) for the
position of the first “0”, “1”, or changed bit in a word
■
Low-power consumption modes : Sleep/stop mode function
■
Supply Supervisor: Low voltage detection circuit for external
VDD5 and internal 1.8V core voltage
■
Clock supervisor
Monitors the sub-clock (32 kHz) and the main clock (4 MHz) ,
■
LIN-USART (full duplex double buffer): 5 channels
■
Clock synchronous/asynchronous selectable
Cypress Semiconductor Corporation
Document Number: 002-04602 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 14, 2016
MB91460K Series
and switches to a recovery clock (CR oscillator, etc.) when the
oscillations stop.
86
■
Clock modulator
■
Clock monitor
■
Sub-clock calibration
Corrects the real-time clock timer when operating with the 32
kHz or CR oscillator
■
Main oscillator stabilisation timer
Generates an interrupt in sub-clock mode after the stabilisation
wait time has elapsed on the 23-bit stabilisation wait time
counter
■
Sub-oscillator stabilisation timer
Generates an interrupt in main clock mode after the stabilisation wait time has elapsed on the 15-bit stabilisation wait time
counter
■
Power supply range 3 V to 5 V (1.8 V internal logic provided by
a step-down voltage converter)
■
Operating temperature range: between 40°C and 105°C
Package and technology
■
Package: 120-pin plastic LQFP (LQFP-120)
■
CMOS 0.18 m technology
Document Number: 002-04602 Rev. *A
Page 2 of 86
MB91460K Series
Contents
86
Pin Description............................................................. 7
MB91F465Kx ................................................................. 7
Power Supply/Ground Pins.......................................... 10
9.
9.1
9.2
9.3
9.4
9.5
9.6
Embedded Program/Data Memory (Flash) ............... 27
Flash Features .............................................................. 27
Operation Modes .......................................................... 27
Flash Access in CPU mode .......................................... 28
Parallel Flash Programming Mode................................ 30
Power on Sequence in Parallel Programming Mode .... 32
Flash Security ............................................................... 32
4.
I/O Circuit Types......................................................... 11
10.
Memory Space............................................................. 34
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Handling Devices .......................................................
Preventing Latch-up.....................................................
Handling of Unused Input Pins ....................................
Power Supply Pins.......................................................
Crystal Oscillator Circuit...............................................
Notes on using External Clock.....................................
Mode Pins (MD_x) .......................................................
Notes on Operating in PLL Clock Mode.......................
Pull-Up Control.............................................................
Notes on PS Register ..................................................
18
18
18
18
18
18
19
19
19
19
11. Memory Maps .............................................................. 35
11.1 MB91F465Kx ................................................................ 35
6.
6.1
6.2
6.3
Notes on Debugger....................................................
Execution of the RETI Command ................................
Break Function.............................................................
Operand Break.............................................................
20
20
20
20
7.
7.1
Block Diagram............................................................ 21
MB91F465Kx ............................................................... 21
8.
8.1
8.2
8.3
8.4
CPU and Control Unit ................................................
Features.......................................................................
Internal Architecture.....................................................
Programming Model.....................................................
Registers......................................................................
11.
Product Lineup............................................................. 4
2.
2.1
Pin Assignment............................................................ 6
MB91F465Kx ................................................................. 6
3.
3.1
3.2
22
22
22
23
24
12. I/O Map......................................................................... 36
12.1 MB91F465Kx ................................................................ 36
12.2 Flash Memory and External Bus Area .......................... 53
13.
Interrupt Vector Table ................................................. 55
14. Recommended Settings ............................................. 60
14.1 PLL and Clockgear settings .......................................... 60
14.2 Clock Modulator Settings .............................................. 61
15.
15.1
15.2
15.3
15.4
15.5
15.6
Electrical Characteristics ........................................... 65
Absolute maximum ratings............................................ 65
Recommended Operating Conditions........................... 67
DC Characteristics ........................................................ 68
A/D Converter Characteristics ...................................... 71
Flash Memory Program/erase Characteristics.............. 75
AC Characteristics ........................................................ 76
16.
Ordering Information .................................................. 82
17.
Package Dimension .................................................... 83
18.
Main Changes in this Edition..................................... 84
Document History ................................................................85
Document Number: 002-04602 Rev. *A
Page 3 of 86
MB91460K Series
1. Product Lineup
MB91V460A
(Evaluation device)
Feature
86
MB91F465KA
MB91F465KB
Max. core frequency (CLKB)
80MHz
80MHz
Max. resource frequency (CLKP)
40MHz
40MHz
Max. external bus freq. (CLKT)
40MHz
40MHz
Max. CAN frequency (CLKCAN)
20MHz
40MHz
Technology
0.35 m
0.18 m
yes
yes
yes (disengageable)
yes
Bit Search
yes
yes
Reset input (INITX)
yes
yes
Hardware Standby input (HSTX)
yes
-
Clock Modulator
yes
yes
Watchdog timer
Watchdog timer (RC osc. based)
Low Power Mode
yes
yes
DMA
5 ch
5 ch
MPU (16 ch) [1]
MPU (2 ch) [1]
MMU/MPU
Flash memory
Emulation SRAM 32bit read data
544 KByte
Satellite Flash memory
n.a.
-
Flash Protection
n.a.
yes
D-RAM
64 KByte
8 KByte
ID-RAM
64 KByte
8 KByte
Flash-cache (F-cache)
16 KByte
4 KByte
4 KByte fixed
4 KByte
RTC
1 ch
1 ch
Free Running Timer
8 ch
8 ch
ICU
8 ch
8 ch
OCU
8 ch
8 ch
Reload Timer
8 ch
8 ch
PPG 16-bit
16 ch
12 ch
PFM 16-bit
1 ch
-
Boot-ROM / BI-ROM
Sound Generator
Up/Down Counter (8/16-bit)
C_CAN
LIN-USART
I2C (400k)
Document Number: 002-04602 Rev. *A
1 ch
-
4 ch (8-bit) / 2 ch (16-bit)
-
6 ch (128msg)
1 ch (32msg)
4 ch + 4 ch FIFO + 8 ch
4 ch + 1 ch FIFO
4 ch
1 ch
Page 4 of 86
MB91460K Series
MB91V460A
(Evaluation device)
MB91F465KA
MB91F465KB
yes (32bit addr, 32bit data)
-
External Interrupts
16 ch
10 ch
NMI Interrupts
1 ch
-
SMC
6 ch
-
LCD controller (40x4)
1 ch
-
ADC (10 bit)
32 ch
26 ch
Alarm Comparator
2 ch
-
Supply Supervisor
(low voltage detection)
yes
yes
Clock Supervisor
yes
yes
Feature
86
FR external bus
Main clock oscillator
4MHz
4MHz
Sub clock oscillator
32kHz
32kHz
RC Oscillator
100kHz
100kHz / 2MHz
PLL
x 20
x 20
DSU4
yes
EDSU
Supply Voltage
yes (32 BP)
[1]
yes (4 BP)
[1]
3V / 5V
3V / 5V
Regulator
yes
yes
Power Consumption
n.a.
< 900 mW
Temperature Range (TA)
0..70 °C
-40..105°C
Package
BGA660
LQFP120
Power on to PLL run
< 20 ms
< 20 ms
Flash Download Time
n.a.
< 5 sec typical
1. MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
Document Number: 002-04602 Rev. *A
Page 5 of 86
MB91460K Series
2. Pin Assignment
2.1
MB91F465Kx
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
VSS5
MONCLK
MD_2
MD_1
X0
X1
VSS5
X1A
X0A
MD_0
P16_1 / PPG9
P16_0 / PPG8
P20_7
P20_6 / SCK3 / CK3
P20_5 / SOT3
P20_4 / SIN3
P20_3
P20_2 / SCK2 / CK2
P20_1 / SOT2
P20_0 / SIN2
P16_5
P16_4
P24_7 / INT7
P24_6 / INT6
P24_5 / INT5
P24_4 / INT4
P24_3 / INT3
P24_2 / INT2
P24_1 / INT1
VDD5
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LQFP-120
QFP-120
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VSS5
P24_0 / INT0
P22_1 / TX4
P22_0 / RX4 / INT12
P15_3 / OCU3 / TOT3
P15_2 / OCU2 / TOT2
P15_1 / OCU1 / TOT1
P15_0 / OCU0 / TOT0
P16_3 / PPG11
P16_2 / PPG10
P17_7 / PPG7
P17_6 / PPG6
P17_5 / PPG5
VSS5
VDD5
P21_7
P21_6 / SCK1 / CK1
P21_5 / SOT1
P21_4 / SIN1
P21_3
P21_2 / SCK0 / CK0
P21_1 / SOT0
P21_0 / SIN0
P17_4 / PPG4
P17_3 / PPG3
P17_2 / PPG2
P16_6
P16_7 / ATGX
INITX
VSS5
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VDD5
P14_0 / ICU0+TIN0 / TIN0 / TTG8/0
P14_1 / ICU1+TIN1 / TIN1 / TTG9/1
P14_2 / ICU2+TIN2 / TIN2 / TTG10/2
P14_3 / ICU3+TIN3 / TIN3 / TTG11/3
P14_4 / ICU4+TIN4 / TIN4 / TTG4
P14_5 / ICU5+TIN5 / TIN5 / TTG5
P14_6 / ICU6+TIN6 / TIN6 / TTG6
P14_7 / ICU7+TIN7 / TIN7 / TTG7
P15_4 / OCU4 / TOT4
P15_5 / OCU5 / TOT5
P15_6 / OCU6 / TOT6
P15_7 / OCU7 / TOT7
P19_6 / FRCK5
VDD5R
VCC18C
VSS5
VDD5
P26_0 / AN24
P26_1 / AN25
P27_0 / AN16
P27_1 / AN17
P27_2 / AN18
P27_3 / AN19
P27_4 / AN20
P27_5 / AN21
P27_6 / AN22
P27_7 / AN23
P28_0 / AN8
VDD5
VSS5
P28_1 / AN9
P28_2 / AN10
P28_3 / AN11
P28_4 / AN12
AVCC5
AVRH5
AVSS
P29_0 / AN0
P29_1 / AN1
P29_2 / AN2
P29_3 / AN3
P29_4 / AN4
P29_5 / AN5
P29_6 / AN6
P29_7 / AN7
P28_5 / AN13
VSS5
P28_6 / AN14
P28_7 / AN15
P22_4 / SDA0 / INT14
P22_5 / SCL0
P19_0 / SIN4
P19_1 / SOT4
P19_2 / SCK4 / CK4
P18_2 / CK6
P18_6 / CK7
P17_0 / PPG0
P17_1 / PPG1
VDD5
86
FPT-120P-M21
Document Number: 002-04602 Rev. *A
Page 6 of 86
MB91460K Series
3. Pin Description
86
3.1
MB91F465Kx
Pin no.
Pin name
I/O
I/O
circuit
type[1]
P14_0 to P14_7
General-purpose input/output ports
ICU0 to ICU7
2 to 9
TIN0 to TIN7
Input capture input pins
I/O
A
TTG0/8 to
TTG3/11,
TTG4 to TTG7
OCU4 to OCU7
General-purpose input/output ports
I/O
A
TOT4 to TOT7
14
19, 20
21 to 28
29,
32 to 35
39 to 46
47, 49, 50
P19_6
CK5
P26_0, P26_1
AN24, AN25
P27_0 to P27_7
AN16 to AN23
P28_0 to P28_4
AN8 to AN12
P29_0 to P29_7
AN0 to AN7
P28_5 to P28_7
AN13 to AN15
SDA0
I/O
A
I/O
B
I/O
B
I/O
B
I/O
B
I/O
B
52
53
54
SCL0
P19_0
SIN4
P19_1
SOT4
I/O
C
SCK4
I/O
C
I/O
A
I/O
A
P18_2, P18_6
CK6, CK7
General-purpose input/output ports
Analog input pins for A/D converter
General-purpose input/output ports
Analog input pins for A/D converter
General-purpose input/output ports
Analog input pins for A/D converter
General-purpose input/output ports
Analog input pins for A/D converter
General-purpose input/output ports
Analog input pins for A/D converter
I2C bus data input/output pin
General-purpose input/output port
I2C bus CLK input/output pin
General-purpose input/output port
Data input pin for USART4
General-purpose input/output port
Data output pin for USART4
General-purpose input/output port
I/O
A
CK4
56, 57
External clock input pin for free-run timer 5
External interrupt input pin
P19_2
55
General-purpose input/output port
General-purpose input/output port
INT14
P22_5
Output compare output pins
Reload timer output pins
P22_4
51
External trigger input pins for reload timer
External trigger input pins for PPG timer
P15_4 to P15_7
10 to 13
Description
Clock input/output pin for USART4
External clock input pin for free-run timer 4
I/O
Document Number: 002-04602 Rev. *A
A
General-purpose input/output port
External clock input pin for free-run timers 6,7
Page 7 of 86
MB91460K Series
Pin no.
86
58, 59
62
63
64
65 to 67
68
69
Pin name
P17_0, P17_1
PPG0, PPG1
I/O
I/O
circuit
type[1]
I/O
A
I
H
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
INITX
P16_7
ATGX
P16_6
P17_2 to P17_4
PPG2 to PPG4
P21_0
SIN0
P21_1
SOT0
P21_2
70
SCK0
72
73
P21_3
P21_4
SIN1
P21_5
SOT1
I/O
A
SCK1
I/O
A
I/O
A
I/O
A
78 to 80
81, 82
P21_7
P17_5 to P17_7
PPG5 to PPG7
P16_2, P16_3
PPG10, PPG11
I/O
A
OCU0 to OCU3
I/O
A
I/O
A
I/O
A
I/O
A
P22_1
TX4
89,
92 to 98
P24_0 to P24_7
99, 100
P16_4, P16_5
INT0 to INT7
General-purpose input/output ports
PPG timer output pins
General-purpose input/output port
Data input pin for USART0
General-purpose input/output port
Data output pin for USART0
Clock input/output pin for USART0
General-purpose input/output port
General-purpose input/output port
Data input pin for USART1
General-purpose input/output port
Data output pin for USART1
Clock input/output pin for USART1
General-purpose input/output port
General-purpose input/output ports
PPG timer output pins
General-purpose input/output ports
PPG timer output pins
Output compare output pins
General-purpose input/output port
I/O
A
INT12
88
General-purpose input/output port
Reload timer output pins
P22_0
RX4
A/D converter external trigger input pin
General-purpose input/output ports
TOT0 to TOT3
87
General-purpose input/output port
External clock input pin for free-run timer 1
P15_0 to P15_3
83 to 86
External reset input pin
General-purpose input/output port
CK1
75
PPG timer output pins
External clock input pin for free-run timer 0
P21_6
74
General-purpose input/output ports
General-purpose input/output port
CK0
71
Description
RX input pin for CAN4
External interrupt input pin
I/O
A
I/O
A
I/O
A
Document Number: 002-04602 Rev. *A
General-purpose input/output port
TX output pin for CAN4
General-purpose input/output ports
External interrupt input pins
General-purpose input/output ports
Page 8 of 86
MB91460K Series
Pin no.
86
101
102
Pin name
P20_0
SIN2
P20_1
SOT2
I/O
I/O
circuit
type[1]
I/O
A
I/O
A
P20_2
103
SCK2
104
P20_3
106
P20_4
SIN3
P20_5
SOT3
SCK3
108
P20_7
P16_0, P16_1
PPG8, PPG9
General-purpose input/output port
Data output pin for USART2
A
Clock input/output pin for USART2
I/O
A
General-purpose input/output port
I/O
A
I/O
A
External clock input pin for free-run timer 2
General-purpose input/output port
Data input pin for USART3
General-purpose input/output port
Data output pin for USART3
General-purpose input/output port
I/O
A
Clock input/output pin for USART3
I/O
A
General-purpose input/output port
I/O
A
CK3
109, 110
Data input pin for USART2
I/O
P20_6
107
General-purpose input/output port
General-purpose input/output port
CK2
105
Description
External clock input pin for free-run timer 3
General-purpose input/output ports
PPG timer output pins
111
MD_0
I
G
Mode setting pin
112
X0A
-
J2
Sub clock (oscillation) input
113
X1A
-
J2
Sub clock (oscillation) output
115
X1
-
J1
Clock (oscillation) output
116
X0
-
J1
Clock (oscillation) input
117
MD_1
I
G
118
MD_2
I
G
119
MONCLK
O
M
Mode setting pins
Clock monitor pin
1. For information about the I/O circuit type, refer to “I/O Circuit Types”.
Document Number: 002-04602 Rev. *A
Page 9 of 86
MB91460K Series
3.2
86
Power Supply/Ground Pins
Pin no.
Pin name
17, 31, 46, 61, 77, 90, 114, 120
VSS5
Description
Ground pins
1, 18, 30, 60, 76, 91
VDD5
15
VDD5R
Power supply pin for internal regulator
38
AVSS5
Analog ground pin for A/D converter
36
AVCC5
Power supply pin for A/D converter
37
AVRH5
Reference power supply pin for A/D converter
16
VCC18C
Capacitor connection pin for internal regulator
Document Number: 002-04602 Rev. *A
Power supply pins
Page 10 of 86
MB91460K Series
4. I/O Circuit Types
86
Type
Circuit
A
Remarks
pull-up control
driver strength
control
data line
CMOS level output (programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50k approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
Document Number: 002-04602 Rev. *A
Page 11 of 86
MB91460K Series
Type
86
Circuit
B
Remarks
pull-up control
driver strength
control
data line
CMOS level output (programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50k approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
C
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50k approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
Document Number: 002-04602 Rev. *A
Page 12 of 86
MB91460K Series
Type
86
Circuit
D
Remarks
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50k approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
E
pull-up control
driver strength
control
data line
CMOS level output (programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50k approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
Document Number: 002-04602 Rev. *A
Page 13 of 86
MB91460K Series
Type
86
Circuit
F
Remarks
pull-up control
driver strength
control
data line
CMOS level output (programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50k approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
G
R
Hysteresis
inputs
H
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
CMOS input pin
12 V withstand (for MD [2:0])
CMOS Hysteresis input pin
Pull-up resistor value: 50 k approx.
Pull-up
Resistor
R
Document Number: 002-04602 Rev. *A
Hysteresis
inputs
Page 14 of 86
MB91460K Series
Type
86
Circuit
Remarks
J1
High-speed oscillation circuit:
■ Programmable between oscillation mode (external crystal
or resonator connected to X0/X1 pins) and Fast external
Clock Input (FCI) mode (external clock connected to X0
pin)
X1
R
■ Feedback resistor = approx. 2 * 0.5 M. Feedback resistor
is grounded in the center when the oscillator is disabled
or in FCI mode.
0
Xout
1
FCI
R
X0
FCI or osc disable
J2
Low-speed oscillation circuit:
■ Feedback resistor = approx. 2 * 5 M. Feedback resistor
Xout
X1A
is grounded in the center when the oscillator is disabled.
R
R
X0A
osc disable
Document Number: 002-04602 Rev. *A
Page 15 of 86
MB91460K Series
Type
86
Circuit
K
Remarks
pull-up control
driver strength
control
data line
CMOS level output (programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50k approx.
LCD SEG/COM output
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
LCD SEG/COM
Document Number: 002-04602 Rev. *A
Page 16 of 86
MB91460K Series
Type
86
Circuit
L
Remarks
pull-up control
driver strength
control
data line
CMOS level output (programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50k approx.
Analog input
LCD Voltage input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
VLCD
M
CMOS level tri-state output(IOL = 5mA, IOH = -5mA)
tri-state control
data line
N
Analog input pin with protection
analog input line
Document Number: 002-04602 Rev. *A
Page 17 of 86
MB91460K Series
5. Handling Devices
86
5.1
Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5) or less than (VSS5) is applied to an input or output pin or if a
voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply
current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply
voltages in excess of the absolute maximum ratings.
5.2
Handling of Unused Input Pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or
pull-down resistor (2K to 10K) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN)
is activated by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be
connected to AVSS5 directly.
5.3
Power Supply Pins
In MB91460K series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to
be at the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pins and
ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation,
to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore,
the power supply pins and ground pins of the MB91460K series must be connected to the current supply source via a low
impedance.It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between
power supply pin and ground pin near this device.This series has a built-in step-down regulator. Connect a bypass capacitor of
4.7 F (use a X7R ceramic capacitor) to VCC18C pin for the regulator.
5.4
Crystal Oscillator Circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should
be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground,
are located near the device and ground.
It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are
surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device.
5.5
Notes on using External Clock
When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described
combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1,
a frequency up to 16 MHz is possible.
Example of using opposite phase supply
X0 (X0A)
X1 (X1A)
Document Number: 002-04602 Rev. *A
Page 18 of 86
MB91460K Series
5.6
86
Mode Pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode
accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on
the printed circuit board as possible and connect them with low impedance.
5.7
Notes on Operating in PLL Clock Mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to
operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-running operation cannot
be guaranteed.
5.8
Pull-Up Control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
5.9
Notes on PS Register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may
result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,the operation before
and after the EIT always proceeds according to specification.
■
The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/DIV0S
instruction:
(a) a user interrupt or NMI is accepted;
(b) single-step execution is performed;
(c) execution breaks due to a data event or from the emulator menu.
1. D0 and D1 flags are updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the
same values as those in 1.
■
The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user
interrupt or NMI source while that interrupt is in the active state.
1. The PS register is updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value
as in 1.
Document Number: 002-04602 Rev. *A
Page 19 of 86
MB91460K Series
6. Notes on Debugger
86
6.1
Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling
routine will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for
low priority level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI
instruction will always break on the first line of the time-base timer interrupt handler).
Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs
debugging.
6.2
Break Function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack
pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user
program actually contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the
hardware break (including an event breaks).
6.3
Operand Break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to
the areas containing the address of system stack pointer as a target of data event break.
Document Number: 002-04602 Rev. *A
Page 20 of 86
MB91460K Series
7. Block Diagram
86
7.1
MB91F465Kx
FR60 CPU
core
Flash-Cache
4 Kbytes
I-bus
32
D-RAM
8 Kbytes
Bit search
Flash memory
544 Kbytes
D-bus
32
CAN
1 channel
RX4
TX4
32 <-> 16
bus adapter
ID-RAM
8 Kbytes
Bus converter
DMAC
5 channels
R-bus
16
Clock modulator
Clock supervisor
Clock monitor
Clock control
Interrupt controller
TTG0/8 to TTG3/11, TTG4 to TTG7
PPG0 to PPG11
PPG timer
12 channels
TIN0 to TIN7
TOT0 to TOT7
Reload timer
8 channels
CK0 to CK7
ICU0 to ICU7
Free-run timer
8 channels
Input capture
8 channels
MONCLK
External interrupt
10 channels
INT0 to INT7,
INT12, INT14
LIN-USART
5 channels
SIN0 to SIN4
SOT0 to SOT4
SCK0 to SCK4
I 2C
1 channel
SDA0
SCL0
Real Time Clock
OCU0 to OCU7
P21_7, P21_3
P20_7, P20_3
P16_4 to P16_6
Document Number: 002-04602 Rev. *A
Output compare
8 channels
General purpose IO ports
without resource, 7 pins
A/D converter
26 channels
AN0 to AN25
ATGX
Page 21 of 86
MB91460K Series
8. CPU and Control Unit
86
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for
embedded applications.
8.1
Features
■
Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
■
General-purpose registers: 32-bit × 16 registers
■
4 Gbytes linear memory space
■
Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
■
Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
■
Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
Basic instruction word length: 16 bits
■
Low-power consumption
Sleep mode/stop mode
8.2
Internal Architecture
■
The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other.
■
A 32-bit 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral
resources.
■
A Harvard Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and
the bus controller.
Document Number: 002-04602 Rev. *A
Page 22 of 86
MB91460K Series
86
8.3
Programming Model
8.3.1
Basic Programming Model
32 bits
Initial value
R0
XXXX XXXXH
...
R1
General-purpose registers
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
RS
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply & divide registers
MDH
ILM
SCR
CCR
MDL
Document Number: 002-04602 Rev. *A
Page 23 of 86
MB91460K Series
86
8.4
Registers
8.4.1
General-purpose register
32 bits
Initial value
R0
XXXX XXXXH
R1
...
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as
pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
8.4.2
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
Document Number: 002-04602 Rev. *A
bit 10 bit 8 bit 7
SCR
bit 0
CCR
Page 24 of 86
MB91460K Series
8.4.3
CCR (Condition Code Register)
86
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SV
S
I
N
Z
V
C
Initial value
- 000XXXXB
SV: Supervisor flag
S: Stack flag
I: Interrupt enable flag
N: Negative enable flag
Z: Zero flag
V: Overflow flag
C: Carry flag
8.4.4
SCR (System Condition Register)
bit 10 bit 9
D1
D0
bit 8
Initial value
T
XX0B
Flag for step division (D1, D0) This flag stores interim data during execution of step division.
Step trace trap flag (T) This flag indicates whether the step trace trap is enabled or disabled.The step trace trap function is used by
emulators. When an emulator is in use, it cannot be used in execution of user programs.
8.4.5
ILM (Interrupt Level Mask Register)
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
8.4.6
PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
Document Number: 002-04602 Rev. *A
Page 25 of 86
MB91460K Series
8.4.7
86
TBR (Table Base Register)
bit 0 Initial value
bit 31
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
8.4.8
RP (Return Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
8.4.9
USP (User Stack Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
The USP register can also be explicitly specified.
The initial value at reset is undefined.
■
■
This register cannot be used with RETI instructions.
8.4.10
Multiply & Divide Registers
bit 31
bit 0
MDH
MDL
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
Document Number: 002-04602 Rev. *A
Page 26 of 86
MB91460K Series
9. Embedded Program/Data Memory (Flash)
86
9.1
Flash Features
■
MB91F465Kx: 544 Kbytes (8 64 Kbytes 4 8 Kbytes) = 4.25 Mbits
■
Programmable wait state for read/write access
■
Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F
■
Boot security
■
Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
9.2
Operation Modes
9.2.1
32-bit CPU mode :
■
CPU reads and executes programs in word (32-bit) length units.
■
Actual Flash Memory access is performed in word (32-bit) length units.
9.2.2
16-bit CPU mode :
■
CPU reads and writes in half-word (16-bit) length units.
■
Program execution from the Flash is not possible.
■
Actual Flash Memory access is performed in half-word (16-bit) length units.
Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start address is 0xBF60.
The parameter description is given in the Hardware Manual in chapter 54.6 "Flash Access Mode Switching".
Document Number: 002-04602 Rev. *A
Page 27 of 86
MB91460K Series
86
9.3
Flash Access in CPU mode
9.3.1
Flash Configuration
9.3.1.1
Flash Memory Map MB91F465Kx
Addr
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
ROMS7
ROMS6
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
addr+0
16bit read/write
addr+1
addr+2
dat[31:16]
addr+3
dat[15:0]
addr+4
addr+5
addr+6
dat[31:16]
32bit read
dat[31:0]
dat[31:0]
Legend
Memory not available in this area
Memory available in this area
Document Number: 002-04602 Rev. *A
addr+7
dat[15:0]
Page 28 of 86
MB91460K Series
9.3.2
86
Flash Access Timing Settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation)
for Flash read and write access.
9.3.2.1
Flash Read Timing Settings (Synchronous Read)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 80 MHz
1
1
3
-
4
to 100 MHz
1
1
3
-
4
not available on MB91F465Kx
Remark
9.3.2.2
Flash Write Timing Settings (Synchronous Write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 32 MHz
1
-
-
0
4
to 48 MHz
1
-
-
0
5
to 64 MHz
1
-
-
0
6
to 80 MHz
1
-
-
0
7
to 100 MHz
1
-
-
0
7
9.3.3
Remark
not available on MB91F465Kx
Address Mapping from CPU to Parallel Programming Mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel
programming.
9.3.3.1
Address Mapping MB91F465Kx
CPU Address
(addr)
Condition
Flash
sectors
FA (flash address) Calculation
14:8000h to 14:FFFFh
addr[2]==0
SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 0D:0000h
14:8000h to 14:FFFFh
addr[2]==1
SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 0D:0000h
+ 00:2000h
08:0000h to 0F:FFFFh
addr[2]==0
SA12, SA14, SA16, SA18
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 00:0000h
08:0000h to 0F:FFFFh
addr[2]==1
SA13, SA15, SA17, SA19
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 - 00:0000h
+ 01:0000h
Note: FA result is without 10:0000h offset for parallel Flash programming . Set offset by keeping FA[20] = 1 as described in section
“Parallel Flash programming mode”.
Document Number: 002-04602 Rev. *A
Page 29 of 86
MB91460K Series
86
9.4
Parallel Flash Programming Mode
9.4.1
Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
MB91F465Kx
FA[20:0]
001F:FFFFh
001F:0000h
SA19 (64KB)
001E:FFFFh
001E:0000h
SA18 (64KB)
001D:FFFFh
001D:0000h
SA17 (64KB)
001C:FFFFh
001C:0000h
SA16 (64KB)
001B:FFFFh
001B:0000h
SA15 (64KB)
001A:FFFFh
001A:0000h
SA14 (64KB)
0019:FFFFh
0019:0000h
SA13 (64KB)
0018:FFFFh
0018:0000h
SA12 (64KB)
SA11 (64KB)
SA10 (64KB)
SA9 (64KB)
SA8 (64KB)
0017:FFFFh
0017:E000h
SA7 (8KB)
0017:DFFFh
0017:C000h
SA6 (8KB)
0017:BFFFh
0017:A000h
SA5 (8KB)
0017:9FFFh
0017:8000h
SA4 (8KB)
SA3 (8KB)
SA2 (8KB)
SA1 (8KB)
SA0 (8KB)
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[20] = 1
Legend
Memory available in this area
Memory not available in this area
Document Number: 002-04602 Rev. *A
Page 30 of 86
MB91460K Series
9.4.2
86
Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s interface circuit enables
direct control of the Flash memory unit from external pins by directly linking some of the signals to General Purpose Ports. Please
see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing
using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory’s Auto Algorithms are available.
Table 1. Correspondence between MBM29LV400TC and Flash Memory Control Signals
MB91F465Kx external pins
MBM29LV400TC
External pins
FR-CPU mode
-
Comment
Flash memory
mode
Normal function
Pin number
INITX
-
INITX
62
RESET
-
FRSTX
P16_7
63
-
-
MD_2
MD_2
118
Set to ‘1’
-
-
MD_1
MD_1
117
Set to ‘1’
-
-
MD_0
MD_0
111
Set to ‘1’
RY/BY
FMCS:RDY bit
RY/BYX
P24_0
89
BYTE
Internally fixed to ’H’
BYTEX
P24_2
93
WE
WEX
P28_3
34
OE
OEX
P28_2
33
CEX
P28_1
32
ATDIN
P22_1
88
Set to ‘0’
-
EQIN
P22_0
87
Set to ‘0’
-
TESTX
P24_3
94
Set to ‘1’
-
RDYI
P24_1
92
Set to ‘0’
A-1
FA0
P19_2
55
Set to ‘0’
A0 to A7
FA1 to FA8
P27_0 to P27_7
21 to 28
FA9 to FA16
P15_0 to P15_3, P15_4,
P15_5 P21_0, P21_1
83 to 86, 10,
11, 68, 69
A16 to A18
FA17 to FA19
P21_2, P21_4, P21_5
70, 72, 73
-
FA20,FA21
P21_6, P28_0
74, 29
DQ0 to DQ7
DQ0 to DQ7
P17_0 to P17_7
58, 59, 65, 66,
67, 78, 79, 80
DQ8 to DQ15
P14_0 to P14_7
2 to 9
CE
-
A8 to A15
Internal control signal +
control via interface circuit
Internal address bus
Internal data bus
DQ8 to DQ15
Document Number: 002-04602 Rev. *A
Set to ‘1’
Page 31 of 86
MB91460K Series
9.5
Power on Sequence in Parallel Programming Mode
The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch:
86
■
■
Minimum wait time after VDD5/VDD5R power on: 2.76 ms
Minimum wait time after INITX rising: 1.0 ms
9.6
Flash Security
9.6.1
Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection
functions of the Flash Security Module:
FSV1: 0x14:8000
FSV2: 0x14:8008
9.6.2
BSV1: 0x14:8004
BSV2: 0x14:800C
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection
of the 8 Kbytes sectors.
9.6.2.1
FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes.
Table 2: Explanation of the bits in the Flash Security Vector FSV1 [31:16]
FSV1[18]
FSV1[17]
FSV1[16]
FSV1[31:19]
Write Protection Write
Protection Read Protection
Level
Flash Security Mode
set all to “0”
set to “0”
set to “0”
set to “1”
Read Protection (all device modes, except
INTVEC mode MD[2:0] “000”)
set all to “0”
set to “0”
set to “1”
set to “0”
Write Protection (all device modes, without
exception)
set all to “0”
set to “0”
set to “1”
set to “1”
Read Protection (all device modes, except
INTVEC mode MD[2:0] “000”) and Write Protection (all device modes)
set all to “0”
set to “1”
set to “0”
set to “1”
Read Protection (all device modes, except
INTVEC mode MD[2:0] “000”)
set all to “0”
set to “1”
set to “1”
set to “0”
Write Protection (all device modes, except
INTVEC mode MD[2:0] “000”)
set to “1”
Read Protection (all device modes, except
INTVEC mode MD[2:0] “000”) and Write
Protection (all device modes except INTVEC
mode MD[2:0] “000”)
set all to “0”
set to “1”
Document Number: 002-04602 Rev. *A
set to “1”
Page 32 of 86
MB91460K Series
9.6.2.2
86
FSV1 (bit15 to bit0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 Kbytes sectors. It
is only evaluated if write protection bit FSV1[17] is set.
Table 3: Explanation of the bits in the Flash Security Vector FSV1 [15:0]:
MB91F465Kx:
Enable Write Pro- Disable Write Protection
tection
FSV1 bit
Sector
Comment
FSV1[0]
-
set to “0”
set to “1”
not available
FSV1[1]
-
set to “0”
set to “1”
not available
FSV1[2]
-
set to “0”
set to “1”
not available
FSV1[3]
-
set to “0”
set to “1”
FSV1[4]
SA4
set to “0”
-
not available
FSV1[5]
SA5
set to “0”
set to “1”
FSV1[6]
SA6
set to “0”
set to “1”
FSV1[7]
SA7
set to “0”
set to “1”
FSV1[8]
-
set to “0”
set to “1”
not available
FSV1[9]
-
set to “0”
set to “1”
not available
FSV1[10]
-
set to “0”
set to “1”
not available
FSV1[11]
-
set to “0”
set to “1”
not available
FSV1[12]
-
set to “0”
set to “1”
not available
FSV1[13]
-
set to “0”
set to “1”
not available
FSV1[14]
-
set to “0”
set to “1”
not available
FSV1[15]
-
set to “0”
set to “1”
not available
write protection is mandatory!
Note: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here
sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the Flash
content or manipulate data by writing.See section “Flash access in CPU mode” for an overview about the sector organisation of the
Flash Memory.
Document Number: 002-04602 Rev. *A
Page 33 of 86
MB91460K Series
9.6.3
86
Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 Kbytes sectors. It
is only evaluated if write protection bit FSV1 [17] is set.
Table 4: Explanation of the bits in the Flash Security Vector FSV2[31:0]
MB91F465Kx:
Enable Write ProDisable Write
FSV2 bit
Sector
tection
Protection
FSV2[3:0]
-
set to “0”
set to “1”
FSV2[4]
SA12
set to “0”
set to “1”
FSV2[5]
SA13
set to “0”
set to “1”
FSV2[6]
SA14
set to “0”
set to “1”
FSV2[7]
SA15
set to “0”
set to “1”
FSV2[8]
SA16
set to “0”
set to “1”
FSV2[9]
SA17
set to “0”
set to “1”
FSV2[10]
SA18
set to “0”
set to “1”
FSV2[11]
SA19
set to “0”
set to “1”
FSV2[31:12]
-
set to “0”
set to “1”
Comment
not available
not available
Note: See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.
10. Memory Space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
■
Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access: 000H to 0FFH
Half word access: 000H to 1FFH
Word data access: 000H to 3FFH
Document Number: 002-04602 Rev. *A
Page 34 of 86
MB91460K Series
11. Memory Maps
86
11.1
MB91F465Kx
MB91F465Kx
00000000H
I/O (direct addressing area)
00000400H
I/O
00001000H
DMA
00002000H
00005000H
Flash-Cache (4 KBytes)
00006000H
00007000H
Flash memory control
00008000H
0000B000H
Boot ROM (4 Kbytes)
0000C000H
CAN
0000D000H
0002E000H
00030000H
D-RAM (0 wait, 8 Kbytes)
ID-RAM (8 Kbytes)
00032000H
00040000H
External bus area
00080000H
Flash memory (512 Kbytes)
00100000H
00148000H
External bus area
Flash memory (32 Kbytes)
00150000H
00180000H
External bus area
00500000H
External data bus
FFFFFFFFH
Note:
Access prohibited areas
Document Number: 002-04602 Rev. *A
Page 35 of 86
MB91460K Series
12. I/O Map
86
12.1
MB91F465Kx
Address
000000H
Register
0
1
2
3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
port data register
Read/write attribute
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1 becomes
the MSB side of the data.)
Note: Initial values of register bits are represented as follows:
“ 1 ”: Initial value “ 1 ”
“ 0 ”: Initial value “ 0 ”
“ X ”: Initial value “ undefined ”
“ - ”: No physical register at this location
Access is barred with an undefined data access attribute.
Document Number: 002-04602 Rev. *A
Page 36 of 86
MB91460K Series
86
Address
Register
0
1
000000H to
000008H
2
3
PDR14 [R/W]
XXXXXXXX
PDR15 [R/W]
XXXXXXXX
Block
Reserved
Reserved
00000CH
000010H
PDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXXXXXX
PDR18 [R/W]
-X---X-
PDR19 [R/W]
- X - - - XXX
000014H
PDR20 [R/W]
XXXX XXXX
PDR21 [R/W]
XXXX XXXX
PDR22 [R/W]
- - XX - - XX
Reserved
000018H
PDR24 [R/W]
XXXXXXXX
Reserved
PDR26 [R/W]
- - - - - - XX
PDR27 [R/W]
XXXXXXXX
00001CH
PDR28 [R/W]
XXXXXXXX
PDR29 [R/W]
XXXXXXXX
000020H to
00002CH
R-bus Port Data Register
Reserved
Reserved
Reserved
000030H
EIRR0 [R/W]
XXXXXXXX
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
External Interrupt (INT0 to INT7)
000034H
EIRR1 [R/W]
XXXXXXXX
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
External Interrupt
(INT8 to INT15)
000038H
DICR [R/W]
-------0
HRCL [R/W]
0 - - 11111
Reserved
Delay Interrupt
000040H
SCR00
[R/W, W]
00000000
SMR00
[R/W, W]
00000000
000044H
ESCR00 [R/W]
00000X00
ECCR00
[R/W, R, W]
-00000XX
000048H
SCR01
[R/W, W]
00000000
SMR01
[R/W, W]
00000000
00004CH
ESCR01 [R/W]
00000X00
ECCR01
[R/W, R, W]
-00000XX
000050H
SCR02
[R/W, W]
00000000
SMR02
[R/W, W]
00000000
000054H
ESCR02 [R/W]
00000X00
ECCR02
[R/W, R, W]
-00000XX
00003CH
Reserved
Document Number: 002-04602 Rev. *A
Reserved
SSR00 [R/W, R]
00001000
RDR00/TDR00
[R/W]
00000000
LIN-USART 0
Reserved
SSR01 [R/W, R]
00001000
RDR01/TDR01
[R/W]
00000000
LIN-USART 1
Reserved
SSR02 [R/W, R]
00001000
RDR02/TDR02
[R/W]
00000000
LIN-USART 2
Reserved
Page 37 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
2
3
000058H
SCR03
[R/W, W]
00000000
SMR03
[R/W, W]
00000000
SSR03 [R/W, R]
00001000
RDR03/TDR03
[R/W]
00000000
00005CH
ESCR03 [R/W]
00000X00
ECCR03
[R/W, R, W]
-00000XX
000060H
SCR04
[R/W, W]
00000000
SMR04
[R/W, W]
00000000
SSR04 [R/W, R]
00001000
RDR04/TDR04
[R/W]
00000000
000064H
ESCR04 [R/W]
00000X00
ECCR04
[R/W, R, W]
-00000XX
FSR04 [R]
- - - 00000
FCR04 [R/W]
0001 - 000
000068H
to
00007CH
LIN-USART 4 with FIFO
Reserved
000080H
BGR100 [R/W]
00000000
BGR000 [R/W]
00000000
BGR101 [R/W]
00000000
BGR001 [R/W]
00000000
000084H
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
BGR103 [R/W]
00000000
BGR003 [R/W]
00000000
000088H
BGR104 [R/W]
00000000
BGR004 [R/W]
00000000
Baudrate Generator
LIN-USART 0 to 4
Reserved
Reserved
Reserved
0000D0H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
- - - - - - 00
ITBAL0 [R/W]
00000000
0000D4H
ITMKH0 [R/W]
00 - - - - 11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
- 0000000
0000D8H
Reserved
IDAR0 [R/W]
00000000
ICCR0 [R/W]
00011111
Reserved
0000DCH
to
0000FCH
LIN-USART 3
Reserved
Reserved
00008CH
to
0000CCH
Block
Reserved
I2 C 0
Reserved
000100H
GCN10 [R/W]
00110010 00010000
Reserved
GCN20 [R/W]
- - - - 0000
PPG Control 0 to 3
000104H
GCN11 [R/W]
00110010 00010000
Reserved
GCN21 [R/W]
- - - - 0000
PPG Control 4 to 7
000108H
GCN12 [R/W]
00110010 00010000
Reserved
GCN22 [R/W]
- - - - 0000
PPG Control 8 to 11
00010CH
Document Number: 002-04602 Rev. *A
Reserved
Reserved
Page 38 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
000110H
PTMR00 [R]
11111111 11111111
000114H
PDUT00 [W]
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R]
11111111 11111111
00011CH
PDUT01 [W]
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R]
11111111 11111111
000124H
PDUT02 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR03 [R]
11111111 11111111
00012CH
PDUT03 [W]
XXXXXXXX XXXXXXXX
000130H
PTMR04 [R]
11111111 11111111
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
000150H
PTMR08 [R]
11111111 11111111
000154H
PDUT08 [W]
XXXXXXXX XXXXXXXX
000158H
PTMR09 [R]
11111111 11111111
00015CH
PDUT09 [W]
XXXXXXXX XXXXXXXX
2
3
PCSR00 [W]
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
0000000 -
PCNL00 [R/W]
000000 - 0
PCSR01 [W]
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
0000000 -
PCNL01 [R/W]
000000 - 0
PCSR02 [W]
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
0000000 -
PCNL02 [R/W]
000000 - 0
PCSR03 [W]
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
0000000 -
PCNL03 [R/W]
000000 - 0
PCSR04 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
PCSR06 [W]
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
PCSR08 [W]
XXXXXXXX XXXXXXXX
PCNH08 [R/W]
0000000 -
PCNL08 [R/W]
000000 - 0
PCSR09 [W]
XXXXXXXX XXXXXXXX
PCNH09 [R/W]
0000000 -
PCNL09 [R/W]
000000 - 0
Block
PPG 0
PPG 1
PPG 2
PPG 3
PPG 4
PPG 5
PPG 6
PPG 7
PPG 8
PPG 9
(Continued)
Document Number: 002-04602 Rev. *A
Page 39 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
000160H
to
00017CH
000180H
2
3
Reserved
ICS01 [R/W]
00000000
Reserved
Reserved
Reserved
ICS23 [R/W]
00000000
000184H
IPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
000198H,
00019CH
0001A0H
Reserved
ADERH [R/W]
00000000 00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
0001B0H
Reserved
0001B4H
Reserved
0001B8H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
0001BCH
Reserved
0001C0H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
0001C4H
Reserved
Document Number: 002-04602 Rev. *A
Output Compare 0 to 3
ADERL [R/W]
00000000 00000000
ADCS1 [R/W]
00000000
TMRLR0 [W]
XXXXXXXX XXXXXXXX
Input Capture 0 to 3
Reserved
0001A4H
0001ACH
Block
A/D Converter
Reserved
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSRH0
[R/W]
- - - 00000
TMCSRL0
[R/W]
0 - 000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSRH1
[R/W]
- - - 00000
TMCSRL1
[R/W]
0 - 000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSRH2
[R/W]
- - - 00000
TMCSRL2
[R/W]
0 - 000000
Reload Timer 0
(PPG 0, PPG 1)
Reload Timer 1
(PPG 2, PPG 3)
Reload Timer 2
(PPG 4, PPG 5)
Page 40 of 86
MB91460K Series
(Continued)
86
Address
0001C8H
Register
0
1
TMRLR3 [W]
XXXXXXXX XXXXXXXX
0001CCH
Reserved
0001D0H
TMRLR4 [W]
XXXXXXXX XXXXXXXX
0001D4H
Reserved
0001D8H
TMRLR5 [W]
XXXXXXXX XXXXXXXX
0001DCH
Reserved
0001E0H
TMRLR6 [W]
XXXXXXXX XXXXXXXX
0001E4H
Reserved
0001E8H
TMRLR7 [W]
XXXXXXXX XXXXXXXX
2
3
TMR3 [R]
XXXXXXXX XXXXXXXX
TMCSRH3
[R/W]
- - - 00000
TMCSRL3
[R/W]
0 - 000000
TMR4 [R]
XXXXXXXX XXXXXXXX
TMCSRH4
[R/W]
- - - 00000
TMCSRL4
[R/W]
0 - 000000
TMR5 [R]
XXXXXXXX XXXXXXXX
TMCSRH5
[R/W]
- - - 00000
TMCSRL5
[R/W]
0 - 000000
TMR6 [R]
XXXXXXXX XXXXXXXX
TMCSRH6
[R/W]
- - - 00000
TMCSRL6
[R/W]
0 - 000000
TMR7 [R]
XXXXXXXX XXXXXXXX
TMCSRL7
[R/W]
0 - 000000
Block
Reload Timer 3
(PPG 6, PPG 7)
Reload Timer 4
(PPG 8, PPG 9)
Reload Timer 5
(PPG 10, PPG 11)
Reload Timer 6
(PPG 12, PPG 13)
Reload Timer 7
(PPG 14, PPG 15)
(ADC)
0001ECH
Reserved
TMCSRH7
[R/W]
- - - 00000
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS0 [R/W]
00000000
Free Running Timer 0
(ICU 0, ICU 1)
0001F4H
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
00000000
Free Running Timer 1
(ICU 2, ICU 3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
00000000
Free Running Timer 2
(OCU 0, OCU1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
00000000
Free Running Timer 3
(OCU 2, OCU3)
Document Number: 002-04602 Rev. *A
Page 41 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
2
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
00 - - 0000
DMAC
Reserved
Reserved
Block
Reserved
000244H
to
0002CCH
0002D0H
3
ICS045 [R/W]
00000000
Reserved
Reserved
ICS67 [R/W]
00000000
0002D4H
IPCP4 [R]
XXXXXXXX XXXXXXXX
IPCP5 [R]
XXXXXXXX XXXXXXXX
0002D8H
IPCP6 [R]
XXXXXXXX XXXXXXXX
IPCP7 [R]
XXXXXXXX XXXXXXXX
0002DCH
OCS45 [R/W]
- - - 0 - - 00 0000 - - 00
OCS67 [R/W]
- - -0 - -00 0000 - -00
0002E0H
OCCP4 [R/W]
XXXXXXXX XXXXXXXX
OCCP5 [R/W]
XXXXXXXX XXXXXXXX
0002E4H
OCCP6 [R/W]
XXXXXXXX XXXXXXXX
OCCP7 [R/W]
XXXXXXXX XXXXXXXX
0002E8H
to
0002ECH
Document Number: 002-04602 Rev. *A
Reserved
Input Capture 4 to 7
Output Compare 4 to 7
Reserved
Page 42 of 86
MB91460K Series
Address
86
Register
0
1
2
3
Block
0002F0H
TCDT4 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS4 [R/W]
00000000
Free Running Timer 4
(ICU4, ICU5)
0002F4H
TCDT5 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS5 [R/W]
00000000
Free Running Timer 5
(ICU6, ICU7)
0002F8H
TCDT6 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS6 [R/W]
00000000
Free Running Timer 6
(OCU4, OCU5)
0002FCH
TCDT7 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS7 [R/W]
00000000
Free Running Timer 7
(OCU6, OCU7)
000300H
to
00038CH
000390H
Reserved
ROMS [R]
11111111 01000011
Reserved
Reserved
000394H
to
0003ECH
Reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
Document Number: 002-04602 Rev. *A
ROM Select Register
Reserved
Bit Search Module
Reserved
Page 43 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
2
3
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
ICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
000474H
ICR52 [R/W]
---11111
ICR53 [R/W]
---11111
ICR54 [R/W]
---11111
ICR55 [R/W]
---11111
000478H
ICR56 [R/W]
---11111
ICR57 [R/W]
---11111
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CH
ICR60 [R/W]
---11111
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
000480H
RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
X0000X00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
00000000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
000488H
Document Number: 002-04602 Rev. *A
Reserved
Block
Interrupt
Controller
Clock
Control
Reserved
Page 44 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
2
3
00048CH
PLLDIVM [R/W]
- - - 00000
PLLDIVN [R/W]
- - 000000
PLLDIVG [R/W]
- - - - 0000
PLLMULG [W]
00000000
000490H
PLLCTRL [R/W]
- - - - 0000
000494H
OSCC1 [R/W]
- - - - - 010
000498H
PORTEN [R/W]
- - - - - - 00
0004A0H
Reserved
0004A4H
Reserved
0004A8H
WTHR [R/W]
- - - 00000
WTMR [R/W]
- - 000000
WTSR [R/W]
- - 000000
Reserved
0004ACH
CSVTR [R/W]
- - - 00010
CSVCR [R/W]
00011100
CSCFG [R/W]
0X000000
Reserved
Block
PLL Interface
Reserved
OSCS1 [R/W]
00001111
OSCC2 [R/W]
- - - - - 010
OSCS2 [R/W]
00001111
Reserved
WTCER [R/W]
- - - - - - 00
Main/Sub Oscillator Control
Port Input Enable Control
WTCR [R/W]
00000000 000 - 00 - 0
WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
0004B0H
CUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
CMT1 [R/W]
00000000 1 - - - 0000
CMCR [R/W]
- 001 - - 00
Reserved
CMT2 [R/W]
- - 000000 - - 000000
Real Time Clock (Watch Timer)
Clock Supervisor / Selector
Calibration of Sub Clock
Clock Modulator
0004C0H
CANPRE [R/W]
0 - - - 0000
CANCKD [R/W]
---0----
0004C4H
LVSEL [R/W]
00000111
LVDET [R/W]
0000 0 - 00
HWWDE [R/W]
- - - - - - 00
HWWD [R/W, W]
00011000
Low Voltage Detection /
Hardware Watchdog
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
00 - - - 000
WPCRL [R/W]
- - - - - - 00
Main/Sub Oscillation
Stabilisation Timer
0004CCH
OSCCR [R/W]
-------0
Reserved
REGSEL [R/W]
- - 000110
REGCTR [R/W]
- - - 0 - - 00
Main Oscillation Standby Control
/ Main/Sub Regulator Control
0004D0H
to
000D08H
Document Number: 002-04602 Rev. *A
Reserved
Reserved
CAN Clock Control
Reserved
Page 45 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
Reserved
000D0CH
2
3
PDRD14 [R]
XXXXXXXX
PDRD15 [R]
XXXXXXXX
000D10H
PDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXXXXXX
PDRD18 [R]
-X---X-
PDRD19 [R]
- X - - - XXX
000D14H
PDRD20 [R]
XXXX XXXX
PDRD21 [R]
XXXX XXXX
PDRD22 [R]
- - XX - - XX
Reserved
000D18H
PDRD24 [R]
XXXXXXXX
Reserved
PDRD26 [R]
- - - - - - XX
PDRD27 [R]
XXXXXXXX
000D1CH
PDRD28 [R]
XXXXXXXX
PDRD29 [R]
XXXXXXXX
000D20H
to
000D48H
000D4CH
Reserved
Reserved
DDR14 [R/W]
00000000
DDR15 [R/W]
00000000
000D50H
DDR16 [R/W]
00000000
DDR17 [R/W]
00000000
DDR18 [R/W]
-0---0-
DDR19 [R/W]
- 0 - - - 000
000D54H
DDR20 [R/W]
0000 0000
DDR21 [R/W]
0000 0000
DDR22 [R/W]
- - 00 - - 00
Reserved
000D58H
DDR24 [R/W]
00000000
Reserved
DDR26 [R/W]
- - - - - - 00
DDR27 [R/W]
00000000
000D5CH
DDR28 [R/W]
00000000
DDR29 [R/W]
00000000
000D8CH
Reserved
Reserved
PFR14 [R/W]
00000000
PFR15 [R/W]
00000000
000D90H
PFR16 [R/W]
0 - - - 0000
PFR17 [R/W]
00000000
PFR18 [R/W]
-0---0-
PFR19 [R/W]
- 0 - - - 000
000D94H
PFR20 [R/W]
- 000 - 000
PFR21 [R/W]
- 000 - 000
PFR22 [R/W]
- - 00 - - 00
Reserved
000D98H
PFR24 [R/W]
00000000
Reserved
PFR26 [R/W]
- - - - - - 00
PFR27 [R/W]
00000000
000D9CH
PFR28 [R/W]
00000000
PFR29 [R/W]
00000000
Document Number: 002-04602 Rev. *A
R-bus Port Direction Register
Reserved
Reserved
000DA0H
to
000DC8H
R-bus Port Data Direct Read
Register
Reserved
Reserved
000D60H
to
000D88H
Block
Reserved
R-bus Port Function Register
Reserved
Reserved
Page 46 of 86
MB91460K Series
(Continued)
86
Address
000DCCH
Register
0
1
Reserved
2
3
EPFR14 [R/W]
00000000
EPFR15 [R/W]
00000000
000DD0H
EPFR16 [R/W]
0-------
EPFR17 [R/W]
--------
EPFR18 [R/W]
-0----0-
EPFR19 [R/W]
-0---0--
000DD4H
EPFR20 [R/W]
-0---0--
EPFR21 [R/W]
-0---0--
EPFR22 [R/W]
--------
Reserved
000DD8H
EPFR24 [R/W]
--------
Reserved
EPFR26 [R/W]
- - - - - - 00
EPFR27 [R/W]
00000000
000DDCH
EPFR28 [R/W]
--------
EPFR29 [R/W]
--------
000DE0H
to
000E08H
000E0CH
Reserved
PODR14 [R/W]
00000000
PODR15 [R/W]
00000000
000E10H
PODR16 [R/W]
00000000
PODR17 [R/W]
00000000
PODR18 [R/W]
-0---0-
PODR19 [R/W]
- 0 - - - 000
000E14H
PODR20 [R/W]
0000 0000
PODR21 [R/W]
0000 0000
PODR22 [R/W]
- - 00 - - 00
Reserved
000E18H
PODR24 [R/W]
00000000
Reserved
PODR26 [R/W]
- - - - - - 00
PODR27 [R/W]
00000000
000E1CH
PODR28 [R/W]
00000000
PODR29 [R/W]
00000000
000E20H
to
000E48H
000E4CH
Reserved
PILR14 [R/W]
00000000
PILR15 [R/W]
00000000
000E50H
PILR16 [R/W]
00000000
PILR17 [R/W]
00000000
PILR18 [R/W]
-0---0-
PILR19 [R/W]
- 0 - - - 000
000E54H
PILR20 [R/W]
0000 0000
PILR21 [R/W]
0000 0000
PILR22 [R/W]
- - 00 - - 00
Reserved
000E58H
PILR24 [R/W]
00000000
Reserved
PILR26 [R/W]
- - - - - - 00
PILR27 [R/W]
00000000
000E5CH
PILR28 [R/W]
00000000
PILR29 [R/W]
00000000
000E60H
to
000E88H
Document Number: 002-04602 Rev. *A
R-bus Port Output Drive Select
Register
Reserved
Reserved
Reserved
R-bus Expansion Port Function
Register
Reserved
Reserved
Reserved
Block
Reserved
R-bus Pin Input Level Select
Register
Reserved
Reserved
Page 47 of 86
MB91460K Series
(Continued)
86
Address
000E8CH
Register
0
1
Reserved
2
3
EPILR14 [R/W]
00000000
EPILR15 [R/W]
00000000
000E90H
EPILR16 [R/W]
00000000
EPILR17 [R/W]
00000000
EPILR18 [R/W]
-0---0-
EPILR19 [R/W]
- 0 - - - 000
000E94H
EPILR20 [R/W]
0000 0000
EPILR21 [R/W]
0000 0000
EPILR22 [R/W]
- - 00 - - 00
Reserved
000E98H
EPILR24 [R/W]
00000000
Reserved
EPILR26 [R/W]
- - - - - - 00
EPILR27 [R/W]
00000000
000E9CH
EPILR28 [R/W]
00000000
EPILR29 [R/W]
00000000
000EA0H
to
000EC8H
000ECCH
Reserved
PPER14 [R/W]
00000000
PPER15 [R/W]
00000000
000ED0H
PPER16 [R/W]
00000000
PPER17 [R/W]
00000000
PPER18 [R/W]
-0---0-
PPER19 [R/W]
- 0 - - - 000
000ED4H
PPER20 [R/W]
0000 0000
PPER21 [R/W]
0000 0000
PPER22 [R/W]
- - 00 - - 00
Reserved
000ED8H
PPER24 [R/W]
00000000
Reserved
PPER26 [R/W]
- - - - - - 00
PPER27 [R/W]
00000000
000EDCH
PPER28 [R/W]
00000000
PPER29 [R/W]
00000000
000EE0H
to
000F08H
000F0CH
Reserved
PPCR14 [R/W]
00000000
PPCR15 [R/W]
00000000
000F10H
PPCR16 [R/W]
00000000
PPCR17 [R/W]
00000000
PPCR18 [R/W]
-0---0-
PPCR19 [R/W]
- 0 - - - 000
000F14H
PPCR20 [R/W]
0000 0000
PPCR21 [R/W]
0000 0000
PPCR22 [R/W]
- - 00 - - 00
Reserved
000F18H
PPCR24 [R/W]
00000000
Reserved
PPCR26 [R/W]
- - - - - - 00
PPCR27 [R/W]
00000000
000F1CH
PPCR28 [R/W]
00000000
PPCR29 [R/W]
00000000
000F20H
to
000F3CH
Document Number: 002-04602 Rev. *A
R-bus Port
Pull-Up/Down Enable
Register
Reserved
Reserved
Reserved
R-bus Expansion
Port Input Level Select
Register
Reserved
Reserved
Reserved
Block
Reserved
R-bus Port Pull-Up/Down Control
Register
Reserved
Reserved
Page 48 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
2
3
Block
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
004FFCH
Reserved
Reserved
005000H
to
005FFCH
MB91F465Kx Instruction RAM/Flash Cache size is 4KB
Instruction RAM / Flash Cache
006000H
to
006FFCH
reserved
reserved
007000H
007004H
FMCS [R/W]
01101000
FMCR [R]
- - - 00000
FMWT [R/W]
11111111 11111111
FCHCR [R/W]
- - - - - - 00 10000011
FMWT2 [R]
- 001 - - - -
007008H
FMAC [R]
00000000 00000000 00000000 00000000
00700CH
FCHA0 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
Document Number: 002-04602 Rev. *A
DMAC
FMPS [R/W]
- - - - - 000
Flash Memory/F-Cache/
I-RAM Control Register
Flash-cache Noncacheable area setting Register
Page 49 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
2
3
Block
007014H
to
007FFCH
Reserved
Reserved
008000H
to
00BFFCH
MB91F465Kx Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH
(instruction access is 1 wait cycle, data access is 1 wait cycle)
Boot ROM area
00C000H
to
00C3FCH
Reserved
Reserved
00C400H
CTRLR4 [R/W]
00000000 00000001
STATR4 [R/W]
00000000 00000000
00C404H
ERRCNT4 [R]
00000000 00000000
BTR4 [R/W]
00100011 00000001
00C408H
INTR4 [R]
00000000 00000000
TESTR4 [R/W]
00000000 X0000000
00C40CH
BRPE4 [R/W]
00000000 00000000
Reserved
00C410H
IF1CREQ4 [R/W]
00000000 00000001
IF1CMSK4 [R/W]
00000000 00000000
00C414H
IF1MSK24 [R/W]
11111111 11111111
IF1MSK14 [R/W]
11111111 11111111
00C418H
IF1ARB24 [R/W]
00000000 00000000
IF1ARB14 [R/W]
00000000 00000000
00C41CH
IF1MCTR4 [R/W]
00000000 00000000
Reserved
00C420H
IF1DTA14 [R/W]
00000000 00000000
IF1DTA24 [R/W]
00000000 00000000
00C424H
IF1DTB14 [R/W]
00000000 00000000
IF1DTB24 [R/W]
00000000 00000000
00C428H
to
00C42CH
CAN 4 Control Register
CAN 4 IF 1 Register
Reserved
00C430H
IF1DTA24 [R/W]
00000000 00000000
IF1DTA14 [R/W]
00000000 00000000
00C434H
IF1DTB24 [R/W]
00000000 00000000
IF1DTB14 [R/W]
00000000 00000000
00C438H,
00C43CH
Reserved
(Continued)
Document Number: 002-04602 Rev. *A
Page 50 of 86
MB91460K Series
Address
86
Register
0
1
2
3
00C440H
IF2CREQ4 [R/W]
00000000 00000001
IF2CMSK4 [R/W]
00000000 00000000
00C444H
IF2MSK24 [R/W]
11111111 11111111
IF2MSK14 [R/W]
11111111 11111111
00C448H
IF2ARB24 [R/W]
00000000 00000000
IF2ARB14 [R/W]
00000000 00000000
00C44CH
IF2MCTR4 [R/W]
00000000 00000000
Reserved
00C450H
IF2DTA14 [R/W]
00000000 00000000
IF2DTA24 [R/W]
00000000 00000000
00C454H
IF2DTB14 [R/W]
00000000 00000000
IF2DTB24 [R/W]
00000000 00000000
00C458H,
00C45CH
IF2DTA24 [R/W]
00000000 00000000
IF2DTA14 [R/W]
00000000 00000000
00C464H
IF2DTB24 [R/W]
00000000 00000000
IF2DTB14 [R/W]
00000000 00000000
00C468H
to
00C47CH
Reserved
TREQR24 [R]
00000000 00000000
00C484H
to
00C48CH
00C490H
NEWDT24 [R]
00000000 00000000
NEWDT14 [R]
00000000 00000000
CAN 4 Status Flags
Reserved
INTPND24 [R]
00000000 00000000
00C4A4H
to
00C4ACH
00C4B0H
TREQR14 [R]
00000000 00000000
Reserved
00C494H
to
00C49CH
00C4A0H
CAN 4
IF 2 Register
Reserved
00C460H
00C480H
Block
INTPND14 [R]
00000000 00000000
Reserved
MSGVAL24 [R]
00000000 00000000
00C4B4H
to
00EFFCH
Document Number: 002-04602 Rev. *A
MSGVAL14 [R]
00000000 00000000
Reserved
Reserved
Page 51 of 86
MB91460K Series
(Continued)
86
Address
Register
0
1
2
3
Block
020000H
to
02FFFCH
MB91F465Kx D-RAM size is 8 Kbytes : 02E000H to 02FFFCH
(data access is 0 wait cycles)
D-RAM area
030000H
to
03FFFCH
MB91F465Kx ID-RAM size is 8 Kbytes : 030000H to 031FFCH
(instruction access is 0 wait cycles, data access is 1 wait cycle)
ID-RAM area
1. depends on the number of available CAN channels
2. ACR0 [11 : 10] depends on bus width setting in Mode vector fetch information
3. TCR [3 : 0] INIT value 0000, keeps value after RST
Document Number: 002-04602 Rev. *A
Page 52 of 86
MB91460K Series
12.2
86
Flash Memory and External Bus Area
12.2.1 MB91F465Kx
32bit read mode
16bit read/write
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
0
1
2
3
4
5
6
7
Block
040000H
to
05FFF8H
reserved
reserved
ROMS0
060000H
to
07FFF8H
reserved
reserved
ROMS1
080000H
to
09FFF8H
SA12 (64KB)
SA13 (64KB)
ROMS2
0A0000H
to
0BFFF8H
SA14 (64KB)
SA15 (64KB)
ROMS3
0C0000H
to
0DFFF8H
SA16 (64KB)
SA17 (64KB)
ROMS4
SA18 (64KB)
FMV [R]
06 00 00 00H
SA19 (64KB)
FRV [R]
00 00 BF F8H
ROMS5
100000H
to
11FFF8H
reserved
reserved
120000H
to
13FFF8H
reserved
reserved
140000H
to
143FF8H
reserved
reserved
144000H
to
17FF8H
reserved
reserved
148000H
to
14BFF8H
SA4 (8KB)
SA5 (8KB)
14C000H
to
14FFF8H
SA6 (8KB)
SA7 (8KB)
0E0000H
to
0FFFF0H
0FFFF8H
ROMS6
150000H
to
17FFF8H
Document Number: 002-04602 Rev. *A
ROMS7
Reserved
Page 53 of 86
MB91460K Series
32bit read mode
16bit read/write
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
86
Address
dat[31:16]
dat[15:0]
Register
0
1
2
3
4
5
6
7
Block
180000H
to
1BFFF8H
ROMS8
1C0000H
to
1FFFF8H
ROMS9
200000H
to
27FFF8H
ROMS10
280000H
to
2FFFF8H
ROMS11
300000H
to
37FFF8H
Reserved
ROMS12
380000H
to
3FFFF8H
ROMS13
400000H
to
47FFF8H
ROMS14
480000H
to
4FFFF8H
ROMS15
Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown
above will be read.
Document Number: 002-04602 Rev. *A
Page 54 of 86
MB91460K Series
13. Interrupt Vector Table
86
Interrupt
Interrupt
number
Interrupt level [1]
Interrupt vector [2]
DMA
Resource
number
Decimal
Hexa-de
cimal
Setting
Register
Register
address
Offset
Default Vector
address
Reset
0
00
-
-
3FCH
000FFFFCH
-
Mode vector
1
01
-
-
3F8H
000FFFF8H
-
System reserved
2
02
-
-
3F4H
000FFFF4H
-
System reserved
3
03
-
-
3F0H
000FFFF0H
-
System reserved
4
04
-
-
3ECH
000FFFECH
-
CPU supervisor mode
(INT #5 instruction) [5]
5
05
-
-
3E8H
000FFFE8H
-
Memory Protection exception [5]
6
06
-
-
3E4H
000FFFE4H
-
System reserved
7
07
-
-
3E0H
000FFFE0H
-
System reserved
8
08
-
-
3DCH
000FFFDCH
-
System reserved
9
09
-
-
3D8H
000FFFD8H
-
System reserved
10
0A
-
-
3D4H
000FFFD4H
-
System reserved
11
0B
-
-
3D0H
000FFFD0H
-
System reserved
12
0C
-
-
3CCH
000FFFCCH
-
System reserved
13
0D
-
-
3C8H
000FFFC8H
-
Undefined instruction exception
14
0E
-
-
3C4H
000FFFC4H
-
NMI request
15
0F
External Interrupt 0
16
10
External Interrupt 1
17
11
External Interrupt 2
18
12
External Interrupt 3
19
13
External Interrupt 4
20
14
External Interrupt 5
21
15
External Interrupt 6
22
16
External Interrupt 7
23
17
Reserved
24
18
Reserved
25
19
Reserved
26
1A
Reserved
27
1B
External Interrupt 12
28
1C
Reserved
29
1D
External Interrupt 14
30
1E
Reserved
31
1F
Document Number: 002-04602 Rev. *A
FH fixed
ICR00
440H
ICR01
441H
ICR02
442H
ICR03
443H
ICR04
444H
ICR05
445H
ICR06
446H
ICR07
447H
3C0H
000FFFC0H
-
3BCH
000FFFBCH
0, 16
3B8H
000FFFB8H
1, 17
3B4H
000FFFB4H
2, 18
3B0H
000FFFB0H
3, 19
3ACH
000FFFACH
20
3A8H
000FFFA8H
21
3A4H
000FFFA4H
22
3A0H
000FFFA0H
23
39CH
000FFF9CH
-
398H
000FFF98H
-
394H
000FFF94H
-
390H
000FFF90H
-
38CH
000FFF8CH
-
388H
000FFF88H
-
384H
000FFF84H
-
380H
000FFF80H
-
Page 55 of 86
MB91460K Series
Interrupt
86
Interrupt
number
Decimal
Hexa-de
cimal
32
20
Reload Timer 0
Reload Timer 1
33
21
Reload Timer 2
34
22
Reload Timer 3
35
23
Reload Timer 4
36
24
Reload Timer 5
37
25
Reload Timer 6
38
26
Reload Timer 7
39
27
Free Run Timer 0
40
28
Free Run Timer 1
41
29
Free Run Timer 2
42
2A
Free Run Timer 3
43
2B
Free Run Timer 4
44
2C
Free Run Timer 5
45
2D
Free Run Timer 6
46
2E
Free Run Timer 7
47
2F
Reserved
48
30
Reserved
49
31
Reserved
50
32
Reserved
51
33
CAN 4
52
34
Reserved
53
35
LIN-USART 0 RX
54
36
LIN-USART 0 TX
55
37
LIN-USART 1 RX
56
38
LIN-USART 1 TX
57
39
LIN-USART 2 RX
58
3A
LIN-USART 2 TX
59
3B
LIN-USART 3 RX
60
3C
LIN-USART 3 TX
61
3D
System reserved
62
3E
Delayed Interrupt
63
3F
Document Number: 002-04602 Rev. *A
Interrupt level [1]
Setting
Register
Register
address
ICR08
448H
ICR09
449H
ICR10
44AH
ICR11
44BH
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
ICR20
454H
ICR21
455H
ICR22
456H
ICR23 [3]
457H
Interrupt vector [2]
DMA
Resource
number
Offset
Default Vector
address
37CH
000FFF7CH
4, 32
378H
000FFF78H
5, 33
374H
000FFF74H
34
370H
000FFF70H
35
36CH
000FFF6CH
36
368H
000FFF68H
37
364H
000FFF64H
38
360H
000FFF60H
39
35CH
000FFF5CH
40
358H
000FFF58H
41
354H
000FFF54H
42
350H
000FFF50H
43
34CH
000FFF4CH
44
348H
000FFF48H
45
344H
000FFF44H
46
340H
000FFF40H
47
33CH
000FFF3CH
-
338H
000FFF38H
-
334H
000FFF34H
-
330H
000FFF30H
-
32CH
000FFF2CH
-
328H
000FFF28H
-
324H
000FFF24H
6, 48
320H
000FFF20H
7, 49
31CH
000FFF1CH
8, 50
318H
000FFF18H
9, 51
314H
000FFF14H
52
310H
000FFF10H
53
30CH
000FFF0CH
54
308H
000FFF08H
55
304H
000FFF04H
-
300H
000FFF00H
-
Page 56 of 86
MB91460K Series
86
Interrupt
Interrupt
number
Decimal
Hexa-de
cimal
64
40
System reserved [4]
[4]
65
41
LIN-USART (FIFO) 4 RX
66
42
LIN-USART (FIFO) 4 TX
67
43
Reserved
68
44
System reserved
Reserved
69
45
Reserved
70
46
Reserved
71
47
Reserved
72
48
Reserved
73
49
I2 C 0
74
4A
Reserved
75
4B
Reserved
76
4C
Reserved
77
4D
Reserved
78
4E
Reserved
79
4F
Reserved
80
50
Reserved
81
51
Reserved
82
52
Reserved
83
53
Reserved
84
54
Reserved
85
55
Reserved
86
56
Reserved
87
57
Reserved
88
58
Reserved
89
59
Reserved
90
5A
Reserved
91
5B
Input Capture 0
92
5C
Input Capture 1
93
5D
Input Capture 2
94
5E
Input Capture 3
95
5F
Document Number: 002-04602 Rev. *A
Interrupt level [1]
Setting
Register
Register
address
(ICR24)
(458H)
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
ICR36
464H
ICR37
465H
ICR38
466H
ICR39
467H
Interrupt vector [2]
DMA
Resource
number
Offset
Default Vector
address
2FCH
000FFEFCH
2F8H
000FFEF8H
-
2F4H
000FFEF4H
10, 56
2F0H
000FFEF0H
11, 57
2ECH
000FFEECH
12, 58
-
2E8H
000FFEE8H
13, 59
2E4H
000FFEE4H
60
2E0H
000FFEE0H
61
2DCH
000FFEDCH
62
2D8H
000FFED8H
63
2D4H
000FFED4H
-
2D0H
000FFED0H
-
2CCH
000FFECCH
64
2C8H
000FFEC8H
65
2C4H
000FFEC4H
66
2C0H
000FFEC0H
67
2BCH
000FFEBCH
68
2B8H
000FFEB8H
69
2B4H
000FFEB4H
70
2B0H
000FFEB0H
71
2ACH
000FFEACH
72
2A8H
000FFEA8H
73
2A4H
000FFEA4H
74
2A0H
000FFEA0H
75
29CH
000FFE9CH
76
298H
000FFE98H
77
294H
000FFE94H
78
290H
000FFE90H
79
28CH
000FFE8CH
80
288H
000FFE88H
81
284H
000FFE84H
82
280H
000FFE80H
83
Page 57 of 86
MB91460K Series
86
Interrupt
Interrupt
number
Decimal
Hexa-de
cimal
Input Capture 4
96
60
Input Capture 5
97
61
Input Capture 6
98
62
Input Capture 7
99
63
Output Compare 0
100
64
Output Compare 1
101
65
Output Compare 2
102
66
Output Compare 3
103
67
Output Compare 4
104
68
Output Compare 5
105
69
Output Compare 6
106
6A
Output Compare 7
107
6B
Reserved
108
6C
Reserved
109
6D
System reserved
110
6E
System reserved
111
6F
PPG0
112
70
PPG1
113
71
PPG2
114
72
PPG3
115
73
PPG4
116
74
PPG5
117
75
PPG6
118
76
PPG7
119
77
PPG8
120
78
PPG9
121
79
PPG10
122
7A
PPG11
123
7B
Reserved
124
7C
Reserved
125
7D
Reserved
126
7E
Reserved
127
7F
Document Number: 002-04602 Rev. *A
Interrupt level [1]
Setting
Register
Register
address
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47 [3]
46FH
ICR48
470H
ICR49
471H
ICR50
472H
ICR51
473H
ICR52
474H
ICR53
475H
ICR54
476H
ICR55
477H
Interrupt vector [2]
DMA
Resource
number
Offset
Default Vector
address
27CH
000FFE7CH
84
278H
000FFE78H
85
274H
000FFE74H
86
270H
000FFE70H
87
26CH
000FFE6CH
88
268H
000FFE68H
89
264H
000FFE64H
90
260H
000FFE60H
91
25CH
000FFE5CH
92
258H
000FFE58H
93
254H
000FFE54H
94
250H
000FFE50H
95
24CH
000FFE4CH
-
248H
000FFE48H
-
244H
000FFE44H
-
240H
000FFE40H
-
23CH
000FFE3CH
15, 96
238H
000FFE38H
97
234H
000FFE34H
98
230H
000FFE30H
99
22CH
000FFE2CH
100
228H
000FFE28H
101
224H
000FFE24H
102
220H
000FFE20H
103
21CH
000FFE1CH
104
218H
000FFE18H
105
214H
000FFE14H
106
210H
000FFE10H
107
20CH
000FFE0CH
108
208H
000FFE08H
109
204H
000FFE04H
110
200H
000FFE00H
111
Page 58 of 86
MB91460K Series
86
Interrupt
Interrupt
number
Decimal Hexa-de
cimal
Reserved
128
80
Reserved
129
81
Reserved
130
82
Reserved
131
83
Real Time Clock
132
84
Calibration Unit
133
85
A/D Converter 0
134
86
Reserved
135
87
Reserved
136
88
Reserved
137
89
Low Voltage Detection
138
8A
Reserved
139
8B
Timebase Overflow
140
8C
PLL Clock Gear
141
8D
DMA Controller
142
8E
Main/Sub OSC stability wait
143
8F
Security vector
144
Used by the INT instruction.
145
to
255
Interrupt level [1]
Setting
Register
Register
address
ICR56
478H
ICR57
479H
ICR58
47AH
ICR59
47BH
ICR60
47CH
ICR61
47DH
ICR62
47EH
Interrupt vector [2]
DMA
Resource
number
Offset
Default Vector
address
1FCH
000FFDFCH
-
1F8H
000FFDF8H
-
1F4H
000FFDF4H
-
1F0H
000FFDF0H
-
1ECH
000FFDECH
-
1E8H
000FFDE8H
-
1E4H
000FFDE4H
14, 112
1E0H
000FFDE0H
-
1DCH
000FFDDCH
-
1D8H
000FFDD8H
-
1D4H
000FFDD4H
-
1D0H
000FFDD0H
-
1CCH
000FFDCCH
-
1C8H
000FFDC8H
-
1C4H
000FFDC4H
-
1C0H
000FFDC0H
-
ICR63
47FH
90
-
-
1BCH
000FFDBCH
-
91
to
FF
-
-
1B8H to
000H
000FFDB8H
to
000FFC00H
-
1. The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is
provided for each interrupt request.
2. The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) .
The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is
initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed.
3. ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0])
4. Used by REALOS
5. Memory Protection Unit (MPU) support
Document Number: 002-04602 Rev. *A
Page 59 of 86
MB91460K Series
14. Recommended Settings
86
14.1
PLL and Clockgear settings
Please note that for MB91F465Kx, the core base clock frequencies are valid in the 1.8V operation mode of the Main regulator and Flash.
Table 5: Recommended PLL divider and clockgear settings
PLL
Input (CLK)
[MHz]
Frequency Parameter
Clockgear Parameter
PLL
Output (X)
[MHz]
Core Base
Clock
[MHz]
Remarks
DIVM
DIVN
DIVG
MULG
MULG
4
2
25
16
24
200
100
[1]
4
2
24
16
24
192
96
[1]
4
2
23
16
24
184
92
[1]
4
2
22
16
24
176
88
[1]
4
2
21
16
20
168
84
[1]
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
1. This setting is not possible at MB91F465Kx
Document Number: 002-04602 Rev. *A
Page 60 of 86
MB91460K Series
14.2
86
Clock Modulator Settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 48MHz.
Base clock frequencies above 48 MHz are not allowed on MB91F465Kx.
The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings should be set according
to base clock frequency.
Table 6: Clock Modulator settings, frequency range and supported supply voltage
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
3
026F
48
44.2
52.5
1
5
02AE
48
41.8
56.4
1
7
02ED
48
39.6
60.9
1
9
032C
48
37.7
66.1
1
11
036B
48
35.9
72.3
1
13
03AA
48
34.3
79.9
1
15
03E9
48
32.8
89.1
2
3
046E
48
41.8
56.4
2
5
04AC
48
37.7
66.1
2
7
04EA
48
34.3
79.9
3
3
066D
48
39.6
60.9
3
5
06AA
48
34.3
79.9
4
3
086C
48
37.7
66.1
5
3
0A6B
48
35.9
72.3
6
3
0C6A
48
34.3
79.9
7
3
0E69
48
32.8
89.1
1
3
026F
44
40.6
48.1
1
5
02AE
44
38.4
51.6
1
7
02ED
44
36.4
55.7
1
9
032C
44
34.6
60.4
1
11
036B
44
33
66.1
1
13
03AA
44
31.5
73
1
15
03E9
44
30.1
81.4
2
3
046E
44
38.4
51.6
2
5
04AC
44
34.6
60.4
2
7
04EA
44
31.5
73
2
9
0528
44
28.9
92.1
Document Number: 002-04602 Rev. *A
Remarks
[1]
[1]
[1]
[1]
Page 61 of 86
MB91460K Series
86
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
3
3
066D
44
36.4
55.7
3
5
06AA
44
31.5
73
4
3
086C
44
34.6
60.4
4
5
08A8
44
28.9
92.1
5
3
0A6B
44
33
66.1
6
3
0C6A
44
31.5
73
7
3
0E69
44
30.1
81.4
[1]
8
3
1068
44
28.9
92.1
[1]
1
3
026F
40
37
43.6
1
5
02AE
40
34.9
46.8
1
7
02ED
40
33.1
50.5
1
9
032C
40
31.5
54.8
1
11
036B
40
30
59.9
1
13
03AA
40
28.7
66.1
1
15
03E9
40
27.4
73.7
2
3
046E
40
34.9
46.8
2
5
04AC
40
31.5
54.8
2
7
04EA
40
28.7
66.1
2
9
0528
40
26.3
83.3
3
3
066D
40
33.1
50.5
3
5
06AA
40
28.7
66.1
3
7
06E7
40
25.3
95.8
4
3
086C
40
31.5
54.8
4
5
08A8
40
26.3
83.3
5
3
0A6B
40
30
59.9
6
3
0C6A
40
28.7
66.1
7
3
0E69
40
27.4
73.7
8
3
1068
40
26.3
83.3
[1]
9
3
1267
40
25.3
95.8
[1]
1
3
026F
36
33.3
39.2
1
5
02AE
36
31.5
42
1
7
02ED
36
29.9
45.3
1
9
032C
36
28.4
49.2
1
11
036B
36
27.1
53.8
1
13
03AA
36
25.8
59.3
Document Number: 002-04602 Rev. *A
Remarks
[1]
[1]
[1]
[1]
Page 62 of 86
MB91460K Series
86
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
15
03E9
36
24.7
66.1
2
3
046E
36
31.5
42
2
5
04AC
36
28.4
49.2
2
7
04EA
36
25.8
59.3
2
9
0528
36
23.7
74.7
3
3
066D
36
29.9
45.3
3
5
06AA
36
25.8
59.3
3
7
06E7
36
22.8
85.8
4
3
086C
36
28.4
49.2
4
5
08A8
36
23.7
74.7
5
3
0A6B
36
27.1
53.8
6
3
0C6A
36
25.8
59.3
7
3
0E69
36
24.7
66.1
8
3
1068
36
23.7
74.7
9
3
1267
36
22.8
85.8
1
3
026F
32
29.7
34.7
1
5
02AE
32
28
37.3
1
7
02ED
32
26.6
40.2
1
9
032C
32
25.3
43.6
1
11
036B
32
24.1
47.7
1
13
03AA
32
23
52.5
1
15
03E9
32
22
58.6
2
3
046E
32
28
37.3
2
5
04AC
32
25.3
43.6
2
7
04EA
32
23
52.5
2
9
0528
32
21.1
66.1
2
11
0566
32
19.5
89.1
3
3
066D
32
26.6
40.2
3
5
06AA
32
23
52.5
3
7
06E7
32
20.3
75.9
4
3
086C
32
25.3
43.6
4
5
08A8
32
21.1
66.1
5
3
0A6B
32
24.1
47.7
5
5
0AA6
32
19.5
89.1
6
3
0C6A
32
23
52.5
Document Number: 002-04602 Rev. *A
Remarks
[1]
[1]
[1]
[1]
Page 63 of 86
MB91460K Series
86
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
7
3
0E69
32
22
58.6
8
3
1068
32
21.1
66.1
9
3
1267
32
20.3
75.9
10
3
1466
32
19.5
89.1
Remarks
[1]
1. These settings are not possible at MB91F465Kx
Document Number: 002-04602 Rev. *A
Page 64 of 86
MB91460K Series
15. Electrical Characteristics
86
15.1
Absolute maximum ratings
Parameter
Symbol
Power supply slew rate
Power supply voltage 1[1]
Power supply voltage 2
[1]
Relationship of the supply voltages
Rating
Min
Max
Unit
Remarks
-
-
50
V/ms
VDD5R
0.3
6.0
V
VDD5
0.3
6.0
V
VDD5-0.3
VDD5+0.3
V
At least one pin of the Ports 25
to 29 (ANn) is used as digital
input or output
VSS5-0.3
VDD5+0.3
V
All pins of the Ports 25 to 29
(ANn) follow the condition of VIA
AVCC5
Analog power supply voltage[1]
AVCC5
0.3
6.0
V
[2]
Analog reference
power supply voltage[1]
AVRH5
0.3
6.0
V
[2]
VI1
Vss5 0.3
VDD5 0.3
V
VIA
AVss5 0.3
AVcc5 0.3
V
Input voltage 1[1]
Analog pin input
voltage[1]
1[1]
VO1
Vss5 0.3
VDD5 0.3
V
ICLAMP
4.0
4.0
mA
[3]
ICLAMP
-
20
mA
[3]
IOL
-
10
mA
“L” level average
output current[5]
IOLAV
-
8
mA
“L” level total maximum
output current
IOL
-
100
mA
IOLAV
-
50
mA
IOH
-
10
mA
“H” level average
output current[5]
IOHAV
-
4
mA
“H” level total maximum
output current
IOH
-
100
mA
IOHAV
-
25
mA
Power consumption
PD
-
500
mW
Operating temperature
TA
40
105
°C
Tstg
55
150
°C
Output voltage
Maximum clamp current
Total maximum clamp current
“L” level maximum
output current[4]
“L” level total average
output current[6]
“H” level maximum
output current[4]
“H” level total average output
current[6]
Storage temperature
at TA = 105°C
1. The parameter is based on VSS5 AVSS5 0.0 V.
2. AVCC5 and AVRH5 must not exceed VDD5 0.3 V
3.
■ Use within recommended operating conditions.
■ Use with DC voltage (current).
■ B signals are input signals that exceed the VDD5 voltage. B signals should always be applied by connecting a limiting resistor between the B
signal and the microcontroller.
Document Number: 002-04602 Rev. *A
Page 65 of 86
MB91460K Series
■ The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time , either
instantaneously or for an extended period, when the B signal is input
86
■ Note that when the microcontroller drive current is low, such as in the low power consumption modes, the B input potential can increase the potential
at the power supply pin via a protective diode, possibly affecting other devices.
■ Note that if the B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through the +B input pin; therefore, the
microcontroller may partially operate.
■ Note that if the B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply
voltage.
■ Do not leave B input pins open.
■ Example of recommended circuit :
Input/output equivalent circuit
Protective diode
VCC
Limiting
resistor
P-ch
B input (0 V to 16 V)
N-ch
R
4. Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins
5. Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period.
6. Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04602 Rev. *A
Page 66 of 86
MB91460K Series
15.2
Recommended Operating Conditions
(VSS5 AVSS5 0.0 V)
86
Parameter
Power supply voltage
Smoothing capacitor at
VCC18C pin
Symbol
Max
VDD5
3.0
-
5.5
V
VDD5R
3.0
-
5.5
V
Internal regulator
AVCC5
3.0
-
5.5
V
A/D converter
CS
-
4.7
-
F
Use a X7R ceramic capacitor or a capacitor that has similar frequency
characteristics.
-
-
50
V/ms
40
-
105
°C
TA
10
ms
Lock-up time PLL
(4 MHz ->16 ...100MHz)
RC Oscillator
Remarks
Typ
Main Oscillation
stabilisation time
ESD Protection
(Human body model)
Unit
Min
Power supply slew rate
Operating temperature
Value
0.6
ms
Vsurge
2
fRC100kHz
50
100
200
kHz
fRC2MHz
1
2
4
MHz
kV
Rdischarge = 1.5k
Cdischarge = 100pF
VDDCORE ≥ 1.65V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
VCC18C
VSS5
AVSS5
CS
Document Number: 002-04602 Rev. *A
Page 67 of 86
MB91460K Series
15.3
DC Characteristics
Note: In the following tables, “VDD” means VDD5 for all pins.
86
In the following tables, “VSS” means VSS5 for all pins.
(VDD5 AVCC5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
Parameter
Symbol
Remarks
VDD 0.3
V
CMOS hysteresis input
-
VDD 0.3
V
4.5 V VDD 5.5 V
0.74 VDD
-
VDD 0.3
V
3 V VDD < 4.5 V
AUTOMOTIVE Hysteresis input is selected
0.8 VDD
-
VDD 0.3
V
-
Port inputs if TTL input is
selected
2.0
-
VDD 0.3
V
VIHR
INITX
-
0.8 VDD
-
VDD 0.3
V
INITX input pin (CMOS
Hysteresis)
VIHM
MD_2 to MD_0
-
VDD 0.3
-
VDD 0.3
V
Mode input pins
VIHX0S
X0, X0A
-
2.5
-
VDD 0.3
V
External clock in
“Oscillation mode”
VIHX0F
X0
-
0.8 VDD
-
VDD 0.3
V
External clock in “Fast
Clock Input mode”
-
Port inputs if CMOS
Hysteresis 0.8/0.2 input
is selected
VSS 0.3
-
0.2 VDD
V
-
Port inputs if CMOS
Hysteresis 0.7/0.3 input
is selected
VSS 0.3
-
0.3 VDD
V
Port inputs if
AUTOMOTIVE
Hysteresis input is selected
VSS 0.3
-
0.5 VDD
V
4.5 V VDD 5.5 V
-
VSS 0.3
-
0.46 VDD
V
3 V VDD < 4.5 V
-
Port inputs if TTL input is
selected
VSS 0.3
-
0.8
V
VILR
INITX
-
VSS 0.3
-
0.2 VDD
V
INITX input pin (CMOS
Hysteresis)
VILM
MD_2 to MD_0
-
VSS 0.3
-
VSS 0.3
V
Mode input pins
VILXDS
X0, X0A
-
VSS 0.3
-
0.5
V
External clock in
“Oscillation mode”
Input “H”
voltage
Condition
-
Port inputs if CMOS
Hysteresis 0.8/0.2 input
is selected
-
Port inputs if CMOS
Hysteresis 0.7/0.3 input
is selected
-
Value
Unit
VIH
Pin name
VIL
Input “L”
voltage
Document Number: 002-04602 Rev. *A
Min
Typ
Max
0.8VDD
-
0.7 VDD
Page 68 of 86
MB91460K Series
(VDD5 AVCC5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
86
Parameter
Input “L”
voltage
Output “H”
voltage
Output “L“
voltage
Input leakage
current
Analog input
leakage
current
Symbol
Pin
name
Condition
VILXDF
X0
-
VOH2
Normal
outputs
VOH5
Normal
outputs
VOH3
I 2C
outputs
VOL2
Normal
outputs
VOL5
Normal
outputs
VOL3
I 2C
outputs
IIL
IAIN
Pnn_m
ANn
[1]
[2]
Value
Unit
Remarks
Min
Typ
Max
VSS 0.3
-
0.2 VDD
V
External clock in
“Fast Clock Input
mode”
VDD 0.5
-
-
V
Driving strength set to
2 mA
VDD 0.5
-
-
V
Driving strength set to
5 mA
VDD 0.5
-
-
V
-
-
0.4
V
Driving strength set to
2 mA
-
-
0.4
V
Driving strength set to
5 mA
3.0V VDD 5.5V,
IOL 3mA
-
-
0.4
V
3.0V VDD 5.5V
TA=25 C
1
-
1
A
3.0V VDD 5.5V
TA=105 C
3
-
3
A
3.0V VDD 5.5V
TA=25 C
1
-
1
A
3.0V VDD 5.5V
TA=105 C
3
-
3
A
4.5V VDD 5.5V,
IOH 2mA
3.0V VDD 4.5V,
IOH 1.6mA
4.5V VDD 5.5V,
IOH 5mA
3.0V VDD 4.5V,
IOH 3mA
3.0V VDD 5.5V,
IOH 3mA
4.5V VDD 5.5V,
IOL 2mA
3.0V VDD 4.5V,
IOL 1.6mA
4.5V VDD 5.5V,
IOL 5mA
3.0V VDD 4.5V,
IOL 3mA
VSS5 < VI < VDD
AVSS5 < VI < AVCC5,
AVRH5
1. Pnn_m includes all GPIO pins. Analog (AN) channels and Pull-Up/Pull-Down are disabled.
2. ANn includes all pins where AN channels are enabled.
Document Number: 002-04602 Rev. *A
Page 69 of 86
MB91460K Series
(VDD5 AVCC5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
86
Parameter
Symbol
Pin name
Condition
Pull-up
resistance
RUP
Pnn_m [1]
INITX
Pull-down
resistance
RDOWN
Pnn_m[2]
CIN
All except VDD5,
VDD5R, VSS5,
AVCC5, AVSS5,
AVRH5
Input
capacitance
ICC
Power supply
current
MB91F-465Kx
ICCH
VDD5R
VDD5R
Value
Unit
Min
Typ
Max
3.0V VDD 3.6V
40
100
160
4.5V VDD 5.5V
25
50
100
3.0V VDD 3.6V
40
100
180
4.5V VDD 5.5V
25
50
100
f 1 MHz
-
5
15
pF
CLKB:
80 MHz
CLKP:
40 MHz
CLKT:
40 MHz
CLKCAN: 40 MHz
-
80
90
mA
TA 25°C
-
30
150
A
TA 105°C
-
400
2000
A
TA 25°C
-
100
500
A
TA 105°C
-
500
2400
A
TA 25°C
-
50
250
A
TA 105°C
-
450
2200
A
Remarks
k
k
Code fetch from Flash
At stop mode [3]
RTC : 4 MHz mode [3]
RTC :
100 kHz mode [3]
32 kHz mode [4 ]
ILVE
VDD5
-
-
70
150
A
External low voltage
detection
ILVI
VDD5R
-
-
50
100
A
Internal low voltage
detection
IOSC
VDD5
-
-
250
500
A
Main clock (4 MHz)
-
-
20
40
A
Sub clock (32 kHz)
1. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input direction.
2. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction.
3. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
4. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled, RC oscillator enabled. Additional current consumption of
Sub oscillator IOSC has to be taken into account
Document Number: 002-04602 Rev. *A
Page 70 of 86
MB91460K Series
15.4
A/D Converter Characteristics
(VDD5 AVCC5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
86
Parameter
Value
Symbol
Pin name
Resolution
-
-
Total error
-
-
3
Nonlinearity error
-
-
2.5
Differential nonlinearity error
-
-
1.9
Zero reading voltage
VOT
ANn
Full scale reading voltage
VFST
ANn
Compare time
Tcomp
-
Sampling time
Conversion time
Tsamp
Unit
Typ
Max
-
-
10
bit
-
3
LSB
-
2.5
LSB
-
1.9
LSB
AVRL
1.5 LSB
AVRL
0.5 LSB
AVRL
2.5 LSB
V
AVRH
3.5 LSB
AVRH
1.5 LSB
AVRH
0.5 LSB
V
0.6
-
16,500
s
4.5 V AVCC5 5.5 V
2.0
-
-
s
3.0 V AVCC5 4.5 V
0.4
-
-
s
4.5 V AVCC5 5.5 V,
REXT < 2 k
1.0
-
-
s
3.0 V AVCC5 4.5 V,
REXT < 1 k
1.0
-
-
s
4.5 V AVCC5 5.5 V
3.0
-
-
s
3.0 V AVCC5 4.5 V
-
-
11
pF
-
-
2.6
k
4.5 V AVCC5 5.5 V
-
-
12.1
k
3.0 V AVCC5 4.5 V
1
-
1
A
TA 25°C
3
-
3
A
TA 105°C
-
Tconv
-
Input capacitance
CIN
ANn
Input resistance
RIN
ANn
Analog input leakage
current
IAIN
ANn
Analog input voltage range
VAIN
ANn
AVRL
-
AVRH
V
-
ANn
-
-
4
LSB
Offset between input channels
Remarks
Min
Note: The accuracy gets worse as AVRH - AVRL becomes smaller
Document Number: 002-04602 Rev. *A
Page 71 of 86
MB91460K Series
86
Parameter
Reference voltage range
Symbol
Pin name
AVRH
Value
Unit
Remarks
Min
Typ
Max
AVRH5
0.75 AVCC5
-
AVCC5
V
AVRL
AVSS5
AVSS5
-
AVCC5 0.25
V
IA
AVCC5
-
2.5
5
mA
A/D Converter
active
IAH
AVCC5
-
-
5
A
A/D Converter not
operated [1]
IR
AVRH5
-
0.7
1
mA
A/D Converter
active
IRH
AVRH5
-
-
5
A
A/D Converter not
operated [2]
Power supply current
Reference voltage current
1. Supply current at AVCC5, if the A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)
2. Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)
Sampling Time Calculation
Tsamp = ( 2.6 kOhm + REXT) 11pF 7; for 4.5V AVCC5 5.5V
Tsamp = (12.1 kOhm + REXT) 11pF 7; for 3.0V AVCC5 4.5V
Conversion Time Calculation
Tconv = Tsamp + Tcomp
Document Number: 002-04602 Rev. *A
Page 72 of 86
MB91460K Series
15.4.1
Definition of A/D Converter Terms
Resolution
Analog variation that is recognizable by the A/D converter.
■
Nonlinearity error
Deviation between actual conversion characteristics and a straight line connecting the zero transition point
(00 0000 0000B 00 0000 0001B) and the full scale transition point (11 1111 1110B 11 1111 1111B).
■
Differential nonlinearity error
Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB.
■
Total error
This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition
error, and nonlinearity error.
■
Total error
3FFH
1.5 LSB’
3FEH
Actual conversion
characteristics
3FDH
{1 LSB’ (N - 1) + 0.5 LSB’}
Digital output
86
004H
VNT
(measurement value)
003H
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS5
AVRH
Analog input
1LSB' (ideal value)
AVRH AVSS5
1024
Total error of digital output N
[V]
VNT {1 LSB' (N 1) 0.5 LSB'}
1 LSB'
N: A/D converter digital output value
VOT' (ideal value) AVSS5 0.5 LSB' [V]
VFST' (ideal value) AVRH 1.5 LSB' [V]
VNT: Voltage at which the digital output changes from (N 1) H to NH
Document Number: 002-04602 Rev. *A
Page 73 of 86
MB91460K Series
86
Nonlinearity error
3FFH
Differential nonlinearity error
Actual conversion characteristics
Actual conversion characteristics
(N+1)H
3FEH
{1 LSB (N - 1) + VOT}
VFST
004H
Digital output
Digital output
Ideal
characteristics
(measurement value)
3FDH
VNT
(measurement value)
003H
NH
(N-1)H
VFST
Actual conversion
characteristics
002H
VNT
(measurement value)
Ideal characteristics
(N-2)H
001H
Actual conversion
characteristics
VTO (measurement value)
AVSS5
AVSS5
AVRH
AVRH
Analog input
Nonlinearity error of digital output N
(measurement value)
Analog input
VNT {1LSB (N 1) VOT}
[LSB]
1LSB
Differential nonlinearity error of digital output N
1LSB
V (N 1) T VNT
1LSB
1 [LSB]
VFST VOT [V]
1022
N: A/D converter digital output value
VOT : Voltage at which the digital output changes from 000H to 001H.
VFST : Voltage at which the digital output changes from 3FEH to 3FFH.
Document Number: 002-04602 Rev. *A
Page 74 of 86
MB91460K Series
15.5
86
Flash Memory Program/erase Characteristics
15.5.1 MB91F465Kx
(TA = 25oC, Vcc = 5.0V)
Parameter
Value
Unit
Remarks
3.6
s
Erasure programming time not included
n*0.9
n*3.6
s
n is the number of Flash sector of the device
23
370
s
System overhead time not included
Min
Typ
Max
Sector erase time
-
0.9
Chip erase time
-
Word (16-bit width) programming time
-
Programme/Erase cycle
10 000
cycle
Flash data retention time
20
year
[1]
1. This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert
high temperature measurements into normalized value at 85oC)
Document Number: 002-04602 Rev. *A
Page 75 of 86
MB91460K Series
15.6
86
AC Characteristics
15.6.1 Clock timing
(VDD5 3.0 V to 5.5 V, Vss5 AVss5 0 V, TA 40°C to 105°C)
Parameter
Clock frequency
Symbol
Pin name
fC
Value
Unit
Condition
16
MHz
Opposite phase external
supply or crystal
100
kHz
Min
Typ
Max
X0
X1
3.5
4
X0A
X1A
32
32.768
Figure 1. Clock timing condition
tC
X0,
X1,
X0A,
X1A
0.8 VCC
0.2 VCC
PWH
PWL
15.6.2 Reset Input Ratings
(VDD5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
Parameter
INITX input time(at power-on)
INITX input time(other than the above)
Symbol
Pin name
Condition
tINTL
INITX
-
Value
Min
Max
Unit
10
-
ms
20
-
s
tINTL
INITX
Document Number: 002-04602 Rev. *A
0.2 VCC
Page 76 of 86
MB91460K Series
15.6.3
86
LIN-USART Timings at VDD5 = 3.0 to 5.5 V
■
Conditions during AC measurements
■
All AC tests were measured under the following conditions:
❐ - IOdrive = 5 mA
❐ - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
❐ - VSS5 = 0 V
❐ - TA = -40°C to +105°C
❐ - Cl = 50 pF (load capacity value of pins when testing)
❐ - VOL = 0.2 x VDD5
❐ - VOH = 0.8 x VDD5
❐ - EPILR = 0, PILR = 1 (Automotive Level == worst case)
(VDD5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
Parameter
Symbol
Pin name
Serial clock
cycle time
tSCYCI
SCKn
SCK ↓→ SOT delay time
tSLOVI
SCKn
SOTn
SOT → SCK ↓ delay time
tOVSHI
SCKn
SOTn
Valid SIN →SCK ↑ setup
time
tIVSHI
SCKn
SINn
SCK ↑→valid SIN hold
time
tSHIXI
Serial clock “H” pulse
width
Condition
VDD5 3.0 V to 4.5 V
VDD5 4.5 V to 5.5 V
Unit
Min
Max
Min
Max
4 tCLKP
-
4 tCLKP
-
ns
30
30
20
20
ns
m
tCLKP 30[1]
-
m
tCLKP 20[1]
-
ns
tCLKP 55
-
tCLKP 45
-
ns
SCKn
SINn
0
-
0
-
ns
tSHSLE
SCKn
tCLKP 10
-
tCLKP 10
-
ns
Serial clock“L” pulse
width
tSLSHE
SCKn
tCLKP 10
-
tCLKP 10
-
ns
SCK ↓→SOT delay time
tSLOVE
SCKn
SOTn
-
2 tCLKP 55
-
2 tCLKP 45
ns
Valid SIN →SCK ↑ setup
time
tIVSHE
SCKn
SINn
10
-
10
-
ns
SCK ↑→valid SIN hold
time
tSHIXE
SCKn
SINn
tCLKP 10
-
tCLKP 10
-
ns
SCK rising time
tFE
SCKn
-
20
-
20
ns
SCK falling time
tRE
SCKn
-
20
-
20
ns
Internal clock
operation
(master
mode)
External clock
operation
(slave mode)
1. Parameter m depends on tSCYCI and can be calculated as :
■ if tSCYCI 2*k*tCLKP, then m k, where k is an integer > 2
■ if tSCYCI (2*k 1)*tCLKP, then m k 1, where k is an integer > 1
Notes :
■
The above values are AC characteristics for CLK synchronous mode.
■ tCLKP
is the cycle time of the peripheral clock.
Document Number: 002-04602 Rev. *A
Page 77 of 86
MB91460K Series
Figure 2. Internal clock mode (master mode)
86
tSCYCI
SCKn
for ESCR:SCES = 0
VOH
VOL
VOL
VOH
SCKn
for ESCR:SCES = 1
VOH
VOL
tSLOVI
tOVSHI
VOH
VOL
SOTn
tIVSHI
tSHIXI
VIH
VIL
SINn
VIH
VIL
Figure 3. External clock mode (slave mode)
tSLSHE
SCKn
for ESCR:SCES = 0
VOH
SCKn
for ESCR:SCES = 1
VOL
tSHSLE
VOH
VOL
VOL
VOH
VOH
VOL
VOH
VOL
tRE
tFE
tSLOVE
SOTn
VOH
VOL
tIVSHE
SINn
Document Number: 002-04602 Rev. *A
VIH
VIL
tSHIXE
VIH
VIL
Page 78 of 86
MB91460K Series
15.6.4
■
86
I2C AC Timings at VDD5 = 3.0 to 5.5 V
Conditions during AC measurements
All AC tests were measured under the following conditions:
❐ -IOdrive 3 mA
❐ -VDD5 3.0 V to 5.5 V, Iload 3 mA
❐ -VSS5 0 V
❐ -TA 40°C to 105°C
❐ -Cl 50 pF
❐ -VOL 0.3 VDD5
❐ -VOH 0.7 VDD5
❐ -EPILR 0, PILR 0 (CMOS Hysteresis VIL/VIH = 0.3 VDD5/0.7 VDD5)
15.6.4.1
Fast Mode:
(VDD5 3.5 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
Parameter
Symbol
Pin name
fSCL
Value
Unit
Min
Max
SCLn
0
400
kHz
tHD;STA
SCLn, SDAn
0.6
-
s
LOW period of the SCL clock
tLOW
SCLn
1.3
-
s
HIGH period of the SCL clock
tHIGH
SCLn
0.6
-
s
tSU;STA
SCLn, SDAn
0.6
-
s
tHD;DAT
SCLn, SDAn
0
0.9
s
SCL clock frequency
Hold time (repeated) START
condition. After this period, the first clock
pulse is generated
Setup time for a repeated START condition
Data hold time for I
2C-bus
devices
tSU;DAT
SCLn SDAn
100
-
ns
Rise time of both SDA and SCL signals
tr
SCLn, SDAn
20 + 0.1Cb
300
ns
Fall time of both SDA and SCL
signals
tf
SCLn, SDAn
20 + 0.1Cb
300
ns
Setup time for STOP condition
tSU;STO
SCLn, SDAn
0.6
-
s
tBUF
SCLn, SDAn
1.3
-
s
Capacitive load for each bus line
Cb
SCLn, SDAn
-
400
pF
Pulse width of spike suppressed by input filter
tSP
SCLn, SDAn
0
(1..1.5) tCLKP
ns
Data setup time
Bus free time between a STOP and START
condition
Remark
[1]
1. The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase
relationship between I2C signals (SDA, SCL) and peripheral clock.
Note: tCLKP is the cycle time of the peripheral clock.
Document Number: 002-04602 Rev. *A
Page 79 of 86
tHD;STA
Document Number: 002-04602 Rev. *A
tf
tr
tHD;DAT
tLOW
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSP
tr
P
tSU;ST0
tBUF
S
tf
86
SCL
SDA
S
MB91460K Series
Page 80 of 86
MB91460K Series
15.6.5
Free-Run Timer Clock
(VDD5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
86
Parameter
Input pulse width
Symbol
Pin name
Condition
tTIWH
tTIWL
CKn
-
Value
Min
Max
4tCLKP
-
Unit
ns
Note: tCLKP is the cycle time of the peripheral clock.
CKn
tTIWH
tTIWL
15.6.6 Trigger Input Timing
(VDD5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to 105°C)
Parameter
Symbol
Pin name
Condition
tINP
ICUn
tATGX
ATGX
Input capture input trigger
A/D converter trigger
Value
Unit
Min
Max
-
5tCLKP
-
ns
-
5tCLKP
-
ns
Note: tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn,
ATGX
Document Number: 002-04602 Rev. *A
Page 81 of 86
MB91460K Series
16. Ordering Information
Part number
86
MB91F465KAPMT-GSE2
MB91F465KBPMT-GSE2
Document Number: 002-04602 Rev. *A
Package
Remarks
120-pin plastic LQFP
(FPT-120P-M21)
not recommended
Lead-free package
Page 82 of 86
MB91460K Series
17. Package Dimension
86
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
120
LEAD No.
"A"
31
1
30
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5
C
2002 FUJITSU LIMITED F120033S-c-4-4
Document Number: 002-04602 Rev. *A
M
0.145
.006
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 83 of 86
MB91460K Series
18. Main Changes in this Edition
Spansion Publication Number: DS07-16606-2E
86
Page
Section
Change Results
4
Product lineup
Technology in m instead of um
4
Product lineup
Temteratur --> Temperature
6
Pin Assignment
Removed the quadratic index mark on upper left corner,Renamed
"FRCKn" into "CKn" (n=0 to 7)
10
Pin Description;
Power supply/Ground pins
Renamed "GND" into "ground"
18
Handling devices;
Power supply pins
Corrected "capacitator" into “capacitor”
21
Block diagram
Renamed "RTC" into "Real Time Clock”,General purpose IO ports:
Added "without resource"
23
Programming model
Renamed Program status register into "PS" (instead of RS)
28
Flash memory map MB91F465Kx
Changed unit "kB" into "KB"
38
I/O Map address 00010CH
Added address 00010CH (Reserved)
45
I/O Map address 0004C0H
Changed “CAN (Clock Control)” into “CAN Clock Control”
49
IO Map after address 7010H
Changed the start address of the Reserved area after 007010H to
007014H
53
I/O Map;
Flash memory and external bus area
Corrected table header (Added "+0 +1 +2 +3" )
60
Recommended Settings;
Clock Modulator settings
Removed all settings for Baseclk > 48 MHz
67
Recommended operating conditions
Corrected "Look-up time PLL" into "Lock-up time PLL"
69
DC Characteristics;
Output "L" voltage
Corrected condition IOH into IOL
70
DC Characteristics; Table foot note
Changed “PullUp/PullDown” into “Pull-Up/Pull-Down”
70
DC Characteristics; IccH
IccH (RTC mode) at 32kHz is similar to 100kHz, footnote added
71
A/D converter characteristics;
Zero reading voltage,
Full scale reading voltage
Corrected Values into “value +- n LSB “and Unit into “V” (Volt)
76
AC Characteristics;
Reset input ratings
INITX at power-on min. 10ms (according to the Main Oscillation Stabilisation Time)
5,76,78
Ambient temperature
Changed the symbol of ambient temperature from Ta into TA
AC Characteristics;
LIN AC Timings
I2C AC Timings
Corrected condition VOL into VOL, VOH into VOH
79
AC Characteristics; I2C AC Timings
Corrected EPILR,PILR condition into "CMOS Hysteresis VIL/VIH =..."
82
Package Dimension
Corrected the link to package web page,Updated package drawing
(latest formatting only)
76,78
NOTE: Please see “Document History” for later revised information.
Document Number: 002-04602 Rev. *A
Page 84 of 86
MB91460K Series
Document History
86
Document Title: MB91F465KA, MB91F465KB, FR60 MB91460K Series, 32-bit Microcontroller Datasheet
Document Number: 002-04602
Revision
ECN
Orig. of
Change
Submission
Date
**
AKIH
11/11/2009
Migrated to Cypress and assigned document number 002-04602.
No change to document contents or format.
*A
5200604
AKIH
04/11/2016
Updated to Cypress template
Document Number: 002-04602 Rev. *A
Description of Change
Page 85 of 86
MB91460K Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
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Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Touch Sensing
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Wireless/RF
PSoC® Solutions
cypress.com/psoc
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/psoc
Technical Support
cypress.com/touch
cypress.com/support
cypress.com/usb
cypress.com/wireless
ARM and Cortex are the trademarks of ARM Limited in the EU and other countries
© Cypress Semiconductor Corporation 2009-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04602 Rev. *A
Revised April 14, 2016
Page 86 of 86