West_Bridge_Antioch_Guide.pdf

West Bridge™ Antioch™
Product Description Guide
Doc. # 001-42576 Rev. *B
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl): 408.943.2600
http://www.cypress.com
Copyrights
Copyright © 2008-2012 Cypress Semiconductor Corporation. All rights reserved.
West Bridge™ and Antioch™ are trademarks of Cypress Semiconductor Corporation (Cypress), along with Cypress® and
Cypress Semiconductor™. All other trademarks or registered trademarks referenced herein are the property of their respective owners.
The information in this document is subject to change without notice and should not be construed as a commitment by
Cypress. While reasonable precautions have been taken, Cypress assumes no responsibility for any errors that may appear
in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of Cypress. Made in the U.S.A.
Disclaimer
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress
does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Flash Code Protection
Cypress products meet the specifications contained in their particular Cypress Data Sheets. Cypress believes that its family of
products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would
be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously improving the code protection features of our products.
2
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Contents
1.
Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2.
3.
Overview .............................................................................................................................................7
1.1.1 Usage Models ........................................................................................................................8
Terms and Abbreviations ....................................................................................................................8
West Bridge Antioch Features ............................................................................................................8
Block Diagram.....................................................................................................................................9
Top Level Functional Blocks ...............................................................................................................9
1.5.1 Processor Interface Port (P-Port)...........................................................................................9
1.5.2 Configuration and Control Registers ......................................................................................9
1.5.3 8051 MCU ............................................................................................................................10
1.5.4 USB Port (U-Port) ................................................................................................................10
1.5.5 NAND Port (S-Port)..............................................................................................................10
1.5.6 SD/MMC/CE-ATA Port (S-Port)............................................................................................11
1.5.6.1
Card Insertion and Removal Detection (CD).......................................................11
1.5.6.2
Write Protection (WP)..........................................................................................12
1.5.6.3
SD_POW.............................................................................................................12
1.5.6.4
SD/MMC System Interface Requirement ............................................................13
1.5.7 Clocking ...............................................................................................................................14
1.5.7.1
Crystal Requirement............................................................................................14
1.5.7.2
External Clock Requirement................................................................................15
Documentation Conventions .............................................................................................................16
Document Revision History ..............................................................................................................16
Pin Descriptions
2.1
2.2
3.3
3.4
17
Pin Assignment Tables .....................................................................................................................18
Ball Map ............................................................................................................................................22
Data Path
3.1
3.2
7
25
Description ........................................................................................................................................25
P-Port Interface .................................................................................................................................25
3.2.1 Modes of Operation..............................................................................................................25
3.2.2 Asynchronous Mode ............................................................................................................25
3.2.3 Synchronous Mode ..............................................................................................................26
3.2.4 Switching the P-Port from Asynchronous Mode to Synchronous Mode...............................26
3.2.5 AC Timing Parameters .........................................................................................................27
3.2.5.1
Asynchronous Mode............................................................................................27
3.2.5.2
Synchronous Mode .............................................................................................31
3.2.5.3
Other P-Port Timings...........................................................................................34
S-Port Interface AC Timing Parameters............................................................................................35
3.3.1 SD/MMC/MMC+ Timings .....................................................................................................35
3.3.2 NAND Timings......................................................................................................................36
Reset/Standby Timing Parameters ...................................................................................................36
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
3
Contents
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
4
Endpoints Overview .......................................................................................................................... 37
3.5.1 Logical Endpoints................................................................................................................. 37
3.5.2 Physical Endpoints............................................................................................................... 37
DMA Overview .................................................................................................................................. 39
3.6.1 DMA Register and Signal Descriptions................................................................................ 40
3.6.2 DMA Read and Write Procedures in ACK Mode .................................................................42
3.6.2.1
Procedure for a DMA Read from Antioch ........................................................... 42
3.6.2.2
Procedure for a DMA Write to Antioch ................................................................ 43
3.6.3 DMA Read and Write Procedures in EOB Mode .................................................................43
3.6.3.1
Procedure for a DMA Read from Antioch ........................................................... 43
3.6.3.2
Procedure for a DMA Write to Antioch ................................................................ 44
3.6.4 Zero Length Data Packet (P-Port  U-Port) ....................................................................... 44
3.6.4.1
Antioch Receives a Zero Length Data Packet from the Host.............................. 44
3.6.4.2
Antioch Sends a Zero Length Data Packet to the Host ...................................... 44
Resource Allocation .......................................................................................................................... 47
P-Port  U-Port................................................................................................................................ 51
3.8.1 Description ........................................................................................................................... 51
3.8.2 P-Port  U-Port Data Path Description............................................................................... 51
3.8.3 P-Port  U-Port Transaction ............................................................................................... 52
3.8.4 U-Port  P-Port Data Path Description............................................................................... 53
3.8.5 U-Port  P-Port Transaction ............................................................................................... 53
U-Port  S-Port (SD and/or 8-bit NAND)......................................................................................... 54
3.9.1 Description ........................................................................................................................... 54
3.9.2 U-Port  S-Port 8-bit NAND Data Path Description............................................................ 54
3.9.3 U-Port  S-Port 8-bit NAND Transaction ............................................................................ 55
3.9.4 S-Port 8-bit NAND  the U-Port Data Path Description...................................................... 55
3.9.5 S-Port 8-bit NAND  U-Port Transaction ............................................................................ 56
3.9.6 U-Port  S-Port SD Data Path Description ......................................................................... 56
3.9.7 U-Port  S-Port SD Transaction ......................................................................................... 57
3.9.8 S-Port SD  U-Port Data Path Description ......................................................................... 57
3.9.9 S-Port SD  U-Port Transaction ......................................................................................... 58
U-Port  S-Port (16-bit NAND) ........................................................................................................ 59
3.10.1 Description ........................................................................................................................... 59
3.10.2 U-Port  S-Port 16-bit NAND Data Path Description.......................................................... 59
3.10.3 U-Port  S-Port 16-bit NAND Transaction .......................................................................... 60
3.10.4 S-Port 16-bit NAND  U-Port Data Path Description.......................................................... 60
3.10.5 S-Port 16-bit NAND  U-Port Transaction .......................................................................... 61
P-Port  S-Port (SD and/or 8-bit NAND) ......................................................................................... 62
3.11.1 Description ........................................................................................................................... 62
3.11.2 P-Port  S-Port 8-bit NAND Data Path Description ............................................................ 62
3.11.3 P-Port  S-Port 8-bit NAND Transaction ............................................................................ 63
3.11.4 S-Port 8-bit NAND  P-Port Data Path Description ............................................................ 64
3.11.5 S-Port 8-bit NAND  P-Port Transaction ............................................................................ 65
3.11.6 P-Port  S-Port SD Data Path Description ......................................................................... 66
3.11.7 P-Port  S-Port SD Transaction ......................................................................................... 67
3.11.8 S-Port SD  P-Port Data Path Description ......................................................................... 68
P-Port  S-Port (16-bit NAND) ........................................................................................................ 70
3.12.1 Description ........................................................................................................................... 70
3.12.2 P-Port  S-Port (16-bit NAND) Data Path Description ....................................................... 70
3.12.3 P-Port  S-Port 16-bit NAND Transaction .......................................................................... 70
3.12.4 S-Port (16-bit NAND)  P-Port Data Path Description ....................................................... 70
3.12.5 S-Port 16-bit NAND  P-Port Transaction .......................................................................... 71
U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port Interleaving................................... 71
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Contents
3.14
3.15
3.16
3.17
3.18
3.13.1 Description ...........................................................................................................................71
3.13.2 U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port Interleaving Data Path Description72
3.13.3 U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port Interleaving Transaction ..73
U-Port  S-Port (16-bit NAND) and U-Port  P-Port Interleaving ..................................................75
3.14.1 Description ...........................................................................................................................75
3.14.2 U-Port  S-Port (16-bit NAND) and U-Port  P-Port Interleaving Data Path Description .76
3.14.3 U-Port  S-Port (16-bit NAND) and U-Port  P-Port Interleaving Transaction..................77
U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port Interleaving ...................................79
3.15.1 Description ...........................................................................................................................79
3.15.2 U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port Interleaving Data Path Description79
3.15.3 U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port Interleaving Transaction...80
U-Port  S-Port (16-bit NAND) and P-Port  S-Port Interleaving...................................................81
3.16.1 Description ...........................................................................................................................81
3.16.2 U-Port  S-Port (16-bit NAND) and P-Port  S-Port Interleaving Data Path Description..81
3.16.3 U-Port  S-Port (16-bit NAND) and P-Port  S-Port Interleaving Transaction ..................82
P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) Interleaving ...................................83
3.17.1 Description ...........................................................................................................................83
3.17.2 P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) Interleaving Data Path Description83
3.17.3 P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) Interleaving Transaction...84
P-Port  U-Port and P-Port  S-Port (16-bit NAND) Interleaving...................................................84
3.18.1 Description ...........................................................................................................................84
3.18.2 P-Port  U-Port and P-Port  S-Port (16-bit NAND) Interleaving Data Path Description..85
3.18.3 P-Port  U-Port and P-Port  S-Port (16-bit NAND) Interleaving Transaction ..................85
4.
Address Space
87
5.
Interrupt
89
6.
Bootup Initialization
93
6.1
6.2
6.3
6.4
6.5
6.6
Reset by Pin (Hard Reset) ................................................................................................................93
Reset by Register (Soft Reset) .........................................................................................................94
Wakeup Mechanism..........................................................................................................................95
Firmware Loading .............................................................................................................................96
6.4.1 Loading the Firmware from the Processor ...........................................................................96
Configuration of Registers.................................................................................................................97
Processor Boot Mode Initialization Transaction ................................................................................98
7.
Mailbox Registers
103
8.
Power
105
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Power Domains...............................................................................................................................105
8.1.1 Power Supply Sequence....................................................................................................105
8.1.2 Power Supply Decoupling Recommendations ...................................................................106
AC-DC Characteristics ....................................................................................................................107
Normal Mode...................................................................................................................................108
Standby Mode .................................................................................................................................108
Suspend Mode ................................................................................................................................109
Core Power Down ...........................................................................................................................109
Working with Power Management Unit (PMU)................................................................................110
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
5
Contents
9.
Register Summary
Glossary
6
113
115
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
1. Introduction
1.1
Overview
The West Bridge Antioch device (CYWB0124AB) is a peripheral controller supporting High-Speed USB and Mass Storage
access as shown in Figure 1-1. This controller provides access from a processor interface and a High-Speed USB (HS-USB)
interface to peripherals including SD, MMC/MMC+, and NAND. It supports interleaving accesses between the processor
interface, the HS-USB, and the peripherals so that an external processor and an external USB Host can transfer data to each
other and to the mass storage peripherals simultaneously.
Figure 1-1. West Bridge Antioch High Level Block Diagram
West Bridge Antioch
Processor
Interface
P
8051
MCU
High-Speed
USB 2.0 XCVR
Control
Registers
U
SLIM TM
Mass Storage Interface
SD/MMC+/CE-ATA
NAND
S
Antioch is available in two package options, the VFBGA and the WLCSP. The WLCSP differs from the VFBGA in the following
ways:
■
The XTALIN input only accepts clock inputs and no crystals. The XTALOUT ball and the XVDDQ power domain do not
exist in this package. The XVDDQ power domain is internally combined with AVDDQ.
■
Because AVDDQ, and hence XVDDQ, are OFF in the Core Power Down mode, the clock input at XTALIN must be
brought to a steady LOW level before entry into Core Power Down mode.
■
NAND functionality is not available. SNVDDQ does not exist as a separate power domain, it is internally combined with
SSVDDQ.
■
The P-Port CLK ball, and hence P-Port synchronous mode operation is not available. The P-Port can be operated only in
asynchronous mode.
■
GVDDQ is not a separate power domain in the WLCSP package; it is internally combined with PVDDQ.
■
Availability of specific signals on the WLCSP option is detailed in Table 2-1 through Table 2-6: Pin Assignments.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
7
Introduction
1.1.1
Usage Models
The controller offers multiple access paths among three different ports - the processor port (for connecting to a handset baseband processor, for example), the HS-USB port (for connecting to an external USB Host), and the mass storage port (for connecting to mass storage devices). DMA is supported so that certain data transfers, such as transfer from/to HS-USB to/from
the processor, and from/to the processor to/from mass storage can occur.
Usage models include USB Host accessing mass Storage, USB Host exchanging data with the handset processor (use as a
modem), and handset processor accessing Mass Storage. It enables all of these accesses to happen independently and
simultaneously, after accounting for the fact that a single resource (such as USB or mass storage) can only issue or receive
one data transfer at a given point in time.
1.2
Terms and Abbreviations
P-Port: Also referred to as “Processor Port”, it is the processor interface of Antioch. It is an interface providing asynchronous
and synchronous memory access to the external processor.
S-Port: Storage Port. It is the port that connects to NAND, SD, MMC or MMC+.
U-Port: HS-USB port. Antioch functions as a USB Device.
Simultaneous Access: For a given port, at any given point in time, data can be transferred either in or out and only from one
source or to one destination. Simultaneous access refers to transfer between independent ports and buffers at the same time.
x': Means the following number is in HEX format. For example, x'1A30 means the number “1A30” is in HEX format.
b': Means the following number is in binary format. For example, b'10101 means the number “10101” is in binary format.
DMA: Direct Memory Access. In West Bridge Antioch, DMA refers to the DMA burst mode that Antioch supports. There is no
DMA engine in this part; the processor at the P-Port controls the DMA operation.
1.3
West Bridge Antioch Features
■
Sync and Async SRAM style processor interface
■
High-Speed USB 2.0 interface to a USB Host
■
SD, MMC, MMC+, CE-ATA mass storage support
■
8/16-bit NAND Flash1 interface
■
Simultaneous access among processor interface, HS USB, and mass storage
■
DMA Slave operating mode with control signals
1. 16-bit NAND supported only when no other mass storage device is present.
8
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Introduction
1.4
Block Diagram
Figure 1-2. West Bridge Antioch Block Diagram
West Bridge Antioch
DQ[15:0]
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
SDIO
Eng
TEST[0]
Upper Byte
1.5
SD_WP
USB Port
(U Port)
SD_POW
SD_CLK
SD_CMD
SD_D[7:0]
NAND_IO[15:8]
NAND_CE2#
NAND_WP#
NAND_R/B#
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
UVALID
D-
TEST[1]
USB 2.0
XCVR
D
+
Lower Byte
TEST[2]
Top Level Functional Blocks
The following sections provide a high-level outline of the top-level functional blocks in Antioch.
1.5.1
Processor Interface Port (P-Port)
This port provides a standard asynchronous and synchronous memory interface that can connect to processors. Through this
interface, the external processor can access the Antioch configuration and status registers, the internal buffers for data to and
from the HS-USB port, the NAND at the S port, and the removable media (SD, MMC, etc.) also at the S port.
1.5.2
Configuration and Control Registers
The Configuration and Control Registers block contains the various configuration registers and interrupt status registers of
Antioch. The external processor accesses the contents of these registers through the P port. The external processor uses this
block to set and examine various configurations of the Antioch and to communicate with Antioch on operations such as DMA,
interrupt, and other status information.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
9
Introduction
1.5.3
8051 MCU
The 8051 MCU does basic transaction management for all the transactions between the P-Port, the S-Port, and the U-Port.
The 8051 does not reside in the data path; it manages the path. The data path is optimized for performance. The 8051 executes firmware that supports NAND, SD, and MMC/MMC+ devices at the S-Port. For the NAND device, the 8051 firmware follows the Smart Media algorithm to support:
■
Physical to logical management
■
ECC correction support (not the actual ECC itself)
■
Wear leveling
■
NAND Flash bad block management
1.5.4
USB Port (U-Port)
The USB Port controls the interface to the High Speed USB 2.0 port. In accordance with the USB 2.0 specification, Antioch
can operate in Full Speed USB mode as well. It consists of the USB transceiver. The USB interface can access and be
accessed by both the P-Port and the S-Port. The Antioch USB interface supports programmable CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
The default enumerated USB device ID (with RENUM='0') depends on the operating mode:
■
Vendor ID (VID) = x'04B4 (Cypress Semiconductor)
■
Product ID (PID) = x'A124 (Antioch normal mode)
■
Device Release (DID) = x'0000 (rev. A silicon), x'0001 (rev. B silicon) and x'0011 (rev. C silicon)
1.5.5
NAND Port (S-Port)
This interface port supports both 8- and 16-bit NAND interfaces, although the 16-bit interface is applicable only when there is
no other mass storage device connected to the S-Port. The NANDCFG pin is used to set the configuration of the S-Port to be
either 16-bit NAND or 8-bit NAND and SD/MMC. Note that in the WLCSP option, the S-Port is not configurable; it only supports a single SD/MMC+ port with no NAND port.
SLC NAND devices are supported. Write performance for SLC NAND is up to 9MB/s, while read performance is up to 13 MB/
s (depending on the NAND device used, errors etc.).
Antioch is responsible for bad-block management and wear-leveling for the NAND device. There is also an Error Correction
Code (ECC) mechanism for the NAND device. Antioch supports single bit error correction and double bit error detection. It
uses a hardware functional block to compute the ECC value and it uses the 8051 firmware for error detection and correction.
Because the ECC computation is based on 512 bytes block, the read/write granularity to the NAND Flash is 512 bytes.
In the NAND interface, the signal pin NAND_R/B# (input) is connected to the external NAND's R/B# (output) signal pin.
Because the external NAND device's R/B# (output) signal pin is open drain configuration, it is required to put a pull-up resistor
as shown in Figure 1-3. The Pull-up (Rp) value varies from 1k ohm to 10k ohm. The Rp value depends on the timing requirement and the NAND Flash manufacturer.
Figure 1-3. NAND_R/B# Requires External Pull-up
Rp
SNVDDQ
Antioch
NAND_CLE
NAND_ALE
NAND_CE#
NAND_RE#
NAND_WE#
NAND_WP#
NAND_R/B#
10
NAND Flash
NAND_IO[7:0]
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Introduction
1.5.6
SD/MMC/CE-ATA Port (S-Port)
This Interface port supports:
1. The Multimedia Card-System Specification, MMCA Technical Committee, Version 4.1.
2. SD Memory card Specification - Part 1, Physical Layer Specification, SD Group, Version 2.0, November 9, 2005.
3. CE-ATA Digital Protocol, Rev 1.1, 28 September, 2005 and CE-ATA Host Design Guidance, Rev 1.0, 29 September, 2005.
The NANDCFG pin is used to set the configuration of the S-Port to be either 16-bit NAND (no SD/MMC device) or 8-bit NAND
and SD/MMC. West Bridge Antioch provides support for 1-bit and 4-bit SD cards, and 1-bit, 4-bit and 8-bit MMC and MMC+
cards. For the SD, MMC/MMC Plus card, this block supports one card for one physical bus interface.
Antioch supports SD commands including the multi-sector program command that is handled by the API.
Compatibility with specific CE-ATA HDD is subject to confirmation with drive vendors.
1.5.6.1
Card Insertion and Removal Detection (CD)
Antioch supports two card insertion/removal detection mechanisms on the S-Port:
1. Usage of the SD_D[3] data for card insertion/removal detection: In the system design, this signal is required to have a
470K pull down resistor connected to SD_D[3]. SD cards have an internal 10K pull up resistor. When the card is inserted
or removed from the SD/MMC connector, the voltage level at the SD_D[3] pin changes and triggers an interrupt to the
8051. This card insertion/removal detection mechanism may not be supported by old MMC cards.
2. Usage of GPIO[0] for card insertion/removal detection: Some SD/MMC connectors facilitate a micro-switch for the card
insertion/removal detection (CD). This micro-switch is connected to the GPIO[0]. When the card is inserted or removed
from the SD/MMC connector, it turns the micro-switch on and off and causes a voltage level change at the GPIO[0] that
triggers the interrupt to the 8051. The card-detect micro-switch polarity is assumed to be the same as the write-protect
micro-switch polarity below. LOW indicates the card is inserted.
Card insertion or removal in the S-Port is communicated to the P-Port via the MCUINT in the P-Port Interrupt Register and the
status bits in the 8051 MCU Status Register (when the SD external bus is allocated to the S-Port). The card insertion/removal
detection interrupt on both SD_D[3] and GPIO[0] can be independently masked (disabled). If a card is inserted when the
Antioch device is in standby or powered down, Antioch will detect this device and interrupt the processor on wakeup if the SD
external bus is allocated to S-Port. On card removal, the SD bus is placed in high-Z state.
When the SD bus (SD_D[7:0]) has no ownership or has been allocated to the processor, the SD_D[3] will be in tri-state or
driven by external signal change. In this case, if SD_D[3] is used for card insertion/removal detection, it must mask the interrupt to avoid the unwanted interrupts. The following four different scenarios describe how to handle card insertion/removal
detection interrupt by the 8051 firmware:
1. SD Bus has no ownership (both processor and Antioch do not own the SD Bus).
a. SD Bus is in tri-state all the time.
b. Card insertion/removal detection interrupt on SD_D[3] must be disabled (masked).
2. SD Bus has no ownership, Antioch gains ownership.
a. Antioch has gained the ownership of the SD Bus.
b. The 8051 firmware needs to clear the card insertion/removal detection interrupt status (or IRQ flag).
c. Enable (unmask) the card insertion/removal detection interrupt.
3. SD Bus is owned by the processor, but is being allocated to Antioch.
a. 8051 sends a SD Bus request message to the processor.
b. When the processor releases the SD Bus with a response message, Antioch writes “1” to the SDIOAVI field of the
External Bus Allocation Register to gain ownership of the SD Bus.
c. After Antioch gains ownership of the SD bus, 8051 firmware needs to clear the card insertion/removal detection interrupt status (or IRQ flag).
d. Enable (unmask) the card insertion/removal detection interrupt.
The detailed procedure of External Bus Allocation is described in Section 3.7.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
11
Introduction
4. SD Bus is owned by Antioch, but is being allocated to the processor.
a. Processor sends a SD Bus request message to Antioch.
b. When the SD bus is available to be allocated to the processor, 8051 needs to disable (mask) the card insertion/
removal detection interrupt on SD_D[3].
c. 8051 releases ownership to the processor.
d. 8051 sends a “bus has been released” message to the processor.
The detailed procedure of External Bus Allocation is described in Section 3.7.
1.5.6.2
Write Protection (WP)
The SD_WP (SD Write Protection) in S-Port is used to connect to the WP micro switch of the SD/MMC card connector. This
signal pin is internally connected to the 8051 GPIO pin so the firmware can detect the SD card Write Protection. Figure 1-4
shows the connection of the WP micro switch to the SD_WP pin.
Figure 1-4. Connecting the WP Micro Switch to the SD_WP Pin
V DD
10K
SD_WP
WP Micro Switch
1.5.6.3
SD_POW
SD_POW is an output pin that provides an option to control the power for the SD/MMC/MMC+ card. This pin is used to connect to the external power switch to turn on/off the power for the SD/MMC/MMC+ card. The output of this pin is controlled by
the 8051 firmware. Figure 1-5 shows the system connectivity of this signal.
12
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Introduction
1.5.6.4
SD/MMC System Interface Requirement
In the SD/MMC specification, a pull-up or pull-down requirement is specified as shown in Figure 1-5. Figure 1-5 also shows
the two different card detect mechanisms, although only one is required for system design.
If SD_D[3] is used for card insertion/removal detection, Q1 should be ON at all times and R8 is not required.
If GPIO[0] is used for card insertion/removal detection, R11 should be a 10k ohm pull-up instead of a 470k ohm pull down.
Figure 1-5. SD/MMC/MMC+ System Interface Requirement
SSVDDQ
Q1
R9
R10
R8
R7
R6
R5
R4
R3
R2
R1
SD_POW
10k ohm x 10
SD_D2
DAT2
SD_D3
DAT3 2
DAT4 3
SD_D4
1
CMD 4
DAT5 5
SD_CMD
SD_D5
CD 6
VSS 7
VDD
8
Antioch
CLK
9
DAT6 10
VSS 2
11
DAT7
12
DAT0
13
DAT1
14
SD_CLK
SD_D6
SD_D7
SD_D0
SD_D1
WP
SD_WP
GND
470k ohm
15
16
Connector Pin Mapping
Connector SD Card MMC Card
1
9
9
2
1
1
3
10
4
2
2
5
11
6
7
3
3
8
4
4
9
5
5
10
12
11
6
6
12
13
13
7
7
14
8
8
15
16
SDSR13-X0-0X00
R11
GPIO0
SD/MMC Connector
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
13
Introduction
1.5.7
Clocking
Antioch allows either a crystal to be connected between the XTALIN and XTALOUT pins or an external clock to be connected
at the XTALIN pin. The power supply level at the crystal supply XVDDQ determines whether a crystal or a clock is provided:
1. When using a crystal, the power supply used for the crystal must be only a 3.3V supply.
2. When using a clock source as an input to Antioch, the voltage level for the clock input is 1.8V.
If XVDDQ is detected to be 1.8V, Antioch assumes that a clock input is provided. For a crystal to be connected, XVDDQ has
to be 3.3V. Note clock inputs at 3.3V level are not supported.
Of the different input frequency configurations supported, as specified below, crystals are supported only at 19.2 and 24 MHz.
At 48 MHz, only clock inputs are supported. The following table specifies XTALSLC[1:0] levels for each clock frequency:
Table 1-1. Clock Selection Inputs (CYWB0124AB)
XTALSLC[1]
XTALSLC[0]
Clock Frequency
Crystal Supported?
0
0
19.2 MHz
Yes
0
1
24 MHz
Yes
1
0
48 MHz
No
1
1
26 MHz
Yes
The XTALIN frequency is independent of the clock/data rate of Antioch core (e.g., 8051) or any of the device interfaces
(including P-Port and S-Port). The internal PLL applies the appropriate clock multiply option depending on the input frequency.
For applications that use an external clock source to drive XTALIN, the XTALOUT pin must be left floating. In addition, Antioch
firmware must ensure that the right firmware registers are initialized. This will give the lowest possible current consumption in
the low-power 'suspend' state. The external clock source must also remain HIGH or LOW and not be toggling, to achieve the
lowest possible current consumption.
1.5.7.1
Crystal Requirement
Antioch has an on-chip oscillator circuit that uses an external 19.2/24 MHz (±100 ppm) crystal with the following characteristics:
■
Parallel resonant
■
Fundamental mode
■
1 mW drive level
■
12 pF (5% tolerance) load capacitors (specified as typical for 24 MHz frequency, load capacitance varies with crystal vendor specifications and frequency used)
An on-chip PLL multiplies the external clock frequency up to 480 MHz, as required by the transceiver/PHY, and internal counters divide it down for use as the 8051 clock. The 8051 clock frequency is 48 MHz.
Figure 1-6. Crystal Configuration
14
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Introduction
1.5.7.2
External Clock Requirement
Antioch can also connect to an external clock, which provides a square wave input to XTALIN. The square wave must conform to the voltage high and low levels specified in Table 9-1 and to rise and fall times specified in Figure 8-2 The connections
for the external OSC or external clock source are shown in Figure 1-7. Table 1-2 shows the input requirement for the external
clock.
Figure 1-7. External Clock Connection
XVDDQ=1.8V
Antioch
PLL
XTALIN
OSC
XTALOUT NC
Using the external clock oscillator for the Antioch
Antioch
PLL
External
Clock Source
XTALIN
XTALOUT NC
Using the external clock source for the Antioch
Table 1-2. External Clock Requirements
Parameter
Description
Vn1
Vn2
Specification
Units
min
max
Supply Voltage Noise @ frequencies >50 MHz
-
100
mV p-p
Supply Voltage Noise @ frequencies <50 MHz
-
20
mV p-p
PN_dc
Input Phase Noise @ DC
-
-75
dB
PN_1k
Input Phase Noise @1kHz offset
-
-104
dB
PN_10k
Input Phase Noise @10 kHz offset
-
-120
dB
PN_100k
Input Phase Noise @100 kHz offset
-
-128
dB
Input Phase Noise @1 MHz offset
-
-130
dB
30
70
%
Jitter
100
ppm
Overshoot
+3
%
Undershoot
-3
%
PN_1M
Duty Cycle
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
15
Introduction
1.6
Documentation Conventions
Table 1-3. Documentation Conventions for Reference Design Guides
Convention
Usage
Courier New
Displays file locations, user entered text, and source code:
C:\ ...cd\icc\
Italics
Displays file names and reference documentation:
Read about the sourcefile.hex file in the PSoC Designer User Guide.
[Bracketed, Bold]
Displays keyboard commands in procedures:
[Enter] or [Ctrl] [C]
File > Open
Represents menu paths:
File > Open > New Project
Bold
Displays commands, menu paths, and icon names in procedures:
Click the File icon and then click Open.
Times New Roman
Displays an equation:
2+2=4
No text, gray table cell
Represents a reserved bit in register tables.
1.7
Revision
16
Document Revision History
PDF Creation Date
**
February 28, 2008
*A
*B
Origin of Change
Description of Change
OSG
New product description guide for West Bridge Antioch.
March 24, 2011
ESH
Added watermark
April 30, 2012
AASI
Posted to external web
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
2. Pin Descriptions
The following tables list the pins for the entire Antioch device by port.
Notes
1. The Reset column indicates the state of signals during Reset (RESET# asserted). The Standby column indicates signal
state during Standby (low-power operating mode via WAKEUP de-assertion) or core VDD deactivation.
2. Unused inputs: Must be connected HIGH/VDD or LOW/GND (negligible difference in current drawn) through a single 10k
pull up resistor. The exceptions are WAKEUP, NANDCFG and CLK. WAKEUP is tied HIGH for normal operation, NANDCFG is tied LOW for 8-bit NAND with SD or tied HIGH for 16-bit NAND with no SD, and CLK is tied LOW for asynchronous mode operation.
3. Unused IOs: For lowest leakage, unused IOs must be connected to a HIGH logic level. Connect the power supply through
a single 10k pull-up resistor for all unused IOs.
4. No Antioch pins have internal pull-up or pull-down resistors. Input/output pins may require external pull-up or pull-down
resistors depending on the application. The pull-up resistors used to indicate speed capability in USB are included in
Antioch and need not be connected externally.
5. UART interface pins are multiplexed with pins from the preceding table to be used during test or debugging modes.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
17
Pin Descriptions
2.1
Pin Assignment Tables
Table 2-1. P-Port
VFBGA
WLCSP
IO
Pin Description
Standby
Reset
-
J2
N/A
CLK
I
Clock for P-port.
-
G1
G8
CE#
I
Chip Select for P-port. Active LOW.
-
-
H3
J6
A[7]
I
Bit 7 of Address Bus for P-port.
-
-
H2
J7
A[6]
I
Bit 6 of Address Bus for P-port.
-
-
H1
J8
A[5]
I
Bit 5 of Address Bus for P-port.
-
-
J3
H6
A[4]
I
Bit 4 of Address Bus for P-port.
-
-
J1
H7
A[3]
I
Bit 3 of Address Bus for P-port.
-
-
K3
J9
A[2]
I
Bit 2 of Address Bus for P-port.
-
-
K2
H8
A[1]
I
Bit 1 of Address Bus for P-port.
-
-
K1
H9
A[0]
I
Bit 0 of Address Bus for P-port.
-
-
G2
G9
DQ[15]
IO
Bit 15 of Data Bus for P-port.
Z
Z
G3
G7
DQ[14]
IO
Bit 14 of Data Bus for P-port.
Z
Z
F1
F8
DQ[13]
IO
Bit 13 of Data Bus for P-port.
Z
Z
F2
F9
DQ[12]
IO
Bit 12 of Data Bus for P-port.
Z
Z
F3
F7
DQ[11]
IO
Bit 11 of Data Bus for P-port.
Z
Z
E1
E9
DQ[10]
IO
Bit 10 of Data Bus for P-port.
Z
Z
E2
E8
DQ[9]
IO
Bit 9 of Data Bus for P-port.
Z
Z
E3
E7
DQ[8]
IO
Bit 8 of Data Bus for P-port.
Z
Z
D1
D9
DQ[7]
IO
Bit 7 of Data Bus for P-port.
Z
Z
D2
D8
DQ[6]
IO
Bit 6 of Data Bus for P-port.
Z
Z
D3
D7
DQ[5]
IO
Bit 5 of Data Bus for P-port.
Z
Z
C1
C9
DQ[4]
IO
Bit 4 of Data Bus for P-port.
Z
Z
C2
C8
DQ[3]
IO
Bit 3 of Data Bus for P-port.
Z
Z
C3
C7
DQ[2]
IO
Bit 2 of Data Bus for P-port.
Z
Z
B1
B9
DQ[1]
IO
Bit 1 of Data Bus for P-port.
Z
Z
B2
B8
DQ[0]
IO
Bit 0 of Data Bus for P-port.
Z
Z
-
-
A1
A9
ADV#
I
Address Valid for P-port. Valid during asynchronous mode. ADV# de-assertion causes address to
be latched.
B3
A8
OE#
I
Output Enable. Controls the data bus output drive.
Ignored during write cycle. Active LOW.
-
-
A2
B7
WE#
I
Write Enable. Signals a read (HIGH) or write
(LOW) access cycle.
-
-
A3
A7
INT#
O
Interrupt Request. Assertion indicates that an
interrupt event has occurred. Active LOW.
Z
Z
O
DMA Request. Assertion indicates to the processor that one or more endpoints are ready to be
written or read. It reflects register
CY_AN_MEM_P0_DRQ EPnDRQ assertions.
Active LOW or HIGH (programmable).
Z
Z
I
DMA Acknowledgement. Assertion indicates DMA
acknowledgement from the processor. Can be
configured in ACK mode (asserted throughout
DMA transfer) or EOB mode (pulsed at end of
DMA transfer). Active LOW or HIGH (programmable).
-
-
A4
B4
18
Pin Name
C6
C5
DRQ#
DACK#
Power
Domain
PVDDQ
VGND
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Pin Descriptions
Table 2-2. S-Port
VFBGA
WLCSP
SD and 8-bit
NAND
Configuration
16-bit NAND
Configuration
IO
G9
H2
SD_D[7]
NAND_IO[15]
IO
G10
H1
SD_D[6]
NAND_IO[14]
F9
G3
SD_D[5]
F10
G2
E9
Pin Description
Standby
Reset
Serve as IO for SD port or NAND Upper IO port
depending on NANDCFG selection.
Z
Z
IO
Serve as IO for SD port or NAND Upper IO port
depending on NANDCFG selection.
Z
Z
NAND_IO[13]
IO
Serve as IO for SD port or NAND Upper IO port
depending on NANDCFG selection.
Z
Z
SD_D[4]
NAND_IO[12]
IO
Serve as IO for SD port or NAND Upper IO port
depending on NANDCFG selection.
Z
Z
F2
SD_D[3]
NAND_IO[11]
IO
Serve as IO for SD port or NAND Upper IO port
depending on NANDCFG selection.
Z
Z
E10
E3
SD_D[2]
NAND_IO[10]
IO
Serve as IO for SD port or NAND Upper IO port
depending on NANDCFG selection.
Z
Z
D9
E2
SD_D[1]
NAND_IO[9]
IO
Serve as IO for SD port or NAND Upper IO port
depending on NANDCFG selection.
Z
Z
D10
E1
SD_D[0]
NAND_IO[8]
IO
Serve as IO for SD port or NAND Upper IO port
depending on NANDCFG selection.
Z
Z
F8
G1
SD_CLK
N/A
O
Clock output for the SD interface. Frequency can
be changed and clock can be disabled through
firmware control.
Z
Z
G8
H3
SD_CMD
N/A
IO
SD Command/Response pin.
Z
Z
Z
Z
H8
G4
SD_POW
N/A
O
SD Power Control. This GPIO can be used to control SD/MMC card power FET if present. HIGH
indicates on, LOW indicates off.
H10
D1
SD_WP
N/A
I
SD Write Protection Detection. Connected to
GPIO for firmware detection. HIGH indicates that
the device connected to the SD port has write protect enabled.
-
-
K7
N/A
NAND_IO[7]
NAND_IO[7:0]
IO
For multiplexed address/data communications
over the NAND port.
Z
Z
K8
N/A
NAND_IO[6]
NAND_IO[6]
IO
For multiplexed address/data communications
over the NAND port.
Z
Z
J8
N/A
NAND_IO[5]
NAND_IO[5]
IO
For multiplexed address/data communications
over the NAND port.
Z
Z
K9
N/A
NAND_IO[4]
NAND_IO[4]
IO
For multiplexed address/data communications
over the NAND port.
Z
Z
J9
N/A
NAND_IO[3]
NAND_IO[3]
IO
For multiplexed address/data communications
over the NAND port.
Z
Z
H9
N/A
NAND_IO[2]
NAND_IO[2]
IO
For multiplexed address/data communications
over the NAND port.
Z
Z
K10
N/A
NAND_IO[1]
NAND_IO[1]
IO
For multiplexed address/data communications
over the NAND port.
Z
Z
J10
N/A
NAND_IO[0]
NAND_IO[0]
IO
For multiplexed address/data communications
over the NAND port.
Z
Z
K6
N/A
NAND_CLE
NAND_CLE
O
NAND Command Latch Enable.
Z
Z
J6
N/A
NAND_ALE
NAND_ALE
O
NAND Address Latch Enable.
Z
Z
J5
N/A
NAND_CE#
NAND_CE#
O
NAND Chip Enable. Active LOW.
Z
Z
K4
N/A
NAND_RE#
NAND_RE#
O
NAND Read Enable. Active LOW.
Z
Z
H6
N/A
NAND_WE#
NAND_WE#
O
NAND Write Enable. Active LOW.
Z
Z
J7
N/A
NAND_WP#
NAND_WP#
O
NAND Write Protect. Active LOW.
Z
Z
-
-
Z
Z
J4
N/A
NAND_R/B#
NAND_R/B#
I
NAND Ready/Busy. NAND output is Open-Drain.
Active LOW.
K5
N/A
NAND_CE2#
NAND_CE2#
O
NAND Chip Enable 2. Allows second NAND
device to be accessed. Active LOW.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Power
Domain
SSVDDQ
VGND
SSVDDQ
VGND
19
Pin Descriptions
Table 2-3. U-Port
VFBGA
WLCSP
Pin Name
A5
A4
D+
IO/Z
USB D+.
Z
Z
A6
A5
D-
IO/Z
USB D-.
Z
Z
Low
Low
A7
B4
UVALIDa
IO
O
Pin Description
External USB Switch Control. Reflects value of
register CY_AN_MEM_PMU_UPDATE.UVALID.
Standby
Reset
Power
Domain
UVDDQ
UVSSQ
a. UVALID is driven LOW during RESET# assertion, WAKEUP de-assertion or when the CY_AN_MEM_PMU_UPDATE.UVALID bit is not driven. The UVALID bit is de-asserted LOW within tSLP time after WAKEUP is de-asserted. During normal operation (WAKEUP=HIGH), UVALID is driven to the level determined by the CY_AN_MEM_PMU_UPDATE.UVALID bit.
Table 2-4. Others
VFBGA
WLCSP
Pin Name
IO
Pin Description
Standby
Reset
A8
A2
XTALIN
I
Input for either crystal or clock signal. XVDDQ is
3.3V for crystal input; XVDDQ is 1.8V for clock
input.
-
-
High
Active4
Power
Domain
XVDDQ
VGND
B8
N/A
XTALOUTa
O
Output to connect to feedback input of crystal.
Should be left floating when external clock at XTALIN.
C10
C2
RESET#b
I
Reset. Asserted to place Antioch into reset mode
and subsequent initialization. Active LOW.
-
-
B10
N/A
RESETOUT
O
Reset Out. De-asserted LOW when RESET# is
asserted LOW. Asserted HIGH after RESET# is
de-asserted and initialization is complete. Reflects
value of RSTCMPT bit.
Z
Low
C9
D3
GPIO[1]
IO
General purpose input/output.
Z
Z
D8
D2
GPIO[0]
IO
General purpose input/output. GPIO[0] can be
used for SD Card Detect with firmware detection.
LOW indicates card is inserted.
Z
Z
C7
C1
WAKEUP
I
Wake Up Signal. 1=normal operation, 0=low
power “sleep” mode. Must be asserted for Antioch
to initialize.
-
-
GVDDQ
VGND
a. XTALOUT is driven HIGH during Standby mode. XTALOUT operates the same during RESET# assertion and normal mode: fixed HIGH when XVDDQ
is 1.8V (ext clock), and actively toggles when XVDDQ is 3.3V (crystal).
b. When RESET# is asserted, the device enters reset state and WAKEUP is ignored.
20
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Pin Descriptions
Table 2-5. Config
VFBGA
C5
C4
WLCSP
C3
C4
Pin Name
XTALSLC[1]
XTALSLC[0]
IO
Pin Description
Standby
Reset
I
Clock Select. For CYWB0124AB XTALSLC[1:0]
can be decoded as: 00=19.2 MHz, 01=24 MHz,
10=48 MHz, 11=26 MHz. For CYWB0113AB:
00=19.2 MHz, 01=13 MHz, 10=38.4 MHz, 11=26
MHz.
-
-
I
Clock Select. For CYWB0124AB XTALSLC[1:0]
can be decoded as: 00=19.2 MHz, 01=24 MHz,
10=48 MHz, 11=26 MHz. For CYWB0113AB:
00=19.2 MHz, 01=13 MHz, 10=38.4 MHz, 11=26
MHz.
-
-
-
-
Power
Domain
GVDDQ
VGND
C6
N/A
NANDCFG
I
S-port Configuration. '0' selects 8-bit NAND and
SD/MMC configuration. '1' selects 16-bit NAND
configuration.
E8
B1
TEST[2]
I
Test mode selection. Should be tied to VGND for
normal operation (CMOS level inputs).
-
-
C8
D4
TEST[1]
I
Test mode selection. Should be tied to VGND for
normal operation (CMOS level inputs).
-
-
D7
A1
TEST[0]
I
Test mode selection. Should be tied to VGND for
normal operation (CMOS level inputs).
-
-
Standby
Reset
Table 2-6. Power
VFBGA
WLCSP
Pin Name
IO
Pin Description
D4, H4
E5, A6
PVDDQ
Power
Power for P-port IO. 1.8V, 2.5V, or 3.3V nominal.
-
-
-
-
N/A
SNVDDQ
Power
Power for NAND port IO. 1.8V, 2.5V, or 3.3V nominal.
B5
B5
UVDDQ
Power
Power for USB IO. 3.3V nominal.
-
-
H7
F1, F3,
F4, G5,
H4, H5,
J2, J3,
J4, J5
SSVDDQ
Power
Power for SD port, to be connected to SNVDDQ if
using 16-bit NAND. 1.8V, 2.5V, or 3.3V nominal.
-
-
D6
N/A
GVDDQ
Power
Power for miscellaneous IO. 1.8V, 2.5V, or 3.3V
nominal.
-
-
B9
B3
AVDDQ
Power
Power for internal PLL and USB serializer. 1.8V
nominal.
-
-
B7
N/A
XVDDQ
Power
Power for crystal or clock IO. 1.8V (clock) or 3.3V
(crystal) nominal.
-
-
D5, G4,
G5, G6,
G7, F7
D6, F6,
G6, J1
VDD
Power
Power for core. 1.8V nominal.
-
-
A10
N/A
VDD33a
Power
Power sequence control supply. 3.3V nominal.
-
-
B6
A3
UVSSQ
Power
Ground for all USB.
-
-
A9
B2
AVSSQ
Power
Ground for PLL.
-
-
E4, E5,
E6, E7,
F4, F5,
F6
B6, D5,
E4, E6,
F5
VGND
Power
Ground for core.
-
-
H5
Power
Domain
a. VDD33: In CYWB0124AB, the pin is no-connect internally. It handles power sequence control in future revisions, such as West Bridge Astoria. When
migrating to Astoria, it must be connected to the highest supply of the device. If USB is used, for example, then VDD33 must be connected to nominal
3.3V (because 3.3V is required for USB). VDD33 must always be supplied in Astoria.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
21
Pin Descriptions
2.2
Ball Map
Figure 2-1. 100 VFBGA Package Top View
Top View
1
2
3
4
5
6
7
8
9
10
A
ADV#
WE#
INT#
DRQ
D+
D-
UVALID
XTALIN
AVSSQ
VDDH
B
DQ[1]
DQ[0]
OE#
DACK
UVDDQ
UVSSQ
XVDDQ
XTALOUT
AVDDQ
C
DQ[4]
DQ[3]
DQ[2]
WAKEUP
TEST[1]
GPIO[1]
RESET#
C
D
DQ[7]
DQ[6]
DQ[5]
PVDDQ
VDD
VDDQ
TEST[0]
GPIO[0]
SD_D[1]
SD_D[0]
D
E
DQ[10]
DQ[9]
DQ[8]
VGND
VGND
VGND
VGND
TEST[2]
SD_D[3]
SD_D[2]
E
F
DQ[13]
DQ[12]
DQ[11]
VGND
VGND
VGND
VDD
SD_CLK
SD_D[5]
SD_D[4]
F
G
CE#
DQ[15]
DQ[14]
VDD
VDD
VDD
VDD
SD_CMD
SD_D[7]
SD_D[6]
G
H
A[5]
A[6]
A[7]
PVDDQ
SD_POW
NAND_IO[2]
SD_WP
H
J
A[3]
PCLK
A[4]
NAND_R/B# NAND_CE# NAND_ALE NAND_WP# NAND_IO[5] NAND_IO[3] NAND_IO[0] J
K
A[0]
A[1]
A[2]
NAND_RE# NAND_CE2# NAND_CLE NAND_IO[7] NAND_IO[6] NAND_IO[4] NAND_IO[1] K
1
2
3
XTALSLC[0] XTALSLC[1] NANDCFG
4
NAND_VDDQNAND_WE# SSVDDQ
5
6
7
8
9
A
RESETOUT B
10
POWER DOMAIN KEY
UVDDQ
GVDDQ
SSVDDQ
VGND
PVDDQ
SNVDDQ
XVDDQ
22
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Pin Descriptions
Figure 2-2. WLCSP Package Top View
1
2
3
4
Top View
5
6
7
8
9
A
TEST[0]
XTALIN
UVSSQ
D+
D-
PVDDQ
INT#
OE#
ADV#
A
B
TEST[2]
AVSSQ
AVDDQ
UVALID
UVDDQ
VGND
WE#
DQ[0]
DQ[1]
B
C
WAKEUP
RESET#
DACK#
DRQ#
DQ[2]
DQ[3]
DQ[4]
C
D
SD_WP
GPIO[0]
GPIO[1]
TEST[1]
VGND
VDD
DQ[5]
DQ[6]
DQ[7]
D
E
SD_D[0]
SD_D[1]
SD_D[2]
VGND
PVDDQ
VGND
DQ[8]
DQ[9]
DQ[10]
E
F
SSVDDQ
SD_D[3]
SSVDDQ
SSVDDQ
VGND
VDD
DQ[11]
DQ[13]
DQ[12]
F
G
SD_CLK
SD_D[4]
SD_D[5]
SD_POW
SSVDDQ
VDD
DQ[14]
CE#
DQ[15]
G
H
SD_D[6]
SD_D[7]
SD_CMD
SSVDDQ
SSVDDQ
A[4]
A[3]
A[1]
A[0]
H
J
VDD
SSVDDQ
SSVDDQ
SSVDDQ
SSVDDQ
A[7]
A[6]
A[5]
A[2]
J
1
2
3
4
5
6
7
8
9
XTALSLC[1] XTALSLC[0]
POWER DOMAIN KEY
UVDDQ
AVDDQ, VDD
SSVDDQ
VGND
PVDDQ
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
23
Pin Descriptions
24
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
3. Data Path
The following sections describe the transaction data path between each port. All the command names in the transaction
description are top level command description names. In a usage case, these command names are required to be translated
to the processor driver API according to the West Bridge Antioch SDK API Guide. For example, the “write to NAND” command is a top level command name, in the API case, it is translated to CyAnStorageWriteAsync().
Antioch supports the transfer of an odd number of bytes (for example 51 bytes). Because the interface of P-Port is a 16-bit
interface, the odd number byte in the last transaction is in DQ[7:0] for little Endian configuration and in DQ[15:8] for the big
Endian configuration.
3.1
Description
West Bridge Antioch has three interface ports: P-Port, S-Port, and U-Port. The following sections describe all possible data
paths between pairs of ports. Section 3.2 describes the behavior of the P-Port interface. Section 3.5 explains the endpoint
behavior in Antioch. Section 3.6 explains the DMA interface mechanism and how it interacts with the processor. Section 3.7
explains resource allocation. It is necessary to read these four sections before reading the data path sections (Section 3.8
through Section 3.18).
3.2
P-Port Interface
The processor port interface allows access to the endpoint buffer memory blocks and configuration registers. Random access
is allowed to the configuration registers. Configured the P-Port DQ bus to be in Little Endian or Big Endian mode through the
P-Port Interface Configuration Register. To reduce port address pin count, the end point buffers can be individually
addressed, but their contents are accessed in burst (FIFO) mode. Refer to Section 3.5 for details on endpoint buffers.
3.2.1
Modes of Operation
The processor port can function in one of the two modes:
■
Asynchronous mode
■
Synchronous mode
3.2.2
Asynchronous Mode
This is the default mode at power up. During this mode the CLK input is held LOW. This mode requires the use of the ADV#
pin, the address valid pin. The Address inputs are latched when ADV# is HIGH. When ADV# is LOW, the Address latch is
transparent whereby any change in Address is reflected to internal access logic. CE# needs to be asserted at least tCVS
before the ADV# rising edge and held asserted throughout the entire operation. ADV# must be toggled to latch the address
for every asynchronous read or write access.
This mode uses the industry-standard SRAM control bus (CE#, OE#, andf WE#). READ operations are initiated by bringing
CE# and OE# LOW while keeping WE# HIGH. Valid data will be driven out of the DQ bus after the specified access time has
elapsed.
WRITE operations occur when CE# and WE# are driven LOW. During asynchronous WRITE operations, the OE# level is a
“Don't Care,” and WE# will override OE#. The data to be written is latched on the rising edge of CE# or WE# (whichever
occurs first).
The most significant address A[7] determines whether configuration registers or EP buffer memory is accessed. When the
configuration memory is selected by asserting address A[7], the address bus points to an exact location of a configuration
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
25
Data Path
register. When A[7] is de-asserted, A[6:0] provide the address of the endpoint buffer being accessed. Access from within the
selected endpoint buffer is performed via internal address counters.
When the EP buffers are selected, each address change starts access at the top of the buffers. The DMA engine in the external processor is expected to maintain the correct access count.
In this mode the port interface works up to equivalent 33 MHz providing a port bandwidth up to 66 MB per second.
3.2.3
Synchronous Mode
Similar to the asynchronous mode, the synchronous mode can be used to access both the configuration registers and the EP
buffers. Address A[7] determines whether the configuration registers or the EP buffers are accessed. Unlike the asynchronous mode, all address, chip enable, and read/write enable inputs are asserted/de-asserted with respect to the CLK input.
These control inputs have to meet their respective setup and hold time constraints. Valid read data is placed on the DQ bus
after the specified clock-to-output access time. The DQ bus will tri-state after tCKHZ following a CLK rising edge with CE# deasserted. OE# is “don't care” during write or deselect cycles.
When the EP buffers are selected, each address change starts access at the top of the buffers. The DMA engine in the external processor is expected to maintain the correct access count.
In this mode, the processor interface port can work at clock speeds up to 33 MHz providing port bandwidth up to 66 MB per
second.
3.2.4
Switching the P-Port from Asynchronous Mode to Synchronous Mode
After reset, the P-Port of Antioch is in asynchronous mode. If the processor needs to switch the P-Port from asynchronous to
synchronous mode, configuration of the P-Port to synchronous mode is required after the selection of Endian mode (the second access). The following procedure shows how to configure the Antioch P-Port for synchronous mode:
1. After RESET# is de-asserted, the processor selects the Endian configuration in asynchronous mode (Antioch is defaulted
in asynchronous mode).
2. The processor sets the IFMODE field to “1” in the P-Port Interface Configuration Register to select the synchronous mode.
3. The processor configures its bus interface to synchronous mode.
4. Processor waits for tMODE time for Antioch to complete the switching from asynchronous to synchronous mode.
5. Processor can now configure the rest of the configuration registers in Antioch and download the firmware to the Antioch
Program RAM in synchronous mode.
Note Antioch does not allow switching between asynchronous and synchronous mode dynamically.
26
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.2.5
3.2.5.1
AC Timing Parameters
Asynchronous Mode
Table 3-1. Asynchronous Mode Timing Parameters
Min or
Max
Spec
Unit
Interface Bandwidth (MBPS)
Max
66.7
MBPS
tAA
Address to Data Valid
Max
30
ns
tOH
Data Output Hold from Address Change
Min
3
ns
tEA
Chip enable access time
Max
30
ns
tAADV
ADV# to Data Valid Access Time
Max
30
ns
tAVS
Address Valid to ADV# HIGH
Min
5
ns
tAVH
ADV# HIGH to Address Hold
Min
b
ns
tCVS
CE# LOW set-up time to ADV# HIGH
Min
5
ns
tVPH
ADV# HIGH Time
Min
15a
ns
ns
Parameter
Description
Read Timing Parameters
2
tVP
ADV# pulse width LOW
Min
7.5
tOE
OE# LOW to Data Valid
Max
22.5
ns
tOLZ
OE# LOW to Low-Z
Min
3
ns
tOHZ
OE# HIGH to High-Z
Max
22.5
ns
tLZ
CE# LOW to Low-Z
Min
3
ns
tHZ
CE# HIGH to High-Z
Max
22.5
ns
Min or
Max
Spec
Unit
Min
30
ns
Parameter
tCW
Write Timing Parameters
CE# LOW to Write End
tAW
Address Valid to Write End
Min
30
ns
tAS
Address Set-up to Write Start
Min
0
ns
tADVS
ADV# Set-up to Write Start
Min
0
ns
tWP
WE# Pulse Width
Min
22
ns
tWPH
WE# HIGH Time
Min
10
ns
tCPH
CE# HIGH Time
Min
10
ns
tAVS
Address Valid to ADV# HIGH
Min
5
ns
tAVH
ADV# HIGH to Address Hold
Min
2b
ns
tCVS
CE# LOW set-up time to ADV# HIGH
Min
5
ns
a
tVPH
ADV# HIGH Time
Min
15
ns
tVP
ADV# pulse width LOW
Min
7.5
ns
tVS
ADV# LOW to end of Write
Min
30
ns
tDW
Data Set-up to Write End
Min
18
ns
tDH
Data Hold from Write End
Min
0
ns
tWHZ
Write to DQ HIGH-Z Output
Max
22.5
ns
tWLZ
End of write to Low-Z output
Min
3
ns
a. In applications where the access cycle time is at least 60 ns, tVPH can be relaxed to 12 ns.
b. In applications where back-to-back accesses are not performed on different endpoint addresses, the minimum tAVH spec can be relaxed to zero nanoseconds.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
27
Data Path
Figure 3-1. Asynchronous Single Read Timing Parameters
A
Valid Address
tAA
tVPH
tAVS
tAVH
ADV#
tHZ
tVP
CE#
tAADV
tEA
tOE
OE#
tOHZ
WE#
DQ
tOLZ
High-Z
Valid Output
tLZ
Figure 3-2. Asynchronous Back-to-Back Read Timing Parameters
A
Valid Address
Valid Address
tAA
tVPH
tAVS
tOH
tAVH
ADV#
tHZ
tVP
CE#
tAADV
tEA
OE#
tOHZ
WE#
DQ
High-Z
Valid Output
Valid Output
tLZ
28
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
Figure 3-3. Asynchronous Back-to-Back Write Timing Parameters
A
Valid Address
tAVS
tVPH
Valid Address
tAVH
tVP
ADV#
tVS
CE#
tCW
OE#
tAW
tWPH
tWP
WE#
tAS
tDW
tOW
tDH
tADVS
DQ_IN
High-Z
Valid Input
Valid Input
tWHZ
tLZ
DQ_OUT
Figure 3-4. Asynchronous Read to Write Timing Parameters
A
Valid Address
ADV#
Valid Address
tAA
tVPH
tAVS
tAVS
tVPH
tAVH
tAVH
tVP
tVP
CE#
Valid Address
tVS
tAADV
tEA
tOE
OE#
tOHZ
tAW
tWP
WE#
tAS
DQ_IN
DQ_OUT
High-Z
tDH
Valid Input
tOLZ
High-Z
tDW
tOW
Valid Input
tWHZ
Valid Output
tLZ
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
29
Data Path
Figure 3-5. Asynchronous Write to Read Timing Parameters
A
Valid Address
tAVS
Valid Address
tAA
tAVH
tAVS
tVP
tAVH
ADV#
tVP
tVS
CE#
tAADV
tOE
OE#
tAW
tWP
WE#
tAS
DQ_IN
DQ_OUT
30
tDW
tDH
Valid Input
tWHZ
tOLZ
Valid Output
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.2.5.2
Synchronous Mode
Table 3-2. Synchronous Mode Timing Parameters
Parameter
Min or
Max
Description
Spec
Unit
FREQ
Interface clock frequency
Max
33
MHz
tCLK
Clock period
Min
30
ns
tCLKH
Clock HIGH time
Min
12
ns
tCLKL
Clock LOW time
Min
12
ns
tS
CE#/WE#/ADDR/DQ Setup time
Min
7.5
ns
tH
CE#/WE#/ADDR/DQ Hold time
Min
1.5
ns
tCO
Clock to valid data
Max
18
ns
tOH
Clock to data hold time
Min
2
ns
tHZ
OE# HIGH to data high-Z
Max
22.5
ns
tLZ
OE# LOW to data low-Z
Min
3
ns
tOE
OE# LOW to Data Valid
Max
22.5
ns
tWHZ
WE# Low to DQ High Z Output
Max
22.5
ns
tWLZ
WE# High to DQ Low Z Output
Min
3
ns
tCKHZ
Clock to data high-Z
Max
18
ns
tCKLZ
Clock to data low-Z
Min
3
ns
Figure 3-6. Synchronous Write Timing Parameters
tCLKH
tCLKL
CLK
tCLK
tH
tS
CE#
A[7:0]
An
An+1
An+2
An+4
An+3
WE#
OE#
DQ[15:0]
(input)
High-Z
DQ[15:0]
(output)
High-Z
tCO
tHZ
tOH
Dn
tLZ
Dn+1
tOE
Note:
- Assumes previous cycle had CE# deselected.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
31
Data Path
Figure 3-7. Synchronous Read Timing Parameters
tCLKH
tCLKL
CLK
tCLK
tH
tS
CE#
A[7:0]
An+1
An
An+2
An+4
An+3
WE#
OE#
DQ[15:0]
(input)
High-Z
DQ[15:0]
(output)
High-Z
tHZ
tOH
tCO
Dn
tLZ
Dn+1
tOE
Note:
- Assumes previous cycle had CE# deselected.
Figure 3-8. Synchronous Read (OE# Fixed Low) Timing Parameters
CLK
CE#
A[7:0]
tH
tS
Ax+1
Ax
Ax+2
WE#
OE#
tCO
DQ[15:0]
(output)
Dx-2
tCKHZ
tOH
Dx-1
Dx
Dx
Dx+1
Note:
- Assumes previous several cycles were Read.
32
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
Figure 3-9. Synchronous Read to Write (OE# Controlled) Timing Parameters
tCLKH
tCLKL
CLK
tCLK
tH
tS
CE#
A[7:0]
Ax+1
Ax
An
An+1
tH
tS
Dn
Dn+1
An+2
WE#
OE#
DQ[15:0]
(input)
High-Z
tOH
DQ[15:0]
(output)
Dx-2
Dx-1
Dn+2
tHZ
Dx
tCO
Note:
- Assumes previous several cycles were Read.
- (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline.
Figure 3-10. Synchronous Read to Write (OE# fixed LOW) Timing Parameters
tCLKH
tCLKL
CLK
tCLK
tH
tS
CE#
A[7:0]
Ax+1
Ax
Ax+2
An
An+1
WE#
tWHZ
OE#
tS
DQ[15:0]
(input)
DQ[15:0]
(output)
High-Z
tCO
Dx-2
tH
Dn
Dn+1
tOH
Dx
Dx-1
tCO
Note:
- Assumes previous several cycles were Read.
- In this scenario, OE# is held LOW.
- (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline.
- No operation is performed during the Ax+2 cycle (true turnaround operation)
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
33
Data Path
Figure 3-11. Synchronous Write to Read Timing Parameters
tCLKH
tCLKL
CLK
tCLK
tH
tS
CE#
A[7:0]
An+1
An
An+2
An+4
An+3
WE#
tWLZ
OE#
tH
tS
Dn
DQ[15:0]
(input)
DQ[15:0]
(output)
Dn+1
tCO
High-Z
tOH
Dn+2
tCKLZ
Note:
- Assumes previous cycle has CE# deselected.
- In this scenario, OE# is held LOW.
3.2.5.3
Other P-Port Timings
DRQ# Min Pulse Width (tDPW) - The minimum duration that DRQ# will be de-asserted following a DRQ acknowledgement
(clear of DMAVAL) is 110 ns in Async mode, or 5 P-Port clock (CLK) cycles in Sync mode.
Same Register Write-to-Read Holdoff (tWRHO) - A read of a particular register must wait for a holdoff period following a write
operation to that same register address to ensure that valid updated data is read. In Async mode, this holdoff time is 150ns
(there must be a valid ADV# cycle to ensure that valid updated data is read). In Sync mode, this holdoff time is 7 P-Port clock
(CLK) cycles.
Register Update-to-Read Holdoff (tURHO) - Some status registers are updated as side-effect from accesses to other registers (for example, clearing the DMAVAL field will automatically clear the associated endpoint buffer bit within the DRQ Status
Register or clear on read for P-Port Interrupt Register). A holdoff time must elapse from the first register access before the
update is reflected in a subsequent read operation. This holdoff time is identical to the tWRHO above.
Change of Mode Time (tMODE) - Time taken by Antioch to switch from asynchronous mode (default) to synchronous mode.
The processor must wait for tMODE time after setting the IFMODE field in the P-Port Interface Configuration Register, before
it attempts to access Antioch in synchronous mode. tMODE is 150ns.
34
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.3
S-Port Interface AC Timing Parameters
3.3.1
SD/MMC/MMC+ Timings
For all conditions, SD/MMC/MMC+ data is driven and sampled on the rising edge of SD_CLK.
Figure 3-12. SD/MMC Timing Waveform - All modes
tSDCLKH
tSDCLK
SD_CLK
tSDCLKL
tSDOS
tSDCKLZ
tSDOH
tSDCKHZ
SD_CMD/
SD_D0-D3
Output
SD_CMD/
SD_D0-D3
Input
tSDIS
tSDIH
Table 3-3. Common Timing Parameters for SD and MMC - During Identification Mode
Parameter
SDFREQ
Description
Min
SD_CLK Interface
clock frequency
Max
Units
400
kHz
tSDCLK
Clock period
2.5
us
tSDCLKH
Clock HIGH time
1.0
us
tSDCLKL
Clock LOW time
1.0
us
Table 3-4. Common Timing Parameters for SD and MMC - During Data Transfer Mode
Parameter
SDFREQ
Description
Min
Max
Units
SD_CLK Interface clock
frequency
5
48
MHz
20.8
200
ns
40
60
%
tSDCLK
Clock period
tSDCLKOD
Clock duty cycle
a
tSCLKR
Clock rise time
3
ns
tSCLKF
a
3
ns
Clock fall time
a. Clock rise/fall times measured between 0.1 and 0.9 of signal swing.
During data transfer mode, the SD_CLK output frequency can be configured by 8051 firmware as follows:
1. 20 MHz, for a card with frequency 0 - 20 MHz.
2. 24 MHz, for a card with frequency 0 - 26 MHz.
3. 48 MHz, for a card with frequency 0 - 52 MHz.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
35
Data Path
Table 3-5. Timing Parameters for SD - All Modes
Parameter
Description
Min
Max
Units
tSDIS
Input Setup time
4
tSDIH
Input Hold time
2.5
ns
tSDOS
Output Setup time
7
ns
tSDOH
Output Hold time
6
ns
tSDCKHZ
Clock to data high-Z
tSDCKLZ
Clock to data low-Z
ns
18
ns
3
ns
Table 3-6. Timing Parameters for MMC - All Modes
Parameter
Description
Min
Max
Units
tSDIS
Input Setup time
4
ns
tSDIH
Input Hold time
4
ns
tSDOS
Output Setup time
6
ns
tSDOH
Output Hold time
6
tSDCKHZ
Clock to data high-Z
tSDCKLZ
Clock to data low-Z
3.3.2
ns
18
ns
3
ns
NAND Timings
The asynchronous signaling to NAND devices is configured via firmware by programming internal registers to generate read/
write waveforms, and may vary based on device vendor and type.
3.4
Reset/Standby Timing Parameters
The Antioch reset mechanism is described in Chapter 6. The Standby mode is described in Section 8.4.
Figure 3-13. Reset and Standby Timing Diagram
Core
Power-Down
VDD
(core)
VDDQ
(I/O)
XTALIN up & stable
before WAKEUP
asserted
XTALIN
tWPW
tWH
WAKEUP
Mandatory
Reset Pulse
RESET#
RESETOUT
Standby
Mode
Hard Reset
Firmware Init
Complete
Mandatory
Reset Pulse
tRH
Firmware Init
Complete
Firmware Init
Complete
High-Z
tRPW
UVALID
USB Switch
Enabled
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘0’
36
tSLP
USB Switch
Disabled
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘1’
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘0’
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
Table 3-7. Reset and Standby Timing Parameters
Parameter
tSLP
Description
Conditions
Min.
Sleep Time
Max.
1
Unit
ms
Clock on XTALIN
1
ms
Crystal on XTALIN-XTALOUT
tWU
Wakeup Time from Standby Mode
5
ms
tWH
WAKEUP High Time
5
ms
tWPW
WAKEUP Pulse Width
5
ms
tRH
RESET# High Time
5
ms
Clock on XTALIN
1
ms
Crystal on XTALIN-XTALOUT
5
ms
1
ms
tRPW
tRR
3.5
RESET# Pulse Width
RESET# Recovery Time
Endpoints Overview
Antioch supports transfer of data among its three ports via endpoint (EP) buffering. Mailbox registers within Antioch facilitate
communication or message-passing between the 8051 MCU and the processor.
3.5.1
Logical Endpoints
■
Antioch supports 16 logical endpoints, which may be configured as shown in Figure 3-14.
■
EP2, EP4, EP6, and EP8 are dedicated to S-Port transfers. Each of these 4 endpoints may be individually allocated for
exclusive use by either P or U port (corresponding to Endpoint Buffers B in Figure 1-2).
■
EP3, EP5, EP7, EP9, EP10, EP11, EP12, EP13, EP14, and EP15 are allocated to the U-port to P-port path (corresponding to Endpoint Buffers A in Figure 1-2).
■
Endpoint allocation is done by the 8051 MCU within Antioch.
■
EP0 and EP1 are control/interrupt endpoints and are accessible only to the 8051 MCU within Antioch.
■
In addition to EP0 and EP1, the 8051 MCU within Antioch has access to EP2, EP4, EP6 and EP8.
■
Each endpoint can be configured to be “IN” or “OUT”. The processor performs DMA transfers to the IN endpoints and from
OUT endpoints. The processor cannot transfer from IN endpoint or to OUT endpoints.
■
There can be up to 10 logical endpoints that are active at any given point in time for the P-Port to U-Port path; there are up
to 4 logical endpoints combined for the U-Port to S-Port and the P-Port to S-Port paths. For example, if Antioch's U-Port is
not accessing the S-Port, the P-Port to S-Port path can use up to 4 logical endpoints. However, only one S-Port endpoint
can be accessed at any given point in time. An S-Port endpoint buffer can either be read from or written to at a time, never
both at the same time. The assignment and activation of endpoints is carried out in firmware. If the USB Host attempts to
access an endpoint that is inactive, it is sent a NAK.
■
During a DMA transfer request to the processor, the EPnDRQ field in the DRQ Status Register, CY_AN_MEM_P0_DRQ
indicates the logical endpoint for which the DMA Request was made. Because EP0 and EP1 are not accessible by the
processor port, EP0DRQ and EP1DRQ are reserved and are not asserted for DMA request to processor port.
■
Note that the processor and Host always use logical endpoint addressing during a DMA read or write access.
3.5.2
■
Physical Endpoints
Logical endpoints are mapped to physical endpoints. Physical endpoints can be dedicated to a logical endpoint or shared
between multiple logical endpoints. All logical endpoints that map to a single physical endpoint share all of its buffers.
Physical endpoints can only map to multiple logical endpoints in the same direction. When multiple logical endpoints are
mapped to a single physical endpoint, the logical endpoints will be served in a first-in-first-out basis. Logical to physical
endpoint mapping is dynamic and can be changed by 8051 firmware except for EP0 and EP1. EP0 and EP1 are always
mapped to dedicated physical EP0 and EP1 endpoints. Also, logical EP for ISO channel requires dedicated physical EP in
the U-Port to P-Port (USB host to external processor) path. For these ISO transfers, only endpoint numbers 3, 5, 7, and 9
can be used.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
37
Data Path
■
There are a total of 11 physical endpoints - 4 physical endpoints (equivalent to 4kB of buffering total) between the U-Port
and the P-Port, 4 physical endpoints between the U-Port and the S-Port, and 3 physical endpoints for EP0, EP1IN and
EP1OUT (accessed only by 8051).
■
EP0 is the default CONTROL endpoint, a bi-directional endpoint that uses a single 64-byte buffer for both IN and OUT
data.
■
EP1IN and EP1OUT use separate 64 byte buffers.
■
Logical endpoints {EP3, EP5, EP7, EP9, EP10, EP11, EP12, EP13, EP14, EP15} between U and P port can be mapped
to the 4 physical endpoints, EP3, EP5, EP7 and EP9, between the U-Port and the P-Port.
■
For P-to-S and U-to-S transfers 4 more 1Kbyte buffers are available. These buffers are allocated to physical endpoints
EP2, EP4, EP6, and EP8 by firmware. The number of buffers allocated to each of these physical endpoints depends on
the packet-size and whether the endpoints are single, double, triple or quad buffered. Figure 3-14 depicts valid endpoint
configurations between the U-Port and S-Port (for physical endpoints PEP2, PEP4, PEP6 and PEP8) or between the UPort and P-Port (for physical endpoints PEP3, PEP5, PEP7, and PEP9).
■
Transactions between the P-Port and the S-Port have a buffering capability equivalent to that between the U-Port and SPort.
Figure 3-14. Endpoint Configuration
38
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
Figure 3-15. Logical and Physical Endpoint Mapping to U-Port
EP0
Phy EP0
EP1
Phy EP1
8051
EP3
EP5
EP7
U – USB Port
EP9
Phy EP3
EP10
Phy EP5
EP11
Phy EP7
EP12
Phy EP9
P – Processor Port
EP13
EP14
EP15
3.6
EP2
Phy EP2
EP4
Phy EP4
EP6
Phy EP6
EP8
Phy EP8
Logical Endpoint
Physical Endpoint
S – Storage Port
DMA Overview
Antioch supports DMA mode data transfer. Antioch functions only as a slave and therefore does not master any DMA command. The processor issues and manages the DMA transfers to and from the Antioch endpoint buffers. The processor's most
significant address bit is used to indicate whether the operation to Antioch is to/from a register or to/from a buffer. The next 7
significant bits are used for addressing, out of which, during a DMA, the 4 least significant address bits A[3:0] are used to
access the 16 logical endpoint buffers. A[6:4] must be maintained at “0” during the operation. During a DMA Read transaction,
Antioch will pop data from the addressed endpoint buffer. During a DMA Write transaction, Antioch will push data into the
addressed endpoint buffer. DMA support for the processor port is from EP2-EP15 (EP0 and EP1 are not accessible from the
processor port; these EPs are only accessible from the 8051).
CE# is asserted (LOW) during a DMA operation. However, in async mode, CE# can be de-asserted (HIGH) after ADV# has
been de-asserted (HIGH) and the data has been read from the endpoint buffer in the case of a read operation, to interrupt the
DMA transfer. To return and continue DMA transfer from the same endpoint buffer, CE# is asserted (LOW) first followed by
ADV# assertion (LOW). The DMA transfer then continues from the same endpoint buffer. In sync mode, CE# can be deasserted any time during a DMA operation. When CE# is re-asserted, the DMA transfer is resumed with the same endpoint
buffer address as long as all the relevant timing parameters are met. It is not permitted to access a different endpoint buffer on
DMA re-assertion in either mode.
A DMA transfer can be interrupted to access a register by sending the appropriate register address on the address bus. It is
required that the DMA transfer to the particular endpoint be completed after the register access is complete. Antioch could
behave in the following two different ways during register access, depending on the two possible behaviors of the processor
DACK# signal (in ACK[Acknowledge] Mode):
1. DACK# (in ACK mode) is de-asserted by the processor during the register access, in which case Antioch de-asserts
DRQ#, but the EPnDRQ bit in the DRQ Status Register for the corresponding endpoint is not cleared. DRQ# is reasserted after time tDPW. When the register access is complete, the processor asserts DACK# (ACK mode) in response
to the DRQ# and the DMA transfer from that endpoint can continue.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
39
Data Path
2. DACK# (in ACK mode) remains asserted by the processor during the register access, in which case Antioch does not deassert DRQ#. The DMA access continues after the register access from where it was discontinued.
Note that when DACK# is configured to be in EOB (End-of-Burst) mode, DACK# is asserted at the end of the burst cycle, and
hence its behavior is not affected in any way when a DMA transfer is interrupted by a register access.
3.6.1
DMA Register and Signal Descriptions
The following registers control DMA operations (in the following description, EPnDRQ represents EP2DRQ to EP15DRQ):
1. DRQ Status Register (CY_AN_MEM_P0_DRQ - Read-Only to processor) contains a register bit for each endpoint indicating whether a DMA is requested (using the unmasked EPnDRQ bit). More than one endpoint buffer can have its EPnDRQ
bit set at a time. The DRQ# pin is asserted when one or more unmasked EPnDRQ bits are set. Although it is possible that
there are more than one unmasked EPnDRQ bits set in this register, only one DMA transfer can occur at a time. If there is
more than one buffer ready for DMA operations, the processor manages the priority between them.
2. DRQ Mask Register (CY_AN_MEM_P0_DRQ_MASK) masks the corresponding bits in the DRQ Status Register
(CY_AN_MEM_P0_DRQ). A “0” in the DRQ Mask Register (CY_AN_MEM_P0_DRQ_MASK) masks the corresponding
bit in the DRQ Status Register (CY_AN_MEM_P0_DRQ), while a “1” unmasks the same. The state of the bits in the DRQ
Status Register reflects the unmasked value, i.e., the DRQ Mask Register and the DRQ Status Register must both be read
and interpreted to determine whether a particular DRQ Status bit is masked or unmasked. If an EPnDRQ bit in this register is “0”, the corresponding DMA Read/Write bit in the DRQ Status Register (CY_AN_MEM_P0_DRQ) should be ignored.
3. The Endpoint Buffer DMA Register is used to initiate and terminate DMA transfers from/to the processor. Bit0 to Bit10 of
Endpoint Buffer DMA Register (CY_AN_MEM_P0_EP2_DMA_REG to CY_AN_MEM_P0_EP15_DMA_REG) contain the
number of bytes that are in the DMA transfer. Bit 12 is the DMAVAL field. When DMAVAL=”1”, a DMA transfer is active
and the value in the COUNT field indicates the number of bytes to be transferred. A DRQ# assertion with that particular
endpoint field set in the DRQ Status Register signifies that the transfer by the processor can proceed. The DMAVAL field
is cleared to “0” at the end of the DMA transfer. Processor writing “0” to the DMAVAL field in this register clears the
EPnDRQ bit for the corresponding endpoint buffer in the DRQ Status Register (CY_AN_MEM_P0_DRQ).
40
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
There are two DMA signal pins as follows (the polarity of these pins is configurable via the DRQPOL and DACKPOL bits in
the P-Port Interface Configuration Register; however, the following discussions and illustrations assume the default polarity).
1. DRQ# (DMA Request) from Antioch to the processor to indicate that Antioch is ready for a DMA transfer to be carried out.
This signal is asserted when at least one of the endpoint buffers has its EPnDRQ bit set in the DRQ Status Register
(CY_AN_MEM_P0_DRQ), after applying the mask bit set in the DRQ Mask Register (CY_AN_MEM_P0_DRQ_MASK).
Figure 3-16 shows the DRQ and DRQ Mask registers block diagram.
CY_AN_MEM_P0_DRQ_MASK
(DRQ Mask Register)
MEP2DRQ
MEP3DRQ
MEP4DRQ
MEP5DRQ
MEP6DRQ
MEP7DRQ
MEP8DRQ
MEP9DRQ
MEP10DRQ
MEP11DRQ
MEP12DRQ
MEP13DRQ
MEP14DRQ
MEP15DRQ
CY_AN_MEM_P0_DRQ
(DRQ Status Register)
Figure 3-16. Antioch's DRQ and DRQ Mask Registers Block Diagram
EP2DRQ
EP3DRQ
EP4DRQ
EP5DRQ
EP6DRQ
EP7DRQ
EP8DRQ
EP9DRQ
EP10DRQ
EP11DRQ
EP12DRQ
EP13DRQ
EP14DRQ
EP15DRQ
DRQ#
DRQINT
2. Configurable DACK# (DMA Acknowledge) signal from the processor to Antioch, which can be configured to behave in
ACK (Acknowledge) or EOB (End-of-Burst) mode. This pin can be configured to behave in either ACK or EOB mode
based on the DACKEOB field in the P-Port Interface Configuration Register. The DACK# signal is not qualified by CE# or
any other signal. DACK# is used if the processor requires that the DRQ# signal be pulsed between DMA operations. If the
DACK# signal is configured to be in ACK mode, and there is at least one unmasked pending DMA request in the DRQ
Status Register, DRQ# is pulsed when DACK# is de-asserted and the DMAVAL field has been cleared. If the signal is configured to be in EOB mode, and there is at least one unmasked pending DMA request in the DRQ Status Register, DRQ#
is pulsed after the DMAVAL field has been cleared and DACK# is asserted. If there is at least one other subsequent DRQ
request pending, DRQ# will remain de-asserted for tDPW time before re-asserting.
a. ACK Mode: DACK# is asserted by the processor, in response to a DRQ# assertion, after it has read the DRQ Status
Register and the Endpoint Buffer DMA Register, to acknowledge receipt of the DRQ# signal. During a read from
Antioch, the read data is expected in the clock cycle following the DACK# assertion. During a write to Antioch, the
write data is supplied in the same clock cycle as the DACK# assertion.
b. EOB Mode: DACK# is asserted by the processor at the end of a DMA transaction. The DMAVAL field in the Endpoint
Buffer DMA Register for the relevant buffer has to be cleared by a processor write either before or in the same clock
cycle as the DACK# assertion.
3. The INT# pin can also signal a DMA Request (similar to DRQ behavior) to the processor, along with the DRQINT field in
the P-Port Interrupt Register. This DRQINT can be masked using the MDRQINT field in the P-Port Interrupt Mask Register
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
41
Data Path
(independent from the settings in the DRQ Mask Register). Refer to Figure 3-16 for mechanism of DRQ# and DRQINT
generation.
Note that while DMA waveforms shown in the following sections depict synchronous timings, the asynchronous behavior is
identical in steps. Also note that the following sections describe a generic DMA transaction. Procedures specific to a particular
transaction are described in Section 3.8 to Section 3.18. For example, during a read from Antioch, DMAVAL is set either by
the processor or by Antioch (on behalf of the USB host) depending on whether the read is from the S-Port or from the U-Port.
The information in this section is to be used in conjunction with that in Section 3.8 through Section 3.18.
3.6.2
DMA Read and Write Procedures in ACK Mode
Figure 3-17. DMA Read from Antioch in ACK Mode
DRQ# re-asserted only if
there is at least one
unmasked pending
request in the DRQ
Status Register
tDPW
DRQ#
DACK#
(ACK)
CE#
R/W#
A[7:0]
Reg
Addr
DQ[15:0]
Reg
Addr
Qn
DRQ Status
Register
Read
3.6.2.1
EP
Addr
EP
Addr
Qm
EP
Addr
EP
Addr
Qn
Qn+1
Endpoint Buffer
DMA Register
Read
Reg
Addr
Qn+2
Qn+3
Reg
Addr
Dm
Write to Endpoint
Buffer DMA Register
sets DMAVAL field = 0
Procedure for a DMA Read from Antioch
1. When a particular OUT endpoint buffer is full with the read data, Antioch writes “1” to the corresponding EPnDRQ bit in the
DRQ Status Register, and it writes the COUNT and sets the DMAVAL field to “1” in the Endpoint Buffer DMA Register.
2. If that particular EPnDRQ bit is not masked, Antioch asserts DRQ# to the processor.
3. The processor reads the DRQ Status Register and the Endpoint Buffer DMA Register and then asserts DACK#.
4. The processor reads data from the Antioch endpoint buffers via DMA.
5. When the DMA transfer is complete, the processor writes “0” to the DMAVAL field of Endpoint Buffer DMA Register. This
clears the DMA Requested bit in the DRQ Status Register. The processor then de-asserts DACK#.
6. Antioch de-asserts DRQ#.
7. If there is any buffer that has its DMA Requested bit set to “1” in the DRQ Status Register and is unmasked according to
the DRQ Mask Register registers, DRQ# is asserted and the process repeats from step 2 (see Figure 3-17).
42
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.6.2.2
Procedure for a DMA Write to Antioch
Figure 3-18. DMA Write to Antioch in ACK Mode
DRQ# re-asserted only if
there is at least one
unmasked pending
request in the DRQ
Status Register
tDPW
DRQ#
DACK#
(ACK)
CE#
R/W#
A[7:0]
Reg
Addr
EP
Addr
Reg
Addr
DQ[15:0]
Qn
Dn
Qm
DRQ Status
Register
Read
EP
Addr
EP
Addr
EP
Addr
Dn+1
Dn+2
Dn+3
Reg
Addr
Reg
Addr
Dm
Write to Endpoint
Buffer DMA Register
sets DMAVAL field = 0
Endpoint Buffer
DMA Register
Read
1. The DMA write operation begins with the processor writing to the COUNT and DMAVAL fields in the Endpoint Buffer DMA
Register. Data sent to the USB host are sent as one complete packet. Data sizes depend on endpoint type: 512 bytes for
bulk endpoint and 1024 bytes for interrupt and isochronous endpoints.
2. Antioch sets the corresponding bit in the DRQ Status Register, and if that particular EPnDRQ bit is not masked, asserts
the DRQ# pin to the processor.
3. The processor reads the DRQ Status Register and then asserts DACK#.
4. The processor transfers data to the Antioch endpoint buffers via DMA.
5. When the DMA transfer is complete, the processor writes “0” to the DMAVAL field in the Endpoint Buffer DMA Register.
This clears the DMA Requested bit in the DRQ Status Register. The processor then de-asserts DACK#.
6. Antioch de-asserts DRQ#.
7. The next DMA write operation, if any, begins from step 2 (see Figure 3-18).
3.6.3
3.6.3.1
DMA Read and Write Procedures in EOB Mode
Procedure for a DMA Read from Antioch
Figure 3-19. DMA Read from Antioch in EOB Mode
DRQ# re-asserted only if
there is at least one
unmasked pending
request in the DRQ
Status Register
tDPW
DRQ#
DACK#
(EOB)
CE#
R/W#
A[7:0]
DQ[15:0]
Reg
Addr
Reg
Addr
Qn
DRQ Status
Register
Read
EP
Addr
Qm
EP
Addr
EP
Addr
EP
Addr
Qn
Qn+1
Reg
Addr
Qn+2
Endpoint Buffer
DMA Register
Read
Qn+3
Reg
Addr
Dm
Write to Endpoint
Buffer DMA Register
sets DMAVAL field = 0
1. When a particular OUT endpoint buffer is full with the read data, Antioch writes to the corresponding bits in the DRQ Status Register, and it writes to the COUNT field and sets the DMAVAL field to “1” in the Endpoint Buffer DMA Register.
2. If that particular EPnDRQ bit is not masked, Antioch asserts the DRQ# to the processor.
3. The processor reads the DRQ Status Register and Endpoint Buffer DMA Register and sets up its internal DMA engine.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
43
Data Path
4. The processor reads data from the Antioch endpoint buffers via DMA.
5. When the DMA transfer is complete, the processor writes “0” to the DMAVAL field in the Endpoint Buffer DMA Register
and asserts the DACK# signal. This causes Antioch to de-assert DRQ#.
6. If there is any buffer that has its DMA Requested bit set to “1” in the DRQ Status Register and is unmasked according to
the DRQ Mask Register, DRQ# is asserted and the process repeats from step 2 (see Figure 3-19).
3.6.3.2
Procedure for a DMA Write to Antioch
Figure 3-20. DMA Write to Antioch in EOB Mode
DRQ# re-asserted only if
there is at least one
unmasked pending
request in the DRQ
Status Register
tDPW
DRQ#
DACK#
(EOB)
CE#
R/W#
A[7:0]
DQ[15:0]
Reg
Addr
Reg
Addr
Qn
DRQ Status
Register
Read
Qm
EP
Addr
EP
Addr
EP
Addr
EP
Addr
Reg
Addr
Dn
Dn+1
Dn+2
Dn+3
Dm
Endpoint Buffer
DMA Register
Read
Reg
Addr
Write to Endpoint
Buffer DMA Register
sets DMAVAL field = 0
1. The DMA write operation begins with the processor writing to the COUNT and DMAVAL fields in the Endpoint Buffer DMA
Register. Data sent to the USB host are sent as one complete packet. Data sizes depend on endpoint type: 512 bytes for
bulk endpoint and 1024 bytes for interrupt and isochronous endpoints.
2. Antioch sets the corresponding bit in the DRQ Status Register and if that particular EPnDRQ bit is not masked, asserts the
DRQ# pin to the processor.
3. The processor reads the DRQ Status Register and sets up its internal DMA engine.
4. The processor transfers data to the Antioch endpoint buffers via DMA.
5. When the DMA transfer is complete, the processor writes “0” to the DMAVAL field in the Endpoint Buffer DMA Register
and asserts the DACK# signal. This causes Antioch to de-assert DRQ#.
6. The next DMA write operation, if any, begins from step 2 (see Figure 3-20).
3.6.4
Zero Length Data Packet (P-Port U-Port)
In the USB protocol, a Zero Length data packet is sent either by the Host or by Antioch (device) to indicate completion of a
function.
3.6.4.1
Antioch Receives a Zero Length Data Packet from the Host
When Antioch receives a Zero Length data packet, which is sent by the Host through the U-Port, the corresponding EPnDRQ
field in the DRQ Status Register is set to “1” and DRQ# at P-Port is asserted (if the corresponding MEPnDRQ field in the DRQ
Mask Register is not masked). When the processor receives the DRQ, it reads the Endpoint Buffer DMA Register. If the
COUNT field in the Endpoint Buffer DMA Register is zero, this indicates that a Zero Length data packet has been received.
The processor is required to clear the EPnDRQ field by resetting the DMAVAL field to zero (“0”).
3.6.4.2
Antioch Sends a Zero Length Data Packet to the Host
When the processor transfers a Zero Length data packet through Antioch to the Host, the processor first needs to write zero
to the COUNT field in the Endpoint Buffer DMA Register and set the DMAVAL field to one (“1”). The corresponding EPnDRQ
field in the DRQ Status Register is set to “1” and DRQ# at P-Port is asserted (if the corresponding MEPnDRQ field in the DRQ
Mask Register is not masked). When the processor receives the DRQ, it resets the DMAVAL field in the Endpoint Buffer DMA
44
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
Register to zero (“0”) for committing the data packet transfer. When the data packet transfer is committed, Antioch checks the
COUNT field. If the COUNT field is zero, Antioch sends a Zero Length data packet to the Host through the U-Port.
Table 3-8. DRQ Status Register
DRQ Status Register
CY_AN_MEM_P0_DRQ
x'A0
When the DRQ# asserts, processor needs to read CY_AN_MEM_P0_DRQ0 and CY_AN_MEM_P0_DRQ1 to find out which endpoint buffer(s) have asserted
the DRQ#.
Field Name
Descriptions
EP2DRQ - EP15DRQ
These fields indicate which endpoint buffer(s) assert the DRQ#
RW
Reset
1:0
Bit
Field
Reserved
Description
R
0
2
EP2DRQ
Endpoint 2 Buffer DRQ Status
0: Endpoint 2 buffer has no DRQ
1: Endpoint 2 buffer has DRQ
R
0
3
EP3DRQ
Endpoint 3 Buffer DRQ Status
0: Endpoint 3 buffer has no DRQ
1: Endpoint 3 buffer has DRQ
R
0
4
EP4DRQ
Endpoint 4 Buffer DRQ Status
0: Endpoint 4 buffer has no DRQ
1: Endpoint 4 buffer has DRQ
R
0
5
EP5DRQ
Endpoint 5 Buffer DRQ Status
0: Endpoint 5 buffer has no DRQ
1: Endpoint 5 buffer has DRQ
R
0
6
EP6DRQ
Endpoint 6 Buffer DRQ Status
0: Endpoint 6 buffer has no DRQ
1: Endpoint 6 buffer has DRQ
R
0
7
EP7DRQ
Endpoint 7 Buffer DRQ Status
0: Endpoint 7 buffer has no DRQ
1: Endpoint 7 buffer has DRQ
R
0
8
EP8DRQ
Endpoint 8 Buffer DRQ Status
0: Endpoint 8 buffer has no DRQ
1: Endpoint 8 buffer has DRQ
R
0
9
EP9DRQ
Endpoint 9 Buffer DRQ Status
0: Endpoint 9 buffer has no DRQ
1: Endpoint 9 buffer has DRQ
R
0
10
EP10DRQ
Endpoint 10 Buffer DRQ Status
0: Endpoint 10 buffer has no DRQ
1: Endpoint 10 buffer has DRQ
R
0
11
EP11DRQ
Endpoint 11 Buffer DRQ Status
0: Endpoint 11 buffer has no DRQ
1: Endpoint 11 buffer has DRQ
R
0
12
EP12DRQ
Endpoint 12 Buffer DRQ Status
0: Endpoint 12 buffer has no DRQ
1: Endpoint 12 buffer has DRQ
R
0
13
EP13DRQ
Endpoint 13 Buffer DRQ Status
0: Endpoint 13 buffer has no DRQ
1: Endpoint 13 buffer has DRQ
R
0
14
EP14DRQ
Endpoint 14 Buffer DRQ Status
0: Endpoint 14 buffer has no DRQ
1: Endpoint 14 buffer has DRQ
R
0
15
EP15DRQ
Endpoint 15 Buffer DRQ Status
0: Endpoint 15 buffer has no DRQ
1: Endpoint 15 buffer has DRQ
R
0
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
45
Data Path
Table 3-9. DRQ Mask Register
DRQ Mask Register
CY_AN_MEM_P0_DRQ_MASK
x'A1
This register is used to mask or unmask the endpoint buffer DRQs.
Field Name
Descriptions
MEP2DRQ - MEP15DRQ
Bit
These fields are used to enable or disable the corresponding DRQ.
Field
Description
RW
Reset
1:0
Reserved
R
0
2
MEP2DRQ
Endpoint 2 Buffer DRQ Mask
0: Disable endpoint 2 buffer DRQ
1: Enable endpoint 2 buffer DRQ
RW
0
3
MEP3DRQ
Endpoint 3 Buffer DRQ Mask
0: Disable endpoint 3 buffer DRQ
1: Enable endpoint 3 buffer DRQ
RW
0
4
MEP4DRQ
Endpoint 4 Buffer DRQ Mask
0: Disable endpoint 4 buffer DRQ
1: Enable endpoint 4 buffer DRQ
RW
0
5
MEP5DRQ
Endpoint 5 Buffer DRQ Mask
0: Disable endpoint 5 buffer DRQ
1: Enable endpoint 5 buffer DRQ
RW
0
6
MEP6DRQ
Endpoint 6 Buffer DRQ Mask
0: Disable endpoint 6 buffer DRQ
1: Enable endpoint 6 buffer DRQ
RW
0
7
MEP7DRQ
Endpoint 7 Buffer DRQ Mask
0: Disable endpoint 7 buffer DRQ
1: Enable endpoint 7 buffer DRQ
RW
0
8
MEP8DRQ
Endpoint 8 Buffer DRQ Mask
0: Disable endpoint 8 buffer DRQ
1: Enable endpoint 8 buffer DRQ
RW
0
9
MEP9DRQ
Endpoint 9 Buffer DRQ Mask
0: Disable endpoint 9 buffer DRQ
1: Enable endpoint 9 buffer DRQ
RW
0
10
MEP10DRQ
Endpoint 10 Buffer DRQ Mask
0: Disable endpoint 10 buffer DRQ
1: Enable endpoint 10 buffer DRQ
RW
0
11
MEP11DRQ
Endpoint 11 Buffer DRQ Mask
0: Disable endpoint 11 buffer DRQ
1: Enable endpoint 11 buffer DRQ
RW
0
12
MEP12DRQ
Endpoint 12 Buffer DRQ Mask
0: Disable endpoint 12 buffer DRQ
1: Enable endpoint 12 buffer DRQ
RW
0
13
MEP13DRQ
Endpoint 13 Buffer DRQ Mask
0: Disable endpoint 13 buffer DRQ
1: Enable endpoint 13 buffer DRQ
RW
0
14
MEP14DRQ
Endpoint 14 Buffer DRQ Mask
0: Disable endpoint 14 buffer DRQ
1: Enable endpoint 14 buffer DRQ
RW
0
15
MEP15DRQ
Endpoint 15 Buffer DRQ Mask
0: Disable endpoint 15 buffer DRQ
1: Enable endpoint 15 buffer DRQ
RW
0
46
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
Table 3-10. Endpoint Buffer DMA Register
Endpoint Buffer DMA Registers
CY_AN_MEM_P0_EP2_DMA_REG
CY_AN_MEM_P0_EP3_DMA_REG
CY_AN_MEM_P0_EP4_DMA_REG
CY_AN_MEM_P0_EP5_DMA_REG
CY_AN_MEM_P0_EP6_DMA_REG
CY_AN_MEM_P0_EP7_DMA_REG
CY_AN_MEM_P0_EP8_DMA_REG
CY_AN_MEM_P0_EP9_DMA_REG
CY_AN_MEM_P0_EP10_DMA_REG
CY_AN_MEM_P0_EP11_DMA_REG
CY_AN_MEM_P0_EP12_DMA_REG
CY_AN_MEM_P0_EP13_DMA_REG
CY_AN_MEM_P0_EP14_DMA_REG
CY_AN_MEM_P0_EP15_DMA_REG
x'A2
x'A3
x'A4
x'A5
x'A6
x'A7
x'A8
x'A9
x'AA
x'AB
x'AC
x'AD
x'AE
x'AF
When the endpoint buffer event occurs, the byte count and DMA valid indicators are stored into the corresponding register. Processor requires reading the
corresponding register to obtain the endpoint buffer byte count for setting up its DMA controller.
Field Name
Descriptions
COUNT
This field indicates number of bytes in the endpoint buffer to be transferred through the processor's DMA.
DMAVAL
These fields indicate what endpoint buffer event (e.g. read or write) assert the DRQ
Bit
10:0
Field
COUNT
11
Description
RW
Reset
Endpoint Buffer Block Size in Bytes (up to 512 or 1024 bytes depending on Endpoint configuration)
COUNT is valid when DMAVAL = 1
RW
0
R
0
RW
0
R
0
Reserved
12
DMAVAL
15:13
3.7
DMA Valid indication
0: No DMA in process
1: DMA process active
Reserved
Resource Allocation
Antioch facilitates sharing of the following buses with an external device. When Antioch is not allocated the resource, it places
the external bus in tri-state mode.
■
SD External Bus
■
NAND External Bus
■
D+/D- Buses
The following registers are used to set up resource allocation, and they need to be loaded by the processor during configuration:
■
External Bus Allocation Register, CY_AN_MEM_P0_RSE_ALLOCATE, contains two bits per resource; an Availability
Semaphore bit to indicate whether the resource is available or not and an Allocation bit that shows ownership of the
resource. Ownership of an external bus can be between Antioch (bus enabled) or an external device (bus tri-stated). This
register needs to be loaded during configuration and can also be modified dynamically.
■
External Bus Allocation Mask Register, CY_AN_MEM_P0_RES_MASK, is used to mask the fields in the Resource Allocation Register, CY_AN_MEM_P0_RSE_ALLOCATE. When enabled, the mask causes the corresponding fields of the
External Bus Allocation Register to be read-only. For example, while MSDIOBUS = '00' (mask enabled), the value of
SDIOAVI cannot be changed.
The External Bus Allocation Register allows each of the SD, NAND, and USB D+/D- external buses to be controllably
enabled/disabled, thereby providing a method to manage bus ownership between Antioch (bus enabled) and an external
device such as the processor (bus tri-stated). Ownership is assigned by writing a '1' to the external bus availability semaphore
(e.g. SDIOAVI), with the owner determined by the value of the external bus allocation bit (e.g. SDIOALLO). A write of '1' to the
semaphore will perform a “test-and-set” operation, where new ownership will be assigned only if the existing value of the
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
47
Data Path
semaphore was '0' (indicating available). If the semaphore had a prior value of '1' (indicating “allocated”), then control of the
external bus already belongs to another owner. In this case, the write operation is unsuccessful to that resource field - the
command to set the semaphore must be reissued only after the semaphore is released (written with '0') by the other owner. A
request to relinquish Semaphore ownership is done through Mailbox messaging. Similarly, notification that a requested
Semaphore has been released is also done through Mailbox messaging. The use of the semaphore ensures that any external
bus state changes (enabled to tri-stated, or vice versa) will happen cleanly.
When the semaphore bit is '0' (available), the external bus is tri-stated but not explicitly allocated to a particular owner
(Antioch or external device). When available, an external bus can be enabled by 8051 write of '1' to the semaphore. As long
as the 8051 owns the semaphore, the 8051 must release its ownership before the processor is allowed to write to tri-state an
external bus. However, if the external bus is in tri-state but the semaphore status is “allocated” and owned by external device
(processor), then the processor must release the semaphore before the bus can be enabled by 8051. In this case, the processor will be notified of a request to enable the external bus by Mailbox message (thereby triggering interrupt).
Writing to the availability semaphores can be masked by the External Bus Allocation Mask Register. A value of '11' in the
mask field enables the write, while a mask value of '00' prevents the write operation to that field.
Usage examples:
Case 1 - External device (processor) owns the SD bus, when Antioch 8051 attempts to enable the SD bus.
1. Initially, SDIOAVI = '1' to indicate “allocated”. SDIOALLO = '1' to indicate “tri-state” (owned by external device). The SD
bus is initially tri-stated.
2. The 8051 writes '1' to SDIOAVI to attempt to enable the bus. Because the semaphore is already owned by the external
device, no bus state change occurs.
3. 8051 reads that the Semaphore is still not available, causing a Mailbox message from 8051 to processor to be sent (with
an interrupt to processor).
4. The processor reads P-Port Mailbox. It identifies a request for Antioch to enable the SD interface.
5. If processor is finished with its SD transactions and approves Antioch's enabling of the SD interface, it writes '0' to the
SDIOAVI semaphore to thereby relinquish ownership.
6. The processor notifies 8051 that the SD Semaphore has been released by sending an 8051 Mailbox message.
7. The 8051 re-issues its write to the semaphore. SDIOAVI and SDIOALLO becomes '1' and '0' respectively. The SD bus
becomes enabled.
8. The 8051 rechecks the semaphore status. Step 3 repeats if still not available.
Case 2 - Antioch owns the SD bus, when external device (processor) attempts to tri-state the SD bus.
1. Initially, SDIOAVI = '1' to indicate “allocated”. SDIOALLO = '0' to indicate allocation to Antioch (bus enabled).
2. The processor writes '1' to SDIOAVI to attempt to tri-state the bus. Because the semaphore is already owned by Antioch
(8051), no bus state change occurs.
3. The processor reads that the SD Semaphore is still not available, causing it to send an 8051 Mailbox message to 8051 to
request release of ownership.
4. The 8051 reads Mailbox to detect the request to change ownership (to tri-state the bus). The 8051 will handle all in-process data transfers to ensure that the tri-state change does not corrupt data in the external SD memory. At the earliest that
8051 can hand off control cleanly, it writes '0' to the SDIOAVI semaphore to release ownership. The SD bus becomes tristated when the semaphore becomes “available”.
5. The 8051 sends a P-Port Mailbox message to the processor to notify that ownership has been released (triggering an
interrupt to the processor).
6. The processor reissues its write to the resource semaphore. SDIOAVI and SDIOALLO becomes '1' and '1' respectively.
The SD bus remains tri-stated, and this external bus resource becomes owned by the processor.
When an S-Port external bus (NAND or SD/MMC/MMC+) is enabled for access by Antioch, the 8051 firmware arbitrates
access privileges between either processor (P-Port) or USB Host (U-Port) data path, based on commands received through
Mailbox or USB control packets. When an external memory resource is allocated to a port, the other port does not have read
or write privileges to it. The processor sends Mailbox messages to request or release ownership.
48
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
Table 3-11. External Bus Allocation Register
External Bus Allocation Registers
CY_AN_MEM_P0_RSE_ALLOCATE
x'98
This register is used for resource allocation for the S-Port and U-Port external buses.
Field Name
Descriptions
SDIOAVI
SD External Bus Availability Semaphore. A value of '0' indicates that there is no owner of the SD external bus (bus in tristate). Write of '1' to the semaphore will grant ownership only if the field value first tests as '0' (otherwise, write will not occur
and ownership not change). Owner can be external device (tri-state), or Antioch (bus enabled) as indicated by the SDIOALLO field. When the value is '1', the owner of the bus is indicated by SDIOALLO.
SDIOALLO
SD External Bus Allocation - this field indicates the owner of the S-Port SD external bus. A value of '0' indicates the bus is
allocated to Antioch (bus enabled), while '1' indicates that the bus is allocated to an external device (bus tri-stated).
NANDAVI
NAND External Bus Availability Semaphore. A value of '0' indicates that there is no owner of the NAND external bus (bus in
tri-state). Write of '1' to the semaphore will grant ownership only if the field value first tests as '0' (otherwise, write will not
occur and ownership not change). Owner can be external device (tri-state), or Antioch (bus enabled) as indicated by the
NANDALLO field. When the value is '1', the owner of the bus is indicated by NANDALLO.
NANDALLO
NAND External Bus Allocation - this field indicates the owner of the S-Port NAND external bus. A value of '0' indicates the
bus is allocated to Antioch (bus enabled), while '1' indicates that the bus is allocated to an external device (bus tri-stated).
USBAVI
USB External Bus Availability Semaphore. A value of '0' indicates that there is no owner of the D+/D- USB external bus (will
be in tri-state). Write of '1' to the semaphore will grant ownership only if the field value first tests as '0' (otherwise, write will
not occur and ownership not change). Owner can be external device (tri-state), or Antioch (bus enabled) as indicated by the
USBALLO field. When the value is '1', the owner of the bus is indicated by USBALLO.
USBALLO
USB External Bus Allocation - this field indicates the owner of the U-Port D+/D- external bus. A value of '0' indicates the bus
is allocated to Antioch (bus enabled), while '1' indicates that the bus is allocated to an external device (bus tri-stated).
Bit
Field
a
Description
SD External Bus Availability Semaphore 0: Available 1: Allocated
0
SDIOAVI
1
SDIOALLOa
SD External Bus Allocation
0: Allocated to Antioch (S-Port)
1: Tri-State (allocated to external device)
2
NANDAVI
NAND Flash External Bus Availability Semaphore
0: Available
1: Allocated
3
NANDALLO
4
RW
SRW*
Reset
b
0
R
1
SRW*
1
NAND Flash External Bus Allocation
0: Allocated to Antioch (S-Port)
1: Tri-State (allocated to external device)
R
0
USBAVIc
USB External Bus Availability Semaphore
0: Available
1: Allocated
SRW*
0
5
USBALLO
USB External Bus Allocation
0: Allocated to Antioch (U-Port)
1: Tri-State (allocated to external device)
R
1
6
USBTRAVI
(Reserved)
USB Transceiver Availability Semaphore (Reserved)
R
0
7
USBTRALO
(Reserved)
USB Transceiver Allocation (Reserved)
R
0
8
FORCE
(Reserved)
Reserved
R
0
Reserved
R
U/D
15:8
a. The SDIOAVI and the SDIOALLO fields control all but the SD_POW pin of the SD interface.
b. “SRW*” indicates fields with normal read and semaphore conditional writes. Bits 0, 2, and 4 are hardware semaphore bits which provide autonomous testand-set functionality to manage ownership between Antioch (bus enabled) and external device (bus tri-state). A write to set this bit will not occur if the prior
value tests as '1' (indicating semaphore is already owned). Only the owner of the external bus resource can write to release the semaphore. For example,
if SDIOAVI='1' and SDIOALLO='0', then Antioch owns this semaphore and hence the processor is unable to clear or take ownership by writing to this semaphore.
c. The USBAVI and the USBALLO fields control the D+ and D- pins, but not the UVALID pin of the U-Port.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
49
Data Path
Table 3-12. External Bus Allocation Mask Register
External Bus Allocation Mask Registers
CY_AN_MEM_P0_RES_MASK
x'9A
This register is used to enable or disable the selection of allocation in the CY_AN_MEM_P0_RSE_ALLOCATE register
Field Name
Descriptions
MSDIOBUS
This field is used to enable or disable the selection of the allocation of SD Port. When mask is enabled, the SD bus availability semaphore bit becomes read-only.
MNANDBUS
This field is used to enable or disable the selection of the allocation of NAND Port. When mask is enabled, the NAND bus
availability semaphore bit becomes read-only.
MUSBBUS
This field is used to enable or disable the selection of the allocation of USB Port D+/D-. When mask is enabled, the USB bus
availability semaphore bit becomes read-only.
Bit
RW
Reset
MSDIOBUS
SD External Bus Allocation Mask
00: Mask enabled (SD bus semaphore bit is read-only)
01: Invalid
10: Invalid
11: Unmasked (SD bus semaphore bit is read/write)
RW
00
MNANDBUS
NAND External Bus Allocation Mask
00: Mask Enabled (NAND bus semaphore bit is read-only)
01: Invalid
10: Invalid
11: Unmasked (NAND bus semaphore bit is read/write)
RW
00
5:4
MUSBBUS
USB External Bus Allocation Mask 00: Mask Enabled (USB bus semaphore bit is read-only)
01: Invalid
10: Invalid
11: Unmasked (USB bus semaphore bit is read/write)
RW
00
7:6
MUSBTR
(Reserved)
USB Transceiver Allocation Mask (Reserved)
R
00
Reserved
R
U/D
1:0
3:2
15:8
50
Field
Description
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.8
3.8.1
P-Port  U-Port
Description
Figure 3-21 shows the data path of P-Port  U-Port. Antioch is a peripheral device and connects to the processor with the PPort.
Figure 3-21. P-Port  U-Port Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
SDIO
Eng
TEST[0]
Upper Byte
8-bit NAND
3.8.2
SD_WP
SD_CMD
USB Port
(U Port)
SD_POW
SD_CLK
SD_D[7:0]
NAND_IO[15:8]
NAND_CE2#
NAND_WP#
NAND_R/B#
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
UVALID
SD/MMC/CEATA
D-
TEST[1]
USB 2.0
XCVR
D
+
Lower Byte
TEST[2]
Host
P-Port  U-Port Data Path Description
The P-Port  U-Port data transaction described below is used in accordance with the DMA protocol described in Section 3.6:
1. Processor writes to the COUNT field (number of bytes that it is going to transfer through the U-Port) and sets the DMAVAL
field to “1” in the corresponding Endpoint Buffer DMA Register.
2. Internally, when the corresponding endpoint buffer is available, the DRQ status bit in the DRQ Status Register is set and
DRQ is asserted (if the corresponding DRQ is not masked).
3. When the processor receives the DRQ, it starts transferring the data to the corresponding endpoint buffer as described in
Section 3.6.2.2 (ACK mode) or Section 3.6.3.2 (EOB mode).
Note DMAVAL field must be reset to “0” after the completion of each transfer.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
51
Data Path
P-Port  U-Port Transaction
3.8.3
Figure 3-22. P-Port  U-Port Transaction
USB Host on U- Port initiates"IN "
transaction to Antioch
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Antioch sends NAK
to the Host
P- Port resource
available ?
No
Yes
1 . Processor load the transfer data count to the COUNT
field in the Enpoint Buffer DMA Register
2 . Processor set DMAVAL in the Enpoint Buffer DMA
Register to “1”
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
When the corresponding Endpoint Buffer is available,
Antioch set the corresponding EPnDRQ to the DRQ
Status Register
No
MEPnDRQ field in
" DRQ Mask
Register" = 1?
No
Polling?
No
Processor writes
“0” to DMAVAL ?
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
INT#
MDRQINT field in
P- Port Interrupt
Mask Register
=
1?
No
EPnDRQ
= 1?
Yes
Yes
No
Yes
DRQ#
Antioch asserts DRQ # to Processor
1 .Antioch asserts INT# to Processor
2 .Processor reads P -Port Interrupt Register
Processor reads the DRQ Status
Registers to find out which endpoint
event(s ) caused the DRQ)
Zero length
packet?
Yes
No
Processor writes the transfer data
to the corresponding Endpoint
Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMAVAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Enpoint Buffer DMA Register
P- Port to U- Port Write Complete
52
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.8.4
U-Port  P-Port Data Path Description
When the host sends the data to the processor through the U-Port by using P-Port's DMA protocol, the transaction is the
same as described in Section 3.6.2.1 (ACK mode) or Section 3.6.3.1 (EOB mode).
3.8.5
U-Port  P-Port Transaction
Figure 3-23. U-Port  P-Port Transaction
USB Host on U- Port initiates
" OUT" transaction to Antioch
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Antioch sends NAK
to the Host
No
P- Port resource
available ?
Yes
1 . U- Port transfers data to the allocated endpoint buffer
2 . DMA VAL in the Enpoint Buffer DMA Register is set
to “1”
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
When the corresponding Endpoint Buffer is filled up,
Antioch set the corresponding EPnDRQ to the DRQ
Status Register
No
MEPnDRQ field in
"DRQ Mask
Register " = 1?
No
Polling?
No
Processor writes
“0” to DMAVAL ?
Yes
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
INT#
DRQ#
MDRQINT field in
P-Port Interrupt
Mask Register =
1?
No
EPnDRQ
= 1?
Yes
No
Yes
Antioch asserts DRQ# to Processor
1 . Antioch asserts INT # to Processor
2 . Processor reads P -Port Interrupt Register
1 . Processor reads the DRQ Status
Registers to find out which endpoint
event(s ) that cause the DRQ
)
2 . Processor reads the COUNT field
from the Enpoint Buffer DMA
Register
3 .Processor uses the COUNT value
to setup it’s own DMA
.
Zero length
packet?
Yes
No
Processor reads the transferred data
from the corresponding Endpoint Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Enpoint Buffer DMA Register
P- Port to U- Port Read Complete
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
53
Data Path
3.9
3.9.1
U-Port  S-Port (SD and/or 8-bit NAND)
Description
The data path for the U-Port  S-Port (SD and/or 8-bit NAND) access is as shown in Figure 3-24. Note that card insertion or
removal in the S-Port is handled via the MCUINT in the P-Port Interrupt Register and the status bits in the 8051 MCU Status
Register (when the SD external bus is allocated to the S-Port).
Figure 3-24. U-Port  S-Port 8-bit NAND and/or SD Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
SDIO
Eng
TEST[0]
Upper Byte
3.9.2
SD_WP
SD_CLK
SD_CMD
USB Port
(U Port)
SD_POW
SD_D[7:0]
NAND_IO[15:8]
NAND_CE2#
NAND_WP#
8-bit NAND
NAND_R/B#
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
UVALID
SD/MMC/CEATA
D-
TEST[1]
USB 2.0
XCVR
D
+
Lower Byte
TEST[2]
Host
U-Port  S-Port 8-bit NAND Data Path Description
1. The Host transfers a block of data to the particular endpoint buffer through the U-port.
2. After the block of data has been completely loaded into the endpoint buffer, Antioch directly loads that block of data from
the endpoint buffer to the 8-bit NAND Flash device.
3. When the block of data has been loaded into the 8-bit NAND Flash device, the 8051 MCU sends a “program” command to
the NAND Flash device to program the data into the memory cell.
4. NAND_RB signal, which is an output from the NAND device, goes LOW to indicate that the data is being programmed into
the NAND Flash device.
5. When NAND_RB signal goes HIGH, 8051 MCU sends a “read status” command to the NAND Flash device to verify if the
programming was successful.
54
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.9.3
U-Port  S-Port 8-bit NAND Transaction
Figure 3-25. U-Port  S-Port 8-bit NAND Transaction
USB Host on U-Port initiates
"OUT" transaction to Antioch
Antioch sends NACK
to the Host
No
S-Port (NAND)
resource available?
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Yes
Data transferred from U-Port to allocated endpoint
buffer
8051 MCU, internal to Antioch, sets up the write to the
8-bit NAND
Data written to 8-bit NAND.
U-Port to S-Port Write Complete
3.9.4
S-Port 8-bit NAND  the U-Port Data Path Description
1. Antioch sends the “read” command protocol to the 8-bit NAND device with the page address.
2. The NAND_RB signal, which is an output from the NAND device, goes LOW to indicate that the data is being transferred
from the Flash array to the data register.
3. When NAND_RB signal goes HIGH, Antioch clocks the NAND_RE signal to transfer a block of data (e.g. 512 bytes) from
the NAND Flash device to the endpoint buffer.
4. When the block of data has been completely loaded into the endpoint buffer, Antioch sends the data from the endpoint
buffer to the host through the U-Port.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
55
Data Path
3.9.5
S-Port 8-bit NAND  U-Port Transaction
Figure 3-26. S-Port 8-bit NAND  U-Port Transaction
USB Host on U-Port initiates "IN"
transaction to Antioch
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Antioch sends NACK
to the Host
No
S-Port (NAND)
resource available?
Yes
8051 MCU, internal to Antioch, sets up the read from
the 8-bit NAND
Data read from 8-bit NAND to endpoint buffer.
Data transferred from endpoint buffer to U-Port
S-Port to U-Port Read
TransferComplete
3.9.6
U-Port  S-Port SD Data Path Description
1. The Host transfers a block of data to the particular endpoint buffer through the U-port.
2. Antioch sends a write command with the SD card block address to the SD card.
3. After receiving the proper response from the SD card, Antioch sends the block of data in the corresponding endpoint buffer is sent to the SD card (suffixed with CRC).
4. The SD card sends back the CRC check result to the Antioch.
56
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.9.7
U-Port  S-Port SD Transaction
Figure 3-27. U-Port  S-Port SD Transaction
USB Host on U-Port initiates
"OUT" transaction to Antioch
Antioch sends NACK
to the Host
No
S-Port (SD)
resource available?
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Yes
Data transferred from U-Port to allocated endpoint
buffer
8051 MCU, internal to Antioch, sets up the write to the
SD
Data written to SD.
U-Port to S-Port Write Complete
3.9.8
S-Port SD  U-Port Data Path Description
1. Antioch sends a “read” command with the SD card block address to the SD card.
2. After receiving the proper response from the SD card, Antioch starts loading the data from the SD card to the endpoint
buffer.
3. When the block of data has been completely loaded in the endpoint buffer, Antioch sends that block of data to the Host
through the U-Port.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
57
Data Path
3.9.9
S-Port SD  U-Port Transaction
Figure 3-28. S-Port SD  U-Port Transaction
USB Host on U-Port initiates "IN"
transaction to Antioch
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Antioch sends NACK
to the Host
No
S-Port (SD)
resource available?
Yes
8051 MCU, internal to Antioch, sets up the read from
the SD
Data read from SD to endpoint buffer.
Data transferred from endpoint buffer to U-Port
S-Port to U-Port Read
TransferComplete
58
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.10
3.10.1
U-Port  S-Port (16-bit NAND)
Description
The data path for the U-Port  S-Port (16-bit NAND) access is as shown in Figure 3-29.
Figure 3-29. U-Port  S-Port (16-bit NAND) Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
SDIO
Eng
TEST[0]
Upper Byte
SD_WP
SD_CMD
USB Port
(U Port)
SD_POW
SD_CLK
NAND_CE2#
NAND_WP#
NAND_R/B#
SD_D[7:0]
NAND_IO[15:8]
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
16-bit NAND
3.10.2
UVALID
D-
TEST[1]
USB 2.0
XCVR
D
+
Lower Byte
TEST[2]
Host
U-Port  S-Port 16-bit NAND Data Path Description
The data path of U-Port  S-Port 16-bit NAND is the same as U-Port  S-Port 8-bit NAND as described in Section 3.9.2.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
59
Data Path
3.10.3
U-Port  S-Port 16-bit NAND Transaction
Figure 3-30. U-Port  S-Port 16-bit NAND Transaction
USB Host on U-Port initiates
"OUT" transaction to Antioch
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Antioch sends NACK
to the Host
No
S-Port (NAND)
resource
available?
Yes
Data transferred from U-Port to allocated endpoint
buffer
8051 MCU, internal to Antioch, sets up the write to the
16-bit NAND
Data written to 16-bit NAND.
U-Port to S-Port Write Complete
3.10.4
S-Port 16-bit NAND  U-Port Data Path Description
The data path of S-Port 16-bit NAND  U-Port is the same as S-Port 8-bit NAND  U-Port as described in Section 3.9.4.
60
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.10.5
S-Port 16-bit NAND  U-Port Transaction
Figure 3-31. S-Port 16-bit NAND  U-Port Transaction
USB Host on U-Port initiates "IN"
transaction to Antioch
Antioch sends NACK
to the Host
No
S-Port (NAND)
resource
available?
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Yes
8051 MCU, internal to Antioch, sets up the read from
16-bit NAND
Data read from 16-bit NAND to endpoint buffer.
Data transferred from endpoint buffer to U-Port
U-Port to S-Port Read Complete
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
61
Data Path
3.11
3.11.1
P-Port  S-Port (SD and/or 8-bit NAND)
Description
The transfer between the P-Port  S-Port (SD and/or 8-bit NAND) access is as shown in Figure 3-32.
Figure 3-32. P-Port  S-Port 8-bit NAND and/or SD Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
USB Port
(U Port)
3.11.2
SD_WP
SD_CMD
SD_POW
SD_CLK
SD_D[7:0]
NAND_IO[15:8]
NAND_CE2#
NAND_WP#
NAND_R/B#
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
8-bit NAND
UVALID
SD/MMC/CEATA
D-
TEST[0]
Upper Byte
D
+
Lower Byte
TEST[1]
USB 2.0
XCVR
SDIO
Eng
TEST[2]
Host
P-Port  S-Port 8-bit NAND Data Path Description
1. Processor sends a “write to NAND” command with the block number (address) of NAND Flash device to the 8051 MCU
Mailbox Registers (CY_AN_MEM_MCU_MAILBOXn).
2. Antioch responds with an acknowledgment to the processor through the P-Port Mailbox Registers.
3. Processor loads the transferred data byte count to the COUNT field and set the DMAVAL to “1” to the corresponding Endpoint Buffer DMA Register.
4. When the corresponding endpoint buffer is available, the DRQ status field in the DRQ Status Register is set, triggering the
assertion of DRQ signal.
5. When the processor receives the DRQ, it needs to read the DRQ Status Register to identify which source(s) requests the
DMA transfer.
6. The processor transfers the data to the designated endpoint buffer.
7. When the transfer is complete, the processor needs to reset the DMAVAL field of the Endpoint Buffer DMA Register to “0”.
This clears the corresponding DRQ status field in the DRQ Status Register.
8. Antioch loads the transferred data from the endpoint buffer to the 8-bit NAND Flash device.
62
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
9. When the block of data has been completely loaded to the 8-bit NAND Flash device, Antioch sends a “program” command
to the NAND device.
10. NAND_RB signal, which is an output from NAND, goes LOW to indicate that the data is being programmed into the NAND
device.
11. When NAND_RB signal goes HIGH, Antioch sends a “read status” command protocol to verify if the programming was
successful.
P-Port  S-Port 8-bit NAND Transaction
3.11.3
Figure 3-33. P-Port  S-Port 8-bit NAND Transaction
Processor acquires a resource for
S- Port( NAND)
Success ?
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Request resource release
for S- Port( NAND)
No
Yes
Processor issues "write to NAND" command to Antioch
through the Mail Box Registers
1 . Processor load the transfer data count to the COUNT
field in the Enpoint Buffer DMA Register
2 . Processor set DMA VAL in the Enpoint Buffer DMA
Register to1”“
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
When the corresponding Endpoint Buffer is available,
Antioch sets the corresponding EPnDRQ in the DRQ
Status Register
No
MEPnDRQ field in
"DRQ Mask
Register" = 1?
No
Polling?
Yes
INT#
DRQ#
Antioch asserts DRQ# to Processor
MDRQINT field in
P- Port Interrupt
Mask Register=
1?
No
EPnDRQ
= 1?
Yes
Processor writes
“0 ” to DMAVAL
?
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
No
No
Yes
1 . Antioch asserts INT# to Processor
2 . Processor reads P
- Port Interrupt Register
Processor reads the DRQ Status
Registers find out which endpoint
event(s ) to cause the DRQ)
Processor writes the transfer data
to the corresponding Endpoint
Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Endpoint Buffer DMA Register
P-Port to S-Port Write Complete
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
63
Data Path
3.11.4
S-Port 8-bit NAND  P-Port Data Path Description
1. Processor sends a “read from NAND” command with the block number of NAND to the 8051 MCU Mailbox Registers
(CY_AN_MEM_MCU_MAILBOXn).
2. Antioch responds with an acknowledgement to the processor through the P-Port Mailbox Registers.
3. The processor then loads the transfer data byte count to the COUNT field and sets the DMAVAL to “1” in the corresponding Endpoint Buffer DMA Register.
4. In the meantime, Antioch generates a “read” command with the page address to the 8-bit NAND Flash device.
5. The NAND_RB signal, which is an output from the NAND device, goes LOW to indicate that the data is being transferred
from the Flash array to the data register.
6. When NAND_RB signal goes HIGH, Antioch clocks the NAND_RE signal to load a block of data from the NAND Flash
device to the endpoint buffer.
7. When the block of data has been completely loaded into the endpoint buffer, Antioch sets the DRQ status bit in the DRQ
Status Register to “1” which triggers the assertion of the DRQ signal to the processor.
8. When the processor receives the DRQ, it reads the DRQ Status Register to identify which source(s) requests the DMA.
9. The processor starts reading the data from the corresponding endpoint buffer.
10. When the transfer is complete, the processor needs to reset the DMAVAL field of the Endpoint Buffer DMA Register to “0”.
This clears the corresponding DRQ status field in the DRQ Status Register.
DMAVAL field must be reset to “0” after the completion of each transfer.
64
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
S-Port 8-bit NAND  P-Port Transaction
3.11.5
Figure 3-34. S-Port 8-bit NAND  P-Port Transaction
Processor acquires a resource for
S- Port( NAND)
Success ?
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Request resource release
for S- Port( NAND)
No
Yes
Processor issues "read from NAND" command to
Antioch through the Mail Box Registers
Processor writes to COUNT field and “1” to the
DMAVAL field in the Endpoint Buffer DMA Register
Antioch requests data from the NAND, which is stored
into the corresponding endpoint buffer.
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
When the corresponding Endpoint Buffer is filled up,
Antioch sets the corresponding EPnDRQ in the DRQ
Status Register
No
MEPnDRQ field in
DRQ Mask
Register" = 1?
No
Polling ?
Yes
INT#
DRQ#
Antioch asserts DRQ # to Processor
MDRQINT field in
P- Port Interrupt
Mask Register =
1?
No
EPnDRQ
= 1?
Yes
Processor writes
“0” to DMAVAL
?
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
No
No
Yes
1 . Antioch asserts INT # to Processor
2 . Processor reads P- Port Interrupt Register
.
Processor reads the DRQ Status
Register to find out which endpoint
event caused the DRQ
Processor reads the transferred data
from the corresponding Endpoint Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Enpoint Buffer DMA Register
S-Port to P-Port Read Complete
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
65
Data Path
3.11.6
P-Port  S-Port SD Data Path Description
1. Processor sends a “write to SD” command with the block number of SD card to the 8051 MCU Mailbox Registers
(CY_AN_MEM_MCU_MAILBOXn).
2. Antioch responds with an acknowledgement to the processor through the P-Port Mailbox Registers.
3. The processor then loads the transferred data byte count to the COUNT field and sets the DMAVAL field to “1” in the corresponding Endpoint Buffer DMA Register.
4. When the corresponding endpoint buffer is available, the DRQ status field in the DRQ Status Register is set, which triggers the assertion of the DRQ signal.
5. When the processor receives the DRQ, it needs to read the DRQ Status Register to identify which source(s) requested
the DMA transfer.
6. The processor transfers the data to the designated endpoint buffer.
7. When the transfer is complete, the processor writes “0” to the DMAVAL field in the Endpoint Buffer DMA Register. This
clears the corresponding DRQ status field in the DRQ Status Register.
8. Antioch sends a “write” command with the SD card block address to the SD card.
9. After receiving the proper response from the SD card, the Antioch sends the block of data in the corresponding endpoint
buffer to the SD card (suffixed with CRC).
10. The SD card sends back the CRC check result to the Antioch.
66
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
P-Port  S-Port SD Transaction
3.11.7
Figure 3-35. P-Port  S-Port SD Transaction
Processor acquires a resource for
S- Port (SD)
Success ?
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Request resource release
for S- Port ( SD )
No
Yes
Processor issues " write to SD " command to Antioch
through the Mailbox Registers
1 . Processor load the transfer data count to the COUNT
field in the Enpoint Buffer DMA Register
2 . Processor set DMA VAL in the Enpoint Buffer DMA
Register to1”“
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
When the corresponding Endpoint Buffer is available,
Antioch sets the corresponding EPnDRQ in the DRQ
Status Register
No
MEPnDRQ field in
"DRQ Mask
Register" = 1?
No
Polling ?
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT# for data
transfer?
No
INT#
DRQ#
Antioch asserts DRQ# to Processor
MDRQINT field in
P- Port Interrupt
Mask Register=
1?
No
EPnDRQ
= 1?
Yes
Processor writes
“0 ” to DMAVAL
?
Yes
No
Yes
1 . Antioch asserts INT# to Processor
2 . Processor reads P- Port Interrupt Register
Processor reads the DRQ Status
Registers find out which endpoint
event(s ) to cause the DRQ)
Processor writes the transfer data
to the corresponding Endpoint
Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Endpoint Buffer DMA Register
P-Port to S-Port Write Complete
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
67
Data Path
3.11.8
S-Port SD  P-Port Data Path Description
1. Processor sends a “read from SD” command with the block number of SD card to the 8051 MCU Mailbox Registers
(CY_AN_MEM_MCU_MAILBOXn).
2. Antioch responds with an acknowledgement to the processor through the P-Port Mailbox Registers.
3. The processor then loads the transfer data byte count to the COUNT field and sets the DMAVAL to “1” in the corresponding Endpoint Buffer DMA Register.
4. Antioch sends a read command with the SD card block address to the SD card.
5. After receiving the proper response from the SD card, Antioch starts loading the data from the SD card to the corresponding endpoint buffer.
6. When the block of data has been completely loaded in the endpoint buffer, Antioch sets the DRQ status field in the DRQ
Status Register, which triggers the assertion of the DRQ signal to the processor.
7. When the processor receives the DRQ, it reads the DRQ Status Register to identify which source(s) requests the DMA.
8. The processor starts reading the transferred data from the corresponding endpoint buffer.
9. When the transfer is complete, the processor needs to reset the DMAVAL field of the Endpoint Buffer DMA Register to “0”.
This clears the corresponding DRQ status field in the DRQ Status Register.
68
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
Figure 3-36. S-Port SD  P-Port Transaction
Processor acquires a resource for
S- Port ( SD )
Success ?
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Request resource release
for S- Port (SD )
No
Yes
Processor issues " read from SD " command to
Antioch through the Mail Box Registers
Processor writes to COUNT field and “1” to the
DMAVAL field in the Endpoint Buffer DMA Register
Antioch requests data from the NAND, which is stored
into the corresponding endpoint buffer.
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
When the corresponding Endpoint Buffer is filled up,
Antioch sets the corresponding EPnDRQ in the DRQ
Status Register
No
MEPnDRQ field in
DRQ Mask
Register" = 1?
No
Polling ?
Yes
INT#
DRQ#
Antioch asserts DRQ # to Processor
MDRQINT field in
P- Port Interrupt
Mask Register =
1?
No
EPnDRQ
= 1?
Yes
Processor writes
“0” to DMAVAL
?
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
No
No
Yes
1 . Antioch asserts INT # to Processor
2 . Processor reads P- Port Interrupt Register
.Processor reads the DRQ Status
Register to find out which endpoint
event caused the DRQ
Processor reads the transferred data
from the corresponding Endpoint Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Enpoint Buffer DMA Register
S-Port to P-Port Read Complete
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
69
Data Path
3.12
3.12.1
P-Port  S-Port (16-bit NAND)
Description
The data path for the P-Port  S-Port (16-bit NAND) access is as shown in Figure 3-37.
Figure 3-37. P-Port  S-Port (16-bit NAND) Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
SDIO
Eng
TEST[0]
Upper Byte
SD_WP
USB Port
(U Port)
SD_POW
SD_CLK
SD_CMD
NAND_CE2#
NAND_WP#
NAND_R/B#
SD_D[7:0]
NAND_IO[15:8]
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
16-bit NAND
3.12.2
UVALID
D-
TEST[1]
USB 2.0
XCVR
D
+
Lower Byte
TEST[2]
Host
P-Port  S-Port (16-bit NAND) Data Path Description
When the P-Port is accessing the 16-bit NAND for a Write operation, the procedure is the same as accessing the 8-bit NAND
as described in Section 3.11.2.
3.12.3
P-Port  S-Port 16-bit NAND Transaction
The transaction flow chart of P-Port  S-Port 16-bit NAND is the same as in P-Port to 8-bit NAND, which is shown in
Figure 3-33.
3.12.4
S-Port (16-bit NAND)  P-Port Data Path Description
When the P-Port is accessing the 16-bit NAND for a Read operation, the procedure is same as accessing the 8-bit NAND as
described in Section 3.11.4.
70
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.12.5
S-Port 16-bit NAND  P-Port Transaction
The transaction flow chart of S-Port 16-bit NAND  P-Port is the same as in 8-bit NAND to P-Port, which is shown in
Figure 3-34.
3.13
3.13.1
U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port
Interleaving
Description
Figure 3-38 shows the data path for the interleaving U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port transactions. Note that card insertion or removal in the S-Port is handled via the MCUINT in the P-Port Interrupt Register and the status bits in the 8051 MCU Status Register.
Figure 3-38. Interleaving U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPIO[1:0]
GPIO
MUX
SD_WP
SD_CLK
SD_CMD
USB Port
(U Port)
SD_POW
SD_D[7:0]
NAND_IO[15:8]
NAND_CE2#
NAND_WP#
8-bit NAND
NAND_R/B#
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
UVALID
SD/MMC/CEATA
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
D-
TEST[0]
Upper Byte
D
+
Lower Byte
TEST[1]
USB 2.0
XCVR
SDIO
Eng
TEST[2]
Host
71
Data Path
3.13.2
U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port Interleaving Data
Path Description
The interleaving transactions of U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port essentially follow the same
procedure as the U-Port  S-Port (SD and/or 8-bit NAND) transaction in Section 3.9 and the P-Port  U-Port transaction in
Section 3.8. Some important points to note in an interleaving transaction:
1. In a general case, there are two separate endpoints set up, one for accesses between U-Port and S-Port (SD and/or 8-bit
NAND) and the other for accesses between U-Port and P-Port.
2. The data transfer between the U-Port and the two endpoint buffers within Antioch does not happen simultaneously in time.
The USB Host accesses data (reads or writes) from or to only one endpoint at a time.
3. There are two steps in any transaction:
a. Transfer of data from data source to allocated endpoint buffer.
b. Transfer of data from endpoint buffer to destination port.
These two steps are independent and are used in pipelining and interleaving blocks of data in an interleaving transaction.
4. For example, consider the case where the U-Port is transferring data to both the S-Port (SD and/or 8-bit NAND) and the
P-Port. The U-Port begins transfer of data to or from one endpoint buffer, either the one corresponding to S-Port (SD and/
or 8-bit NAND) or the one corresponding to P-Port (the USB Host decides which one). When that transfer is done (either
the particular endpoint buffer is full or one block of USB data is complete), the Antioch device initiates a DMA transfer if
the destination is the P-Port or the 8051 MCU initiates a command if the destination is the S-Port (SD and/or 8-bit NAND).
5. During the transfer of data from the first endpoint buffer to its destination, the second transaction from the U-Port proceeds
by transferring data to the other endpoint buffer. In this way, the process interleaves between the two data blocks that
could be from the same source (the U-Port in this case).
6. If one requesting port is required to wait due a resource not being available during an interleaving transaction, it is
resolved as follows:
a. If the delay is on the P-Port, the DRQ# or DMA Request signal is not issued to the processor. The DRQ# is issued only
when the endpoint buffer resource is ready to send or receive data.
b. If the delay is on the U-Port, a NAK signal is sent to accommodate the interleaving.
72
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port Interleaving
Transaction
3.13.3
The following transaction examples assume that the USB Host initiates the U-Port  P-Port transaction earlier in time than
the U-Port  S-Port (SD and/or 8-bit NAND) transaction.
Figure 3-39. U-Port  S-Port (SD and/or 8-bit NAND) and U-Port  P-Port Interleaving Transaction
The Host initiates an “OUT”
transaction to Antioch
Antioch sends NACK
to the Host
Antioch sends NACK
to the Host
S- Port Transfer
No
S- Port or P- Port
Transfer?
S- Port( SD or
NAND) resource
available?
No
P- Port resource
available ?
Yes
Yes
Data transferred from -U Port to endpoint
buffer allocated to S
- Port
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
P- Port Transfer
1 . U- Port transfers data to the allocated endpoint buffer
2 . DMA VAL in the Enpoint Buffer DMA Register is set
to “1”
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
8051 MCU, internal to Antioch, sets up
the write to the SD or -8 bit NAND
When the corresponding Endpoint Buffer is filled up,
Antioch set the corresponding EPnDRQ to the DRQ
Status Register
No
Data written to SD or 8- bit NAND
.
MEPnDRQ field in
"DRQ Mask
Register " = 1?
U- Port to S- Port Write Complete
No
Polling?
No
Processor writes
“0” to DMAVAL ?
Yes
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
INT#
MDRQINT field in
P-Port Interrupt
Mask Register =
1?
No
EPnDRQ
= 1?
Yes
No
Yes
DRQ#
Antioch asserts DRQ# to Processor
1 . Antioch asserts INT # to Processor
2 . Processor reads P -Port Interrupt Register
1 . Processor reads the DRQ Status
Registers to find out which endpoint
event(s ) that cause the DRQ
)
2 . Processor reads the COUNT field
from the Enpoint Buffer DMA
Register
3 .Processor uses the COUNT value
to setup it’s own DMA
.
Zero length
packet?
Yes
No
Processor reads the transferred data
from the corresponding Endpoint Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Enpoint Buffer DMA Register
P- Port to U - Port Read Complete
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
73
Data Path
Figure 3-40. S-Port (SD and/or 8-bit NAND)  U-Port and P-Port  U-Port Interleaving Transaction
The Host initiates an “IN”
transaction to Antioch
Antioch sends NACK
to the Host
Antioch sends NACK
to the Host
S- Port Transfer
No
S- Port or P- Port
Transfer?
P- Port Transfer
S- Port( SD or
NAND) resource
available?
Data read from SD or 8- bit NAND to
endpoint buffer.
No
P- Port resource
available?
Yes
8051 MCU, internal to Antioch, sets up
the read from the SD or 8- bit NAND
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Yes
1 . Processor load the transfer data count to the COUNT
field in the Enpoint Buffer DMA Register
2 . Processor set DMAVAL in the Enpoint Buffer DMA
Register to “1”
The flow chart and the path at this
side ( blue in color) are not described
The part is handled by
in Data Path Description
Processor software
When the corresponding Endpoint Buffer is available,
Antioch set the corresponding EPnDRQ to the DRQ
Status Register
No
Data transferred from endpoint buffer to
U- Port
MEPnDRQ field in
" DRQ Mask
Register" = 1?
S- Port to U- Port Read Transfer
Complete
No
Polling?
No
Processor writes
“0” to DMAVAL ?
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
INT#
DRQ#
MDRQINT field in
P- Port Interrupt
Mask Register
=
1?
No
EPnDRQ
= 1?
Yes
Yes
No
Yes
Antioch asserts DRQ # to Processor
1 .Antioch asserts INT# to Processor
2 .Processor reads P -Port Interrupt Register
Processor reads the DRQ Status
Registers to find out which endpoint
event(s ) caused the DRQ)
Zero length
packet?
Yes
No
Processor writes the transfer data
to the corresponding Endpoint
Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMAVAL
= 0?
No
Processor writes"0 " to DMAVAL
in the Enpoint Buffer DMA Register
P- Port to U- Port Write Complete
74
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.14
3.14.1
U-Port  S-Port (16-bit NAND) and U-Port P-Port Interleaving
Description
Figure 3-41 shows the data path for the interleaving P-Port  U-Port and U-Port  S-Port (16-bit NAND) transactions.
Figure 3-41. P-Port  U-Port and U-Port  S-Port (16-bit NAND) Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
16-bit NAND
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
SD_WP
SD_CMD
USB Port
(U Port)
SD_POW
SD_CLK
NAND_CE2#
NAND_WP#
NAND_R/B#
SD_D[7:0]
NAND_IO[15:8]
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
UVALID
D-
TEST[0]
Upper Byte
D
+
Lower Byte
TEST[1]
USB 2.0
XCVR
SDIO
Eng
TEST[2]
Host
75
Data Path
3.14.2
U-Port  S-Port (16-bit NAND) and U-Port  P-Port Interleaving Data Path
Description
The interleaving transactions of P-Port  U-Port and U-Port  S-Port (16-bit NAND) essentially follow the same procedure
as the P-Port  U-Port transaction in Section 3.8 and the U-Port  S-Port (16-bit NAND) transaction in Section 3.10. Some
important points to note in an interleaving transaction:
1. In the general case, there are two separate endpoints set up, one for accesses between U-Port and S-Port (16-bit NAND)
and the other for accesses between U-Port and P-Port.
2. The data transfer between the U-Port and the two endpoint buffers within Antioch does not happen simultaneously in time.
The USB Host accesses data (reads or writes) from or to only one endpoint at a time.
3. There are two steps in any transaction:
a. Transfer of data from data source to allocated endpoint buffer.
b. Transfer of data from endpoint buffer to destination port.
These two steps are independent and are used in pipelining and interleaving blocks of data in an interleaving transaction.
4. For example, consider the case where the U-Port is transferring data to both the S-Port (16-bit NAND) and the P-Port. The
U-Port begins transfer of data to or from one endpoint buffer, either the one corresponding to S-Port (16-bit NAND) or the
one corresponding to P-Port (the USB Host decides which one). When that transfer is done (either the particular endpoint
buffer is full or one block of USB data is complete), the Antioch device initiates a DMA transfer if the destination is the PPort or the 8051 MCU initiates a command if the destination is the S-Port (16-bit NAND).
5. During the transfer of data from the first endpoint buffer to its destination, the second transaction from the U-Port proceeds
by transferring data to the other endpoint buffer. In this way, the process interleaves between the two data blocks that
could be from the same source (the U-Port in this case).
6. If one requesting port is required to wait due a resource not being available during an interleaving transaction, it is
resolved as follows:
a. If the delay is on the P-Port, the DRQ# or DMA Request signal is not issued to the processor. The DRQ# is issued only
when the endpoint buffer resource is ready to send or receive data.
b. If the delay is on the U-Port, a NAK signal is sent to accommodate the interleaving.
76
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
U-Port  S-Port (16-bit NAND) and U-Port  P-Port Interleaving Transaction
3.14.3
The following transaction examples assume that the USB Host initiates the U-Port  P-Port transaction earlier in time than
the U-Port  S-Port (16-bit NAND) transaction.
Figure 3-42. U-Port  S-Port (16-bit NAND) and U-Port  P-Port Interleaving Transaction
The Host initiates an “OUT”
transaction to Antioch
Antioch sends NACK
to the Host
Antioch sends NACK
to the Host
S- Port or P- Port
Transfer?
S- Port Transfer
No
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
P- Port Transfer
S- Port(NAND)
resource
available ?
No
P- Port resource
available ?
Yes
Yes
Data transferred from -U Port to endpoint
buffer allocated to S
- Port
1 . U- Port transfers data to the allocated endpoint buffer
2 . DMA VAL in the Enpoint Buffer DMA Register is set
to “1”
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
8051 MCU, internal to Antioch, sets up
the write to the 16-bit NAND
When the corresponding Endpoint Buffer is filled up,
Antioch set the corresponding EPnDRQ to the DRQ
Status Register
No
Data written to 16-bit NAND
.
MEPnDRQ field in
"DRQ Mask
Register " = 1?
U- Port to S- Port Write Complete
No
Polling?
No
Processor writes
“0” to DMAVAL ?
Yes
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
INT#
MDRQINT field in
P-Port Interrupt
Mask Register =
1?
DRQ#
No
EPnDRQ
= 1?
Yes
No
Yes
Antioch asserts DRQ # to Processor
1 . Antioch asserts INT # to Processor
2 . Processor reads P -Port Interrupt Register
1 . Processor reads the DRQ Status
Registers to find out which endpoint
event(s ) that cause the DRQ
)
2 . Processor reads the COUNT field
from the Enpoint Buffer DMA
Register
3 .Processor uses the COUNT value
to setup it’s own DMA
.
Zero length
packet?
Yes
No
Processor reads the transferred data
from the corresponding Endpoint Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Enpoint Buffer DMA Register
P- Port to U- Port Read Complete
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
77
Data Path
Figure 3-43. S-Port (16-bit NAND)  U-Port and P-Port  U-Port Interleaving Transaction
The Host initiates an “IN”
transaction to Antioch
Antioch sends NACK
to the Host
Antioch sends NACK
to the Host
S- Port Transfer
No
S- Port or P- Port
Transfer?
P- Port Transfer
S- Port ( NAND )
resource
available?
Data read from 16-bit NAND to
endpoint buffer
.
No
P- Port resource
available?
Yes
8051 MCU, internal to Antioch, sets up
the read from the 16-bit NAND
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Yes
1 . Processor load the transfer data count to the COUNT
field in the Enpoint Buffer DMA Register
2 . Processor set DMAVAL in the Enpoint Buffer DMA
Register to “1”
The flow chart and the path at this
side ( blue in color) are not described
The part is handled by
in Data Path Description
Processor software
When the corresponding Endpoint Buffer is available,
Antioch set the corresponding EPnDRQ to the DRQ
Status Register
No
Data transferred from endpoint buffer to
U- Port
MEPnDRQ field in
" DRQ Mask
Register" = 1?
S- Port to U - Port Read Transfer
Complete
No
Polling?
No
Processor writes
“0” to DMAVAL ?
Yes
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
INT#
MDRQINT field in
P- Port Interrupt
Mask Register
=
1?
No
EPnDRQ
= 1?
Yes
Yes
No
Yes
DRQ#
Antioch asserts DRQ # to Processor
1 .Antioch asserts INT# to Processor
2 .Processor reads P -Port Interrupt Register
Processor reads the DRQ Status
Registers to find out which endpoint
event(s ) caused the DRQ)
Zero length
packet?
Yes
No
Processor writes the transfer data
to the corresponding Endpoint
Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMAVAL
= 0?
No
Processor writes"0 " to DMAVAL
in the Enpoint Buffer DMA Register
P- Port to U- Port Write Complete
78
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.15
3.15.1
U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port
Interleaving
Description
Figure 3-44 shows the data path for the interleaving U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port transactions.
Figure 3-44. U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
USB Port
(U Port)
3.15.2
SD_WP
SD_CLK
SD_CMD
SD_POW
SD_D[7:0]
NAND_IO[15:8]
NAND_CE2#
NAND_WP#
NAND_R/B#
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
8-bit NAND
UVALID
SD/MMC/CEATA
D-
TEST[0]
Upper Byte
D
+
Lower Byte
TEST[1]
USB 2.0
XCVR
SDIO
Eng
TEST[2]
Host
U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port Interleaving Data
Path Description
The interleaving transactions of U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port essentially follow the same
procedure as the U-Port  S-Port (SD and/or 8-bit NAND) transaction in Section 3.9 and the P-Port  S-Port transaction in
Section 3.11. Some important points to note in an interleaving transaction:
1. There is a single endpoints set up for each direction, accesses between U-Port and S-Port (SD and/or 8-bit NAND) and PPort and S-Port share an endpoint (if the accesses are in the same direction - e.g. both are IN or both are OUT).
2. The data transfer between the S-Port and the endpoint buffer within Antioch does not happen simultaneously in time. The
S-Port accesses data (writes or reads) from or to only one device (e.g. either NAND Flash device or SD card) at a time.
3. There are two steps in any transaction:
a. Transfer of data from data source to allocated endpoint buffer.
b. Transfer of data from endpoint buffer to destination port.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
79
Data Path
These two steps are independent and are used in pipelining and interleaving blocks of data in an interleaving transaction.
c. If the U-Port is required to wait due to a resource not being available during an interleaving transaction, a NAK signal
is sent to accommodate the interleaving.
3.15.3
U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port Interleaving
Transaction
Figure 3-45. U-Port  S-Port (SD and/or 8-bit NAND) and P-Port  S-Port Interleaving Transaction
USB Host on U- Port initiates
" OUT" transaction to Antioch
Processor acquires a resource for
S- Port (SD)
Antioch sends NACK
to the Host
Success ?
No
S- Port ( SD or
NAND) resource
available?
Request resource release
for S- Port ( SD )
No
Yes
Processor issues " write to SD " command to Antioch
through the Mailbox Registers
Yes
Data transferred from -U Port to
endpoint buffer allocated to S- Port
8051 MCU, internal to Antioch, sets
up the write to the SD or 8-bit NAND
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
1 . Processor load the transfer data count to the COUNT
field in the Enpoint Buffer DMA Register
2 . Processor set DMA VAL in the Enpoint Buffer DMA
Register to1”“
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
When the corresponding Endpoint Buffer is available,
Antioch sets the corresponding EPnDRQ in the DRQ
Status Register
No
Data written to SD or 8- bit NAND
.
MEPnDRQ field in
"DRQ Mask
Register" = 1?
No
Polling ?
Yes
U- Port to S- Port Write Complete
Poll DRQ
Status Register
Yes
Use DRQ# or
INT # for data
transfer?
No
INT#
DRQ#
Antioch asserts DRQ# to Processor
MDRQINT field in
P- Port Interrupt
Mask Register=
1?
No
EPnDRQ
= 1?
Yes
Processor writes
“0 ” to DMAVAL
?
Yes
No
Yes
1 . Antioch asserts INT# to Processor
2 . Processor reads P- Port Interrupt Register
Processor reads the DRQ Status
Registers find out which endpoint
event(s ) to cause the DRQ)
Processor writes the transfer data
to the corresponding Endpoint
Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Endpoint Buffer DMA Register
P-Port to S-Port Write Complete
80
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.16
3.16.1
U-Port  S-Port (16-bit NAND) and P-Port  S-Port Interleaving
Description
Figure 3-46 shows the data path for the interleaving U-Port  S-Port (16-bit NAND) and P-Port  S-Port transactions.
Figure 3-46. Simultaneous U-Port  S-Port (16-bit NAND) and P-Port  S-Port Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
USB Port
(U Port)
3.16.2
SD_WP
SD_POW
SD_CLK
SD_CMD
NAND_CE2#
NAND_WP#
NAND_R/B#
SD_D[7:0]
NAND_IO[15:8]
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
16-bit NAND
UVALID
D-
TEST[0]
Upper Byte
D
+
Lower Byte
TEST[1]
USB 2.0
XCVR
SDIO
Eng
TEST[2]
Host
U-Port  S-Port (16-bit NAND) and P-Port  S-Port Interleaving Data Path
Description
The simultaneous transactions of U-Port  S-Port (16-bit NAND) and P-Port  S-Port essentially follow the same procedure
as the U-Port  S-Port (16-bit NAND) transaction in Section 3.10 and the P-Port  S-Port (16-bit NAND) transaction in
Section 3.12. Some important points to note in an interleaving transaction:
1. There are two separate endpoints set up, one for accesses between U-Port and S-Port (16-bit NAND) and the other for
accesses between P-Port and S-Port.
2. The data transfer between the S-Port and the two endpoint buffers within Antioch does not happen simultaneously in time.
The S-Port accesses data (writes or reads) from or to only one endpoint at a time.
3. There are two steps in any transaction:
a. Transfer of data from data source to allocated endpoint buffer.
b. Transfer of data from endpoint buffer to destination port.
These two steps are independent and are used in pipelining and interleaving blocks of data in an interleaving transaction.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
81
Data Path
4. If one requesting port is required to wait due a resource not being available during an interleaving transaction, it is
resolved as follows:
a. If the delay is on the P-Port, the DRQ# or DMA Request signal is not issued to the processor. The DRQ# is issued only
when the endpoint buffer resource is ready to send or receive data.
b. If the delay is on the U-Port, a NAK signal is sent to accommodate the interleaving.
U-Port  S-Port (16-bit NAND) and P-Port  S-Port Interleaving Transaction
3.16.3
Figure 3-47. U-Port  S-Port (16-bit NAND) and P-Port  S-Port Interleaving Transaction
USB Host on U- Port initiates
" OUT" transaction to Antioch
Processor acquires a resource for
S- Port( NAND)
Success ?
Antioch sends NACK
to the Host
The portion is the resource
management that is handled
by 8051 firmware and is not
described in Data Path
Description.
Request resource release
for S- Port( NAND)
No
Yes
No
S- Port( NAND)
resource available
?
Yes
Data transferred from -UPort to
endpoint buffer allocated to -SPort
8051 MCU, internal to Antioch, sets
up the write to the 16-bit NAND
Processor issues "write to NAND" command to Antioch
through the Mail Box Registers
1 . Processor load the transfer data count to the COUNT
field in the Enpoint Buffer DMA Register
2 . Processor set DMA VAL in the Enpoint Buffer DMA
Register to1”“
The flow chart and the path at this
side ( blue in color) are not described
in Data Path Description
The part is handled by
Processor software
When the corresponding Endpoint Buffer is available,
Antioch sets the corresponding EPnDRQ in the DRQ
Status Register
No
MEPnDRQ field in
"DRQ Mask
Register" = 1?
Data written to 16- bit NAND
.
No
Polling?
Yes
INT#
DRQ#
Antioch asserts DRQ# to Processor
MDRQINT field in
P- Port Interrupt
Mask Register=
1?
No
EPnDRQ
= 1?
Yes
Processor writes
“0 ” to DMAVAL
?
Yes
Poll DRQ
Status Register
Yes
U- Port to S- Port( NAND) Write
Complete
Use DRQ# or
INT # for data
transfer?
No
No
Yes
1 . Antioch asserts INT# to Processor
2 . Processor reads P-Port Interrupt Register
Processor reads the DRQ Status
Registers find out which endpoint
event(s ) to cause the DRQ)
Processor writes the transfer data
to the corresponding Endpoint
Buffer
Processor’s own
DMA counter or
data transfer
counter = 0?
No
Yes
Yes
DMA VAL
= 0?
No
Processor writes "0 " to DMAVAL
in the Endpoint Buffer DMA Register
P-Port to S-Port Write Complete
82
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.17
3.17.1
P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND)
Interleaving
Description
Figure 3-48 shows the data path for the interleaving P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) transactions.
Figure 3-48. Interleaving P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
TEST[0]
Upper Byte
8-bit NAND
3.17.2
SD_WP
SD_CLK
SD_CMD
USB Port
(U Port)
SD_POW
SD_D[7:0]
NAND_IO[15:8]
NAND_CE2#
NAND_WP#
NAND_R/B#
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
UVALID
SD/MMC/CEATA
D-
TEST[1]
USB 2.0
XCVR
SDIO
Eng
D
+
Lower Byte
TEST[2]
Host
P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) Interleaving Data
Path Description
The interleaving transactions of P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) essentially follow the same
procedure as the P-Port  U-Port transaction in Section 3.8 and the P-Port  S-Port (SD and/or 8-bit NAND) transaction in
Section 3.11. Some important points to note in an interleaving transaction:
1. There are two separate endpoints set up, one for accesses between P-Port and S-Port (SD and/or 8-bit NAND) and the
other for accesses between P-Port and U-Port.
2. The data transfer between the P-Port and the two endpoint buffers within Antioch does not happen simultaneously in time.
The P-Port accesses data (writes or reads) from or to only one endpoint at a time.
3. There are two steps in any transaction:
a. Transfer of data from data source to allocated endpoint buffer.
b. Transfer of data from endpoint buffer to destination port.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
83
Data Path
These two steps are independent and are used in pipelining and interleaving blocks of data in an interleaving transaction.
4. If one requesting port is required to wait due a resource not being available during an interleaving transaction, it is
resolved as follows:
a. If the delay is on the P-Port, the DRQ# or DMA Request signal is not issued to the processor. The DRQ# is issued only
when the endpoint buffer resource is ready to send or receive data.
b. If the delay is on the U-Port, a NAK signal is sent to accommodate the interleaving.
3.17.3
P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) Interleaving
Transaction
The transaction flow chart of P-Port  U-Port and P-Port  S-Port (SD and/or 8-bit NAND) Interleaving is the same as
Figure 3-22, Figure 3-23, Figure 3-33, Figure 3-34, and Figure 3-35.
3.18
3.18.1
P-Port  U-Port and P-Port  S-Port (16-bit NAND) Interleaving
Description
Figure 3-49 shows the data path for the interleaving P-Port  U-Port and P-Port  S-Port (16-bit NAND) transactions.
Figure 3-49. Interleaving P-Port  U-Port and P-Port  S-Port (16-bit NAND) Data Path
West Bridge Antioch
DQ[15:0]
Microprocessor
CE#
ADV#
OE#
WE#
INT#
DRQ#
DACK#
RESETOUT
Processor Interface Port
(P Port)
XTALIN
CLK
A[7:0]
XTALOUT
Configuration and Control
Registers Block
XTALSLC[1]
XTALSLC[0]
End Point
Buffers A
MUX
CY Smart USB
2.0 Engine
MUX
MUX
24KB
Prog
RAM
8051 MCU
WAKEUP
RESET#
End Point
Buffers B
GPI[1:0]
GPIO
MUX
USB Port
(U Port)
84
SD_WP
SD_CMD
SD_POW
SD_CLK
NAND_CE2#
NAND_WP#
NAND_R/B#
SD_D[7:0]
NAND_IO[15:8]
NAND_RE#
NAND_WE#
NAND_ALE
NAND_CE#
NAND_CLE
NAND_IO[7:0]
NANDCFG
SD and NAND Port
(S Port)
16-bit NAND
UVALID
D-
TEST[0]
Upper Byte
D
+
Lower Byte
TEST[1]
USB 2.0
XCVR
SDIO
Eng
TEST[2]
Host
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Data Path
3.18.2
P-Port  U-Port and P-Port  S-Port (16-bit NAND) Interleaving Data Path
Description
The interleaving transactions of P-Port  U-Port and P-Port  S-Port (16-bit NAND) essentially follow the same procedure
as the P-Port  U-Port transaction in Section 3.8 and the P-Port  S-Port (16-bit NAND) transaction in Section 3.12. Some
important points to note in an interleaving transaction:
1. There are two separate endpoints set up, one for accesses between P-Port and S-Port (16-bit NAND) and the other for
accesses between P-Port and U-Port.
2. The data transfer between the P-Port and the two endpoint buffers within Antioch does not happen simultaneously in time.
The P-Port accesses data (writes or reads) from or to only one endpoint at a time.
3. There are two steps in any transaction:
a. Transfer of data from data source to allocated endpoint buffer.
b. Transfer of data from endpoint buffer to destination port.
These two steps are independent and are used in pipelining and interleaving blocks of data in an interleaving transaction.
4. If one requesting port is required to wait due a resource not being available during an interleaving transaction, it is
resolved as follows:
a. If the delay is on the P-Port, the DRQ# or DMA Request signal is not issued to the processor. The DRQ# is issued only
when the endpoint buffer resource is ready to send or receive data.
b. If the delay is on the U-Port, a NAK signal is sent to accommodate the interleaving.
3.18.3
P-Port  U-Port and P-Port  S-Port (16-bit NAND) Interleaving Transaction
The transaction flow chart of P-Port  U-Port and P-Port  S-Port (SD and 8-bit NAND) Interleaving is the same as
Figure 3-22, Figure 3-23, Figure 3-33, and Figure 3-34.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
85
Data Path
86
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
4. Address Space
Antioch has three address spaces for the processor access - Endpoint Buffers, Firmware Loading (during the reset initialization), and Registers. Table 4-1 summarizes these address space with the address range.
Table 4-1. Antioch Address Space Summary
Address Space Name
Address Space Range (A[7:0])
Endpoint Buffers
x'02 - x'0F
Firmware Loading
x'02 (through the EP2)
Configuration/Control Registers
x'80 - x'FF
The most significant address A[7] determines whether configuration registers or EP buffer memory is accessed. When the
configuration memory is selected by asserting address A[7], the address bus points to an exact location of a configuration
register. When A[7] is de-asserted, A[6:0] provide the address of the endpoint buffer being accessed. Access from within the
selected endpoint buffer is performed via internal address counters.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
87
Address Space
88
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
5. Interrupt
The interrupt signal (INT) is triggered by the different events defined in the P-Port Interrupt Register, which is the highest hierarchy interrupt status register. Each of the interrupt events can be masked and unmasked by the corresponding field in P-Port
Interrupt Mask Register. Figure 5-1 shows the interrupt hierarchy block diagram. Table 5-1 and Table 5-2 show all the interrupt status registers.
CY_AN_MEM_PLL_LOCK_LOSS_STAT
Register
CY_AN_MEM_PWR_MAGT_STAT
Register
CY_AN_MEM_P0_MAILBOX Register
CY_AN_MEM_P0_DRQ_REG
Register
CY_AN_MEM_Pn_MCU_STAT
Register
DRQSTAT
CY_AN_MEM_P0_INTR_REG
P-Port Interrupt
Register
CY_AN_MEM_P0_INT_MASK_REG
P-Port Interrupt Mask
Register
Figure 5-1. Antioch Interrupt Events Hierarchy Block Diagram
MPLLLOCKINT
MPMINT
MMBINT
MDRQINT
MMCUINT
PLLLOCKINT
PMINT
Int#
MBINT
DRQINT
MCUINT
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
89
Interrupt
Table 5-1. P-Port Interrupt Register
P-Port Interrupt Registers
CY_AN_MEM_P0_INTR_REG
x'90
This registers is the top level interrupt register. When a hardware interrupt is asserted, the processor needs to read this register to identify
what event(s) triggered the interrupt. The details of the event can be read through the status register that corresponds to the bit field. The
interrupts can be masked by the CY_AN_MEM_P0_INT_MASK_REG register. The processor can monitor the particular interrupt event by
polling this register.
Field Name
Descriptions
MCUINT
This bit is set to “1” to indicate that the internal MCU (8051) has asserted an interrupt. The MCU interrupt events will
be indicated by CY_AN_MEM_P0_MCU_STAT register. This bit will be reset to “0” after reading the
CY_AN_MEM_P0_MCU_STAT register.
DRQINT
This bit is set to “1” to indicate one or more than one DRQ event happened. It requires reading the DRQ Status
Register to find out which DRQ event trigger the interrupt.
MBINT
This bit is set to “1” when 8051 MCU sends a message to the P-Port Mailbox Register. This bit is cleared when the
processor reads the P-Port Mailbox Register0.
PMINT
This bit is set to “1” when the Antioch wakes up from stand by mode (as indicated by the WAKEUP field of the
Power Management Control and Status Register). This field is cleared when the processor reads the Power Management Control and Status Register.
PLLLOCKINT
This bit set to “1” when the internal PLL lock loses. Processor needs to read the PLL Lock Loss Status Register
(CY_AN_MEM_PLL_LOCK_LOSS_STAT) to clear the status.
Bit
Field
4:0
5
MCUINT
10:6
Description
RW
Reset
Reserved
R
0
MCU (8051) Interrupt
0: MCU does not generate an interrupt
1: MCU interrupt asserted
R
0
Reserved
R
0
0
11
DRQINT
DRQ Event Interrupt
0: No DRQ event
1: One or more than one DRQ event happened (need to read the DRQ register to find out
the DRQ event)
R
12
MBINT
Mailbox interrupt
0: No message is sent by 8051
1: Receive a message from 8051. This status bit is cleared by reading the P-Port Mailbox
Register. R
0
13
PMINT
Power Management Interrupt
0: No interrupt from Power Management Control and Status register
1: Interrupt from Power Management Control and Status register (e.g. wake up)
R
0
14
PLLLOC
KINT
PLL Lock Loss Interrupt
0: PLL lock is not lost
1: PLL lock lost
R
0
Reserved
R
0
15
90
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Interrupt
Table 5-2. P-Port Interrupt Mask Register
P-Port Interrupt Mask Registers
CY_AN_MEM_P0_INT_MASK_REG
x'91
This register corresponds to the bit field of CY_AN_MEM_P0_INTR_REG register to enable or disable the interrupt events that generate
the hardware interrupts (INT#) to the processor at P-Port.
Field Name
Descriptions
MMCUINT
Set “1” to this bit field to enable the MCU interrupt. Reset this bit field to “0” to disable the MCU interrupt.
MDRQINT
Set “1” to this bit field to enable the DRQ Event Interrupt. Reset this bit field to “0” to disable the DRQ Event Interrupt.
MMBINT
Set “1” to this bit field to enable the Mail Box Interrupt. Reset this bit field to “0” to disable the Mail Box Interrupt
MPMINT
Set “1” to this bit field to enable the Power Management Interrupt (e.g. Wake Up from standby mode). Reset this bit
field to “0” to disable the Power Management Interrupt
MPLLLOCKINT
Set “1” to this bit field to enable the PLL Lock Loss Interrupt. Reset this bit field to “0” to disable the PLL Lock Loss
Interrupt.
Bit
Field
4:0
5
MCUINT
10:6
Description
RW
Reset
Reserved
R
0
Mask MCU (8051) Interrupt
0: Disable MCU interrupt
1: Enable MCU interrupt
RW
0
Reserved
R
0
11
MDRQINT
Mask DRQ Event Interrupt
0: Disable DRQ Event Interrupt
1: Enable DRQ Event Interrupt
RW
0
12
MMBINT
Mask Mailbox interrupt
0: Disable Mailbox Interrupt
1: Enable Mailbox Interrupt.
RW
0
13
MPMINT
Mask Power Management interrupt
0: Disable Power Management interrupt
1: Enable Power Management Interrupt
RW
0
14
PLLLOC
KINT
Mask PLL Lock Loss Interrupt
0: Disable PLL Lock Loss interrupt
1: Enable PLL Lock Loss Interrupt
RW
0
15
Reserved
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
91
Interrupt
92
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
6. Bootup Initialization
The initialization of Antioch involves three steps: Reset, Configuration of registers, and Firmware loading. Initialization takes
place on hard reset, which is triggered by the RESET# input pin, and Whole Device soft reset, which is triggered by writing
“11” to the RSTCTRL field of the Soft Reset Control Register. The hard reset and Whole Device soft reset have the same
behavior. Figure 6-1 shows the high level reset and initialization timing diagram. Reset/standby timing parameters are
described in Section 3.4.
6.1
Reset by Pin (Hard Reset)
The Hard Reset involves the RESET# input pin, the RESETOUT output pin and the WAKEUP input pin. When the RESET#
input pin is pulsed, Antioch de-asserts (drives LOW) the RESETOUT output (RSTCMPT field in the Soft Reset Control Register is tied to RESETOUT signal). The WAKEUP pin is a don't care while RESET# is driven LOW. The WAKEUP pin has to be
asserted HIGH for initialization to occur. When Antioch is ready for general operations (after firmware is initialized), it asserts
the RESETOUT signal HIGH. A Hard Reset needs to be carried out every time Antioch's core has been powered down and is
then powered back up.
The use of the RESET# pin has the following characteristics:
■
For as long as RESET# is asserted, RESETOUT is de-asserted LOW. All other IOs, with the exception of UVALID and
XTALOUT, are high-Z during RESET# assertion (default values of IOs during reset are listed in Table 2-1 through
Table 2-6).
■
After RESET# is de-asserted, RESETOUT remains de-asserted. If WAKEUP is also asserted at this time, Antioch starts
performing the internal initialization which includes loading the 8051 MCU firmware. During this initialization period, the
processor also configures the P-Port Endian Configuration Register and other configuration registers.
■
No data transfer functions should be performed on Antioch until the processor has configured all configuration registers,
loaded the 8051 firmware, and exited Configuration Mode (8051 firmware resets the CFGMODE field of P-Port Interface
Configuration Register to “0”).
■
To summarize the behavior of Antioch based on the level of the RESET# AND WAKEUP pins, refer to Table 6-1.
Table 6-1. RESET# and WAKEUP behavior
RESET#
WAKEUP
Action
0
Don't Care
Device in Reset
1
0
Standby modea
1
1
Normal mode of operationa
a. Antioch will enter this mode in the case that it has been
properly reset and initialized previously. If not initialized
previously, the behavior is as follows:
RESET#=1, WAKEUP=0: Antioch requires RESET# to be
pulsed after initial power-up for valid Standby low-power
state. RESETOUT will be tri-stated until WAKEUP is asserted HIGH.
RESET#=1, WAKEUP=1: Device does not enter initialization mode until RESET# has been pulsed with WAKEUP asserted. Without a RESET# pulse after the
assertion of WAKEUP, Antioch will continue to remain in
pre-initialization state.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
93
Bootup Initialization
At initial power up and each time the core is powered up, it is mandatory for a Hard Reset (asserting RESET# input) to be performed with the WAKEUP pin asserted.
8051 firmware resets CFGMODE field and sets
RSTCMPT field to release the Antioch from the
initialization state
If firmware load by Processor: Processor writes “00” to
RSTCTRL field to release 8051 from reset state. 8051
starts to execute the firmware.
Load the firmware from Processor
Processor configures all configuration registers
Processor configures CY_AN_MEM_P0_ENDIANT
Register for Endiant configuration.
WAKEUP field of CY_AN_MEM_PWR_MAGT_STAT
Register = 1 indicates that the internal PLL gets locked
CFGMODE field in CY_AN_MEM_P0_VM_SET is set
External power and clock are stable
Figure 6-1. Reset and Initialization Timing Diagram
RESET#
WAKEUP
RESETOUT
and
RSTCMPT
6.2
Reset by Register (Soft Reset)
The Soft Reset involves the processor setting the bits appropriately in the Soft Reset Control Register. The RSTCTRL bits in
the Soft Reset Control Register control the type of Soft Reset. There are two types of Soft Reset, namely:
1. MCU PC Reset - During MCU PC Reset, only the 8051 MCU Program Counter is reset to the starting address (its Program RAM contents are maintained). This reset will not reset any registers. The firmware code does not need to be
reloaded following an 8051 MCU PC Reset.
2. Whole Device Reset - This Reset is identical to Hard Reset described in Section 6.1. The firmware code must be reloaded
following a Whole Device Reset.
When the processor performs a Whole Device soft reset of Antioch by writing “11” to the RSTCTRL field, Antioch internally
generates a reset pulse. After the internal reset pulse de-asserts, the RSTCTRL field is set to “01” to keep the 8051 in reset
during download of the firmware code and register configuration.
The processor is required to reset the RSTCTRL field to “00” via the P-Port after it finishes loading the firmware. The 8051
then begins firmware initialization.
The RSTCMPT field identifies the end of firmware initialization and the enabling of normal data transfer. It provides the same
function as the CFGMODE field of P-Port Interface Configuration register (with opposite polarity).
94
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Bootup Initialization
Table 6-2. Soft Reset Control Register
Soft Reset Control Registers
CY_AN_MEM_RST_CTRL_REG
x'81
This register is used to initiate different types of Antioch reset.
Field Name
Descriptions
RSTCTRL
Reset Control. This field selects the different software reset for the Antioch:
MCU Reset - This reset resets the 8051 MCU only. After this reset, the Antioch is not required to reload the firmware or reconfigure the Antioch configuration registers.
Whole Device Reset - This reset acts similar to a hardware reset by resetting the whole Antioch. This reset requires
reloading of the firmware and reconfiguration of all configuration registers.
RSTCMPT
This field is used to report the Antioch's status after reset. This field is the same value as the RESETOUT pin. When
this field is “0”, it indicates that Antioch is in initialization state. After reset de-asserts, Antioch is in initialization state
during which the internal PLL locks, followed by the processor loading the 8051 firmware and Antioch configuration
registers. In this state, the Antioch is not in the normal operation mode except to allow downloading the firmware
from P-Port and read/write to the configuration registers. RSTCTRL must be set to '00' after processor download is
complete to enable 8051. The RSTCMPT field is set to '1' by 8051 after firmware initialization is complete.
Bit
1:0
2
15:3
6.3
Field
Description
RW
Reset
RSTCTRL
Reset Control
00: No Soft Reset is applied
01: MCU Reset - reset 8051 MCU PC only.
10: Reserved
11: Whole Reset - this reset is same as hardware reset. It requires reloading the firmware
and reconfigures all configuration registers.
RW
01
RSTCMPT
Reset Complete
0: Antioch is in reset and initialization state. In this state, U-Port and S-Port is not ready for
access.
1: Antioch completes the reset and initialization. It is ready for accessing the U-Port and SPort from P-Port
R
0
Reserved
R
U/D
Wakeup Mechanism
After the device has been properly reset and initialized, Antioch stays in normal operation mode as long as the WAKEUP pin
is asserted. When WAKEUP is de-asserted, Antioch enters standby mode as described in Section 8.4. When WAKEUP is
asserted, Antioch exits standby mode. Antioch interrupts the processor and sets the PMINT field in the P-Port Interrupt Register and the WAKEUP field in the Power Management Control and Status Register. The interrupt bit is cleared when the processor reads the Power Management Control and Status Register.
If the WAKEUP pin is not used by an application, it must be tied HIGH to enable normal operation.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
95
Bootup Initialization
6.4
Firmware Loading
The estimated size of the firmware for the 8051 MCU within Antioch, and therefore the size of the RAM is 24kB. Note that the
Program RAM is supplied by VDD (core) and the firmware needs to be reloaded every time VDD (core) is applied or reapplied. The 8051 MCU firmware is loaded to the Program RAM by the processor Boot Mode (Antioch default).
6.4.1
Loading the Firmware from the Processor
After power on reset, the processor at the P-Port loads the 8051 firmware to the 8051 Program RAM. The firmware image is
required to be split into chunks of 64 bytes for download. The last chunk of the firmware image can be between 2 and 64
bytes, but must be an even number of bytes. The processor first loads the 4 byte SETUP packet through the EP2 buffer to
Antioch. After that, the processor starts loading the firmware image in chunks of 64 bytes. After the completion of firmware
load, the P-Port processor is required to release the 8051 MCU from reset by writing “00” to RSTCTRL. The SETUP packet is
shown in Figure 6-2 and the firmware loading flowchart is shown in Figure 6-3.
■
After a whole-chip reset, the 8051 MCU is in soft reset. (Note the 8051 is in reset because the RSTCTRL defaults to “01”).
■
The processor polls the WAKEUP field in the Power Management Control and Status Register
(CY_AN_MEM_PWR_MAGT_STAT) to ensure the PLL is locked before configuring the configuration registers.
■
The processor must first configure the P-Port Endian Configuration Register and then configures the rest of the configuration registers (addresses 0x80 through 0xFB).
■
The firmware is downloaded from the processor using the following steps. Antioch has a 24kB program/data memory. So,
total firmware needs to be less than that size. The downloaded firmware needs to be broken down into chunks of 2 to 64
bytes (the data packet must be transferred in an even number of bytes) for the download.
a. The processor writes the value 4 to the COUNT field of EP2 Endpoint Buffer DMA Register
(CY_AN_MEM_P0_EP2_DMA_REG) and sets DMAVAL field of the EP2 Endpoint Buffer DMA Register. This step is
sending a request for the EP2 buffer for data transfer.
b. If the internal EP2 buffer is available, the EP2DRQ field in the DRQ Status Register is set to “1” (for polling) and the
DRQ signal (for DMA) is asserted.
c. After the EP2DRQ field is set to “1”, the processor loads the 4 byte SETUP packet to Endpoint Buffer EP2. In the
SETUP packet, the first and second bytes define the Program RAM Destination Address (DA) and the third and fourth
bytes define the total data packet length - dataLength (dataLength must be an even number of bytes). Figure 6-2
shows the SETUP packet format.
d. After the 4 byte SETUP packet has been loaded to EP2, the processor resets the DMAVAL field of the EP2 Endpoint
Buffer DMA Register to zero. This step indicates the internal mechanism that the download is complete and also
resets the EP2DRQ field to “0” and de-asserts the DRQ signal. For further details, refer to Section 3.6.
e. Internally, Antioch takes the 4-byte SETUP packet (Destination Address and packet Length) and encodes it to an 8byte setup token(s).
f.
After the SETUP packet has been sent, processor starts preparing to load the data packet (firmware image).
g. The processor writes dataLength (number of bytes of the following data packet) to the COUNT field (2 to 64, must be
even number of bytes) and sets the DMAVAL field to “1” of EP2 Endpoint Buffer DMA Register
(CY_AN_MEM_P0_EP2_DMA_REG). As in step a, this step is sending a request for the EP2 buffer for data transfer.
h. The processor waits for EP2 DRQ (either by polling the EP2DRQ or by waiting for the assertion of DRQ signal).
i.
When EP2 is available, Antioch sets EP2DRQ to “1” and the DRQ signal is asserted.
j.
When EP2DRQ is set or DRQ signal is asserted, the processor loads the data packet (firmware) to Endpoint Buffer
EP2.
k. After the data packet has been loaded to EP2, the processor is required to reset of the DMAVAL field of the EP2 Endpoint Buffer DMA Register to “0”. This step indicates to the internal mechanism that the download is complete and also
resets the EP2DRQ field to “0” and de-asserts the DRQ signal. For further details, refer to Section 3.6.
l.
Antioch resets EP2 DRQ and de-asserts the DRQ signal.
m. Repeat step g to step l until the firmware image loading is complete.
■
96
The processor releases the 8051 MCU from reset by writing “00” to the RSTCTRL field of the
CY_AN_MEM_RST_CTRL_REG register. Internally, the de-assertion of the CPU reset is gated to ensure that the last
chunk of firmware has been transferred from the write FIFO to the 8051 program memory. The 8051 then starts executing
its program.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Bootup Initialization
■
The firmware running on 8051 then clears the CFGMODE field in the P-Port Interface Configuration Register
(CY_AN_MEM_P0_VM_SET) by writing a “0”. This step causes Antioch's RESETOUT pin and RSTCMPT field in Soft
Reset Control Register to go HIGH. Note the CFGMODE field is accessible only to Antioch firmware.
Figure 6-2. The SETUP Packet Format
The Format of 4 bytes SETUP Packet
Program RAM Addr LSB
1 st Byte
Program RAM Addr MSB
2 nd Byte
Data Packet Length LSB
3 rd Byte
Data Packet Length MSB
4 th Byte
* Data Packet Length must be even
number of byte
Figure 6-3. Firmware Loading by Processor Flow Chart
Start Firmware
Download
Load 4 bytes
SETUP Packet
2 to 64 bytes
Data Packet
(must be even
number of byte)
No
Load Firmware
Complete?
YES
Set RSTCTL field in
CY_AN_MEM_RST_CTRL_REG register to “00”
Done
6.5
Configuration of Registers
West Bridge Antioch internal registers must be set up following a Hard Reset or a Whole Device soft reset via the Soft Reset
Control Register. In this stage, the external processor provides the values by writing to the registers.
Note that the default values in registers will allow the processor to program the internal 8051 and access all registers.
At any time when the RESET# input is de-asserted (and reset timing is satisfied), the external processor can write to the configuration registers. The processor must ensure that all registers are properly configured. The processor can override the values in the configuration registers in this setup. 8051 firmware must reset the CFGMODE field in the “P-Port Interface
Register” to indicate the completion of reset initialization. When complete, Antioch de-asserts the RESETOUT pin and resets
the CFGMODE field in the P-Port Interface Configuration Register to “0”.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
97
Bootup Initialization
6.6
Processor Boot Mode Initialization Transaction
Figure 6-4 shows the Initialization flow chart after RESET# signal is de-asserted.
Figure 6-4. Processor Boot Mode Initialization Flow Chart
RESET signal de-assert
RESETOUT signal still asserted
RSTCMPT field is reset (“0”)
NO
WAKEUP = “1”?
YES
1. Processor MUST CONFIGURE the "Endian Configuration Register"
2. Processor configures all other configuration registers
3. Processor load the 8051 firmware to 8051 Program RAM through
the EP2 Endpoint Buffer.
4. Processor write “00” to RSTCTRL field of “Soft Reset Control
Register"
5. 8051 starts running its firmware
6. CFGMODE is cleared, and RESETOUT pin and RSTCMPT field are both set by Antioch.
Initialization is completed
Table 6-3. P-Port Endian Configuration Register
P-Port Endian Configuration Registers
CY_AN_MEM_P0_ENDIAN
x'82
This register is used to configure the bus Endian order for the P-Port interface. This register must be configured first after reset before loading
the firmware from the processor. Both bit 0 and bit 8 must have the same value written to them. Therefore, irrespective of the actual Endian
configuration of the bus before configuration, it will be configured to the right Endian configuration after bit 0 and bit 8 are set to the correct
value.
Field Name
Descriptions
ENDIANL
P-Port Byte Order: This field configures the 16-bit P-Port interface byte ordering to be Little Endian or Big Endian
ordering. This field must be configured first after reset.
ENDIANH
P-Port Byte Order: This field configures the 16-bit P-Port interface byte ordering to be Little Endian or Big Endian
ordering. This field must be configured first after reset.
Bit
Field
Description
RW
Reset
ENDIANL
P-Port endian selection
0: P-Port is set to Little Endian
1: P-Port is set to Big Endian
RW
0
7:1
Reserved
R
0
8
ENDIANH
P-Port endian selection
0: P-Port is set to Little Endian
1: P-Port is set to Big Endian
RW
0
Reserved
R
0
0
15:9
98
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Bootup Initialization
Table 6-4. P-Port Interface Configuration Register
P-Port Interface Configuration Registers
CY_AN_MEM_P0_VM_SET
x'83
This register is used to configure the P-Port interface
Field Name
Descriptions
VMTYPE
P-Port Interface Type - This field is used to configure the interface type that connects to the P-Port.
VMWIDTH
P-Port Interface Data Bust Width - This field is for future. The field is read only and always shows the data bus width
is 16-bit.
FLOWCTRL
P-Port Flow Control - This field is for future use. This field is read only and always shows flow control for the P-Port
is disabled.
Interface Mode - This field is program the interface mode of Antioch. The Antioch can interface with the processor
either in asynchronous or synchronous mode. The Antioch is in asynchronous mode by default after power up and
can be switched to sync mode.
IFMODE
CFGMODE
Configuration Mode - This field is read-only to the processor. This field is set to “1” when the Antioch performs either
Hard Reset or Soft Reset. CFGMODE= '1' indicates that Antioch is in configuration mode. In this mode, the processor can load the 8051 firmware code to the internal RAM through the P-Port interface, and write/update the configuration registers. After the configuration is complete and 8051 reset de-asserted by the processor, 8051 firmware
must reset this field to “0” to exit to normal operation mode.
Antioch can't directly enter into Configuration Mode by setting this field to “1” during normal operation. If it requires
a firmware upgrade, it can use the Software Reset to enter into Configuration Mode to load the firmware. However,
when this mode is entered, the U-Port and S-Port are disconnected, the ongoing transfer process is stopped and
the transferring data, which in the endpoint buffer, is corrupted.
DACKEOB
This bit is used to configure the DMA acknowledge signal (DACK#) from the processor to behave in ACK or EOB
mode.
OVERRIDE
Override Enable - This field is used to force deterministic values onto the INT# and DRQ# outputs (as determined
by INTOVERD and DRQOVERD bits). It is only used for debug.
INTOVERD
INT# signal Override - This field contains the value to drive out from INT# when OVERRIDE = '1'. INTOVERD: '0' =
Drive LOW, '1' = Drive HIGH.
DRQOVERD
DRQ# signal Override - This field contains the value to drive out from DRQ# when OVERRIDE = '1'. DRQOVERD:
'0' = Drive De-asserted, '1' = Drive Asserted. Assertion level is determined by setting of DRQPOL field.
DRQPOL
DRQ# Polarity Select - This field determines the polarity of the DRQ# output signal. DRQ# is active LOW when
DRQPOL = '0'. DRQ# is active HIGH when '1'.
DACKPOL
DACK# Polarity Select - This field determines the polarity of the DACK# input signal. DACK# is active LOW when
DRQPOL = '0'. DACK# is active HIGH when '1'.
Bit
Field
Description
RW
Reset
2:0
VMTYPE
P-Port Interface Type 000: Reserved 001: Reserved 010: Reserved 011: Reserved 100:
Reserved 101: RAM 110: Reserved 111: Reserved
3
VMWIDTH
P-Port Interface Data Bus Width 0: 16-bits 1: Reserved for the future
R
0
3
VMWIDTH
P-Port Interface Data Bus Width 0: 16-bits 1: Reserved for the future
R
0
4
FLOWCTRL
P-Port Flow Control. 0: Disable 1: Reserved for the future
R
0
5
IFMODE
P-Port Interface Mode 0: Asynchronous Interface Mode 1: Synchronous Interface Mode
RW
0
6
CFGMODE
Configuration Mode 0: Normal operation mode. 1: Configuration mode. *This bit is reset to
“0” by 8051 firmware after completing all the configuration process.
R
1
7
DACKEOB
DMA Acknowledge Configuration 0: EOB mode 1: ACK mode
RW
0
8
OVERRIDE
Override Enable 0: No Override (normal operation) 1: Override INT# and DRQ# with values
determined by INTOVERD and DRQOVERD, respectively
RW
0
9
INTOVERD
Override Value for INT# output signal 0: Drive LOW 1: Drive HIGH
RW
0
0
R
101
10
DRQOVERD
Override Value for DRQ# output signal 0: Drive De-asserted Level 1: Drive Asserted Level
RW
11
DRQPOL
Polarity Select for DRQ# Output signal 0: Active LOW 1: Active HIGH
RW
0
12
DACKPOL
Polarity Select for DACK# Input signal 0: Active LOW 1: Active HIGH
RW
0
Reserved
R
U/D
15:13
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
99
Bootup Initialization
Table 6-5. 8051 MCU Status Register
8051 MCU Status Register
CY_AN_MEM_P0_MCU_STAT
x'94
This register contains the status of the MCU. A read of this register will clear it, and clear the MCUINT field of its corresponding
CY_AN_MEM_P0_INTR_REG register.
Field Name
Descriptions
CARDINS
This field is set when an SD/MMC card has been inserted. It is cleared when this register is read.
CARDREM
Bit
This field is set when an SD/MMC card has been removed. It is cleared when this register is read.
Field
Description
0
CARDINS
0: No action has occurred.
1: An SD/MMC card has been inserted.
1
CARDREM
0: No action has occurred.
1: An SD/MMC card has been Removed.
15:2
RW
Reset
R
0
R
0
Reserved
Table 6-6. PLL Lock Loss Status Register
PLL Lock Loss Status Register
CY_AN_MEM_PLL_LOCK_LOSS_STAT
x'C4
This register shows the status of PLL Lock
Field Name
Descriptions
PLLSTAT
This field shows the current status of PLL Lock. If this bit field is set, it indicates the PLL Lock is lost. When this field
is set, it triggers an interrupt (if MPLLLOCKINT field is set).
Bit
0
15:1
100
Field
PLLSTAT
Description
PLL Lock Loss Status
0: PLL Lock is not lost
1: PLL Lock is lost
RW
R
Reset
0
Reserved
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Bootup Initialization
Table 6-7. Drive Strength and Slew Rate Control Register
Drive Strength and Slew Rate Control Register
CY_AN_MEM_IROS_IO_CFG
x'C1
This register is used to configure the drive strength and slew rate of the IOs.
Field Name
Descriptions
GPIODRVST
G-Port IO Drive Strength Control.
GPIOSLEW
G-Port IO Slew Rate Control.
PPIODRVST
P-Port IO Drive Strength Control.
PPIOSLEW
P-Port IO Drive Strength Control.
SSPIODRVST
SS-Port IO Drive Strength Control
SSPIOSLEW
SS-Port IO Slew Rate Control.
SNPIODRVST
SN-Port Drive Strength Control.
SNPIOSLEW
SN-Port Slew Rate Control
Bit
Field
Description
RW
Reset
1:0
GPIODRVST
G-Port IO Drive Strength
00: Full Strength
01: Three Quarter Strength
10: Half Strength
11: Quarter Strength
2
GPIOSLEW
G-Port IO Slew Rate
0: Slow
1: Fast
RW
0
4:3
PPIODRVST
P-Port IO Drive Strength
00: Full Strength
01: Three Quarter Strength
10: Half Strength
11: Quarter Strength
RW
00
5
PPIOSLEW
P-Port IO Slew Rate
0: Slow
1: Fast
RW
0
7:6
Reserved
R
U/D
9:8
SSPIODRVST
SS-Port IO Drive Strength
00: Full Strength
01: Three Quarter Strength
10: Half Strength
11: Quarter Strength
RW
00
10
SSPIOSLEW
SS-Port IO Slew Rate
0: Slow
1: Fast
RW
0
12:11
SNPIODRVST
SN-Port IO Drive Strength
00: Full Strength
01: Three Quarter Strength
10: Half Strength
11: Quarter Strength
RW
00
13
SNPIOSLEW
SN-Port IO Slew Rate
0: Slow
1: Fast
RW
0
Reserved
R
U/D
15:14
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
RW
00
101
Bootup Initialization
Table 6-8. Antioch Configuration ID Register
Antioch Configuration ID Register
CY_AN_MEM_CM_WB_CFG_ID
x'80
A read from this register will return the Version Number and Hardware ID.
Field Name
Descriptions
VER
Version Number. This field will store the version number for the West Bridge Antioch device.
HDID
Bit
Hardware ID. This field will store the West Bridge Antioch device ID.
Field
Description
RW
Reset
3:0
VER
This field stores the West Bridge Antioch silicon version number
R
Version
15:4
HDID
This filed stores the West Bridge Antioch device ID
R
H/W ID
Note Configuration ID for Antioch silicon (CYWB0124AB) is as follows:
Rev A silicon - x'A100, Rev B silicon - x'A101, Rev C silicon - x'A103.
102
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
7. Mailbox Registers
Antioch provides a total of 8 mailbox registers for communication between the processor at P-Port and 8051 MCU. Four of the
mailbox registers are for the processor to send a message to the 8051 MCU. The other four mailbox registers P-Port Mailbox
Register are for the 8051 MCU to send a message to the processor. There are 8 bytes of mailbox message capability each for
the processor and the 8051 MCU.
When the processor sends the message to 8051 through the 8051 MCU Mailbox Register, Antioch internally generates an
interrupt to 8051 MCU to indicate that a message has been sent by the processor. At the same time, the MBNOTRD field in
8051 MCU Mailbox Status Register is set to “1”. The MBNOTRD field in 8051 MCU Mailbox Status Register is set to “1” to
show to the processor that the 8051 has not read the message from the 8051 MCU Mailbox Register. This field is cleared
when 8051 reads the message from 8051 MCU Mailbox Status Register. When 8051 sends a message to the processor
through the P-Port Mailbox Register, MBINT field in the P-Port Interrupt Register is set to “1” and an interrupt signal at P-Port
triggers the processor's interrupt. Processor reads the P-Port Mailbox Register to clear the MBINT field.
“Commands” to Antioch are communicated from the processor to the 8051 MCU within Antioch through the four 8051 MCU
Mailbox Registers. Antioch communicates the status or results of the commands back to the processor using the four P-Port
Mailbox Registers.
Table 7-1. 8051 MCU Mailbox Register
8051 MCU Mailbox Register
CY_AN_MEM_MCU_MAILBOX0
CY_AN_MEM_MCU_MAILBOX1
CY_AN_MEM_MCU_MAILBOX2
CY_AN_MEM_MCU_MAILBOX3
x'F8
x'F9
x'FA
x'FB
These registers are used for message-passing between the processor and the 8051 MCU within Antioch. This register is read-write to the
processor and read-only to the 8051 MCU. When the processor write to CY_AN_MEM_MCU_MAILBOX0 register, it triggers an internal interrupt to the 8051 MCU. In this case, if the processor passes multi bytes message to 8051 MCU, it must first write to
CY_AN_MEM_MCU_MAILBOX1 to CY_AN_MEM_MCU_MAILBOX3 and then final write to CY_AN_MEM_MCU_MAILBOX0 register. Internally MCU accesses these registers one byte at a time. The internal interrupt is cleared when the 8051 MCU reads the least significant byte
of this register. The interrupt to 8051 will not be cleared if the processor reads this register.
Field Name
Descriptions
MESSAGE
Bit
15:0
This field contains the 16-bit message that the processor communicates to the 8051 MCU.
Field
MESSAGE
Description
Mailbox message from processor to 8051 MCU
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
RW
RW
Reset
0
103
Mailbox Registers
Table 7-2. P-Port Mailbox Register
P-Port Mailbox Register
CY_AN_MEM_P0_MAILBOX0
CY_AN_MEM_P0_MAILBOX1
CY_AN_MEM_P0_MAILBOX2
CY_AN_MEM_P0_MAILBOX3x'F0
x'F0
x'F1
x'F2
x'F3
These registers are used for message-passing between the 8051 MCU and the processor. These registers are read-only to the processor
and are read-write to the 8051 MCU. When the 8051 MCU writes the message into CY_AN_MEM_P0MAILBOX0, which triggers an interrupt
to the processor. In this case, if 8051 MCU pass multi bytes message to processor, it must first write to CY_AN_MEM_P0MAILBOX1 to
CY_AN_MEM_P0MAILBOX3 registers and then finally writes to CY_AN_MEM_P0MAILBOX0. When the MCU writes to the least significant
byte of this register, the interrupt to the processor is triggered. The interrupt is cleared when the processor reads this register. The interrupt
will not be cleared if the 8051 MCU reads the register.
Field Name
Descriptions
MESSAGE
Bit
15:0
This field contains the 16-bit message that the 8051 MCU communicates to the processor.
Field
MESSAGE
Description
Mailbox message from 8051 MCU to processor
RW
R
Reset
0
Table 7-3. 8051 MCU Mailbox Status Register
8051 MCU Mailbox Status Register
CY_AN_MEM_MCU_MB_STAT
x'92
This register shows the status that if the 8051 MCU complete reading the message from the Mailbox Register.
Field Name
Descriptions
MBNOTRD
This field shows the status of the 8051 MCU Mailbox Registers. When the processor send the message to 8051
MCU through the 8051 MCU Mailbox Register this field is set to “1”. When the 8051 has read the message, which
was sent by the processor, from the 8051 MCU Mailbox Register, this field is reset to “0”. processor requires checking this field before sending the message to the 8051 MCU Mailbox Register.
Bit
0
15:1
104
Field
MBNOTRD
Description
RW
Reset
Mailbox Not Read
0: 8051 MCU Mailbox register is empty or have been read by 8051
1: 8051 has not read the message from the 8051 MCU Mailbox register
R
0
Reserved
R
U/D
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
8. Power
8.1
Power Domains
Antioch has three main groups of power supply domains:
*VDDQ: This refers to a group of four independent supply domains for the digital IOs. The nominal voltage level on these supplies can be 1.8V, 2.5V or 3.3V. Specifically, the four separate IO power domains are:
■
PVDDQ - P-Port processor interface IO
■
SNVDDQ - S-Port NAND interface IO
■
SSVDDQ - S-Port SD interface IO
■
GVDDQ - Other miscellaneous IO
(UVDDQ for USB IO is also an IO power domain and is listed separately)
VDD: This is the supply voltage for the logic core. The nominal supply voltage level is 1.8V. This supplies the core logic circuits. The same supply must also be used for AVDDQ.
VDD33: This is a no-connect internally in CYWB0124AB. This is an independent 3.3V nominal supply that handles power
sequence control in future revisions. It must be connected to the highest supply to the device to enable easy migration.
AVDDQ: This is the 1.8V supply for PLL and USB serializer analog components. The same supply must also be used for
VDD. Maximum permitted noise on AVDDQ is 20 mV p-p.
UVDDQ: This is the 3.3V nominal supply for the USB IO and some analog circuits. This supply powers the USB transceiver.
XVDDQ: This is the clock IO supply: 3.3V for XTAL, or 1.8V for external clock.
Figure 8-1. Antioch Power Supply Domains
*VDDQ
VDD
UVDDQ
D+
I/O
D-CORE
USB-IO
D-
Noise guideline for all supplies except AVDDQ is maximum 100mV p-p. All IO supplies of Antioch must be ON when the system is active even if Antioch is not being used. Note that UVDDQ must be always powered up.
The core VDD can be deactivated at any time to preserve power, provided that there is a minimum impedance of 1 k?
between the VDD pin and ground. All IOs are tri-stated when the core is disabled.
8.1.1
Power Supply Sequence
The power supplies can be independently sequenced without damaging the part. All power supplies have to be up and stable
before the device can operate. In the absence of all supplies being stable, the remaining domains will be in low-power
(standby) state.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
105
Power
8.1.2
Power Supply Decoupling Recommendations
VDD - 2.2 µF, 0.1 µF
AVDDQ - Although AVDDQ must be tied to the same 1.8V supply as VDD, it must be routed separately with 0.1 µF and 0.01
µF decoupling capacitors.
UVDDQ - 2.2 µF, 0.1 µF
Other supplies - do not have specific decoupling requirements, use 2.2 µF and 0.1 µF. If more than one of these supply pins
is tied to the same voltage supply, one set of decoupling should suffice.
106
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Power
8.2
AC-DC Characteristics
Table 8-1. DC Specifications
Min.
Typ.
Max.
Unit
VDD
Parameter
Core Voltage Supply
1.7
1.8
1.9
V
AVDDQ
Analog Voltage Supply
1.7
1.8
1.9
V
XVDDQ
Crystal Voltage Supply
3.0
3.3
3.6
V
XVDDQ
Clock Voltage Supply
1.7
1.8
1.9
V
Processor Interface IO
1.7
1.8, 2.5,
3.3
3.6
V
GVDDQa
Miscellaneous IO Voltage Supply
1.7
1.8, 2.5,
3.3
3.6
V
SNVDDQa
S-Port NAND IO Voltage Supply
1.7
1.8, 2.5,
3.3
3.6
V
SSVDDQba
S-Port SD IO Voltage Supply
1.7
1.8, 2.5,
3.3
3.6
V
UVDDQc
USB Voltage Supply
3.0
3.3
3.6
V
VDD33
Power Sequence Control Voltage
Supply
3.0
3.3
3.6
V
VIH1d
Input HIGH Voltage 1
All ports except USB, 2.0V<Vcc<3.6V
0.625*VC
C
VCC +
0.3
V
VIH2d
Input HIGH Voltage 2
All ports except USB, 1.7V<Vcc<2.0V
VCC-0.4
VCC +
0.3
V
VIL
Input LOW Voltage
–0.3
0.25*VC
C
V
PVDDQ
a
Description
Conditions
VOH
Output HIGH Voltage
IOH(MAX) = -0.1 mA
VOL
Output LOW Voltage
IOL(MIN) = 0.1 mA
IIX
Input Leakage Current
All IO signals held at VDDQ
IOZ
Output Leakage Current
All IO signals held at VDDQ
ICC Core
Operating Current of Core Voltage
Supply (VDD) and Analog Voltage
Supply (AVDDQ)
ICC Crystal
ICC USB
0.9*VCC
V
0.1*VCC
V
–1
1
µA
–1
1
µA
Outputs Tri-stated
110
mA
Operating Current of Crystal Voltage
Supply (XVDDQ)e
XTALOUT Floating
5
mA
Operating Current of USB Voltage
Supply (UVDDQ)e
Operating and terminated for High-speed mode
25
mA
2500
µA
1. *VDDQ=3.3V nominal (3.0-3.6V)
ISB1
2. Outputs and Bidirs High or Floatingf
Total Standby Current of Antioch
when the device is in Suspend mode 3. XTALOUT Floating
5. D+ Floating, D- Grounded, UVALID Driven Low
5. Device in Suspend mode
ISB2
Total Standby Current of Antioch
when the device is in Standby mode
ISB3
Total Standby Current of Antioch
when the device is in Core Power
Down mode
250g
1. *VDDQ=3.3V nominal (3.0-3.6V)
25ºC
45
2. Outputs and Bidirs High or Floatingf
3. XTALOUT Floating
4. D+ Floating, D- Grounded, UVALID Driven Low
85ºC
290
25ºC
25
85ºC
170
1. Outputs and Bidirs High or Floatingf
2. XTALOUT Floating
3. D+ Floating, D- Grounded, UVALID Driven Low
4. Core Powered Down
µA
µA
a. The interfaces with a voltage range are adjustable with respect to the IO voltage and thus will support multiple IO voltages.
b. The SSVDDQ IO voltage can be dynamically changed (e.g. from high range to low range) as long as the supply voltage undershoot does not surpass the
lower minimum voltage limit. SSVDDQ levels for SD modes: 2.0V-3.6V, MMC modes: 1.7V-3.6V.
c. When U-Port is in a disabled state, UVDDQ can go down to 2.4V, provided UVDDQ is still the highest supply voltage level.
d. Vcc = pertinent VDDQ value.
e. Active Current Conditions: 1) UVDDQ: USB transmitting 50% of the time, receiving 50% of the time; 2) PVDDQ/SNVDDQ/SSVDDQ/GVDDQ: Active Current
Depends on IO Activity, Bus Load and Supply Level; 3) XVDDQ: Assume highest frequency clock (48 MHz) or Crystal (26 MHz).
f. The Outputs/Bidirs that are forced low in standby mode can increase IO supply standby current beyond specified value.
g. ISB1 typical value is not a maximum specification, but a typical value. Isb1 maximum current value specified for 85°C.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
107
Power
Table 8-2. Capacitance
Parameter
CIN
Description
Max.
Input Capacitance, except D+/DInput Capacitance, D+/D-
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCCIO
Output Capacitance
Unit
9
pF
15
pF
10
pF
Figure 8-2. AC Test Loads and Waveforms
8.3
Normal Mode
Normal Mode is the mode in which Antioch is fully functional. This is the mode in which data transfer functions described in
this document are performed.
8.4
Standby Mode
Standby Mode is the mode in which Antioch is in a low-power state. This is the lowest power mode of Antioch while still maintaining external supply levels. This mode is entered through the de-assertion of the WAKEUP input pin or the setting of the
STNDBY bit in the Power Management Control and Status Register. It is exited by asserting the WAKEUP ball if the mode
was entered by de-asserting the WAKEUP ball. Exiting Standby mode can also be accomplished by asserting CE# LOW.
When exiting Standby mode, the 8051 is in reset and it is required to be released from reset by the processor writing to the
Soft Reset Control Register.
In this mode, the following characteristics apply:
■
All configuration register settings and program RAM contents are preserved. However, data in the buffers or other parts of
the data path, if any, is not guaranteed in values. Therefore, external processor should take care that needed data is read
before putting Antioch into this Standby Mode.
■
The program counter is reset on waking up from Standby mode.
■
All outputs are tri-stated (except UVALID), and IO will be placed in input only configuration. Values of IOs in Standby mode
are listed in Table 2-1 through Table 2-6.
■
Core power supply needs to be retained.
■
Hard Reset can be performed by asserting the RESET# input, and Antioch will perform initialization.
■
PLL is disabled.
■
Soft Reset is ignored.
Reset/standby timing parameters are described in Section 3.4.
108
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Power
8.5
Suspend Mode
This mode is entered internally by 8051 (external processor can only initiate entry into this mode through Mailbox commands). This mode is exited by the D+ bus going LOW, GPIO[0] going to a pre-determined state or by asserting CE# LOW.
In the Suspend Mode of Antioch
■
The clocks are shut off. The PLL is disabled.
■
All IOs maintain their previous state.
■
Core power supply needs to be retained.
■
The states of the configuration registers, endpoint buffers and the program RAM are maintained. All transactions need to
be complete before Antioch enters Suspend mode (state of outstanding transactions are not preserved).
■
The firmware resumes its operation from where it was suspended, because the program counter is not reset.
■
Only inputs that are sensed are RESET#, GPIO[0], D+ and CE#. These three are wake-up sources (each can be individually enabled, disabled).
■
Hard Reset can be performed by asserting the RESET# input, and Antioch will perform initialization.
8.6
Core Power Down
The core power supply VDD is powered down in this state. AVDDQ is tied to the same supply as VDD and is hence, also powered down. This mode is entered by powering down VDD and AVDDQ simultaneously, and exited by powering up VDD and
AVDDQ, performing the reset and initialization sequence, following by firmware download. All endpoint buffers, configuration
registers and the program RAM do not maintain state. It is necessary to reload the firmware on exiting from this mode. It is
required that all VDDQ power supplies (except AVDDQ) are on and not powered down in this mode. There is a requirement of
a minimum impedance of 1 k between the VDD pin and ground.
In the WLCSP option, AVDDQ is internally tied to XVDDQ. As a result, the clock input at XTALIN must be brought to a steady
LOW level before entry into Core Power Down mode.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
109
Power
8.7
Working with Power Management Unit (PMU)
Figure 8-3. PMU Related Signals Including UVALID
3.3V
Antioch
recovers
from reset.
VCC_USB
0V
1.8V
tRR
VCC_CORE
0V
RESET#
WAKEUP
RESETOUT
PROCESSOR
WRITE TO
GPIO
Reset and
Initialization
of Antioch
UVALID
Normal Mode of Operation
Entry into
Power Down
mode
10us
D+/D-
Hi-Z
Normal Operation D+/D- Singal Level
Antioch may be used with a Power Management Unit (PMU) that allows switching of the USB interface, or detection of USB
connection/disconnection. The UVALID signal is essentially a GPIO output that can control this USB switch state. Power management in the Antioch device is dependent on several factors. Figure 8-3 depicts the sequence of events in a power-up or
power-down operation.
■
When UVDDQ (USB) is stable at 3.3V, it causes the UVALID signal from Antioch to the external Power Management unit
to de-assert (go LOW).
■
Antioch then follows the initialization procedures described in the section.
■
After initialization is complete and RESETOUT has been asserted to the processor by Antioch, the processor issues a
write to the UVALID field in the PMU Update Register indicating the same.
■
This causes Antioch to assert the UVALID signal (drive HIGH) to the external Power Management unit.
■
Device enters normal operation mode.
■
If VDD (core) supply is powered-down, then the UVALID signal is de-asserted and the device enters power-down mode.
The entire reset and initialization cycle has to be repeated to resume normal operation.
Note that if UVALID needs to be driven HIGH when the Antioch D+/D- interface is enabled, the user needs to ensure that
UVALID is externally set appropriately during Debug/Manufacturing mode (because UVALID will default LOW before register
config via USB).
110
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Power
Table 8-3. PMU Update Register
PMU Update Register
CY_AN_MEM_PMU_UPDATE
x'85
This register is for the processor to communicate to Antioch when it is woken up due to activity sensed by the external Power Management
Unit (PMU). This register will indicate to Antioch the reason for the processor to wake up Antioch from standby.
Field Name
Descriptions
UVALID
This field is directly output to the UVALID pin.
USBUPDATE
This field indicates to Antioch that a USB event was the reason to wake up from standby.
SDIOUPDATE
Bit
This field indicates to Antioch that a SD event was the reason to wake up from standby.
Field
Description
RW
Reset
0
UVALID
UVALID Output State.
0: UVALID Pin = 0
1: UVALID Pin = 1
1
USBUPDATE
USB Event Update
0: USB event not cause of wake up
1: USB event is cause of wakeup
RW
0
2
SDIOUPDATE
SD Event Update
0: SD event not cause of wake up
1: SD event is cause of wakeup
RW
0
15:3
RW
0
Reserved
Table 8-4. Power Management Control and Status Register
Power Management Status Register
CY_AN_MEM_PWR_MAGT_STAT
x'95
This register indicates the power status of the Antioch (e.g. if the Antioch woke up from standby mode) and allows Standby to be initiated by
register write.
Field Name
Descriptions
WAKEUP
This field indicates whether the Antioch has woken up. “Woken up” is defined as PLL getting locked and the Antioch
is ready to function and communicate to all ports. WAKEUP is asserted following de-assertion of RESET# hard
reset or full-chip soft reset.
STNDBY
This field initiates Standby mode in Antioch when written with '1'. After initiating standby, the processor must deassert CE# until the Standby duration has elapsed (because CE# assertion is one condition that will wake up Antioch). This bit is automatically reset to '0' by hardware upon Antioch wake up from Standby mode.
Bit
Field
Description
RW
Reset
0
WAKEUP
Wake up (from reset or Standby mode)
0: Not wake up from reset or Standby mode
1: Wake up from reset or Standby mode.
1
STNDBY
Standby Control (to initiate Standby mode)
0: Normal operating mode
1: Initiate Standby mode
RW
0
Reserved
R
U/D
15:2
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
R
0
111
Power
112
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
9. Register Summary
Table 9-1. Register Summary
Register Name
Register Description
Type
Address
CY_AN_MEM_CM_WB_CFG_ID
Antioch Configuration Identification (ID) Register
CY_AN_MEM_RST_CTRL_REG
Software Reset Control Register
x'80
x'81
CY_AN_MEM_P0_ENDIAN
Endian Configuration Register
x'82
CY_AN_MEM_P0_VM_SET
P-Port Interface Configuration Register
x'83
CY_AN_MEM_PMU_UPDATE
PMU Update Register
x'85
CY_AN_MEM_P0_INTR_REG
P-Port Interrupt Status Register
x'90
CY_AN_MEM_P0_INT_MASK_REG
P-Port Interrupt Mask Register
x'91
CY_AN_MEM_MCU_MB_STAT
8051 MCU Mailbox Status Register
x'92
CY_AN_MEM_P0_MCU_STAT
8051 MCU Status Register
x'94
CY_AN_MEM_PWR_MAGT_STAT
Power Management Control and Status Register
x'95
CY_AN_MEM_P0_RSE_ALLOCATE
External Bus Allocation Registers
x'98
CY_AN_MEM_P0_RES_MASK
External Bus Allocation Mask Registers
x'9A
CY_AN_MEM_P0_DRQ
DRQ Status Register
x'A0
CY_AN_MEM_P0_DRQ_MASK
DRQ Mask Register
x'A1
CY_AN_MEM_P0_EP2_DMA_REG
Endpoint 2 Buffer DMA Register
x'A2
CY_AN_MEM_P0_EP3_DMA_REG
Endpoint 3 Buffer DMA Register
x'A3
CY_AN_MEM_P0_EP4_DMA_REG
Endpoint 4 Buffer DMA Register
x'A4
CY_AN_MEM_P0_EP5_DMA_REG
Endpoint 5 Buffer DMA Register
x'A5
CY_AN_MEM_P0_EP6_DMA_REG
Endpoint 6 Buffer DMA Register
x'A6
CY_AN_MEM_P0_EP7_DMA_REG
Endpoint 7 Buffer DMA Register
x'A7
CY_AN_MEM_P0_EP8_DMA_REG
Endpoint 8 Buffer DMA Register
x'A8
CY_AN_MEM_P0_EP9_DMA_REG
Endpoint 9 Buffer DMA Register
x'A9
CY_AN_MEM_P0_EP10_DMA_REG
Endpoint 10 Buffer DMA Register
x'AA
CY_AN_MEM_P0_EP11_DMA_REG
Endpoint 11 Buffer DMA Register
x'AB
CY_AN_MEM_P0_EP12_DMA_REG
Endpoint 12 Buffer DMA Register
x'AC
CY_AN_MEM_P0_EP13_DMA_REG
Endpoint 13 Buffer DMA Register
x'AD
CY_AN_MEM_P0_EP14_DMA_REG
Endpoint 14 Buffer DMA Register
x'AE
CY_AN_MEM_P0_EP15_DMA_REG
Endpoint 15 Buffer DMA Register
x'AF
CY_AN_MEM_IROS_IO_CFG
Drive Strength and Slew Rate Control Register
x'C1
CY_AN_MEM_PLL_LOCK_LOSS_STAT
PLL Lock Loss Status Register
x'C4
CY_AN_MEM_P0_MAILBOX0
P-Port Mailbox Register0
x'F0
CY_AN_MEM_P0_MAILBOX1
P-Port Mailbox Register1
x'F1
CY_AN_MEM_P0_MAILBOX2
P-Port Mailbox Register2
x'F2
CY_AN_MEM_P0_MAILBOX3
P-Port Mailbox Register3
x'F3
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
113
Register Summary
Table 9-1. Register Summary (continued)
Register Name
Register Description
Type
Address
CY_AN_MEM_MCU_MAILBOX0
8051 MCU Mailbox Register0
CY_AN_MEM_MCU_MAILBOX1
8051 MCU Mailbox Register1
x'F9
CY_AN_MEM_MCU_MAILBOX2
8051 MCU Mailbox Register2
x'FA
CY_AN_MEM_MCU_MAILBOX3
8051 MCU Mailbox Register3
x'FB
114
x'F8
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Glossary
accumulator
In a CPU, a register in which intermediate results are stored. Without an accumulator, it would be
necessary to write the result of each calculation (addition, subtraction, shift, and so on.) to main
memory and read them back. Access to main memory is slower than access to the accumulator,
which usually has direct paths to and from the arithmetic and logic unit (ALU).
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
active low
1. A logic signal having its asserted state as the logic 0 state.
2. A logic signal having its logic 1 state as the lower voltage of the two states: inverted logic.
address
The label or number identifying the memory location (RAM, ROM, or register) where a unit of
information is stored.
algorithm
A procedure for solving a mathematical problem in a finite number of steps that frequently
involve repetition of an operation.
ambient temperature
The temperature of the air in a designated area, particularly the area surrounding the device.
analog
See analog signals.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog output
An output that is capable of driving any voltage between the supply rails, instead of just a logic 1
or logic 0.
analog signals
A signal represented in a continuous form with respect to continuous times, as contrasted with a
digital signal represented in a discrete (discontinuous) form in a sequence of time.
analog-to-digital (ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The <PageNumber>digital-to-analog (DAC) converter performs the reverse operation.
AND
See <PageNumber>Boolean Algebra.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
115
Glossary
API (Application Programming Interface)
A series of software routines that comprise an interface between a computer application and
lower-level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
array
An array, also known as a vector or list, is one of the simplest data structures in computer programming. Arrays hold a fixed number of equally-sized data elements, generally of the same
data type. Individual elements are accessed by index using a consecutive range of integers,
instead of to an associative array. Most high level programming languages have arrays as a
built-in data type. Some arrays are multi-dimensional, meaning they are indexed by a fixed number of integers; for example, by a group of two integers. One- and two-dimensional arrays are
the most common. Also, an array can be a group of capacitors or resistors connected in some
common form.
assembly
A symbolic representation of the machine language of a specific processor. Assembly language
is converted to machine code by an assembler. Usually, each line of assembly code produces
one machine instruction, though the use of macros is common. Assembly languages are considered low level languages; where as C is considered a high level language.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
attenuation
The decrease in intensity of a signal as a result of absorption of energy and of scattering out of
the path to the detector, but not including the reduction due to geometric spreading. Attenuation
is usually expressed in dB.
B
bandgap reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
bias current
The constant low level DC current that is used to produce a stable operation in amplifiers. This
current can sometimes be changed to alter the bandwidth of an amplifier.
binary
The name for the base 2 numbering system. The most common numbering system is the base
10 numbering system. The base of a numbering system indicates the number of values that may
exist for a particular positioning within a number for that system. For example, in base 2, binary,
each position may have one of two values (0 or 1). In the base 10, decimal, numbering system,
each position may have one of ten values (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9).
116
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Glossary
bit
A single digit of a binary number. Therefore, a bit may only have a value of ‘0’ or ‘1’. A group of 8
bits is called a byte. Because the PSoC's M8C is an 8-bit microcontroller, the PSoC's native data
chunk size is a byte.
bit rate (BR)
The number of bits occurring per unit of time in a bit stream, usually expressed in bits per second
(bps).
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
Boolean Algebra
In mathematics and computer science, Boolean algebras or Boolean lattices, are algebraic
structures which “capture the essence” of the logical operations AND, OR, and NOT and the set
theoretic operations union, intersection, and complement. Boolean algebra also defines a set of
theorems that describe how Boolean equations can be manipulated. For example, these theorems are used to simplify Boolean equations, which will reduce the number of logic elements
needed to implement the equation.
The operators of Boolean algebra may be represented in various ways. Often they are simply
written as AND, OR, and NOT. In describing circuits, NAND (NOT AND), NOR (NOT OR), XNOR
(exclusive NOT OR), and XOR (exclusive OR) may also be used. Mathematicians often use +
(for example, A+B) for OR and for AND (for example, A*B) (because in some ways those operations are analogous to addition and multiplication in other algebraic structures) and represent
NOT by a line drawn above the expression being negated (for example, ~A, A_, !A).
break-before-make
The elements involved go through a disconnected state entering (‘break”) before the new connected state (“make”).
broadcast net
A signal that is routed throughout the microcontroller and is accessible by many blocks or systems.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
byte
A digital storage unit consisting of 8 bits.
C
C
A high level programming language.
capacitance
A measure of the ability of two adjacent conductors, separated by an insulator, to hold a charge
when a voltage differential is applied between them. Capacitance is measured in units of Farads.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
117
Glossary
capture
To extract information automatically through the use of software or hardware, instead of to handentering of data into a computer file.
chaining
Connecting two or more 8-bit digital blocks to generate16-, 24-, and even 32-bit functions.
Chaining allows certain signals such as Compare, Carry, Enable, Capture, and Gate to be produced from one block to another.
checksum
The checksum of a set of data is generated by adding the value of each data word to a sum. The
actual checksum can simply be the result sum or a value that must be added to the sum to generate a pre-determined value.
clear
To force a bit/register to a value of logic ‘0’.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
clock generator
A circuit that is used to generate a clock signal.
CMOS
The logic gates constructed using <PageNumber>MOS transistors connected in a complementary manner. CMOS is an acronym for complementary metal-oxide semiconductor.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
In a computer system, an arrangement of functional units according to their nature, number, and
chief characteristics. Configuration pertains to hardware, software, firmware, and documentation. The configuration will affect system performance.
configuration space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crowbar
A type of over-voltage protection that rapidly places a low resistance shunt (typically an SCR)
from the signal to one of the power supply rails, when the output voltage exceeds a predetermined value.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy
check (CRC)
A calculation used to detect errors in data communications, typically performed using a linear
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
D
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
data stream
A sequence of digitally encoded signals used to represent information in transmission.
118
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Glossary
data transmission
The sending of data from one place to another by means of signals over a channel.
debugger
A hardware and software system that allows the user to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
decimal
A base-10 numbering system, which uses the symbols 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 (called digits)
together with the decimal point and the sign symbols + (plus) and - (minus) to represent numbers.
default value
Pertaining to the pre-defined initial, original, or specific setting, condition, value, or action a system will assume, use, or take in the absence of instructions from the user.
device
The device referred to in this manual is the PSoC chip, unless otherwise specified.
die
An unpackaged integrated circuit (IC), normally cut from a wafer.
digital
A signal or function, the amplitude of which is characterized by one of two discrete values: ‘0’ or
‘1’.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
digital logic
A methodology for dealing with expressions containing two-state variables that describe the
behavior of a circuit or system.
digital-to-analog (DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation.
direct access
The capability to obtain data from a storage device, or to enter data into a storage device, in a
sequence independent of their relative positions by means of addresses that indicate the physical location of the data.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
E
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave similar to the first system.
External Reset (XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
F
falling edge
A transition from a logic 1 to a logic 0. Also known as a negative edge.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
119
Glossary
feedback
The return of a portion of the output, or processed portion of the output, of a (usually active)
device to the input.
filter
A device or process by which certain frequency components of a signal are attenuated.
firmware
The software that is embedded in a hardware device and executed by the CPU. The software
may be executed by the user, but it may not be modified.
flag
Any of various types of indicators used for identification of a condition or event (for example, a
character that signals the termination of a transmission).
Flash
An electrically programmable and erasable, volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that
the data is retained when power is off.
Flash bank
A group of Flash ROM blocks where Flash block numbers always begin with ‘0’ in an individual
Flash bank. A Flash bank also has its own block level protection information.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes.
flip-flop
A device having two stable states and two input terminals (or types of input signals) each of
which corresponds with one of the two states. The circuit remains in either state until it is made
to change to the other state by application of the corresponding signal.
frequency
The number of cycles or events per unit of time, for a periodic function.
G
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
gate
1. A device having one output channel and one or more input channels, such that the output
channel state is completely determined by the input channel states, except during switching
transients.
2. One of many types of combinational logic elements having at least two inputs (for example,
AND, OR, NAND, and NOR (also see <PageNumber>Boolean Algebra)).
ground
1. The electrical neutral line having the same potential as the surrounding earth.
2. The negative side of DC power supply.
3. The reference point for an electrical system.
4. The conducting paths between an electric circuit or equipment and the earth, or some conducting body serving in place of the earth.
H
hardware
120
A comprehensive term for all of the physical parts of a computer or embedded system, as distinguished from the data it contains or operates on, and the software that provides instructions for
the hardware to accomplish tasks.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Glossary
hardware reset
A reset that is caused by a circuit, such as a POR, watchdog reset, or external reset. A hardware
reset restores the state of the device as it was when it was first powered up. Therefore, all registers are set to the POR value as indicated in register tables throughout this document.
hexidecimal
A base 16 numeral system (often abbreviated and called hex), usually written using the symbols
0-9 and A-F. It is a useful system in computers because there is an easy mapping from four bits
to a single hex digit. Thus, one can represent every byte as two consecutive hexadecimal digits.
Compare the binary, hex, and decimal representations:
bin = hex = dec
0000b = 0x0 = 0
0001b = 0x1 = 1
0010b = 0x2 = 2
...
1001b = 0x9 = 9
1010b = 0xA = 10
1011b = 0xB = 11
...
1111b = 0xF = 15
So the decimal numeral 79 whose binary representation is 0100 1111b can be written as 4Fh in
hexadecimal (0x4F).
high time
The amount of time the signal has a value of ‘1’ in one period, for a periodic digital signal.
I
I2C
A two-wire serial computer bus by Phillips Semiconductors. I2C is an Inter-Integrated Circuit. It is
used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal
bus system for building control electronics. I2C uses only two bi-directional pins, clock and data,
both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. I2C™ is a trademark of the Philips Semiconductors.
ICE
The in-circuit emulator that allows users to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
idle state
A condition that exists whenever user messages are not being transmitted, but the service is
immediately available for use.
impedance
1. The resistance to the flow of current caused by resistive, capacitive, or inductive devices in a
circuit.
2. The total passive opposition offered to the flow of electric current. Note the impedance is
determined by the particular combination of resistance, inductive reactance, and capacitive
reactance in a given circuit.
input
A point that accepts data, in a device, process, or channel.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
121
Glossary
input/output (IO)
A device that introduces data into or extracts data from a system.
instruction
An expression that specifies one operation and identifies its operands, if any, in a programming
language such as C or assembly.
integrated circuit (IC)
A device in which components such as resistors, capacitors, diodes, and transistors are formed
on the surface of a single piece of semiconductor.
interface
The means by which two systems or devices are connected and interact with each other.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
J
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption
that occurs on serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or
phase of successive cycles.
K
keeper
A circuit that holds a signal to the last driven value, even when the signal becomes un-driven.
L
latency
The time or delay that it takes for a signal to pass through a given circuit or network.
least significant bit
(LSb)
The binary digit, or bit, in a binary number that represents the least significant value (typically the
right-hand bit). The bit versus byte distinction is made by using a lower case “b” for bit in LSb.
least significant byte
(LSB)
The byte in a multi-byte word that represents the least significant values (typically the right-hand
byte). The byte versus bit distinction is made by using an upper case “B” for byte in LSB.
Linear Feedback Shift
Register (LFSR)
A shift register whose data input is generated as an XOR of two or more elements in the register
chain.
load
The electrical demand of a process expressed as power (watts), current (amps), or resistance
(ohms).
logic function
A mathematical function that performs a digital operation on digital data and returns a digital
value.
122
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Glossary
look-up table (LUT)
A logic block that implements several logic functions. The logic function is selected by means of
select lines and is applied to the inputs of the block. For example: A 2 input LUT with 4 select
lines can be used to perform any one of 16 logic functions on the two inputs resulting in a single
logic output. The LUT is a combinational device; therefore, the input/output relationship is continuous, that is, not sampled.
low time
The amount of time the signal has a value of ‘0’ in one period, for a periodic digital signal.
low voltage detect
(LVD)
A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a
selected threshold.
M
M8C
An 8-bit Harvard Architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the Flash, SRAM, and register space.
macro
A programming language macro is an abstraction, whereby a certain textual pattern is replaced
according to a defined set of rules. The interpreter or compiler automatically replaces the macro
instance with the macro contents when an instance of the macro is encountered. Therefore, if a
macro is used 5 times and the macro definition required 10 bytes of code space, 50 bytes of
code space will be needed in total.
mask
1. To obscure, hide, or otherwise prevent information from being derived from a signal. It is usually the result of interaction with another signal, such as noise, static, jamming, or other forms
of interference.
2. A pattern of bits that can be used to retain or suppress segments of another pattern of bits, in
computing and data processing systems.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the
slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, will reduce the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed signal
The reference to a circuit containing both analog and digital techniques and components.
mnemonic
A tool intended to assist the memory. Mnemonics rely on not only repetition to remember facts,
but also on creating associations between easy-to-remember constructs and lists of data. A two
to four character string representing a microprocessor instruction.
mode
A distinct method of operation for software or hardware. For example, the Digital PSoC block
may be in either counter mode or timer mode.
modulation
A range of techniques for encoding information about a carrier signal, typically a sine-wave signal. A device that performs modulation is known as a modulator.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
123
Glossary
Modulator
A device that imposes a signal on a carrier.
MOS
An acronym for metal-oxide semiconductor.
most significant bit
(MSb)
The binary digit, or bit, in a binary number that represents the most significant value (typically the
left-hand bit). The bit versus byte distinction is made by using a lower case “b” for bit in MSb.
most significant byte
(MSB)
The byte in a multi-byte word that represents the most significant values (typically the left-hand
byte). The byte versus bit distinction is made by using an upper case “B” for byte in MSB.
multiplexer (mux)
1. A logic function that uses a binary value, or address, to select between a number of inputs
and conveys the data from the selected input to the output.
2. A technique which allows different input (or output) signals to use the same lines at different
times, controlled by an external signal. Multiplexing is used to save on wiring and IO ports.
N
NAND
See <PageNumber>Boolean Algebra.
negative edge
A transition from a logic 1 to a logic 0. Also known as a falling edge.
net
The routing between devices.
nibble
A group of four bits, which is one-half of a byte.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current,
or data.
NOR
See <PageNumber>Boolean Algebra.
NOT
See <PageNumber>Boolean Algebra.
O
OR
See <PageNumber>Boolean Algebra.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
output
The electrical signal or signals which are produced by an analog or digital block.
P
parallel
124
The means of communication in which digital data is sent multiple bits at a time, with each simultaneous bit being sent over a separate line.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Glossary
parameter
Characteristics for a given block that have either been characterized or may be defined by the
designer.
parameter block
A location in memory where parameters for the SSC instruction are placed before execution.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
path
1. The logical sequence of instructions executed by a computer.
2. The flow of an electrical signal through a circuit.
pending interrupts
An interrupt that has been triggered but has not been serviced, either because the processor is
busy servicing another interrupt or global interrupts are disabled.
phase
The relationship between two signals, usually the same frequency, that determines the delay
between them. This delay between signals is either measured by time or angle (degrees).
Phase-Locked Loop
(PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pin
A terminal on a hardware component. Also called lead.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts will
involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
positive edge
A transition from a logic 0 to a logic 1. Also known as a rising edge.
posted interrupts
An interrupt that has been detected by the hardware but may or may not be enabled by its mask
bit. Posted interrupts that are not masked become pending interrupts.
Power On Reset (POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is
one type of hardware reset.
program counter
The instruction pointer (also called the program counter) is a register in a computer processor
that indicates where in memory the CPU is executing instructions. Depending on the details of
the particular machine, it holds either the address of the instruction being executed, or the
address of the next instruction to be executed.
protocol
A set of rules. Particularly the rules that govern networked communications.
PSoC
Cypress MicroSystems’ Programmable System-on-Chip (PSoC) mixed signal array. PSoC™
and Programmable System-on-Chip™ are trademarks of Cypress MicroSystems, Inc.
PSoC blocks
See analog blocks and digital blocks.
PSoC Designer
The software for Cypress MicroSystems’ Programmable System-on-Chip technology.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
125
Glossary
pulse
A rapid change in some characteristic of a signal (for example, phase or frequency), from a
baseline value to a higher or lower value, followed by a rapid return to the baseline value.
pulse width modulator
(PWM)
An output in the form of duty cycle which varies as a function of the applied measurand.
R
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
resistance
The resistance to the flow of electric current measured in ohms for a conductor.
revision ID
A unique identifier of the PSoC device.
ripple divider
An asynchronous ripple counter constructed of flip-flops. The clock is fed to the first stage of the
counter. An n-bit binary counter consisting of n flip-flops that can count in binary from 0 to 2n - 1.
rising edge
See positive edge.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
routine
A block of code, called by another block of code, that may have some general or frequent use.
routing
Physically connecting objects in a design according to design rules set in the reference library.
runt pulses
In digital circuits, narrow pulses that, due to non-zero rise and fall times of the signal, do not
reach a valid high or low level. For example, a runt pulse may occur when switching between
asynchronous clocks or as the result of a race condition in which a signal takes two separate
paths through a circuit. These race conditions may have different delays and are then recombined to generate a glitch or when the output of a flip-flop becomes metastable.
S
sampling
The process of converting an analog signal into a series of digital values or reversed.
schematic
A diagram, drawing, or sketch that details the elements of a system, such as the elements of an
electrical circuit or the elements of a logic diagram for a computer.
seed value
An initial value loaded into a linear feedback shift register or random number generator.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a
single device or channel.
126
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Glossary
set
To force a bit/register to a value of logic 1.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift
The movement of each bit in a word one position to either the left or right. For example, if the hex
value 0x24 is shifted one place to the left, it becomes 0x48. If the hex value 0x24 is shifted one
place to the right, it becomes 0x12.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
sign bit
The most significant binary digit, or bit, of a signed binary number. If set to a logic 1, this bit represents a negative quantity.
signal
A detectable transmitted energy that can be used to carry information. As applied to electronics,
any transmitted electrical impulse.
silicon ID
A unique identifier of the PSoC silicon.
skew
The difference in arrival time of bits transmitted at the same time, in parallel transmission.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
software
A set of computer programs, procedures, and associated documentation concerned with the
operation of a data processing system (for example, compilers, library routines, manuals, and
circuit diagrams). Software is often written first as source code, and then converted to a binary
format that is specific to the device on which the code will be executed.
software reset
A partial reset executed by software to bring part of the system back to a known state. A software reset will restore the M8C to a know state but not PSoC blocks, systems, peripherals, or
registers. For a software reset, the CPU registers (CPU_A, CPU_F, CPU_PC, CPU_SP, and
CPU_X) are set to 0x00. Therefore, code execution will begin at Flash address 0x0000.
SRAM
An acronym for static random access memory. A memory device allowing users to store and
retrieve data at a high rate of speed. The term static is used because, after a value has been
loaded into an SRAM cell, it will remain unchanged until it is explicitly altered or until power is
removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
stack
A stack is a data structure that works on the principle of Last In First Out (LIFO). This means that
the last item put on the stack is the first item that can be taken off.
stack pointer
A stack may be represented in a computer’s inside blocks of memory cells, with the bottom at a
fixed location and a variable stack pointer to the current top cell.
state machine
The actual implementation (in hardware or software) of a function that can be considered to consist of a set of states through which it sequences.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
127
Glossary
sticky
A bit in a register that maintains its value past the time of the event that caused its transition, has
passed.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
switching
The controlling or routing of signals in circuits to execute logical or arithmetic operations, or to
transmit data between specific points in a network.
Switch phasing
The clock that controls a given switch, PHI1 or PHI2, in respect to the switch capacitor (SC)
blocks. The PSoC SC blocks have two groups of switches. One group of these switches is normally closed during PHI1 and open during PHI2. The other group is open during PHI1 and
closed during PHI2. These switches can be controlled in the normal operation, or in reverse
mode if the PHI1 and PHI2 clocks are reversed.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock
signal.
2. A system whose operation is synchronized by a clock signal.
T
tap
The connection between two blocks of a device created by connecting several blocks/components in a series, such as a shift register or resistive voltage divider.
terminal count
The state at which a counter is counted down to zero.
threshold
The minimum value of a signal that can be detected by the system or sensor under consideration.
transistors
The transistor is a solid-state semiconductor device used for amplification and switching, and
has three terminals: a small current or voltage applied to one terminal controls the current
through the other two. It is the key component in all modern electronics. In digital circuits, transistors are used as very fast electrical switches, and arrangements of transistors can function as
logic gates, RAM-type memory, and other devices. In analog circuits, transistors are essentially
used as amplifiers.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
U
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user
The person using the PSoC device and reading this manual.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
128
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
Glossary
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
V
Vdd
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 or 3.3 volts.
volatile
Not guaranteed to stay the same value or level when not in scope.
Vss
A name for a power net meaning "voltage source." The most negative power supply signal.
W
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU will reset after a specified
period of time.
waveform
The representation of a signal as a plot of amplitude versus time.
X
XOR
See <PageNumber>Boolean Algebra.
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B
129
Glossary
130
West Bridge Antioch Product Description Guide, Doc. # 001-42576 Rev. *B