1 2 3 4 History 80MHz, length-matched, 50Ohm TL TRACE[0..15] TRACECLK TRACECTL TRACE[0..15] TRACECLK TRACECTL M_JTAG_TDO M_JTAG_TDI M_JTAG_TMS M_JTAG_TCK M_JTAG_NTRST M_RST_X M_JTAG_RTCK M_JTAG_TDO M_JTAG_TDI M_JTAG_TMS M_JTAG_TCK M_JTAG_NTRST M_RST_X M_JTAG_RTCK P0_[0..63] P1_[0..63] P2_[0..63] P3_[0..63] P0_[0..63] P1_[0..63] P2_[0..63] P3_[0..63] Doc Rev.: 0.5: Changes: - initial version derived from EMA-MB9EF120-020 (calypso-atlas EMA) A - first full version for review - included changes/corrections after first revision. !Trace-Connector pinning changed!: swapped TRACECTL and TRACECLK, then with TRACE[31..16] - updated according to latest changes in calypso-atlas-EMA and atlas-SK 0.6: 0.7: 0.8: 0.9: 0.10: 0.11: 40MHz, TMS, TDI, TCK length-matched, all as short as possible.All apart from other Signals. MODE B U_03_header 03_header.SchDoc MODE A U_02_atlas-trace 02_atlas-trace.SchDoc APX_SDINP APX_SDINM APX_SDOUTP APX_SDOUTM U_04_debug_apix 04_debug_apix.SchDoc - minor changes after review. - APIX data-signals routed to bottom-header using 100nF-series Cs as jumpers (see layout-hints!) - APIX-Connector changed to Firewire 4-pin. B - APIX power-supply revisited according to new information. - APIX connector: EMC revisited. - jumper for APIX power supply from target - minor updates to APIX connections; TVS changed. - CM-Chokes at APIX: new lib-device replaces former version. Identical type, but correc pin-layout (was wrong in original device). - Updated XTals to uniform values, corrected their load-capacitors. - Sheet 2, R4/R5 swapped values (both form a 3-pa was conflicting with description. - Sheet 3: APIX-Cs were made NP by default. C - Sheet 4: APIX L4 vertically (x(!)-axis) mirrore - Sheet 4: APIX TSV1 updated from lib which now i the two NC-pads belonging to pads 1 resp. avoid DRC-warnings and allow differential - Sheet 4: APIX TVS1 pin-pairs swapped according (email Huber as of 2011-07-13,02h46) - Sheet 2: R6 made NP by default (RTCK-feedback) MODE T_JTAG_TDO T_JTAG_TDI T_JTAG_TCK T_JTAG_TMS T_JTAG_NTRST T_JTAG_TDO T_JTAG_TDI T_JTAG_TCK T_JTAG_TMS T_JTAG_NTRST T_RST_X T_RST_X 0.12: 0.13: 0.14: APX_SDINP APX_SDINM APX_SDOUTP APX_SDOUTM 0.15: 40MHz, TMS, TDI, TCK mostly length-matched, all as short as possible.All apart from other signals, if possible. APX_SDINP APX_SDINM APX_SDOUTP APX_SDOUTM 0.16: C D /************************************************************************/ /* (C) Fujitsu Semiconductor Europe GmbH */ /* The schematic is provided without charge for demonstration purposes */ /* only, subject to alterations. */ /* FSEU does not warrant that the deliverables do not infringe any */ /* third party intellectual property right (IPR). In the event that */ /* the deliverables infringe a third party IPR it is the sole */ /* responsibility of the customer to obtain necessary licenses to */ /* continue the usage of the deliverable. */ /* FSEU disclaims any warranty and liability. */ /* (V1.3) */ /************************************************************************/ 0.17: 0.18: D Product: EMA-MB9DF120-001 Sheet: 1 Drawn by: File: 1 2 3 of 4 Olaf Behrendt 01_overview.SchDoc Fujitsu Semiconductor Europe GmbH Doc Revision: V0.18 HW Revision: Rev1.0 Date: 2011-07-18 http://mcu.emea.fujitsu.com [email protected] 4 2 3 *1: Soldering-Jumpers R4: 20MHz Osc enabled (default) R5: 4MHz Osc enabled open: illegal! PCB-hint: share common pad to avoid placing both at the same time (short!). Keep away from noisy signals! 4 PIC901 COC9 C9 1n PIR1302 PIC601COC6 PIC701 C6 PIC801 C8 COC8 PIC100n 602 PIC10µ 702 PIC802 10µ COR14 R14 PIR1402 *11 0R0 6 7 8 MCU_VDD PIR1301 NP [0R0] Pairs: 7/8, 25/26, 40/41, 53/54 PIR1401 MCU_DVCC PIC201 VDDA PIC202 PIC1COC13 302 PIC1402COC14 PIC1502COC15 PIC10 1COC10 PIC1COC11 01 PIC11n 301 PIC1401 1n PIC1501 1n PIC100n 10 2 PIC10µ 1 02 WE.742792656 PIC1202 10µ C13 all XOsc: Load-cap calculation based on 8pF stray-capacitance (estimated) crit (noise) crit (noise) crit (noise) APX_VCC3 (incl. wires) (incl. wires) (incl. wires) GND 5 COR13 R13 PIL101 PIC902 crit (noise) (incl. wires) APIX-Phy requires 20MHz Osc! GND WE.742792656 PIL102 COL1 L1 COC7 C7 APX_VCC12 C14 C15 C10 C11 PIL301 COL3 L3 GND COC2 C2 100n PIC301 PIC302 C12 COR15 R15 PIR1502 COR16 R16 PIL302 PIR1602 *11 One 1nF close to each pad MCU_VDP3 0R0 Pad PIC3901 18pF COQ1 Q1 COTP1 TP1 PIQ102 PITP101 COC52 C52 18pFPIC5201 COC17 PIC1702 C16 PIC1601 C17 8pF COQ2 Q2 PIQ101 PIQ202 8pFPIC1701 COC38 PIC3802 C36 PIC3601 COTP2 TP2 PIQ201 C38 8pF COQ3 Q3 PIQ302 PITP201 4MHz 32768Hz PIC3602 COC36 Side PIR1601 To Connector (sheet 04) 8pFPIC3801 PIC20 1 To Receptacle (sheet 03) 100nF PIC20 2 Top To Connector (sheet 04) PITP301 COC4 C4 100n PIC501 PIC502 COC5 C5 100n Bot To Receptacle (sheet 03) PIC2101 COC20 C20 100n PIC2102 PIC2 01 COC21 C21 100n PIC2 02 COC22 C22 100n A GND Route on top through 100nF Cs (sheet 04) to connector, route on bottom through 100nF (sheet 03) to 176-pin receptacle. Only one set of Cs may be populated. Keep traces from CPU-Pads to Cs as short as possible. Keep Y-stubs to Cs as short as possible. See Drawing for concept. *10 COTP3 TP3 PIQ301 20MHz PIC402 Pairs: 215/216, 259/260, 285/286 MCU_VDP5 PCB VDEA *10: short traces, SDIN/OUT are matched&balanced diff. pairs. PCB-hints: 2 100R diff/50R com transmission-lines (Microstrip). perfectly length-matched, fully mitered. Keep away from other signals! APIXClock COC39 C39 PIC1602 COC16 MainClock SubClock PIC5202 PIC401 GND 100nF PIR1501 NP [0R0] A PIC3902 COC3 C3 100n PIC1201 COC12GND Via 1 *11: Soldering-jumpers for APIX-power: upper: from MCU (this board). lower: from target-board. open: illegal! PCB-hint: share common pad to avoid placing both at the same time (short!). Keep away from noisy signals! Pairs: 62/63, 82/83, 95, 105/106, 115, 126/127, 142, 161/162, 179/180 MCU_VDP3 PIC2301 PIC2302 PIC2401 COC23 C23 100n PIC2402 PIC2501 COC24 C24 100n PIC2502 COC25 C25 100n PIC2601 PIC2602 COC26 C26 100n PIC2701 PIC2702 COC27 C27 100n PIC2801 PIC2802 COC28 C28 100n PIC2901 PIC2902 PIC30 1 COC29 C29 100n PIC30 2 PIC3101 COC30 C30 100n PIC3102 COC31 C31 100n GND NLP300000630 P3_[0..63] PIC6COC69 901 C69 PICCOC55 5C55 01 PIC5C56 601 PIC5COC54 401 COC56 C54 223 PIU30223 224 PIU30224 225 PIU30225 226 PIU30226 227 PIU30227 228 PIU30228 229 PIU30229 230 PIU30230 231 PIU30231 232 PIU30232 233 PIU30233 234 PIU30234 235 PIU30235 236 PIU30236 237 PIU30237 238 PIU30238 239 PIU30239 240 PIU30240 241 PIU30241 242 PIU30242 243 PIU30243 244 PIU30244 245 PIU30245 246 PIU30246 247 PIU30247 248 PIU30248 249 PIU30249 250 PIU30250 251 PIU30251 252 PIU30252 253 PIU30253 254 PIU30254 255 PIU30255 256 PIU30256 257 PIU30257 258 PIU30258 259 PIU30259 260 PIU30260 261 PIU30261 262 PIU30262 263 PIU30263 264 PIU30264 265 PIU30265 266 PIU30266 267 PIU30267 268 PIU30268 269 PIU30269 270 PIU30270 271 PIU30271 272 PIU30272 273 PIU30273 274 PIU30274 275 PIU30275 276 PIU30276 277 PIU30277 278 PIU30278 279 PIU30279 280 PIU30280 281 PIU30281 282 PIU30282 283 PIU30283 284 PIU30284 285 PIU30285 286 PIU30286 287 PIU30287 288 PIU30288 289 PIU30289 290 PIU30290 291 PIU30291 292 PIU30292 293 PIU30293 294 PIU30294 295 PIU30295 296 P0_40 P0_41 P0_42 P0_43 NLP0044 P0_44 *9 NLP0040 P0_40 PITP601 NLP0042 COTP7 TP7 NLP0043 P0_43 WDG_OBSERVE NLP0045 P0_45 PITP701 NLP0046 P0_46 NLP0047 P0_47 NLP0048 P0_48 NLP0049 P0_49 *9: place on top, avoid long stubs P0_50 NLP0050 POP200000630 POP2063 POP2062 POP2061 POP2060 POP2059 POP2058 POP2057 POP2056 POP2055 POP2054 POP2053 POP2052 POP2051 POP2050 POP2049 POP2048 POP2047 POP2046 POP2045 POP2044 POP2043 POP2042 POP2041 POP2040 POP2039 POP2038 POP2037 POP2036 POP2035 POP2034 POP2033 POP2032 POP2031 POP2030 POP2029 POP2028 POP2027 POP2026 POP2025 POP2024 POP2023 POP2022 POP2021 POP2020 POP2019 POP2018 POP2017 POP2016 POP2015 POP2014 POP2013 POP2012 POP2011 POP2010 POP209 POP208 POP207 POP206 POP205 POP204 POP203 POP202 POP201 POP200 P2_[0..63] NLP0051 P0_51 NLP0062 P0_62 NLP0063 P0_63 NLP2032 P2_32 NLP200000630 P2_[0..63] NLP2033 P2_33 NLP2034 P2_34 NLP2035 P2_35 NLP2036 P2_36 NLP2037 P2_37 NLP2038 P2_38 NLP2039 P2_39 C P2_40 NLP2040 P2_41 NLP2041 NLP2042 P2_42 NLP2043 P2_43 NLP2044 P2_44 P2_45 NLP2045 P2_46 NLP2046 NLP2047 P2_47 M_JTAG_TDO POM0JTAG0TDO POM0JTAG0TDI M_JTAG_TDI POM0JTAG0TCK M_JTAG_TCK POM0JTAG0RTCK M_JTAG_RTCK COR6 R6 PIR602 *5 PIR601 NP [0R0] M_JTAG_TMS POM0JTAG0TMS POM0JTAG0NTRST M_JTAG_NTRST PIU30296 *5: R-Jumper closed: connect RTCK to debug-connector open: leave RTCK unused (default) !!CAUTION: must be open with trace-board 1.0 or below!! 2k4/1% P3_24 P3_23 P3_22 P3_32 P3_31 P3_30 P3_29 P3_28 P3_27 P3_26 P3_25 NP [0R0] NC VSS VSS VDD VDD VSS VSS P0_40 P0_41 NC P0_42 P0_43 P0_44 NC NC NC NC NC NC NC NC NC P0_45 P0_46 P0_47 P0_48 P0_49 NC NC P0_50 P0_51 P0_62 P0_63 P2_32 NC P2_33 VDP5 VDP5 VSS VSS P2_34 P2_35 P2_36 P2_37 P2_38 P2_39 NC NC NC NC NC NC P2_40 P2_41 P2_42 P2_43 P2_44 P2_45 P2_46 P2_47 VSS VSS VDP5 VDP5 JTAG_TDO JTAG_TDI JTAG_TCK VSS VSS VDD VDD JTAG_TMS JTAG_NTRST NC GND PIC3402 PIC3501 COC34 C34 100n PIC3502 COC35 C35 100n GND COU3 U3 MB9DF126PFFS PIC40 1 TRACE[15] TRACE[14] P3_21 P3_20 TRACE[13] VSS VDP3 P3_19 TRACE[12] P3_18 P3_17 TRACE[11] TRACE[10] P3_16 P3_15 P3_14 TRACE[9] TRACE[8] P3_13 VSS VSS VDP3 VDP3 P3_42 P3_41 TRACE[7] P3_40 P3_39 TRACE[6] P3_38 TRACE[5] P3_37 VSS VDP3 P3_36 P3_35 P3_34 P3_33 P1_25 P1_24 TRACECTL TRACECLK VDP3 VDP3 VSS VSS P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 VSS VDP3 P3_06 P3_05 P3_04 P3_03 TRACE[4] P3_02 P3_01 TRACE[3] TRACE[2] VSS VSS VDP3 VDP3 P3_00 P1_33 P1_32 TRACE[1] P1_31 P1_30 TRACE[0] PIU3075 NLTRACE15 TRACE15 NLTRACE14 TRACE14 NLP3021 P3_21 NLP3020 P3_20 NLTRACE13 TRACE13 GND B PIC4201 NLP3019 P3_19 NLTRACE12 TRACE12 NLP3018 P3_18 NLP3017 P3_17 PIC4202 NLTRACE11 TRACE11 NLTRACE10 TRACE10 PIC4 01 NLP3013 P3_13 PIC4 02 PIL902 BLM18PG600SN1D PIC5902 COC59 C59 100n PIC5901 NLP108NLP109NLP1010NLP101NLP1012NLP1013NLP1014NLP1015 NLP103NLP104NLP105NLP106NLP107 NLP1016NLP1017NLP1018NLP1019NLP1020 NLP102N1LP102 NLP1023 PIC4801 P3_38 NLP3038 PIC4802 NLTRACE6 TRACE6 PIC4701 COC46 C46 10µ PIC4702 COC47 C47 10µ COC48 C48 10µ PIC4901 PIC4902 PIC50 1 COC49 C49 10µ PIC50 2 PIC5101 COC50 C50 10µ PIC5102 COC51 C51 10µ caps per power domain distibuted evenly over PCB/domain. NLP1025 P1_25 NLP1024 P1_24 TRACECTL POTRACECTL POTRACECLK TRACECLK C NLP3012 P3_12 P3_11 NLP3011 NLP3010 P3_10 NLP309 P3_9 NLP308 P3_8 NLP307 P3_7 NLP306 P3_6 NLP305 P3_5 NLP304 P3_4 P3_3 NLP303 TRACE4 NLTRACE4 NLP302 P3_2 NLP301 P3_1 NLTRACE3 TRACE3 TRACE2 NLTRACE2 NLP300 P3_0 NLP1033 P1_33 NLP1032 P1_32 TRACE1 NLTRACE1 P1_31 NLP1031 NLP1030 P1_30 NLTRACE0 TRACE0 TRACE[0..15] NLTRACE0000150 5 PIC4602 GND NLP3036 P3_36 NLP3035 P3_35 NLP3034 P3_34 NLP3033 P3_33 NLP103N4LP1035NLP1036NLP1037NLP1038 4 PIC4601 COC45 C45 10µ NLP3037 P3_37 Analog reference supply filter 3 PIC4502 NLTRACE5 TRACE5 TRACE[0..15] POTRACE0000150 POTRACE15 POTRACE14 POTRACE13 POTRACE12 POTRACE11 POTRACE10 POTRACE9 POTRACE8 POTRACE7 POTRACE6 POTRACE5 POTRACE4 POTRACE3 POTRACE2 POTRACE1 POTRACE0 /************************************************************************/ /* (C) Fujitsu Semiconductor Europe GmbH */ /* The schematic is provided without charge for demonstration purposes */ /* only, subject to alterations. */ /* FSEU does not warrant that the deliverables do not infringe any */ /* third party intellectual property right (IPR). In the event that D */ /* the deliverables infringe a third party IPR it is the sole */ /* responsibility of the customer to obtain necessary licenses to */ /* continue the usage of the deliverable. */ /* FSEU disclaims any warranty and liability. */ /* (V1.3) */ /************************************************************************/ Product: EMA-MB9DF120-001 Sheet: 2 Drawn by: File: Olaf Behrendt 02_atlas-trace.SchDoc of 4 P1_[0..63] NLP100000630 2 PIC4501 MCU_VDD NLP3040 P3_40 NLP3039 P3_39 GND NLP10 NLP101 NLP102 COC44 C44 10µ GND NLP3042 P3_42 NLP3041 P3_41 NLTRACE7 TRACE7 P1_34 P1_35 P1_36 P1_37 P1_38 1n P1_21 P1_22 P1_23 C61 COC61 P1_16 P1_17 P1_18 P1_19 P1_20 PIC580100n 2 PIC6102 PIC5702 P1_8 P1_9 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 PIC5COC58 80C58 1 PIC6101 10µ P1_3 P1_4 P1_5 P1_6 P1_7 PIL901 MCU_AVSS5 PIC5701 COC57 C57 L9 COL9 P1_2 C60 COC60 100n PIC60 2 PIC4302 MCU_VDP3 NLTRACE9 TRACE9 NLTRACE8 TRACE8 MCU_DVCC MCU_VDD MCU_VDP3 P1_0 P1_1 PIC60 1 COC43 C43 10µ GND NLP3016 P3_16 NLP3015 P3_15 NLP3014 P3_14 PIL802 close to pad COL8 L8 PIC4301 COC42 C42 10µ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 crit (noise) (incl. wires) PIL801 COC41 C41 10µ PIC4102 MCU_VDP5 GND BLM18PG600SN1D MCU_AVRH5 PIC4101 COC40 C40 10µ PIC40 2 148 PIU30148 147 PIU30147 146 PIU30146 145 PIU30145 144 PIU30144 143 PIU30143 142 PIU30142 141 PIU30141 140 PIU30140 139 PIU30139 138 PIU30138 137 PIU30137 136 PIU30136 135 PIU30135 134 PIU30134 133 PIU30133 132 PIU30132 131 PIU30131 130 PIU30130 129 PIU30129 128 PIU30128 127 PIU30127 126 PIU30126 125 PIU30125 124 PIU30124 123 PIU30123 122 PIU30122 121 PIU30121 120 PIU30120 119 PIU30119 118 PIU30118 117 PIU30117 116 PIU30116 115 PIU30115 114 PIU30114 113 PIU30113 112 PIU30112 111 PIU30111 110 PIU30110 109 PIU30109 108 PIU30108 107 PIU30107 106 PIU30106 105 PIU30105 104 PIU30104 103 PIU30103 102 PIU30102 101 PIU30101 100 PIU30100 99 PIU3099 98 PIU3098 97 PIU3097 96 PIU3096 95 PIU3095 94 PIU3094 93 PIU3093 92 PIU3092 91 PIU3091 90 PIU3090 89 PIU3089 88 PIU3088 87 PIU3087 86 PIU3086 85 PIU3085 84 PIU3084 83 PIU3083 82 PIU3082 81 PIU3081 80 PIU3080 79 PIU3079 78 PIU3078 77 PIU3077 76 PIU3076 75 MCU_AVDD5 1 PIC3401 COC33 C33 100n MCU_VDP3 PIU301 PIU302 PIU30 PIU304 PIU305 PIU306 PIU307 PIU308 PIU309 PIU301 PIU301 PIU3012 PIU301 PIU3014 PIU3015 PIU3016 PIU3017 PIU3018 PIU3019 PIU302 PIU3021 PIU302 PIU302 PIU3024 PIU3025 PIU3026 PIU3027 PIU3028 PIU3029 PIU30 PIU301 PIU302 PIU30 PIU304 PIU305 PIU306 PIU307 PIU308 PIU309 PIU304 PIU3041 PIU3042 PIU304 PIU304 PIU3045 PIU3046 PIU3047 PIU3048 PIU3049 PIU305 PIU3051 PIU3052 PIU3053 PIU3054 PIU305 PIU3056 PIU3057 PIU3058 PIU3059 PIU306 PIU3061 PIU3062 PIU306 PIU3064 PIU3065 PIU306 PIU3067 PIU3068 PIU3069 PIU307 PIU3071 PIU3072 PIU307 PIU3074 D P1_[0..63] POP100 POP100000630 POP1063 POP1062 POP1061 POP1060 POP1059 POP1058 POP1057 POP1056 POP1055 POP1054 POP1053 POP1052 POP1051 POP1050 POP1049 POP1048 POP1047 POP1046 POP1045 POP1044 POP1043 POP1042 POP1041 POP1040 POP1039 POP1038 POP1037 POP1036 POP1035 POP1034 POP1033 POP1032 POP1031 POP1030 POP1029 POP1028 POP1027 POP1026 POP1025 POP1024 POP1023 POP1022 POP1021 POP1020 POP1019 POP1018 POP1017 POP1016 POP1015 POP1014 POP1013 POP1012 POP1011 POP1010 POP109 POP108 POP107 POP106 POP105 POP104 POP103 POP102 POP101 PIC3 02 GND NC NC AVSS5 AVRH5 AVDD5 NC DVCC DVCC DVSS DVSS P1_00 P1_01 NC P1_02 NC NC NC P1_03 P1_04 P1_05 P1_06 P1_07 DVSS DVSS DVCC DVCC P1_08 P1_09 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 NC NC DVSS DVSS DVCC DVCC P1_16 P1_17 P1_18 P1_19 P1_20 NC NC P1_21 P1_22 P1_23 DVSS DVSS DVCC DVCC NC NC NC NC NC NC NC VDP3 VDP3 VSS VSS P1_34 P1_35 P1_36 P1_37 P1_38 VDD VDD VSS VSS NLP000000630 P0_[0..63] POP000 POP000000630 POP0063 POP0062 POP0061 POP0060 POP0059 POP0058 POP0057 POP0056 POP0055 POP0054 POP0053 POP0052 POP0051 POP0050 POP0049 POP0048 POP0047 POP0046 POP0045 POP0044 POP0043 POP0042 POP0041 POP0040 POP0039 POP0038 POP0037 POP0036 POP0035 POP0034 POP0033 POP0032 POP0031 POP0030 POP0029 POP0028 POP0027 POP0026 POP0025 POP0024 POP0023 POP0022 POP0021 POP0020 POP0019 POP0018 POP0017 POP0016 POP0015 POP0014 POP0013 POP0012 POP0011 POP0010 POP009 POP008 POP007 POP006 POP005 POP004 POP003 POP002 POP001 P0_[0..63] PITP501P0_42 PIC3 01 MCU_DVCC B COTP6 TP6 RTC_WOT COC32 C32 100n PIU302 PIU3021 PIU302 PIU30219 PIU30218 PIU30217 PIU30216 PIU30215 PIU30214 PIU3021 PIU3021 PIU3021 PIU3021 PIU3029 PIU3028 PIU3027 PIU3026 PIU3025 PIU3024 PIU302 PIU302 PIU3021 PIU302 PIU3019 PIU30198 PIU30197 PIU30196 PIU30195 PIU30194 PIU30193 PIU30192 PIU3019 PIU3019 PIU30189 PIU3018 PIU30187 PIU30186 PIU30185 PIU30184 PIU3018 PIU30182 PIU3018 PIU3018 PIU30179 PIU30178 PIU3017 PIU30176 PIU30175 PIU30174 PIU3017 PIU30172 PIU3017 PIU30170 PIU30169 PIU30168 PIU30167 PIU3016 PIU30165 PIU30164 PIU3016 PIU30162 PIU3016 PIU3016 PIU30159 PIU30158 PIU30157 PIU30156 PIU3015 PIU30154 PIU3015 PIU30152 PIU3015 PIU3015 PIU30149 crit (noise) (incl. wires) MCU_VDD MCU_VDP5 COTP5 TP5 SYSC_CKOTX MCU_VDD PIC510µ 02 PIC5100n 602 PIC51n 402 GND NLP0041 PITP401P0_41 PIC3202 one cap closest to each pad/pair to adjascent VSS-pad/pair (route under). PIC610µ 902 GND COTP4 TP4 SYSC_CKOT PIR8COR8 01 MCU_VDP5 PIC3201 NLP1029NLP102N8LP1027NLP1026 PIL602 WE.742792656 Pairs: 71/72, 154/155, 226/227, 292/293 MCU_VDD NLP3024NLP3023NLP302 P1_29 P1_28 P1_27 P1_26 PIR1201 *11 NP [0R0] VDE5 COL6 L6 PIR802 NLP3032NLP3031NLP3030NLP3029NLP3028NLP3027NLP3026NLP3025 R8 PIL601 POAPX0SDINM APX_SDINM POAPX0SDINP APX_SDINP COR4PIR401 COR5PIR501 R4 1nF close to pad PIR1101 PIR502 R5 0R0 POAPX0SDOUTP APX_SDOUTP POAPX0SDOUTM APX_SDOUTM 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 PIC5301 MCU_VDP5 COR11 R11 PIR1102 COC53 C53 1n COR12 R12 PIR1202 NLM0X0NLM0X1NLXTAL0NLXTAL1 PIR402 *1 NC NC NC NC NC NC VDP5 VDP5 RSTX NC MODE X1A NC X0A NC VSS X0 X1 XTAL0 XTAL1 AVSS_OSC MOSC_BOPT AVCC5_OSC NC AVSS AVCC12 AVSS AVCC3 RREF AVCC3 SDOUTP NC AVSS SDOUTM AVCC3 SDINM SDINP AVSS NC NC NC NC VDP3 VDP3 VSS VSS P1_29 P1_28 P1_27 P1_26 P3_32 P3_31 P3_30 P3_29 P3_28 P3_27 P3_26 P3_25 VSS VSS VDP3 VDP3 P3_24 P3_23 P3_22 VSS VSS VDD VDD NC NC NC NC NC close to pad PIC5302 M_X0 M_X1 XTAL0 XTAL1 0R0 NLM0X1A NLM0X A POMODE MODE POM0RST0X M_RST_X M_X0A GND M_X1A POP300 POP300000630 POP3063 POP3062 POP3061 POP3060 POP3059 POP3058 POP3057 POP3056 POP3055 POP3054 POP3053 POP3052 POP3051 POP3050 POP3049 POP3048 POP3047 POP3046 POP3045 POP3044 POP3043 POP3042 POP3041 POP3040 POP3039 POP3038 POP3037 POP3036 POP3035 POP3034 POP3033 POP3032 POP3031 POP3030 POP3029 POP3028 POP3027 POP3026 POP3025 POP3024 POP3023 POP3022 POP3021 POP3020 POP3019 POP3018 POP3017 POP3016 POP3015 POP3014 POP3013 POP3012 POP3011 POP3010 POP309 POP308 POP307 POP306 POP305 POP304 POP303 POP302 POP301 P3_[0..63] 6 7 Doc Revision: HW Revision: Date: V0.18 Rev1.0 2011-07-18 Fujitsu Semiconductor Europe GmbH http://mcu.emea.fujitsu.com [email protected] 8 2 3 5 6 7 8 NLP300000630 P3_[0..63] A C64 PIC6401 POAPX0SDINM APX_SDINM C65 PIC6501 COC66 C66 PIC6601 POAPX0SDOUTM APX_SDOUTM COC67 C67 POAPX0SDOUTP PIC6701 APX_SDOUTP POMODE MODE POT0RST0X T_RST_X PIC6402 NP [100n] COC65 NLP3032NLP303N1LP3030NLP3029NLP3028NLP3027NLP3026NLP3025 NLP3024NLP3023NLP302 PIC6502 NP [100n] PIC6602 NP [100n] PIC6702 NP [100n] NLP102N9LP1028NLP1027NLP1026 VDDA VDE5 VDEA MCU_VDP5 P3_24 P3_23 P3_22 COC64 POAPX0SDINP APX_SDINP P3_32 P3_31 P3_30 P3_29 P3_28 P3_27 P3_26 P3_25 POP300 POP300000630 POP3063 POP3062 POP3061 POP3060 POP3059 POP3058 POP3057 POP3056 POP3055 POP3054 POP3053 POP3052 POP3051 POP3050 POP3049 POP3048 POP3047 POP3046 POP3045 POP3044 POP3043 POP3042 POP3041 POP3040 POP3039 POP3038 POP3037 POP3036 POP3035 POP3034 POP3033 POP3032 POP3031 POP3030 POP3029 POP3028 POP3027 POP3026 POP3025 POP3024 POP3023 POP3022 POP3021 POP3020 POP3019 POP3018 POP3017 POP3016 POP3015 POP3014 POP3013 POP3012 POP3011 POP3010 POP309 POP308 POP307 POP306 POP305 POP304 POP303 POP302 POP301 P3_[0..63] A 4 P1_29 P1_28 P1_27 P1_26 1 MCU_VDD MCU_VDP3 MCU_VDD NLP000000630 P0_[0..63] POP000000630 POP0063 POP0062 POP0061 POP0060 POP0059 POP0058 POP0057 POP0056 POP0055 POP0054 POP0053 POP0052 POP0051 POP0050 POP0049 POP0048 POP0047 POP0046 POP0045 POP0044 POP0043 POP0042 POP0041 POP0040 POP0039 POP0038 POP0037 POP0036 POP0035 POP0034 POP0033 POP0032 POP0031 POP0030 POP0029 POP0028 POP0027 POP0026 POP0025 POP0024 POP0023 POP0022 POP0021 POP0020 POP0019 POP0018 POP0017 POP0016 POP0015 POP0014 POP0013 POP0012 POP0011 POP0010 POP009 POP008 POP007 POP006 POP005 POP004 POP003 POP002 POP001 POP000 P0_[0..63] NLP200000630 P2_[0..63] POP200000630 POP2063 POP2062 POP2061 POP2060 POP2059 POP2058 POP2057 POP2056 POP2055 POP2054 POP2053 POP2052 POP2051 POP2050 POP2049 POP2048 POP2047 POP2046 POP2045 POP2044 POP2043 POP2042 POP2041 POP2040 POP2039 POP2038 POP2037 POP2036 POP2035 POP2034 POP2033 POP2032 POP2031 POP2030 POP2029 POP2028 POP2027 POP2026 POP2025 POP2024 POP2023 POP2022 POP2021 POP2020 POP2019 POP2018 POP2017 POP2016 POP2015 POP2014 POP2013 POP2012 POP2011 POP2010 POP209 POP208 POP207 POP206 POP205 POP204 POP203 POP202 POP201 POP200 P2_[0..63] B 134 PIU20134 135 PIU20135 136 PIU20136 NLP0040 P0_40 NLP0041 P0_41 NLP0042 P0_42 NLP0043 P0_43 NLP0044 P0_44 NLP0045 P0_45 NLP0046 P0_46 NLP0047 P0_47 NLP0048 P0_48 NLP0049 P0_49 NLP0050 P0_50 NLP0051 P0_51 NLP0062 P0_62 NLP0063 P0_63 NLP2032 P2_32 NLP2033 P2_33 137 PIU20137 138 PIU20138 139 PIU20139 140 PIU20140 141 PIU20141 142 PIU20142 143 PIU20143 144 PIU20144 145 PIU20145 146 PIU20146 147 PIU20147 148 PIU20148 149 PIU20149 150 PIU20150 151 PIU20151 152 PIU20152 153 PIU20153 154 PIU20154 NLP2034 P2_34 NLP2035 P2_35 NLP2036 P2_36 NLP2037 P2_37 NLP2038 P2_38 NLP2039 P2_39 NLP2040 P2_40 NLP2041 P2_41 NLP2042 P2_42 NLP2043 P2_43 NLP2044 P2_44 NLP2045 P2_45 NLP2046 P2_46 NLP2047 P2_47 155 PIU20155 156 PIU20156 157 PIU20157 158 PIU20158 159 PIU20159 160 PIU20160 161 PIU20161 162 PIU20162 163 PIU20163 164 PIU20164 165 PIU20165 166 PIU20166 167 PIU20167 168 PIU20168 169 PIU20169 170 PIU20170 171 PIU20171 172 PIU20172 173 PIU20173 174 PIU20174 175 PIU20175 176 PIU20176 POT0JTAG0TDO T_JTAG_TDO POT0JTAG0TDI T_JTAG_TDI POT0JTAG0TCK T_JTAG_TCK POT0JTAG0TMS T_JTAG_TMS POT0JTAG0NTRST T_JTAG_NTRST VSS VDD VSS P0_40 P0_41 P0_42 P0_43 P0_44 P0_45 P0_46 P0_47 P0_48 P0_49 P0_50 P0_51 P0_62 P0_63 P2_32 P2_33 VDP5 VSS P2_34 P2_35 P2_36 P2_37 P2_38 P2_39 P2_40 P2_41 P2_42 P2_43 P2_44 P2_45 P2_46 P2_47 VSS VDP5 JTAG_TDO JTAG_TDI JTAG_TCK VSS VDD JTAG_TMS JTAG_NTRST GND COU2 U2 EMA-HD-176-001 AVSS5 AVRH5 AVDD5 DVCC DVSS P1_00 P1_01 P1_02 P1_03 P1_04 P1_05 P1_06 P1_07 DVSS DVCC P1_08 P1_09 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 DVSS DVCC P1_16 P1_17 P1_18 P1_19 P1_20 P1_21 P1_22 P1_23 DVSS DVCC VDP3 VSS P1_34 P1_35 P1_36 P1_37 P1_38 VDD VSS 133 PIU20133 VDP5 RSTX MODE X1A X0A VSS5 XTAL0 XTAL1 VSSA VDE5_OSC VSSA VDDA VSSA VDEA_VCO RREF VDEA SDOUTP VSSA SDOUTM VDEA SDINM SDINP VSSA VDP3 VSS P1_29 P1_28 P1_27 P1_26 P3_32 P3_31 P3_30 P3_29 P3_28 P3_27 P3_26 P3_25 VSS VDP3 P3_24 P3_23 P3_22 VSS VDD 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PIU2013 PIU2013 PIU2013 PIU2019 PIU2018 PIU2017 PIU2016 PIU2015 PIU2014 PIU2013 PIU201 PIU201 PIU20120 PIU2019 PIU2018 PIU2017 PIU2016 PIU201 5 PIU2014 PIU2013 PIU201 PIU201 PIU201 PIU2019 PIU2018 PIU2017 PIU2016 PIU2015 PIU2014 PIU2013 PIU201 PIU201 PIU201 PIU209 PIU2098 PIU2097 PIU2096 PIU2095 PIU2094 PIU2093 PIU209 PIU2091 PIU209 PIU2089 GND MCU_VDP3 P3_21 P3_20 P3_19 P3_18 P3_17 P3_16 P3_15 P3_14 P3_13 VSS VDP3 P3_42 P3_41 P3_40 P3_39 P3_38 P3_37 P3_36 P3_35 P3_34 P3_33 P1_25 P1_24 VDP3 VSS P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P3_06 P3_05 P3_04 P3_03 P3_02 P3_01 VSS VDP3 P3_00 P1_33 P1_32 P1_31 P1_30 NLP3021 P3_21 NLP3020 P3_20 NLP3019 P3_19 NLP3018 P3_18 NLP3017 P3_17 NLP3016 P3_16 NLP3015 P3_15 NLP3014 P3_14 NLP3013 P3_13 88 PIU2088 87 PIU2087 86 PIU2086 85 PIU2085 84 PIU2084 83 PIU2083 82 PIU2082 81 PIU2081 80 PIU2080 79 PIU2079 78 PIU2078 77 PIU2077 NLP3042 P3_42 NLP3041 P3_41 NLP3040 P3_40 NLP3039 P3_39 NLP3038 P3_38 NLP3037 P3_37 NLP3036 P3_36 NLP3035 P3_35 NLP3034 P3_34 NLP3033 P3_33 76 PIU2076 75 PIU2075 74 PIU2074 73 PIU2073 72 PIU2072 71 PIU2071 70 PIU2070 69 PIU2069 68 PIU2068 67 PIU2067 66 PIU2066 65 PIU2065 64 PIU2064 63 PIU2063 62 PIU2062 61 PIU2061 60 PIU2060 59 PIU2059 58 PIU2058 57 PIU2057 56 PIU2056 55 PIU2055 54 PIU2054 53 PIU2053 52 PIU2052 51 PIU2051 50 PIU2050 49 PIU2049 48 PIU2048 47 PIU2047 46 PIU2046 45 PIU2045 B NLP1025 P1_25 NLP1024 P1_24 NLP3012 P3_12 NLP3011 P3_11 NLP3010 P3_10 NLP309 P3_9 NLP308 P3_8 NLP307 P3_7 NLP306 P3_6 NLP305 P3_5 NLP304 P3_4 NLP303 P3_3 NLP302 P3_2 NLP301 P3_1 NLP300 P3_0 NLP1033 P1_33 NLP1032 P1_32 NLP1031 P1_31 NLP1030 P1_30 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PIU201 PIU20 PIU203 PIU204 PIU205 PIU206 PIU207 PIU208 PIU209 PIU201 PIU201 PIU201 PIU2013 PIU2014 PIU2015 PIU2016 PIU2017 PIU2018 PIU2019 PIU20 PIU201 PIU20 PIU203 PIU204 PIU205 PIU206 PIU207 PIU208 PIU209 PIU203 PIU2031 PIU203 PIU203 PIU2034 PIU2035 PIU2036 PIU2037 PIU2038 PIU2039 PIU204 PIU2041 PIU204 PIU2043 PIU204 MCU_AVRH5 MCU_AVDD5 MCU_DVCC MCU_VDD MCU_AVSS5 MCU_VDP3 C C POP100000630 POP1063 POP1062 POP1061 POP1060 POP1059 POP1058 POP1057 POP1056 POP1055 POP1054 POP1053 POP1052 POP1051 POP1050 POP1049 POP1048 POP1047 POP1046 POP1045 POP1044 POP1043 POP1042 POP1041 POP1040 POP1039 POP1038 POP1037 POP1036 POP1035 POP1034 POP1033 POP1032 POP1031 POP1030 POP1029 POP1028 POP1027 POP1026 POP1025 POP1024 POP1023 POP1022 POP1021 POP1020 POP1019 POP1018 POP1017 POP1016 POP1015 POP1014 POP1013 POP1012 POP1011 POP1010 POP109 POP108 POP107 POP106 POP105 POP104 POP103 POP102 POP101 POP100 P1_[0..63] D NLP101N6LP1017NLP1018NLP1019NLP1020NLP102N1LP102 NLP1023 P1_34 P1_35 P1_36 P1_37 P1_38 NLP108NLP109NLP1010NLP101 NLP1012NLP1013NLP1014NLP1015 P1_16 P1_17 P1_18 P1_19 P1_20 P1_21 P1_22 P1_23 NLP100NLP101NLP102NLP103NLP104NLP105NLP106NLP107 P1_8 P1_9 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 GND NLP1034NLP103N5LP1036NLP1037NLP1038 NLP100000630 P1_[0..63] /************************************************************************/ /* (C) Fujitsu Semiconductor Europe GmbH */ /* The schematic is provided without charge for demonstration purposes */ /* only, subject to alterations. */ /* FSEU does not warrant that the deliverables do not infringe any */ /* third party intellectual property right (IPR). In the event that */ /* the deliverables infringe a third party IPR it is the sole */ /* responsibility of the customer to obtain necessary licenses to */ /* continue the usage of the deliverable. */ /* FSEU disclaims any warranty and liability. */ /* (V1.3) */ /************************************************************************/ 1 2 D 3 4 5 6 Product: EMA-MB9DF120-001 Sheet: 3 Drawn by: File: Olaf Behrendt 03_header.SchDoc 7 of 4 Doc Revision: HW Revision: Date: V0.18 Rev1.0 2011-07-18 Fujitsu Semiconductor Europe GmbH http://mcu.emea.fujitsu.com [email protected] 8 1 2 3 4 5 6 7 8 Debug, Trace COX1 X1 POMODE MODE PIX101 PIX103 PIX105 PIX107 PIX109 POTRACE0 POTRACE0000150 POTRACE15 POTRACE14 POTRACE13 POTRACE12 POTRACE11 POTRACE10 POTRACE9 POTRACE8 POTRACE7 POTRACE6 POTRACE5 POTRACE4 POTRACE3 POTRACE2 POTRACE1 TRACE[0..15] NLTRACE0000150 TRACE[0..15] A CORN1 RN1 4*100k CORN2 RN2 4*100k CORN4 RN4 4*100k CORN5 RN5 4*100k GND POTRACECLK TRACECLK POTRACECTL TRACECTL PIRN108 PIRN106 PIRN107 PIRN105 PIRN104 PIRN102 PIRN208 PIRN103 PIRN101 PIRN207 PIRN206 PIRN204 PIRN205 PIRN203 PIRN202 PIRN408 PIRN406 PIRN201 PIRN407 PIRN405 PIRN404 PIRN402 PIRN403 PIRN401 PIRN508 PIRN506 PIRN504 PIRN507 PIRN505 PIRN503 PIRN502 PIRN501 PIX1011 PIX1013 PIX1015 NLT31 T31 NLT30 T30 NLT29 T29 NLT28 T28 NLT27 T27 PIX1017 PIX1019 PIX1021 NLT26 T26 NLT25 T25 NLT24 T24 NLT23 T23 NLT22 T22 NLT21 T21 NLT20 T20 NLT19 T19 NLT18 T18 NLT17 T17 NLT16 T16 PIX1023 PIX1025 PIX1027 PIX1029 PIX1031 PIX1033 PIX1035 PIX1037 PIX1039 PIX1041 PIX1043 PIX1045 PIX1047 PIX1049 PIX1051 NLTRACE15 TRACE15 NLTRACE14 TRACE14 NLTRACE13 TRACE13 NLTRACE12 TRACE12 NLTRACE11 TRACE11 NLTRACE10 TRACE10 NLTRACE9 TRACE9 NLTRACE8 TRACE8 NLTRACE7 TRACE7 NLTRACE6 TRACE6 NLTRACE5 TRACE5 NLTRACE4 TRACE4 NLTRACE3 TRACE3 NLTRACE2 TRACE2 NLTRACE1 TRACE1 NLTRACE0 TRACE0 PIX1053 PIX1055 PIX1057 PIX1059 PIX1061 PIX1063 PIX1065 PIX1067 PIX1069 PIX1071 PIX1073 PIX1075 PIX1077 PIX1079 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 MCU_AVDD5 MCU_AVRH5 PIX102 PIX104 PIX106 PIX108 PIX1010 MCU_AVSS5 PIX1012 PIX1014 PIX1016 PIX1018 PIX1020 PIX1022 A PIX1024 PIX1026 MCU_VDP5 PIX1028 PIX1030 PIX1032 PIX1034 PIX1036 MCU_DVCC PIX1038 PIX1040 PIX1042 MCU_VDP3 PIX1044 PIX1046 PIX1048 PIX1050 PIX1052 MCU_VDD PIX1054 PIX1056 PIX1058 PIX1060 PIX1062 D_TARGET_NJTAGEN PIX1064 PIX1066 POM0JTAG0TDO M_JTAG_TDO POM0JTAG0TDI M_JTAG_TDI POM0JTAG0TMS M_JTAG_TMS POM0JTAG0TCK M_JTAG_TCK POM0JTAG0RTCK M_JTAG_RTCK POM0JTAG0NTRST M_JTAG_NTRST POM0RST0X M_RST_X POT0RST0X T_RST_X PIX1068 PIX1070 PIX1072 PIX1074 PIX1076 PIX1078 PIX1080 Header 2x40 GND GND COC1 C1 MCU_VDP3 close to pads PIC101 COR1 R1 PIR102 NLD0TARGET0NJTAGEN D_TARGET_NJTAGEN 10k B COU1 U1 20 PIR101 PIU1020 19 PIU1019 2 PIU102 3 PIU103 POT0JTAG0TDO T_JTAG_TDO POT0JTAG0TDI T_JTAG_TDI POT0JTAG0TMS T_JTAG_TMS POT0JTAG0TCK T_JTAG_TCK POT0JTAG0NTRST T_JTAG_NTRST COR2 R2 PIR202 10k GND 4 PIU104 5 PIU105 6 PIU106 7 PIU107 8 PIU108 9 PIU109 PIR201 PIC102 GND 100n Vcc OE GND NC A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 10 PIU1010 1 PIU101 B 18 PIU1018 17 PIU1017 16 PIU1016 15 PIU1015 14 PIU1014 13 PIU1013 12 PIU1012 11 PIU1011 PIR302 COR3 10k GND R3 PIR301 SN74CB3Q3245PW close to header APIX-Port NLAPX0SDINM APX_SDINM COC18 C18 PIC1801 COC19 C19 PIC1901 POAPX0SDOUTP APX_SDOUTP NLAPX0SDOUTP APX_SDOUTP POAPX0SDOUTM APX_SDOUTM NLAPX0SDOUTM COC62 APX_SDOUTM PIC6201 C62 COC37 C37 PIC3701 PIC1902 100n PIL401 PIL402 COX2 X2 2 PIX202 TPB+ 1 PIX201 TPB4 PIX204 TPA+ 3 PIX203 TPA- DLW21SR670HQ2 PIL404 PIL403 COL5 L5 PIC3702 100n PIC6202 100n PIL504 PIL503 DLW21SR670HQ2 PIL501 *1: High-Speed transmission-lines (each pair). PCB-hints: 2 100R diff/50R com transmission-lines (Microstrip). perfectly length-matched, fully mitered. Keep away from other signals! *1 COL4 L4 PIC1802 100n MX540300471 PIX20SH1 PIX20SH2 PIL502 SH2 POAPX0SDINM APX_SDINM NLAPX0SDINP APX_SDINP SH1 POAPX0SDINP APX_SDINP crit (noise) *2 4 6 5 PITVS104 PITVS106 PITVS105 1 8 2 PITVS10 PITVS108 PITVS102 PIC6302 COC63 C63 100nPIC6301 COTVS1 TVS1 HSP061-4NY8 *2: Route very short PIRR7 COR7 701 PIR1M0 702 C C GND D PITVS107 7 PITVS103 3 VERY close to header GND GND /************************************************************************/ /* (C) Fujitsu Semiconductor Europe GmbH */ /* The schematic is provided without charge for demonstration purposes */ /* only, subject to alterations. */ /* FSEU does not warrant that the deliverables do not infringe any */ /* third party intellectual property right (IPR). In the event that */ /* the deliverables infringe a third party IPR it is the sole */ /* responsibility of the customer to obtain necessary licenses to */ /* continue the usage of the deliverable. */ /* FSEU disclaims any warranty and liability. */ /* (V1.3) */ /************************************************************************/ 1 2 D 3 4 5 6 Product: EMA-MB9DF120-001 Sheet: 4 Drawn by: File: Olaf Behrendt 04_debug_apix.SchDoc 7 of 4 Doc Revision: HW Revision: Date: V0.18 Rev1.0 2011-07-18 Fujitsu Semiconductor Europe GmbH http://mcu.emea.fujitsu.com [email protected] 8 1 2 3 4 History Doc Rev.: 0.2: 0.3: 80MHz, length-matched, 50Ohm TL A 0.4 0.5 U_02_emu-PCB_interface 02_emu-PCB_interface.SchDoc U_03_trace_debug_connector 03_trace_debug_connector.SchDoc 0.6 TRACECLK TRACECTL TRACE[0..31] TRACECLK TRACECTL TRACE[0..31] 0.7: JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK JTAG_NTRST JTAG_RTCK JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK JTAG_NTRST JTAG_RTCK 0.9: RST_X 0.8: 0.10: 0.11: RST_X 40MHz, TMS, TDI, TCK length-matched, all as short as possible.All apart from other Signals. Keep stubs as short as possible for the upper 4 signals. B 0.12: 0.13: HW-Rev. >1.0: V0.14: C D Changes: initial Version for quotes. added 100nF to voltage-supervisor, entered values for R9..14 (DCDC converter, voltage supervisor). compiled, resolved errors/warnings. new MODE-signal from emu-PCB tied to jumper via 100k. Reset-Supervisor: Part-No. was incomplete, completed to "TPS3106K33DBV" Trace-connector hdr/rec swapped (wrong pin-numbering) All jumpers set to 2mm pitch (some were 2.54mm) GND connection of C18+C22 close to U2 corrected JP10,JP15,JP16 changed to MCU_VDP3/MCU_VDP5 Minor corrections to part-numbers/comments according to new BOM. !Trace-Connector pinning changed!: TRACE[31..16] swapped with TRACECTL/-CLK (same ordering in group) !Trace-Connector pinning changed!: swapped TRACECTL and TRACECLK Jumper added to reset-controller to disable tracegenerated resets. Changes due to VDP3 being disableable (new information): - change net to 3V3 at: - reset-controller.Vdd (from MCU_VDP3) - bus-switch.Vdd (from MCU_VDP3) - LED-VDD, LED-RST supply (from MCU_VDP3) - DEBUG_VDD (fixed; Jumper obsolete => also renamed) - Trace-Jumpers (replaces MCU_VDP5(!)) - add diode from VDP5 (at jumper) to DCDC-converter (supply from target for JTAG-interface and 2 LEDs) - changed op-mode of DCDC to auto-powersave (MODE-pin from Vin to Gnd) - D3 moved to C19 (same net, but more clearly the power-input) - JP10 renumbered to JP18 (a different JP10 was deleted) - D3 removed, added JP19 to select between VDP5 (target) and wall-cube) - JTAG_RTCK from debug/trace-connector pin 74 through U1 (switch) to RTCK-jumper (replaces direct TCK-feedback). - JTAG: removed pull-jumpers and associated parts (obsolete). - TRACE-Connectors: Supply-Jumpers removed, VREF/VSUPPLY tied to 3V3 /************************************************************************/ /* (C) Fujitsu Semiconductor Europe GmbH */ /* The schematic is provided without charge for demonstration purposes */ /* only, subject to alterations. */ /* FSEU does not warrant that the deliverables do not infringe any */ /* third party intellectual property right (IPR). In the event that */ /* the deliverables infringe a third party IPR it is the sole */ /* responsibility of the customer to obtain necessary licenses to */ /* continue the usage of the deliverable. */ /* FSEU disclaims any warranty and liability. */ /* (V1.3) */ /************************************************************************/ 2 B C D Product: EMA-FCR4-TRACE-001 Sheet: 1 Drawn by: File: 1 A 3 of 3 Olaf Behrendt 01_overview.SchDoc Fujitsu Semiconductor Europe GmbH Doc Revision: V0.14 HW Revision: Rev1.1 Date: 08.06.2011 http://mcu.emea.fujitsu.com [email protected] 4 1 2 3 4 5 *1 COJP1 JP1 COL1 L1 *4: Jumper open: target board connected (default). closed: stand-alone operation. PIX107 PIX109 NLTRACE31 TRACE31 NLTRACE30 TRACE30 NLTRACE29 TRACE29 NLTRACE28 TRACE28 NLTRACE27 TRACE27 NLTRACE26 TRACE26 NLTRACE25 TRACE25 NLTRACE24 TRACE24 NLTRACE23 TRACE23 NLTRACE22 TRACE22 NLTRACE21 TRACE21 NLTRACE20 TRACE20 NLTRACE19 TRACE19 NLTRACE18 TRACE18 NLTRACE17 TRACE17 NLTRACE16 TRACE16 POTRACECLK TRACECLK POTRACECTL TRACECTL PIX1015 PIX1017 PIX1019 PIX1021 PIX1023 PIX1025 PIX1027 PIX1029 PIX1031 PIX1033 PIX1035 PIX1037 PIX1039 PIX1041 PIX1043 PIX1045 NLTRACE15 TRACE15 NLTRACE14 TRACE14 NLTRACE13 TRACE13 NLTRACE12 TRACE12 NLTRACE11 TRACE11 TRACE10 NLTRACE10 NLTRACE9 TRACE9 NLTRACE8 TRACE8 NLTRACE7 TRACE7 NLTRACE6 TRACE6 NLTRACE5 TRACE5 NLTRACE4 TRACE4 TRACE3 NLTRACE3 NLTRACE2 TRACE2 NLTRACE1 TRACE1 NLTRACE0 TRACE0 B PIX1011 PIX1013 NLTRACE0000310 TRACE[0..31] POTRACE0000310 POTRACE31 POTRACE30 POTRACE29 POTRACE28 POTRACE27 POTRACE26 POTRACE25 POTRACE24 POTRACE23 POTRACE22 POTRACE21 POTRACE20 POTRACE19 POTRACE18 POTRACE17 POTRACE16 POTRACE15 POTRACE14 POTRACE13 POTRACE12 POTRACE11 POTRACE10 POTRACE9 POTRACE8 POTRACE7 POTRACE6 POTRACE5 POTRACE4 POTRACE3 POTRACE2 POTRACE1 POTRACE0 TRACE[0..31] PIX1047 PIX1049 PIX1051 PIX1053 PIX1055 PIX1057 PIX1059 PIX1061 PIX1063 PIX1065 PIX1067 PIX1069 PIX1071 PIX1073 PIX1075 PIX1077 PIX1079 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 COC2 C2 PIC202 100n PIC302 COC3 C3 10µ PIX108 PIX1010 MCU_AVSS5 PIC402 COC5 C5 1n PIC502 PIC601 COC6 C6 100n PIC602 PIC701 PIL202 PIJP401PIJP402 PIJP402 BLM21PG221SN1D PIC801 COC7 C7 10µ PIC702 3V3 MCU_VDP3 MCU_VDP5 PIL301 MCU_DVCC PIX1030 PIC901 PIX1032 COC9 C9 1n PIX1034 PIX1036 PIC10 1 MCU_DVCC PIC902 PIX1038 COC10 C10 R14 COR14 330k/1% PIR502 PIR501 PILD302 PILD301 1k8 LEDye/2mA COLD4 LD4 PILD402 PILD401 PIT103 1k0 PIT102 PIT101 LEDgn/4mA 10k COT1 T1 BC847C COLD5 LD5 COJP6 JP6 2 PIT202 DVCC COT2 T2 COC12 C12 100n PIC1 02 PIT201 RST_X PIC1202 3 PIT203 PILD502 BSS84 PILD501 PIR602 COR6 R6 LEDrd/2mA PIR601 1k8 GND MCU_VDP3 PIX1040 PIX1042 PIX1044 PIX1046 GND NLD0TARGET0NJTAGEN D_TARGET_NJTAGEN PIX1048 *2 PIX1050 MCU_VDD PIX1052 COC13 close to pads C13 PIX1054 PIX1056 PIC1301 PIX1058 GND PIX1060 PIX1062 PIJP801 3V3 PIC1302 U1 COU1 100n 10 20 GND Vcc PIU1020 1 19 PIU101 NC OE PIU1019 PIU1010 PIX1064 MCU_VDP5 COJP8 JP8 PIC1401 JP 3 pin PIJP802 PIJP803 COR7 R7 PIR702 PIR701 10k PIC1402 GND PIC1501 COC14 C14 1n PIC1601 COC15 C15 PIC1502 100n PIC1602 COL4 L4 PIL401 PIL402 BLM21PG600SN1D COJP7 JP7 PIJP701PIJP702 PIJP702 VDP5 PIC1701 COC16 C16 10µ COC17 C17 PIC1702 100n NLD0DEBUG0NJTAGEN D_DEBUG_NJTAGEN PIX1066 18 PIX1068 PIX1070 PIU1018 17 PIU1017 PIX1072 PIU1016 16 15 PIU1015 14 PIU1014 13 PIU1013 12 PIU1012 11 PIU1011 PIX1074 PIX1076 COR8 R8 PIX1078 PIX1080 PIR802 GND PIR801 10k B1 B2 B3 B4 B5 B6 B7 B8 2 A1 PIU102 3 A2 PIU103 4 A3 PIU104 5 A4 PIU105 6 A5 PIU106 7 A6 PIU107 8 A7 PIU108 9 A8 PIU109 POJTAG0TDO JTAG_TDO POJTAG0TCK JTAG_TCK POJTAG0TMS JTAG_TMS POJTAG0TDI JTAG_TDI POJTAG0NTRST JTAG_NTRST JTAG_RTCK POJTAG0RTCK GND *2: Jumper 1-2: debug from target (trace disabled) 2-3: debug from trace-PCB (default) open: disables both JTAG-ports. B COJP19 JP19 PWR_SRC COX2 X2 PIX203 SN74CBT3245APW PIX2044 5V +-10%/800mA close to header 10MQ040N D1 COD1 PID102 PID101 PIX201 1 COL5 L5 PIL501 PIL502 BLM21PG221SN1D CD2 OD2 PID202 PID201 2 PIX202 CON_ROKA P6SMB6.8A PIJP1901 COU2 U2 3 PIJP1902 PIU203 PIJP1903 PIC1901 PIC1902 COC19 C19 PIC210 COU3 U3 VDD SENSE 3 NMR 2 PIU302 VSS NRSTVDD NRSTSNS 1 PIU301 5 PIU305 VIN 7 EN1 9 PIU209 EN2 2 M/DAT PIC2102 FB1 PIU207 SW1 PIU202 DEF_1 COC21 C21 8 PIU208 EP PIU20EP GND PGND 4 PIU204 6 COL6 L6 PIU206 PIL602 5 PIL601 2µ2H PIU205 10 SW2 PIU2010 ADJ2 PIU201 1 R9 COR9 PIR902 PIR1002 COR10 R10 COC20 C20 PIC2001 COL7 L7 PIL702 2µ2H PIL701 COR11 R11 PIR1102 PIR1202 R12 COR12 820k/1% PIR901 COC18 C18 PIR1001 PIC1801 180k/1% 33p PIC2002 360k/1% PIR1101 COC22 C22 PIC2201 360k/1% PIR1201 3V3 3.3V/500mA 1V2 1.2V/1A 22µ PIC1802 22µ PIC2202 TPS62420DRC PIJP1802CJP18 OJP18 PIJP1801 PWR_RST *3: Jumper open: disable reset from target. closed: allow reset from target (default). PIC23100n 01 PIR401 COR5 R5 PIJP601PIJP602 PIJP602 PIC1201 COC11 C11 10µ 100n PIC10 2 PIL302 BLM21PG221SN1D PIC1 01 *5 PIR1402 PIR301 PIR402 COR4 R4 COJP9 JP9 6 PIR302 3V3 COL3 L3 PIX1026 PIX1028 NLT0RST0XNLRST0X PIU306 4 PIU304 A PILD201 GND PIX1024 PIJP901 PIJP902 PIC2COC23 3C23 02 PILD101 PILD202 1k8 COR3 R3 VDP3 PIC802 PIX1022 *3 T_RST PIR1401 COR2 R2 MCU_VDD GND COR13 R13 3V3 330k/1% PIR201 LEDor/2mA COLD3 LD3 COC8 C8 100n PORST0X RST_X PIR1301 PIR202 PIX1020 Header 2x40 PIR1302 PILD102 1k8 COJP4 JP4 PIL201 PIC501 PIX1016 PIX1018 GND MCU_VDD PIR101 COR1 R1 LEDor/2mA COLD2 LD2 COL2 L2 MCU_VDP3 crit (noise) COLD1 LD1 PIR102 MCU_DVCC 100n MCU_VDP5 GND 8 align in one row at PCB-edge 1V2 VDD COC4 C4 GND AVRH COJP5 JP5 PIJP501 PIJP502 AVSS PIX106 PIJP101PIJP102 PIJP102 PIC401 AVDD COJP3 JP3 PIJP301 PIJP302 PIX102 PIX104 PIX1012 PIX1014 MCU_VDP5 COC1 C1 1n PIL102 BLM21PG221SN1D PIC301 7 1 PIX105 PIJP201 PIJP202 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 PIC102 PIC201 22µ 10k PIX101 PIX103 PIL101 PIC101 100µ MODE PIR2601 MCU_VDD 3 PIR2602 COJP2 JP2 COX1 X1 COR26 R26 PIJP1701 PIJP1702 PIJP1702 GND *1 MCU_AVDD5 MCU_AVRH5 *4 COJP17 JP17 T_RST_X RST_X A *1: Jumpers open: Power from target-PCB (default). closed: Power from trace-PCB. must all be closed if module is being used stand-alone. Jumper VDD can be closed alone if emu-PCB has its VDD bridges removed (Vdd from trace, other power from target). Layout hints: use 2mm Jumpers. 6 GND GND GND GND both inductors: Wuerth 744025002 GND *5: Jumper open: disable reset from reset-controller (default). closed: allow reset from reset-controller. ). PIU303 TPS3106K33DBV GND C D C /************************************************************************/ /* (C) Fujitsu Semiconductor Europe GmbH */ /* The schematic is provided without charge for demonstration purposes */ /* only, subject to alterations. */ /* FSEU does not warrant that the deliverables do not infringe any */ /* third party intellectual property right (IPR). In the event that */ /* the deliverables infringe a third party IPR it is the sole */ /* responsibility of the customer to obtain necessary licenses to */ /* continue the usage of the deliverable. */ /* FSEU disclaims any warranty and liability. */ /* (V1.3) */ /************************************************************************/ D All parts in brackets [] are not soldered 1 2 3 Product: EMA-FCR4-TRACE-001 Sheet: 2 Drawn by: File: 4 5 6 7 of 3 Doc Revision: HW Revision: Olaf Behrendt Date: 02_emu-PCB_interface.SchDoc V0.14 Rev1.1 08.06.2011 Fujitsu Semiconductor Europe GmbH http://mcu.emea.fujitsu.com [email protected] 8 1 2 3 4 5 6 7 8 A A 3V3 PIR1501 PIR1COR17 7R17 01 PIR1601 COR15 R15 COR20 PIRCOR18 18R18 01 PIR2R20 01 PIR1502 PIR1747k 02 POJTAG0NTRST JTAG_NTRST POJTAG0TDI JTAG_TDI POJTAG0TMS JTAG_TMS POJTAG0TCK JTAG_TCK POJTAG0TDO JTAG_TDO PORST0X RST_X PIR1847k 02 PIR247k 02 1 PIX303 3 PIX305 5 PIX307 7 PIX309 9 PIX3011 11 PIX3013 13 PIX3015 15 PIX3017 17 PIX3019 19 PIX301 JTAG_NTRST JTAG_TDI JTAG_TMS JTAG_TCK NLJTAG0RTCK0O JTAG_RTCK_O JTAG_TDO NLRST0X RST_X DBREQ NLDBACK DBACK POJTAG0RTCK JTAG_RTCK *2 PIJP1403 JP14 COJP14 RTCK-sel PIR1602 33R 2 4 PIX304 6 PIX306 8 PIX308 10 PIX3010 12 PIX3012 14 PIX3014 16 PIX3016 18 PIX3018 20 PIX3020 PIX302 Header 2x10 GND PIJP1402 PIJP1401 PIR2502 COR23 PIR2R23 301 PIR2COR24 401 R24 COR25 R25 47k PIR2501 B COR16 R16 33R JTAG Connector COX3 X3 *2: Jumper 1-2: pull RTCK low. 2-3: connect RTCK. open: leave RTCK open (default). PIR247k 302 PIR247k 402 B GND TRACECLK POTRACECLK DBACK TRACE Connector COX4 X4 1 3 5 PIX407 7 PIX409 9 PIX4011 11 PIX4013 13 PIX4015 15 PIX4017 17 PIX4019 19 PIX4021 21 PIX4023 23 PIX4025 25 PIX4027 27 PIX4029 29 PIX4031 31 PIX4033 33 PIX4035 35 PIX4037 37 PIX401 PIX403 NLDBREQ DBREQ RST_X JTAG_TDO NLJTAG0TDO JTAG_RTCK_O NLJTAG0TCK JTAG_TCK NLJTAG0TMS JTAG_TMS NLJTAG0TDI JTAG_TDI NLJTAG0NTRST JTAG_NTRST NLTRACE15 TRACE15 TRACE14 NLTRACE14 NLTRACE13 TRACE13 TRACE12 NLTRACE12 NLTRACE11 TRACE11 NLTRACE10 TRACE10 NLTRACE9 TRACE9 NLTRACE8 TRACE8 PIX405 PIX40G1 PIX40G3 PIX40G5 C 2 PIX402 4 PIX404 6 PIX406 8 PIX408 10 PIX4010 12 PIX4012 14 PIX4014 16 PIX4016 18 PIX4018 20 PIX4020 22 PIX4022 24 PIX4024 26 PIX4026 28 PIX4028 30 PIX4030 32 PIX4032 34 PIX4034 36 PIX4036 38 PIX4038 G1 G2 G3 G4 G5 3V3 NLTRACE7 TRACE7 NLTRACE6 TRACE6 NLTRACE5 TRACE5 NLTRACE4 TRACE4 NLTRACE3 TRACE3 TRACE2 NLTRACE2 NLTRACE1 TRACE1 NLTRACE0 TRACE0 PIX40G2 PIX40G4 C Mictor 2x19 POTRACECTL TRACECTL X5 COX5 TRACE31 NLTRACE31 NLTRACE30 TRACE30 TRACE29 NLTRACE29 TRACE28 NLTRACE28 TRACE27 NLTRACE27 TRACE26 NLTRACE26 TRACE25 NLTRACE25 TRACE24 NLTRACE24 PIX501 1 PIX503 3 PIX505 5 PIX507 7 PIX509 9 PIX5011 11 PIX5013 13 PIX5015 15 PIX5017 17 PIX5019 19 PIX5021 21 PIX5023 23 PIX5025 25 PIX5027 27 PIX5029 29 PIX5031 31 PIX5033 33 PIX5035 35 PIX5037 37 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 PIX502 PIX504 PIX506 3V3 PIX508 PIX5010 PIX5012 PIX5014 PIX5016 PIX5018 PIX5020 PIX5022 PIX5024 PIX5026 PIX5028 TRACE23 NLTRACE23 TRACE22 NLTRACE22 TRACE21 NLTRACE21 TRACE20 NLTRACE20 TRACE19 NLTRACE19 NLTRACE18 TRACE18 TRACE17 NLTRACE17 PIX5030 PIX5032 PIX5034 PIX5036 PIX5038 TRACE16 NLTRACE16 G1 G2 PIX50G2 PIX50G3 G3 G4 PIX50G4 PIX50G5 G5 PIX50G1 Mictor 2x19 GND TRACE[0..31] POTRACE0 POTRACE0000310 POTRACE31 POTRACE30 POTRACE29 POTRACE28 POTRACE27 POTRACE26 POTRACE25 POTRACE24 POTRACE23 POTRACE22 POTRACE21 POTRACE20 POTRACE19 POTRACE18 POTRACE17 POTRACE16 POTRACE15 POTRACE14 POTRACE13 POTRACE12 POTRACE11 POTRACE10 POTRACE9 POTRACE8 POTRACE7 POTRACE6 POTRACE5 POTRACE4 POTRACE3 POTRACE2 POTRACE1 D GND TRACE[0..31] NLTRACE0000310 /************************************************************************/ /* (C) Fujitsu Semiconductor Europe GmbH */ /* The schematic is provided without charge for demonstration purposes */ /* only, subject to alterations. */ /* FSEU does not warrant that the deliverables do not infringe any */ /* third party intellectual property right (IPR). In the event that */ /* the deliverables infringe a third party IPR it is the sole */ /* responsibility of the customer to obtain necessary licenses to */ /* continue the usage of the deliverable. */ /* FSEU disclaims any warranty and liability. */ /* (V1.3) */ /************************************************************************/ 1 2 D Product: EMA-FCR4-TRACE-001 Sheet: 3 Drawn by: File: 3 4 5 6 7 of 3 Doc Revision: HW Revision: Olaf Behrendt Date: 03_trace_debug_connector.SchDoc V0.14 Rev1.1 08.06.2011 Fujitsu Semiconductor Europe GmbH http://mcu.emea.fujitsu.com [email protected] 8