Freescale Semiconductor Mask Set Errata MC56F84xxx_1N27E Rev. 19 JUN 2015 Mask Set Errata for Mask 1N27E This report applies to mask 1N27E for these products: • MC56F84789 • MC56F84786 • MC56F84769 • MC56F84766 • MC56F84763 • MC56F84553 • MC56F84550 • MC56F84543 • MC56F84540 • MC56F84587 • MC56F84585 • MC56F84567 • MC56F84565 • MC56F84462 • MC56F84452 • MC56F84451 • MC56F84442 • MC56F84441 Table 1. Errata and Information Summary Erratum ID Erratum Title e9432 eFlexPWM: Fractional delay block may powerup with an output of 1 instead of 0 e6307 Improper shortening of fractional PWM periods during reload cycles. Table 2. Revision History Revision Changes 17 SEP 2014 Initial revision 17 OCT 2014 This revision only expands the part number. Table continues on the next page... © 2015 Freescale Semiconductor, Inc. Table 2. Revision History (continued) Revision Changes As far as the actual errata: No changes in this revision 19 JUN 2015 The following errata were added. • e9432 The following errata were revised. • e6307 e9432: eFlexPWM: Fractional delay block may powerup with an output of 1 instead of 0 Description: eFlexPWM output PWM2A may be set to 1 upon powering up the fractional delay block. Because there is no reset signal to the flops in the fractional delay block to force a specific reset state, the output must be cleared by creating a pulse on the PWM. This issue only occurs when using the fractional delay block and only lasts until the first time that PWM channel transitions. Workaround: After powering up the fractional delay block of the eFlexPWM by setting FRCTRL[FRAC_PU] and waiting the required power up time, program the VAL* registers to create a PWM pulse (>0% duty cycle) and run for at least one PWM period to clear the state of the registers in the analog block. This can be done prior to enabling the PWM outputs so that external circuitry is not affected. e6307: Improper shortening of fractional PWM periods during reload cycles. Description: When using fractional PWM periods (FRACVAL is non-zero), the PWM period will be shortened by an amount from 0 to 31/32 clock periods during PWM periods where register reloads occur. Workaround: Do not use fractional PWM periods by keeping FRACVAL1==0. Mask Set Errata for Mask 1N27E, Rev. 19 JUN 2015 2 Freescale Semiconductor, Inc. How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits based on the Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo and are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. All rights reserved. © 2015 Freescale Semiconductor, Inc. Document Number: MC56F84XXX_1N27E Rev. 19JUN2015