Beyond DSPs StarCore MSC8xxx and DSP56K Families - Brochures

Next-Generation Digital Signal Processors
November 2010
Beyond DSPs
Giving Customers Another Choice
INCLUDING
StarCore MSC8xxx and
DSP56K Families
(Including Symphony
Audio DSPs)
Beyond DSPs
Table of Contents
History of Freescale/Motorola DSPs
2
Technical Highlights: A closer look at the StarCore DSP families
3
MSC815x and MSC825x Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
StarCore DSP Roadmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SC3850 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DSP Core Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAPLE-B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CLASS Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RISC-Based QUICC Engine Subystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Serial RapidIO® Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PCI Express® Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDR2/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Time-Division Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application Solutions
18
Wireless Base Stations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Medical Imaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Aerospace and Defense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Advanced Test and Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Development Software, Tools and Reference Designs
30
CodeWarrior Development Studio for StarCore 10.0 DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Voice Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Video Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Base Station Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MSC8156 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MSC8156ADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MSC8156AMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
P2020—MSC8156 AdvancedMC™ Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Technical Highlights: A closer look at the DSP56K families
43
DSP56K Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DSP56K Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Application Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
DSP56K Family Development Software,
Tools and Reference Designs
49
Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DSPAUDIOEVM Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Symphony SoundBite Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DSP563xx Evaluation Module (DSP563xxEVME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Ecosystem Partners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
This document contains information on a new product. Specifications and information herein are subject to change without notice.
freescale.com/DSP
Next-Generation Digital Signal Processors 1
Application Solutions
Overview
Freescale DSP Evolution
1986
First 56K DSPs
introduced to
the market
2006
StarCore-based
SC3400 core
technology
introduced to
the market
1998
StarCore
architecture
2009
Focus on the base station market
• SC3850 core released
• 19 design wins, including many to top
wireless infrastructure equipment manufacturers
2007
Multicore DSP5672x
introduced to the market
1986
1996
1998
1996
First single DSP chip
implementation of
Dolby® Digital and
DTS 5.1 decoders
on the 56009
1999
2003
1999
StarCore-based
SC140 core
technology
introduced to
market
2006
2007
2008
2009
2003
StarCore-based
SC1400 core
technology
introduced to
market
2010
2010
Focus on additional markets
• Medical, aerospace, defense, test
and measurement markets
• Freescale brings a new era of
stability, drive and success
to the DSP market
2008
Change of corporate
management
• March 2008—Rich Beyer joins Freescale as CEO
• September 2008—Lisa Su joins Freescale as
Senior VP of embedded processors
• Focus on core markets, prioritization of
strategic markets
• Increased investment for DSP, architecture and tools
• Exited other non-strategic markets
History of Freescale/Motorola DSPs
Freescale Semiconductor (under the
In 1998, Freescale introduced the high-
In 2010, the focus for the StarCore DSPs
Motorola brand) introduced our first
performance StarCore architecture to
expanded with the introduction of the
DSP to the market in 1986 with the
the broad market. In 2008, Rich Beyer
MSC825x family and the MSC8152/
introduction of the general purpose
joined Frescale as CEO and Lisa Su
MSC8251 broad market DSPs. These
digital signal processors (DSPs) based
was appointed Senior Vice President for
new products are targeted for process
on the 56K architecture. The 56K general
embedded processors. They recognized
intensive applications in the video, voice,
purpose DSPs evolved into an extensive
the growth potential in DSP markets and
medical, aerospace, defense and test and
family of embedded DSPs, including 56K
substantially increased investments in
measurement markets and provide the
DSPs with integrated audio software
the StarCore DSP architecture and tools.
optimal blend of cost effectiveness and
called the Symphony DSP line. These
This increased investment in StarCore has
high performance throughput.
DSPs remain popular across a wide
resulted in the highest performance DSPs
range of applications, including audio and
on the market today. Initially, the base
industrial control. Due to the very large
station market was the primary focus
customer base and continued popularity
for high-performance StarCore DSPs. In
of these products, we will be releasing
2009, the SC3850 core was released as
new 56K products in 2011.
the building block core of the MSC8156
six-core high-performance DSP. The
MSC8156 has been an overwhelming
success in the base station market with
17 major design wins, including eight
of the top 10 wireless infrastructure
equipment companies.
2 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Application Solutions
Overview
Technical Highlights
A closer look at the
StarCore DSP families
freescale.com/dsp
Next-Generation Digital Signal Processors 3
Technical Highlights
MSC815x and MSC825x Family Overview
The MSC815x and MSC825x families
MSC815x and MSC825x Family
of DSPs are based on the industry’s
highest performance DSP core, built on
StarCore technology, and designed for the
512 KB
Backside
L2 Cache
advanced processing requirements and
capabilities of today’s high-performance,
defense and advanced test and
measurement markets.
By leveraging the 45 nm process
technology in a highly integrated SoC, the
1024 KB
Shared
M3 Memory
32 KB
I-Cache
64-bit DDR-2/3
Memory
Controller
SPI
I2C
DUART
CLASS Fabric
Clocks/Reset
GPIO
DMA
HSSI
TDM
DMA
QE
Ethernet
MSC815x and MSC825x families of DSPs
deliver industry-leading performance and
1GE 1GE
power savings. These DSPs are based
x4
on SC3850 StarCore technology. The
SC3850 DSP core has earned leading
PCIe
x4
Security
Engine
MAPLE-B
Accelerator
(Only on the
MSC815x devices)
sRIO
video, voice, medical imaging, aerospace,
32 KB
D-Cache
sRIO
high-end industrial applications for the
StarCore
SC3850 DSP Core
x4
8-lane 3.125G SerDes
benchmark results from independent
signal-processing technology analysis
firm Berkeley Design Technology, Inc.
(BDTI). Specifically, Freescale’s SC3850
1.2 GHz core registered a fixed-point
BDTIsimMark2000™ score of 18,500—
the highest score of any DSP architecture
tested by BDTI to date. The combination
of the award-winning SC3850 core and
the richest and highest performance DSP
peripherals available serve to accelerate
system performance and result in a
family of DSPs that offer up to twice the
performance of competitors’ parts.
4 Next-Generation Digital Signal Processors
Despite being the highest performing
MSC815x and MSC825x families helps to
DSP available in the broad market
enable software and tool reuse, allowing
today, these DSPs are also extremely
scalability from a single-core device to
price competitive. Starting at $75 USD
multicore devices, or to create multiple
MSRP, the MSC815x and MSC825x
products from the same hardware.
DSP families offer the industry’s best
value and integration and may save
customers up to one million USD over
the product’s lifetime in processor cost.
In addition to silicon savings, pin and
peripheral compatibility across the
Beyond DSPs, November 2010
Technical Highlights
Pin for Pin Compatibility
Device
MSC8156
MSC8154
MSC8152
MSC8151
MSC8256
MSC8254
MSC8252
MSC8251
SC8350 DSP Cores
6
4
2
1
6
4
2
1
Core Speed (MHz)
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
Up to
48000
Up to
32000
Up to
16000
Up to 8000
1 GHz
800 MHz
Up to
32000
1 GHz
Core Performance
(16-bit MMACs)
1 GHz
800 MHz
Up to
48000
Up to
16000
Up to 8000
Shared M3 Memory
1 MB
1 MB
I-Cache (per core)
32 KB
32 KB
D-Cache (per core)
32 KB
32 KB
L2 I-Cache (per core)
512 KB
512 KB
2 (800 MHz)
2 (800 MHz)
PCI Express®
1
1
GEMAC (RGMII, SGMII)
2
2
Serial RapidIO®
2
2
TDM
4
4
SPI
1
1
UART
1
1
I2C
1
1
Turbo/Virterbi Accelerators
1
FFT/DFT/CRC Accelerators
1
DDR2/3
Processor Technology
Package
Key Features and Benefits
• The MSC815x and MSC825x DSPs
deliver a high level of performance
and integration, combining one, two,
four or six new and enhanced, fully
programmable SC3850 cores, each
running at up to 1 GHz.
• The MSC815x family has added
performance from a multi-accelerator
platform engine (MAPLE-B) for fast
Fourier transforms (FFT), inverse fast
Fourier transforms (iFFT), discrete
Fourier transforms (DFT), inverse
discrete Fourier transforms (iDFT) and
Turbo and Viterbi decoding.
freescale.com/DSP
45 nm
45 nm
783 Ball
FC-PBGA
783 Ball
FC-PBGA
• A high-performance internal RISC-
• A rich peripheral set includes two Serial
based QUICC Engine subsystem
RapidIO® (four lane) interfaces, two
supports multiple networking protocols
Gigabit Ethernet interfaces for network
to help provide reliable data transport
communications, a PCI Express® x4
over packet networks while significantly
interface and four multi-channel TDM
offloading processing from the DSP
interfaces.
cores. TCP/IP stack control via the
• The system is tied together with
integrated QUICC Engine coprocessor
high-speed, high-bandwidth chip-
allows fast communication between
level arbitration and switching fabric
FPGA and DSP to DSP.
(CLASS). The CLASS is a non-blocking,
• Comprehensive memory support
fully pipelined, low latency fabric
includes two 64-bit DDR3 running
interconnect based on a single module
at 800 MHz to enable fast system
and therefore has uniformity in data
throughput for multicore DSPs, GPP
capability with an integrated MMU and
full ECC protection on all memories.
transfer.
• Supports industrial temperature grade:
-40ºC to +105ºC junction.
Next-Generation Digital Signal Processors 5
Technical Highlights
StarCore DSP Roadmap
StarCore DSP Roadmap
Accelerated
Performance
• Base Station
• Medical
Production
Next Generation
Pin-for-Pin
Compatible
Devices
Sample
MSC8156, MSC8154
• 6/4 SC3850 1 GHz+ Cores
• MAPLE-B Coprocessor
• Serial RapidIO®, PCI Express®
Optimized Performance
• Aerospace and
Defense
• Test and
Measurement
MSC8144
• 4 SC3400
1 GHz Core
Next Generation
MSC8256, MSC8254
• 6/4 SC3850 1 GHz+ Cores
• Serial RapidIO, PCI Express
MSC812x
Cost Optimized
• Medical
• General Purpose
• 4 SC140
300–500 MHz Core
MSC812x
• 3/2 SC140
300–400 MHz Core
MSC711x
• 1 SC140
266–300 MHz Core
MSC8152, MSC8151
MSC8252, MSC8251
• 2/1 SC3850 1 GHz+ Cores
• Serial RapidIO, PCI Express
Available Now
Freescale is no stranger to multicore DSP
design. From the StarCore inception in
1998, we are on our fourth generation of
StarCore cores and our third generation
of multicore DSPs with additions to the
StarCore family already in development.
We offer cost-effective, high-performance
DSPS to meet the performance
requirements of process-intensive
applications such as medical imaging or
voice communications. The new MSC825x
and MSC815x DSPs are the world’s first
Next Generation
• 2/1 SC3850 1 GHz+ Cores
• MAPLE-B Coprocessor
• Serial RapidIO, PCI Express
Freescale Product Longevity
Freescale has a longstanding track record
of providing long-term production support
for our products. Freescale is pleased
to provide a formal Product Longevity
Program for the market segments we
2011
2012
The MSC815x, MSC825x and 5672x
families of DSPs are included in the
Product Longevity Program. For terms
and conditions and to obtain a list of
available products, visit freescale.com/
productlongevity.
serve. For market segments in which
Freescale participates, Freescale will
make a broad range of devices available
for a minimum of 10 years. Life cycles
begin at the time of launch.
DSPs available in the 45 nm
process technology.
6 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Technical Highlights
SC3850 Core
The SC3850 DSP core features an
innovative architecture that addresses
SC3850 DSP Core Block Diagram
the performance requirements of today’s
Data and Program Memory
processing intensive DSP applications.
64
64
XBD
32
XAD
32
XBA
XPA
high performance, low power, efficient
128
XPD
32
intensive applications by providing
XAA
This flexible DSP core supports compute-
compilation and high code density.
Each high-performance core is binary
StarCore technology.
OCE
Program
Sequencer
Performing eight MACs per cycle, the
AGU
Register File
BTB
SC3850 core delivers up to 8000 16-bit
MMACS using an internal 1 GHz clock
2 AAUs
PSEQ
at 1V. Operation includes a multiply-
DALU
Register File
BMU
Internal
Bus
compatible with previous generations of
4 ALUs
(2 16 x 16
MAC each)
AGU
DALU
Instruction Bus
accumulate command with associated
data movements and pointer updates.
Resource Stall Unit (RSU)
The StarCore SC3850 DSP core and
SC3850 DSP Core
subsystem is an evolution of the StarCore
SC3400 DSP core and subsystem that
enhances many of the original core and
subsystem components and optimizes
overall performance and memory
hierarchy to target future application
needs.
SC3850 Benefits
• Improved control/compiled code
performance
• Better operation of DSP intensive
kernels
• Minimizing memory system stalls to
increase core use
16 32-bit address registers, freely
Both integer (signed and unsigned)
accessible by address generation
and fractional data types
instructions
Packed fractional complex data type
• Instruction set
four objects on the same register) for
32 and 48 instructions
SIMD operations
High orthogonality of operands
Rich instruction set for DSP and
• Main core resources
Four data ALU execution units
Two integer and address generation
units
16 40-bit data registers with eight
guard bits, freely accessible by data
ALU instructions
• Very high numerical throughput for DSP
operations
control features
Each data ALU can perform two
Good compiler target
16 x 16 multiplications per cycle
• Very high execution parallelism
Up to six instructions executed
in a single clock cycle, statically
Key Features
Several packed data types (two to
16-bit instruction set, expandable to
scheduled
Variable length execution set (VLES)
execution model
Up to four data ALU instructions
and two memory access/integer
instructions per cycle
• Data type support
Byte (8-bit), word (16-bit) and long
(total of eight multiplications for all
ALUs), which can be used for:
- Dot product acceleration
(40 + (16 x 16) + (16 x 16))
- SIMD2 multiplication and
accumulation into two 20-bit
register portions
- Acceleration of complex
multiplication
- Acceleration of extended precision
multiplication
(32-bit) data widths, supported by
instructions and memory moves
freescale.com/DSP
Next-Generation Digital Signal Processors 7
Technical Highlights
• Application specific instructions
• Control features
• Low-power design
for acceleration of the following
Zero-overhead hardware loops with
Low-power wait and stop
algorithms:
up to four levels of nesting
instructions
FFT
A branch target buffer (BTB) for
Fully static logic
Video processing
accelerating execution of change of
Viterbi
flow instructions
Baseband operations
• High throughput memory interface
• OS support
Precise memory exception support
TheSC3850 DSP core technology
achieved a BDTIsimMark2000 score of
18,500—the highest score of any DSP
architecture tested by BDTI to date.
Unified, 32-bit byte addressable
for advanced OS
memory space
User and supervisor privilege levels,
score of 16,690 previously set by Texas
Dual Harvard architecture that
supporting a protected, task-
Instrument’s 1.2 GHz C66X DSP.
permits one 128-bit program access
oriented execution model
and two 64-bit data accesses per
Full support for memory protection
cycle
and address translation in the off-
Core to data memory throughput of
core memory management unity
up to 16 GB per second, at 1 GHz
Exception and normal stack pointer
core frequency
for software stack support
Support of Big Endian, Little Endian
Low task switch overhead using
and Mixed Endian memory policies
wide stack save and restore
• Zero overhead modulo arithmetic
support for address pointers
• Advanced pipeline
12-stage, fully interlocked pipeline
No stalls for memory load to register
MAC operation and result storage
Speculation of conditionally
executed instructions and change of
flow execution paths
This score exceeds the BDTImark2000
instructions
• Rich set of real-time debug capabilities
through an on-chip emulator (OCE)
Real-time PC, data address and data
breakpoint capabilities
Up to six hardware breakpoint
channels and unlimited debuggerenabled software breakpoints
Single stepping
Externally forced instructions in
debug mode by the host processor
Precise detection of PC breakpoints
PC tracing with filtering and
compression options
Support for Nexus IEEE-ISTO 50012003™ standard with off-core ready
modules
8 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Technical Highlights
DSP Core Subsystem
Each SC3850 core is embedded in a DSP
subsystem that enhances the power of
DSP Subsystem Block Diagram
Interrupts
Master MBus
the SC3850 core and provides a simple
222
128
interface to each SC3850 core.
DMA Bus
128
The DSP core subsystem includes:
M2 DMA Bus (128 bits wide)
• An SC3850 core
L2 Cache
DMA Bridge
• Instruction channel with a 32 KB
instruction cache that supports
advanced prefetching
EPIC
Debug Support
Timer
DPU
• Data channel built around a 32 KB
Instruction
Channel
OCE
data cache, which supports advanced
MMU
Data
Channel
prefetching
Write Queue
• Memory management unit (MMU) for
task protection and address translation
• Unified 512 KB L2 cache with
partitioning support for multitasking
64
SC3850 Core
Xa
64
Xb
128
P
reconfigurable in 64 KB partitions as
M2 memory
• Write queue that interfaces between the
core and the data channel
• Data cache
• Unified L2 cache
32 KB
512 KB
Eight ways with 16 lines per way
Eight ways with 1024 indices
Can serve two data accesses in
64-byte line size
parallel (XA, XB)
Physically addressed
Multi-task support
Maximum user flexibility for real-time
Real-time support through locking
support through address partitioning
flexible boundaries
of the cache
Software coherency support (Cache
Rich cache policy support
The subsystem has the following units
ISA or sweep)
and distinctive features:
Multi-channel, two-dimensional
Write-back writing policy
software prefetch support
• Instruction cache
• Dual timer for internal use (such as
RTOS)
• Extended programmable interrupt
controller (EPIC) supporting 256
interrupts
• Real-time debug support with the OCE
and a debug and profiling unit (DPU)
Write-through writing policy
Software coherency support with
32 KB
Hardware line prefetch capability
seamless transition from L1 cache
Eight ways with 16 lines per way
Cache performance ISA support
coherency operation
Multi-task support
(DFETCH touch loading and
External memory interface
Real-time support through locking
DMALLOC)
MBus unified address separate data
flexible boundaries
• MMU
bus, with 32-bit address and 128-bit
Prefetch capability
Virtual to physical address translation
data
Software coherency support (sweep)
Task protection
Supports asynchronous clock ratio
PFETCH touch loading instruction
Defines the memory and access
support
attributes of memory regions
freescale.com/DSP
Next-Generation Digital Signal Processors 9
Technical Highlights
• Debug and profiling
• Interrupt handling
• Two general-purpose 32-bit timers
for RTOS support
On-chip emulator (OCE) for core-
Extended programmable interrupt
related debug and profiling support
controller (EPIC) to handle 256
Debug and profiling unit (DPU) for
interrupts, including from internal
Wait processing state, where the
subsystem level debug and profiling
sources
clocks of the core and caches are
support
Supports 222 interrupts external
gated but peripherals operate
Debug state, single stepping and
to the MSC8156 SC3850 DSP
Stop processing state for full clock
command insertion from the host
subsystem, independently configured
gating
debugger
as maskable or non-maskable
Breakpoints on PC, data address and
32 priority levels for interrupts
data bus values
Asynchronous and synchronous
More than 40 event counting options
interrupts
• Low-power design modes of operation
in six parallel counters
Cache debug mode enabling
observation of the cache state (cache
array, tags, valid and dirty bits, etc.)
and to change the contents of the
data cache array
Real-time tracing of PC, task ID and
profiling information to the main
memory
10 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Technical Highlights
MAPLE-B
The MAPLE-B is an algorithm accelerator
MAPLE-B
for Turbo, Viterbi, FFT/iFFT, DFT/iDFT
and CRC algorithms. It consists of a
programmable system interface (PSIF),
Clock Domain 3
MBus
64 Slave
controller with CRC accelerator, DMA
SBus
32 Slave
64
MBus
Master 1
64
MBus
Master 2
capabilities and three accelerators
attached using an IP interface.
• Turbo/Viterbi processing element:
Performs up to 200 Mbps of Turbo
Interrupts
Clock Domain 2
Green
Clock Domain 3
decoding (six iterations) or up to 115
Clock Domain 1
PSIF
CRC PE
B bus
fftbus
dftbus
Mbps of K=9 (zero tail) Viterbi decoding
points at up to 350 million samples per
64
64
64
second
TVPE
• FFT processing element: FFT and iFFT
for sizes 128, 256, 512, 1024 or 2048
FFT PE
DFT PE
• DFT processing element: DFT and iDFT
for sizes up to 1536 points at up to 175
million samples per second
Highlights of the MAPLE-B include:
• Software-friendly buffer descriptor-
• Flexible and advanced FFT/DFT
acceleration:
The PSIF has two 64-bit wide MBus
based handshake and task assignment
FFT/iFFT for sizes 128, 256, 512,
master ports used to transfer input and
with minimal overhead on DSP cores
1024, 2048 points at up to 280 Msps
for control
DFT/iDFT for LTE sizes at up to 175
output data to and from system memory
and a 64-bit MBus slave port that allows
• Runs at 450 MHz
Msps
any host to access its internal memories.
• Highly flexible and programmable Turbo
In 10 MHz WiMAX case up to 350
Hosts access internal memories to
perform the following functions:
• Place buffer descriptors in the PSIF
internal memory
and Viterbi decoder supporting various
configurable decoding parameters
(polynomials, rate, binary/duo, tail bit,
zero tail)
Msps of 1024 points FFT
• High-speed CRC calculation/check
accelerator for:
LTE code and transport block in UL
• Access the MAPLE-B parameter RAM
Up to 200 Mbps of Turbo decoding
and DL
• Access the processing element
for low latency and advanced
WiMAX PHY burst CRC in UL and DL
registers
The PSIF internal registers are accessed
using the SBus.
antenna systems or up to 100 Mbps
of K=7 tail bit multi-iteration Viterbi
decoding for low latency data/control
channels decoding
The four accelerator processing elements
Support for WCDMA, CDMA2K,
include the following:
WiMAX and 3G-LTE standards
• Turbo/Viterbi Processing Element
CB CRC (LTE) or APQ (all standards)
(TVPE)
Turbo decoding stopping criteria for
• FFT processing element (FFTPE)
low power/low latency and higher
• DFT processing element (DFTPE)
statistical system capacity
• CRC processing element (CRCPE)
Rate de-matching, HARQ support
freescale.com/DSP
accelerated
Next-Generation Digital Signal Processors 11
Technical Highlights
CLASS Fabric
The chip-level arbitration and switching
system (CLASS) is the central internal
CLASS Fabric
Target Devices
interconnect system for the MSC815x and
CCSR
MAPLE
Extended
Core 4–5
Bridge
0
1
2
MSC825x DSP families. The CLASS is a
non-blocking, full-fabric interconnect that
Extended
Core 2–3
Bridge
Extended
Core 0–1
Bridge
DDR
DDR
Controller 1 Controller 2
M3
allows any initiator to access any target
in parallel with another initiator-target
couple. The CLASS uses a fully pipelined
3
4
Target Ports
low latency design and demonstrates
6
7
Chip Level Arbitration and Switching System (CLASS)
per-target prioritized round-robin
arbitration, highly optimized to the target
characteristics.
5
0
1
2
3
4
Initiator Ports
5
6
7
8
9
10
11
bottlenecks and permits high bandwidth
fully pipelined traffic.
SerDes
Bridge
DMA Controller
Initiator Devices
and miss latency. Controlling the
intradevice data flow, the CLASS reduces
MAPLE
Peripherals
Bridge
power dissipation, memory technology
Extended
Core5
Extended
Core4
Extended
Core3
provide an optimized trade off between
Extended
Core2
separate from the SC3850 core clock to
Extended
Core1
SC3850 core speed). The CLASS clock is
Extended
Core0
The CLASS operates at 500 MHz (half the
• Write transactions can have a maximum
pipeline of three acknowledged
requests before completing the
• Programmable masking priority for
starvation elimination
• Multiplexing the initiator buses
The CLASS is ready for use and does
transaction toward the initiator
not require any special configuration
• Programmable priority mapping
to perform non-blocking pipelined
• Programmable auto priority upgrade
aligned transactions according to the
• Address decoding for target selection
target capabilities (maximal burst size,
transactions from any initiator to any
memory.
The CLASS modules implement the
and multi target demultiplexing
Programmable address space start/
following features:
end registers per target for flexible
• Non-blocking, full-fabric interconnect
address decoding (resolution of 4
• Full bandwidth utilization toward
KB). Not supported in the reduced
each target
• Allows full pipeline when a specific
initiator accesses a specific target
• Allows full pipeline when accesses are
generated by one or more initiators to
specific targets
• Read transactions can have a maximum
pipeline of 16 acknowledged requests
before completing the transaction
toward the initiator
configuration option
Fixed priority between address
according to the arbitration winner
• Normalizing mode that splits non-
power-of-2 burst, burst alignment, full
size burst, data-beat alignment, wrap
size)
• Error detection and handling
The CLASS identifies illegal
addresses addresses that do
not belong to any of the address
decoding results, allowing
windows or fall inside the negative
overlapping and deduction of
windows
address windows
• Per-target arbitration algorithm
Four-level prioritization
Each level implements pseudo
round-robin arbitration algorithm
The CLASS stores the illegal address,
reports the error and generates an
interrupt
• Debug and profiling unit (CDPU)
support
Weighted arbitration
Optimized data bus utilization mode
12 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Technical Highlights
RISC-Based QUICC Engine Subsystem
The QUICC Engine subsystem is a
versatile RISC-based communication
RISC-Based QUICC Engine
Data Path Interfaces to
External Memories
processor that supports multiple external
interfaces and protocols independently
from the core processor(s) in an
integrated processing device.
Interrupt Cont
In the MSC815x and MSC825x, the
SDMAs
Multi-User
RAM
32-bit RISC
QUICC Engine includes two Gigabit
ROM
32-bit RISC
ROM
Instruction
RAM
Ethernet controllers (supporting both
RGMII and SGMII interfacing) and one SPI
Control
Peripheral Bus
interface. With the QUICC Engine block,
packet processing up to and beyond layer
4 (TCP/UDP) can be offloaded from the
UCC1
UCC3
SGMII
RGMII
SGMII
RGMII
MIGSK
MIGSK
SPI1
SC3850 cores. This allows the cores to be
relieved of the data transfer and handling
overhead commonly associated with
Ethernet tasks.
QUICC Engine packet processing allows
the programmer to create multiple
independent data and control flows
between each core and each QUICC
Engine Ethernet controller enabling
the flexibility of both symmetric and
HSSI
asymmetric multicore processing models.
SerDes
SerDes
SGMII
SGMII
The QUICC Engine can be clocked at up
to 500 MHz, and is comprised of:
• Dual RISC engines
Internal interfaces to the core and
peripherals
Parameter RAM
Buffer descriptors
RGMII
RGMII
• Two programmable unified
Serial management interface MDC/
communication controllers (UCCs),
MDIO
each of which provides dedicated
Transmitter network management
support for an Ethernet controller for
and diagnostics
RGMII/SGMII interfaces
Receiver network management and
Multi-threading operation
Supports lossless flow control and
diagnostics
Serial numbers
PAUSE flow control for full duplex
operation
Enhanced MIB statistics
Instruction RAM (IRAM)
• Serial DMA controller
• Clocking
Signal multiplexing
Baud-rate generation
• Dedicated interrupt controller with
interrupt signals for each MSC815x
core
- Transmit flow control via a host
command
- Automatic transmit flow control
according to programmable
receive FIFO thresholds
Frame filtering and address
recognition
VLAN support
IEEE® Std. 802.1p/Q QoS support
• Serial peripheral interface (SPI)
- Programmable MAC parameter in
flow control frame
Full collision support
Framing support for single and multibuffered Ethernet frames
freescale.com/DSP
Next-Generation Digital Signal Processors 13
Technical Highlights
Serial RapidIO® Architecture
The RapidIO architecture provides high
data bandwidth, low-latency capability,
Serial RapidIO®
To/From
CLASS
and support for high-performance I/O
devices. The MSC815x and MSC825x
21Gbps
parts include a Serial RapidIO architecture
OCeaN
DMA A
that supports two ports, a RapidIO
OCN2
MAG_A
21Gbps
OCN2
MAG_B
OCeaN
DMA B
message unit (RMU) and two RapidIO
DMA units. The Serial RapidIO ports
OCeaN Fabric
Eight ports at core/3
comply with the RapidIO Interconnect
Specification, Revision 1.2, which
supports 1x/4x operation up to
3.125 Gbaud.
processed packets are sent back to the
host. Each Serial RapidIO port supports
read, write, messages, doorbells and
PEX
1x/2x/4x
Protocol Converter
Protocol Converter
SerDes1
SerDes2
PEX
SRIO
SGMII
to the MSC815x/825x device and the
SGMII
for processing are sent from the host
SRIO
a Serial RapidIO switch. Packets ready
SRIO_B
1x/4x
SGMII
MUX
SGMII
can either connect directly to a host or
SGMII
The MSC815x and MSC825x devices
SRIO_A
1x/4x
To/From
QE
maintenance accesses. The RapidIO DMA
units are used for NWRITE, NWRITE_R,
NREAD and SWRTE operations, while
the RMU controls message and doorbell
operations. The buffers in the Serial
RapidIO endpoints support packets up to
256 bytes.
The two Serial RapidIO ports can be
configured to perform pass-through
operations between them. This
connectivity allows packets to be
forwarded to the next device connected
to the second RapidIO port.
Features
• Two Serial RapidIO ports supporting
1x/4x operation up to 3.125 Gbaud
with a RapidIO messaging unit and two
RapidIO DMA units
• Each Serial RapidIO port supports
• Each RapidIO DMA unit supports:
read, write, messages, doorbells and
Four high-speed/high-bandwidth
maintenance accesses
channels accessible by local and
Small and large transport information
remote masters
field only
Basic DMA operation modes (direct,
Priority flow
simple chaining)
Pass-through between the two ports
Extended DMA operation modes
that allows cascading devices using
(advanced chaining and stride
the Serial RapidIO and enabling
capability)
message/data path between the two
Programmable bandwidth control
Serial RapidIO ports without core
between channels
intervention. A message/data not
Up to 256 bytes for DMA sub-block
designated for the specific device
passes through to the next device
• RapidIO messaging unit supports:
Two outbound message queues
transfers to maximize performance
over the RapidIO interface
Three priority levels supported for
source and destination transactions
Two inbound message queues
One outbound doorbell queue
One inbound doorbell queue
One inbound port-write queue
14 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Technical Highlights
PCI Express® Controller
The PCI Express® controller supports
and write operations to local memory
communication with PCI Express devices
space. When configured as an EP device,
connected to the MSC815x or MSC825x
the PCI Express controller accepts
devices for high-bandwidth data transfers.
configuration transactions to the internal
It complies with the PCI Express Base
PCI Express configuration registers.
Specification, Revision 1.0a and connects
Message generation and acceptance are
to a 2.5 GHz serial interface configurable
for up to a x4 interface.
supported in both RC and EP modes.
The address translation mapping unit
Features
• Complies with the PCI Express Base
Specification, Revision 1.0a
• Supports root complex (RC) and
endpoint (EP) configurations
• 32- and 64-bit address support
• x4, x2 and x1 link support
• PCI Express configuration registers
The PCI Express controller can be
(ATMU) maps transactions from the
configured to operate as either a root
MSC815x or MSC825x devices to the
complex (RC) or an endpoint (EP)
PCI Express controller as a memory, I/O,
• 256 byte maximum payload size
device. As an RC device, the PCI
message or configuration transaction via
• ATMU
Express controller connects the core and
translation windows. Transactions from
• Three inbound general purpose
memory subsystem to I/O devices and
the PCI Express controller are mapped to
translation windows and one
configures the EP devices during device
the MSC815x/MSC825x internal platform
configuration window
discovery and enumeration. It can also
via inbound translation windows. For
act as an initiator and a target device.
outbound transactions, the MSC815x/
As an initiator, the PCI Express controller
MSC825x supports four translation
supports memory read and write
windows and one default window. For
operations with a maximum transaction
inbound transactions, the MSC815x/
size of 256 bytes. As a target interface,
MSC825x supports three inbound
the PCI Express controller accepts read
windows and one configuration window.
freescale.com/DSP
(type 0 in EP mode, type 1 in RC mode)
• Four outbound translation windows and
one default window
• Supports eight non-posted and four
posted PCI Express transactions
• Credit-based flow control management
• Supports PCI Express messages and
interrupts
Next-Generation Digital Signal Processors 15
Technical Highlights
DDR2/3
The MSC815x and MSC825x DSP
provide up to a maximum 1 GB of DDR
The memory interface supports voltages
families support two DDR controllers for
space for each controller. Discrete,
of 1.5V (SSTL_15) for DDR3 and 1.8V
external memory expansion. The DDR
unbuffered and registered dual rank
(SSTL_18) for DDR2. Accesses to memory
SDRAM interface is useful when an
memory modules (DIMMs) are supported.
are burst oriented, with support for burst
application requires additional code or
length of eight for DDR3 and burst length
Built-in error checking and correcting
data storage to supplement the internal
of four for DDR2. For DDR3, on-chip ZQ
(ECC) protection ensures reliable
M2 or M3 memory.
operation. When ECC is enabled, the DDR
The DDR controllers can interface with
memory controller corrects all single-bit
JEDEC-compliant 8- or 16-bit DDR2 or
errors and detects all double-bit errors
DDR3. The data bus interface is 64/72 or
within the 64-bit or 32-bit data bus.
32/40 bits wide. Each controller supports
calibration is supported to adjust output
driver and on-die termination impedance.
DDR3 also supports write leveling to
compensate for the flight time skew delay
with respect to the strobe and
clock signals.
two physical bands or chip selects to
Features/Category
DDR2
DDR3
Package
BGA
BGA
Densities
256 MB to 8 GB
512 MB to 8 GB
Voltage
1.8V core and I/O
1.8V core and I/O
SSTL_18
SSTL_15
I/O Signalling
Internal Memory Banks
4 to 8
8
Up to 800 Mbps
Up to 800 Mbps
On-die termination for data group, VTT termination
for address, command and control
On-die termination for data group, VTT termination
for address, command and control. Supports
dynamic ODT
Data Strobes
Differential (recommended) or single-ended
Differential
Burst Length
BL-4, 8 (4-bit prefetch)
BL-8 (Burst chop4) 8-bit prefetch
CL/tRCD/tRP
15 ns each
12 ns each
Data Rate
Termination
Master Reset
No
Yes
ODT (On-Die Termination)
Yes
Yes
Off-chip (OCD)
On-chip with ZQ pin (ZQ calibration)
Driver Calibration
Leveling
Interface Data Bus Width
DIMM Support
Full ECC Support
No
Yes
32/40-bit and 64/72-bit
32/40-bit and 64/72-bit
Discrete, unbuffered and registered 64 MB through
8 GB
Discrete, unbuffered and registered 64 MB through
8 GB and mirrored DIMMS
Single error correction/detection, double error
detection
Single error correction/detection, double error
detection
Yes
Yes
Self Refresh Support
16 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Technical Highlights
Time-Division Multiplexing
The time-division multiplexing (TDM)
TDM Modules Diagram
T3clk
TDM3TSN T3sync
TDM3TCK
R3clk
TDM3TDT T3data 0
TDM3RCK
TDM3RSN R3sync
T2clk
TDM3RDT R3data 0
TDM2TSN T2sync
TDM2TCK
R2clk
TDM2TDT T2data 0
TDM2RSN R2sync
TDM2RCK
TDM1TCK Rxclk (common)
TDM2RDT R2data 0
TDM1TSN Rxsync (common)
TDM1TDT Txdata 3
TDM1RCK Txdata 2
hardware A-law/μ-law conversion is
TDM1RDT Rxdata 2
be configured to 2, 4, 8 or 16 bits. A
TDM1RSN Rxdata 3
up to 62.5 Mbps. Time slot sizes can
TDM0TDT Txdata 0
256 bidirectional channels running at
TDM0RSN Rxdata 1
identical TDM modules, each supporting
TDM0RCK Txdata 1
The TDM interface is composed of four
TDM0RDT Rxdata 0
common buses such as the ST-Bus.
TDM0TCK Txclk (common)
to most E1/T1 framers as well as to
TDM0TSN Txsync (common)
interface provides a glueless connection
supported for 8-bit channels.
TDM0
Each TDM module can operate in
TDM1
TDM2
TDM3
independent or shared mode. In
independent mode, the transmit and
receive have separate clock, frame sync
RTSAL[3-0]=0001
CTS=1
RTSAL[3-0]=0001
CTS=1
RTSAL[3-0]=0000
CTS=0
RTSAL[3-0]=0000
CTS=0
and data links with up to 256 transmit
channels and up to 256 receive channels.
In shared clock and sync mode, the
clock and frame sync signals are shared
between the two receive data links and
two transmit data links. Each of the two
transmit and data links support up to 128
channels. In shared data link mode, up to
• Independent receive and transmit
mode
• Shared sync and clock mode
• Shared data link
• 2-, 4-, 8- or 16-bit word size. All
• Hardware A-law/μ-law conversion
clock and frame sync. Each link supports
• Up to 62.5 Mbps data rate per TDM
Features
• Four independent TDM modules.
Together, the four TDM modules
support up to 1K time slots for
active or inactive
• Support for either 0.5 ms (4 frames)
or 1 ms (8 frames) latency
• Glueless interface to E1/T1 framers
channels share the same size
four full-duplex data links share the same
up to 128 channels.
• Each channel can be programmed as
module
• Up to 16 MB per channel buffer
where A/μ law buffer size has
double size
• Separate or shared interrupts for
receive and transmit
receive and 1K time slots for transmit
freescale.com/DSP
Next-Generation Digital Signal Processors 17
Application Solutions
Application Solutions
18 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Application Solutions
Wireless Base Stations
The MSC8156 and MSC8154 high-
3G-LTE, Single Sector 20 MHz Channel Card
performance StarCore DSPs are the
the very highest performance in multicore
baseband DSPs. With up to 6 GHz DSP
core performance, this fully programmable
DDR2/DDR3
perfect solution for the industry’s need for
MSC8156
DDR
sRIO 4x
sRIO 4x
GbE
advanced DSP subsystem offers up to
performance. This performance is
proven by successful deployments of the
DDR2/DDR3
48 GMACs (8- or 16-bit) of processing
sRIO
Switch
Tsi 568A
4x
MSC8572
Back Plane
GbE
GbE
PHY
PHY
GbE
GbE
sRIO
DDR
LB
MSC8156
DDR
sRIO 4x
sRIO 4x
GbE
Port0
Port1
Flash
DDR2/DDR3
MSC8156 at several of the top wireless
infrastructure OEMs.
RF
Code compatibility with the previous
generation MSC8144 DSP ensures
seamless software migration to the new
MSC8156 DSPs.
sRIO-CPRI
Bridge
4x
• One MSC8156 device allocated to DL
processing
• sRIO switch for full connectivity
Additional value drivers for the base
between devices, with option to remove
station market include:
sRIO switch using pass through feature
• Control code efficiency at GPP level
(TBV)
• Low latency memory hierarch
• High-throughput, low-latency baseband
accelerators
• Small front-end bridge needed in case
of CPRI/OBSAI backplane
pertinent to different systems
WiMAX Three Sector 10 MHz
Channel Card
topologies
• Three sectors 10 MHz
• Advanced high-speed interfaces
• High speed/wide external DDR
interfaces
• Drives a low BOM channel card
3G-LTE, Single Sector
20 MHz Channel Card
• 20 MHz use case, 4 x 4 DL and 2 x 2
UL MIMO
• Suitable for UL SIMO and basic UL
MIMO schemes
• Peak data rates per sector are assumed
• Downlink: Four Tx antenna,
beamforming, 100 Mbps max per
sector
• Uplink: Eight Rx antenna, 14 Mbps max
per sector
• Serial RapidIO switch for full
connectivity between devices, with
option to remove Serial RapidIO switch
using pass-through feature (TBV)
• Small front-end bridge needed in case
of CPRI/OBSAI backplane
to be 300 Mbps DL/150 Mbps UL as
supported by category 5 type user
equipment with multi-user UL MIMO
• One MSC8156 device allocated to UL
processing
freescale.com/DSP
Next-Generation Digital Signal Processors 19
Application Solutions
Video
High-definition video applications requiring
superb video quality and support for scalable
solutions are best served by the MSC825x
DSP family coupled with Freescale’s
extensive off-the-shelf codec libraries.
Freescale was first to introduce a fully
featured 1080P30 HD H.264/SVC
embedded solution supporting temporal,
spatial and quality scalability, available
for free download and evaluation. SVC,
together with over 30 video, audio and
voice codecs, running on the highperformance MSC825x devices, enables a
variety of high-end video applications.
Key advantages of Freescale’s hardware
and software solutions for video
applications:
• Highest performing multicore DSP
platform available with the ability to
support HD H.264/SVC and other
advanced codecs
• Programmable DSP and software
codecs allow customers to add
proprietary code and tweak solution to
best suit the target market
• Rich device peripherals: Dual 4x Serial
RapidIO, 4x PCI Express and dual
Videoconferencing
Multipoint Control Unit
MSC825x devices, together with the rich
The videoconferencing multi-point
media codec libraries, are well suited for
control unit is a key element in modern
videoconferencing applications and their
videoconferencing systems, enabling
H.264/SVC, high video quality and system
interoperability and communication
flexibility requirements.
between participants using a wide variety
Freescale’s software codecs support low
delay encoding and decoding required
in videoconferencing applications and
maintain high quality at low bitrates. The
support of fully featured SVC further
of end point terminals. The multi-point
control unit, often referred to as a bridge,
establishes conference calls between
three or more people for converged video,
voice and data conferences.
assists when combating unreliable
MSC825x is used for performing encode,
networks or network bottlenecks by use
decode and other image processing
of the scalability options for maintaining a
functions required in the multi-point
high quality video transmission.
control unit.
Rich device peripherals allow seamless
Serial RapidIO and PCI Express high
connectivity to other system components,
bandwidth interfaces enable transfer of
such as FPGA or a host processor, and
raw video data between devices in multi-
also allow for multi-device solutions
device solutions that are prevalent in
required in videoconferencing MCUs.
videoconferencing infrastructure systems.
Freescale offers a rich portfolio of video
Rich software codec libraries allow
software technologies, including H.264
interoperability of participants connecting
baseline profile running at 1080p30 and
with advanced and legacy end-points and
legacy support for H.263/MPEG-4. Please
enable maximum flexibility in MCU design
contact your Freescale representative for
with no performance degradation for
more information.
support of lower resolution streams.
Gigabit Ethernet allow flexible multidevice system solutions and seamless
connectivity to FPGAs or other system
components
• 2x DDR3 at 800 MHz for high data rate
video applications
• 2-, 4- and 6-core, pin-compatible
devices for scalable system solutions
• All codecs scale to support multiple
streams of lower resolution with no
performance degradation
• H.264/SVC, H.264BP, MPEG-4, MPEG2, G.729, AAC and many other video,
voice and audio components available
from Freescale or ecosystem partners
• Freescale video and audio production
codecs are shipping in today’s leading
media products
20 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Application Solutions
HDMI/DVI
Receiver
Display 1
HDMI/DVI
Receiver
systems are used to make video-enabled
to point) or multiple participants (multi
point). A typical EP will feature at least
one HD camera and one screen while
high-end (telepresence) systems will
include three HD cameras and three
large screens to better emulate a face
to face meeting and an additional data
channel. Processing elements in the EP
must perform at least a single encode
and decode of HD video and additional
image processing functions, such as
image resize and on-screen display.
High-end room systems require multiple
simultaneous encodes and decodes at
frame rates up to 60 frames per second.
MSC825x is used for performing the
encode, decode and other image
processing functions connected on the
one end via PCIe interface to an FPGA
for image capture and display and on
the other end to a host processor for
network connectivity. Based on specific
system requirements, one or more DSP
devices can be used to perform the
Camera 2
HDMI/DVI
Receiver
Display 2
HDMI/DVI
Receiver
DDR
Controller
DDR
4x
Decode
Voltage
Regulator
Resize/
OSD/PIP
Encode
TDM
calls between two participants (point
FPGA
SERDES
Camera 1
SERDES
Videoconferencing end point (EP)
Room System and Telepresence Videoconferencing End Point
Optional
Mic Array
Voltage
Regulator
DSP
Optional DSPs
for Dual Channels
PCIe
GE
Key Pad
GE
Local Host
MPU
IR
USB
Remote Control/
RF Remote Control
Voltage Regulator
Freescale Technology
Enterprise IP-PBX Block Diagram
Optional
Voltage
Regulator
Voltage
Regulator
DDR
Voltage
Regulator
DDR
Controller
MPU
GE
multiple encode and decode functions
SERDES
Videoconferencing End Point
(EP)
4x
SRIO/PCIe
Switch
Fabric
4x
4x
DDR
DDR
DDR
Controller
DDR
Controller
DSP
GE
GE
Optional
Dual SRIO
while utilizing the high bandwidth
Optional
Serial RapidIO ports for inter-device
connectivity.
Media Gateway
Please refer to media gateway application
Conferencing End Points
Voltage
Regulator
DSP Farm
Freescale Technology
section on page 23.
freescale.com/DSP
Next-Generation Digital Signal Processors 21
Application Solutions
Voice
VoIP (Voice over IP) is becoming a
video and data applications. Customers
Express and/or the Gigabit Ethernet
more frequently utilized technology
can use the MSC825x family to architect
interfaces. The MSc825x family offers up
as customers discover its cost and
very flexible and scalable solutions for
to four TDM interfaces, each supporting a
quality benefits. As the communications
media-over-IP equipment. Due to the
maximum of 256 channels of narrow-band
industry completes the migration from
programmability and flexibility of the DSP
voice. These can then connect to T1/E1
circuit-switched to packet-switched
family, customers can adjust the mix of
TDM ports.
infrastructure, equipment manufacturers
media traffic being processed in real time.
require system solutions that include:
• Comprehensive design tools and
system-level solutions
• DSP devices that offer increasing levels
of signal processing and integration
• Peripherals that provide the ability
to interface with both packet- and
circuit-switched networks and software
support
voice (narrow and wide-band) software
essential signal processing functions for
technologies, along with voice
voice, fax and modem data applications.
enhancement, tone detection and
At the heart of a typical media processing
generation, video and modem/fax-related
subsystem are multiple MSC825x DSPs.
functions.
Typical functions include voice encoding
Please contact your Freescale
and decoding (wide band and narrow
representative for more information.
band), tone detection, voice activity
detection/comfort noise generation/
The challenges in today’s packet-based
packet loss concealment (VAD/CNG/
networks are to reduce overall cost
PLC), echo cancellation (EC), as well as
(increased integration), reduce power
modem and fax data modulation and
consumption and create a unified
demodulation.
approach to transporting voice, video
and additional media. The Freescale
MSC825x family of DSPs is a fully
software-programmable series of DSP
solutions suitable not only for voice,
22 Next-Generation Digital Signal Processors
Freescale offers a rich portfolio of
The DSP subsystem is designed to run
The DSP subsystem interfaces to a host
processor (typically a Freescale processor
built on Power Architecture® technology,
such as a QorIQ processor) via the PCI
Beyond DSPs, November 2010
Application Solutions
• Packet based (IP to IP)
• Programmability and flexibility
for converged voice and video
Voltage
Regulator
communications
4x
SRIO/PCIe
Switch
4x
• High channel density, 100s to 1000s of
GE
GE
DDR
Controller
DSP
Decode
MPU
2 interconnect
• Low power consumption
DDR
Optional
DDR
Controller
• High-bandwidth/low-latency DSP layer
Voltage
Regulator
Voltage
Regulator
DDR
SERDES
Application highlights and requirements:
Media Gateway Block Diagram
SERDES
Media Gateway
(Unified Communications)/
Session Border Controllers
IP Switch
GE
Transcode/
Transrate
GE
GE
Encode
Optional
channels
• Hardware support for redundancy
DSP Farm
Voltage
Regulator
Enterprise Application
Application highlights and requirements:
• TDM support for conventional POTs or
T1/E1 interfaces (TDM to IP)
Freescale Technology
• Medium to low channel density,
scalability from 10s to 100s of
channels
Enterprise IP-PBX Block Diagram
• Requires specialized functions for
telephone interface such as line echo
cancellation
Optional
SerDes
SerDes/
PCIe
Switch
MPU
RGMII
RGMII
L2
Ethernet
Switch
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
SerDes DDR
SerDes DDR
SerDes DDR
SerDes DDR
Voice SerDes
Enc/Dec
SerDes
Voice
Enc/Dec
Signaling
DSP
DSP
DSP
DSP
Voice
Enc/Dec
Signaling
DSP
Echo Cancellation
Voice
Enc/Dec
Signaling
DSP
Echo
Cancellation
RTP/RTCP
Voice
Enc/Dec
Signaling
Echo
Cancellation
RTP/RTCP
UDP/IP
Voice
Enc/Dec
Signaling
Echo
Cancellation
RTP/RTCP
UDP/IP
Jitter
Buffer
Signaling
Echo
Cancellation
RTP/RTCP
UDP/IP
Jitter
Buffer
Echo
Cancellation
RTP/RTCP
UDP/IP
Buffer
RGMIIJitter
TDM
RTP/RTCP
UDP/IP
Buffer
RGMIIJitter
TDM
UDP/IP
Buffer
RGMIIJitter
TDM
Buffer
RGMIIJitter TDM
RGMII
RGMII
T1/E1
Framer/
TDM
TDM
DSP Farm
freescale.com/DSP
Next-Generation Digital Signal Processors 23
Application Solutions
Medical Imaging
The complexities of medical imaging
require extraordinary processing power.
Modalities such as ultrasound, X-ray,
Ultrasound
HV Pulse
Generator
Transducer
magnetic resonance imaging (MRI) and
DAC
RX Beamformer
computed tomography (CT) scans all
and high levels of connectivity. These
Signal Conditioning
Tx/Rx
Switches
LNA
VGA
RF
Demodulation
and MSC825x families of high-
reconstruction and image processing at
Spectral
Doppler
Processing
(D Mode)
CW (Analog)
Beamformer
ADC
Power
Management
User Interface
performance DSPs which are capable of
B-Mode
Processing
Scan
Conversion
the heart of medical imaging systems.
Color
Doppler
(PW)
Processing
(F Mode)
USB
MSC815x and MSC825x devices
Keypad
offer unprecedented I/O and memory
bandwidth with the ability to combine PCI
DSP/DSC
ADC
AAF
needs are addressed by the MSC815x
performing the compute intensive image
Beamforming
Control
DAC
push performance limits for advanced
integrated I/O, rigorous data processing
TX Beamformer
Freescale Technology
Display
Memory
Wireless
Comm
Audio
Output
Optional
Express, Serial RapidIO and/or Gigabit
Ethernet and one or two 64-bit DDR2/3
sends ultrasonic waves through the
additional signal processing functions,
such as medical image reconstruction.
patient and detects the echoes of the
such as filtering, demodulation and scan
bounced back waves, applies digital
conversion required for achieving the
The MSC815x device family also
processing to these signals and builds an
desired output image.
features a dedicated DFT/FFT hardware
image to be shown on a screen.
interfaces for data intensive applications
accelerator capable of running up to 350
Mega samples/sec. Off-loading these
functions from the cores leaves ample
processing headroom for additional
system requirements or enables the use
processing libs in order to accelerate
can be best realized on MSC815x or
development time for our end customers.
MSC825x high-performance single- or
Please contact your Freescale
multicore DSP devices which are capable
representative for more information.
of single- or dual-core devices.
of performing the data intensive B mode
Ultrasound
modes of doppler processing that are
Ultrasound is a non-invasive medical
imaging technique used to visualize
muscles, tendons, pathological lesions
and many internal organs and other
structures. It plays an important role
during prenatal care and is commonly
used as a diagnostic tool. Ultrasound
24 Next-Generation Digital Signal Processors
Freescale plans to offer B-mode
Image reconstruction and processing
image reconstruction and the different
integral parts of any ultrasound system.
Doppler processing can be accelerated by
use of the dedicated FFT/DFT units in the
Maple hardware coprocessor to achieve
greater throughput and better utilization
of the device’s resources. MSC815x and
MSC825x DSP families are also ideal for
Beyond DSPs, November 2010
Application Solutions
Digital X-Ray Scanner
Digital X-Ray
Digital X-ray imaging uses digital sensors
Power
Management
instead of traditional photographic film.
A common X-ray system is composed
of an analog front end where the actual
X-ray is performed and transmitted to a
X-Ray
Emissor
Photo
Transimp
Detector Grid
Amp
digital image processing unit for image
ADC
reconstruction, processing and display
DSP/DSC
Capacitive
Sensing
and
Touch Screen
Display
generation.
SPI/SCI
The signal processing and conditioning
used to generate radiography involves
the transformation of signals from the
spatial domain to frequency domain by
USB
use of Fourier Transform, performing
MUX
MCU/MPU
convolutions on the transformed data and
inverse transform back to spatial domain.
The MSC815x family of devices with
Freescale Technology
Optional
the MAPLE coprocessor containing the
dedicated DFT/FFT hardware accelerators
is ideal for implementing these functions
and other image processing techniques
used in X-ray applications.
MAPLE Coprocessor DFT/FFT Performance
Standard Compliance
FFT sizes: 128, 256, 512, 1024, 2048 points
DFT sizes: Variable-length DFT/IDFT
processing of 2k·3m·5n·12, up to 1536 points
freescale.com/DSP
Data Rates
Comments
FFFT 2048: Up to 280 Mega samples/sec
Advanced scaling options
FFT 1024: Up to 350 Mega samples/sec
Guard bands insertion in iFFT
DFT: Up to 175 Mega samples/sec
Next-Generation Digital Signal Processors 25
Application Solutions
Aerospace and Defense
Mission-Critical Applications
MSC8156 and P2020 Hardware Block Diagram
MSC815x and MSC825x DSPs provide
a number of features critical to the
including high processing performance,
SRIO
FPGA
aerospace and defense industries,
MSC8156
SRIO
P2020
IP/TDM
Many mission critical devices have an
MSC825x family members have both
inherent need for fast capture of data
PCI Express 1.0 and multiple four lane
and processors with high processing
Serial RapidIO interfaces in order to
longevity*.
performance as well as high throughput.
create the fastest possible throughput
Mission critical applications also use a
between FPGA, QorIQ communications
A key need for aerospace and defense
large number of FFT/DFT calculations.
processors or other DSPs. Freescale
customers is test time and costs. With
The high performance of the MSC815x
provides multiple development platforms
the scalability allowed by the MSC815x
and MSC825x families of DSPs, ranging
with MSC8156 to FPGA (MSC8156ADS)
and MSC825x families, customers can
from 1 GHz single-core DSPs up to 6 GHz
or MSC8156 to QorIQ (MSC8156 and
use the single-core MSC8251 for one
multicore DSPs with FFT/DFT/Virterbi
P2020 AdvancedMC™ reference design)
program and the MSC8256 six-core
and Turbo coprocessor blocks, combined
with freely available schematics, gerber
DSP for different projects using the
with a 500 MHz switching fabric, make
and orchard files to accelerate board
same hardware enabled by the pin-for-
them a perfect solution for a number of
development. A small front-end bridge
pin compatibility of our MSC825x and
mission critical needs. In a large portion
is required in case of a CPRI/OBSAI
MSC815x families, reducing the need for
of mission critical applications, high-
backplane.
full retest or verification.
performance DSPs connect to FPGAs
high throughput I/Os, flexible
programmable architecture, extended
temperatures and 10+ years of product
or to QorIQ devices. All MSC815x and
Software Defined Radio
Software Defined Radio
Software defined radio (SDR) systems
decade in order to overcome wireless
communication interoperability issues.
SDR is now necessary for emergency/
with a strong pull from consumer
segments. The common requirements
of this application space include pure
DDR2/DDR3
public safety and military communications
DDR2/DDR3
have become prevalent in the last
MSC8156
DDR
sRIO 4x
sRIO 4x
GbE
sRIO
switch
Tsi 568A
4x
MSC8572
Back Plane
GbE
GbE
PHY
PHY
GbE
GbE
sRIO
DDR
LB
MSC8156
DDR
sRIO 4x
sRIO 4x
GbE
Port0
Port1
Flash
DDR2/DDR3
programmable processing performance
and multitasking. The MSC815x math
capability allows it to handle various
modem processing functions, including
filtering, modulation, demodulation, error
correction encoding and decoding as
well as a minimum product lifetime of 10
years*. The MSC815x is complimented by
the MPC8572 communications
RF
sRIO-CPRI
Bridge
4x
processor, built on Power Architecture
technology, which is an optimized
networking processor that allows high
communications throughput and reliability
in a wireless radio communication
product.
Key Features
• Downlink: Four Tx antennas,
beamforming, 100 Mbps max per sector
• Uplink: Eight Rx antennas, 14 Mbps
max per sector
• Serial RapidIO switch for full
connectivity between devices, with
*Products may be supported by Freescale’s Product
Longevity Program. For Terms and Conditions and to
obtain a list of available products, visit
freescale.com/productlongevity.
26 Next-Generation Digital Signal Processors
option to remove Serial RapidIO switch
using pass-through feature (TBV)
Beyond DSPs, November 2010
Application Solutions
Radar/Sonar
Radar/Sonar Block Diagram
The MSC8156 DSP is ideally suited
for radar, sonar or infrared as a standalone system or as an integrated part
RF
Generator
(Exciter)
Power Amplifier
Waveform
Generator
Doppler Test Signal
Circulator
Dual
Directional
Coupler
Antenna
Driver
MRF6VXXX
of a military or aerospace end product.
With 6 GHz of processing power, full
Receiver
ECC memory protection and a 10+ year
product life cycle*, the MSC8156 DSP
is an ideal choice for high-performance
radar, sonar or infrared solutions. With
Signal
Processor
MSC8156
Timing and
Control
many application processing requirements
Data/Control
Processor
relying heavily on FFT/DFT/FIR
algorithms, the MAPLE-B coprocessor
with a hardware accelerated FFT/ DFT
and Turbo/Virterbi coprocessing allow
Status Information
Timing and
Control
Power
Arch
Communications
Interface
Prime Power
customers to call the required functions
via predefined APIs.
*Products may be supported by Freescale’s Product
Longevity Program. For Terms and Conditions and to
obtain a list of available products, visit
freescale.com/productlongevity.
freescale.com/DSP
Next-Generation Digital Signal Processors 27
Application Solutions
Advanced Test and Measurement
Testing is a necessary requirement for
Freescale’s MSC815x and MSc825x
Freescale’s latest generation of DSP
manufacturers of consumer and industrial
families of devices are particularly well
processors helps to solve these
electronic equipment. Irrespective of
suited to many of these sub-segments.
challenges by offering a total of eight
the market segment, products must be
Boasting not only the highest performing
lanes of SerDes high-speed interconnect
tested before being shipped to the end
fixed-point DSP core on the market,
designed to support un-paralleled
customer. There are certain sub segments
but also a rich array of high-speed
bandwidth and low latency data exchange
within the overall test and measurement
interconnect and memory interfaces.
with the following interface combinations:
market where the use of advanced digital
Furthermore, the MSC815x family of
• Two 1x/4x Serial RapidIO ports
signal processing is prevalent. The three
DSPs is backed by MAPLE-B technology,
sub segments and applications are as
which accelerates common algorithms
• One 1x/4x Serial RapidIO ports, one
follows:
found on DSPs targeted at many of the
• Communications test equipment
applications listed at left. One of the
Wireless testers (WiMAX, Wi-Fi,
WCDMA, 4G-LTE)
Wireline testers (packet switched and
circuit switched)
• Automated/semiconductor test
equipment
Digital/analog testers
common challenges of DSPs, generally
in test and measurement, and wireless
test and measurement in particular, is
the availability and use of high-speed
1x Serial RapidIO port and two SGMII
ports
• One 1x/4x Serial RapidIO port and a
PCI Express port
• One 1x/4x Serial RapidIO port, two
SGMII ports and a PCI Express port
peripheral interfaces that allow high
Freescale complements this interconnect
amounts of data to be stored and
with two 64-bit, 800 MHz data rate, DDR-
processed in real time.
III interfaces.
• General purpose test
Signal generators and analyzers
28 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Application Solutions
Wireless Handset Test
Equipment
Wireless Handset Test Equipment
The following system diagrams show
examples of a DSP-based wireless
handset test and measurement system.
DDR
DDR
DDR3
DDR3
(optional)
SRIO x4
The system demonstrates a standard
Flash
Antenna/Radio
Interface
PCIe x4
Digital Radio
Interface
(AID, DIA,
DDC, DUC)
SRIO x4
I2C
Flash
may be used to perform physical layer
formatting between the layer 1 processing
functions performed on the MSC8156,
MSC8156
FPGA
DDR3
SRIO x4
DDR3
(optional)
DDR
DDR
Gigabit
Ethernet
PCIe x4
Host
Interface
Optional
SRIO x4
Oversampled data is down converted
from and to the radio card. An FPGA
SRIO x4
SRIO x4
I2C
the radio and antenna interfaces.
(decimated) or upsampled (interpolated)
Layer 2 Control
QorIQ Host
MSC8156
(optional)
baseband system where modulated
radio data is sent and received from
Layer
Signal
Processing
SRIO x4
Antenna
Signal
Condition/
Formatting
or multiple MSC8156s, and the radio
card. Processing is subsequently split
into layer 1 (MIMO support, downlink and
PCI-Based Single DSP Test System
uplink physical and transport channel
access, radio link control and packet
PCIe x4
data convergence) typically performed
on a host processor such as Freescale’s
QorIQ P4040 or P4080 communications
Signal
Processing/Conditioning
(DDC/DUC etc.)
Host
Interface
processing) and layer 2 processing (media
Signal
Processing
SRIO x4
IC
DDR3
(optional)
DDR
DDR
Analog I/F,
Sensors,
ADC/DAC
FPGA/PLD
(optional)
2
DDR3
Line I/F
SRIO x4
MSC815x
processors.
Signal
Acquisition
Detector
Sensor
Flash
Modular Test Platform
Single Board
Computer
DDR
DDR
Flash
Network Interface
Card
QorIQ
Host
Processor
PCIE x4
RGMII
DDR
DDR
Network
Processor
Flash
PCIE x4
RGMII
PCIe
RJ45
RJ45
Switched PCIe
Backplane
PCIe
PCIe
PCIe
Signal
Acquisition
PCIe
x4
freescale.com/DSP
sRIO
x4
sRIO
x4
sRIO
x4
sRIO
x4
PCIe
Line I/F
FPGA/
PLD
Detector
MSC8156
MSC8156
MSC8156
I2C
I2C
I2C
DDR
DDR
DDR
DDR
Flash
DDR
DDR
DDR
DDR
Flash
DDR
DDR
DDR
DDR
Sensor
Flash
Next-Generation Digital Signal Processors 29
Application Solutions
Development Software,
Tools and Reference
Designs
30 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
StarCore MSC8xxx Development Tools
CodeWarrior Development Studio
for StarCore 10.0 DSPs
Software Analysis, Profiling
and Trace
Compiler
With an extensive array of tools,
provides developers with choices in
developers save time by quickly
developing high-performance code. For
identifying and resolving functional and
developers who do not want to spend
performance issues. CodeWarrior IDE
time hand-tuning their applications for
for StarCore DSPs has a sophisticated
the maximum possible performance,
Debugging Tools
profiler that helps the developer pinpoint
CodeWarrior’s compiler has aggressive
cache performance or stall problems as
optimization options that do the job.
Debugging multicore architectures can
well as show how ALUs and AGUs are
Developers who want to obtain the
be a challenging task. CodeWarrior IDE
being utilized. The trace analyzer provides
maximum performance possible can
includes a wide range of debugging
a view of the sequence of instruction
choose from a wide selection of intrinsic
tools simplifying the task of multicore
execution that led the processor to be in
functions that implement common tasks
embedded programming. CodeWarrior’s
a problem state. Through trace points,
in a way that most efficiently utilizes the
multicore debugging features such as
the developer can pinpoint the precise
architecture. The documentation provided
core grouping and multicore run control
segments of code that are of interest.
with the tools includes descriptions of
make this task much easier. The MMU
Sometimes user applications corrupt
how and when to use different intrinsic
configurator provides a way to debug
system register values. The register
functions, and examples that illustrate
RTOS virtual memory management
analyzer can quickly identify unexpected
their use.
problems by allowing the developer
hardware states and alert the programmer
to see and experiment with and even
to a problem.
CodeWarrior Development Studio is an
Eclipse-based, completely integrated
development environment (IDE) that
provides a highly visual and automated
framework to accelerate the development
of the most complex embedded
applications.
generate code for different MMU settings.
The on-chip emulation (OCE) configurator
provides an easy way for developers to
monitor for different types of accesses to
critical areas of memory.
CodeWarrior’s optimizing compiler
SmartDSP OS RTOS (SDOS)
SDOS is Freescale’s optimized multicore
StarCore OS. It offers highly efficient
program execution with extensive
functionality, including an integrated
network stack, a compact and lightweight
kernel with real-time, priority-based, preemptable execution. It is offered royalty
free to Freescale customers and offers
packaged drivers along with kernel and
driver source code.
freescale.com/DSP
Next-Generation Digital Signal Processors 31
StarCore MSC8xxx Development Tools
Voice Software
Freescale and certain key partners offer
Voice Codecs
an extensive range of voice-related
Low Complexity: Narrow/Wide Band
G711
G.729 B
PLC
G722.1 ( C )
G.726 ( A )
Mid Complexity: Narrow/Wide Band
G.723.1A
GSM-HR (raw bitstream output)
G.729 ( I )
GSM-EFR
iLBC
High Complexity: Narrow/Wide Band
G.728
EVRC-A
G722.2 (AMR-WB)
High Complexity: Wide Band
AAC-LC/LD
AAC-HE
software technologies for license in
source code or binary code format. Our
voice software portfolio covers many
standardized ITU-T, IETF and 3GPP
voice and voice-related technologies.
In addition, Freescale has a number of
patented technologies for advanced voice
applications like wide band conferencing,
sample rate conversion, automatic
level control and narrow band line echo
cancellation.
AMR-NB
G722 with Annex IV
EVRC-B
EVRC-WB
Voice Enhancement Devices
Low Complexity
ALC-WB
Whatever your voice application, whether
circuit-switched, packet-switched, TDM
or IP-based, narrow band, wide band or
extended wide band, Freescale and our
third-party network are likely to have the
technology you need.
All software is covered by complete
documentation explaining the memory,
performance requirements and integration
of the respective technologies.
GSM-FR
VADCNG
NR
Sample Rate Convertor
N-Way Conferencing
Voice Activity Det (VAD)
Stand Alone
Mid Complexity
G.168
FAX/Modem
Caller ID (depends on v.23
pump)
T.38
V.21/V.27/V.29/V.17
(as part of T.38 package)
V.23
V.32/V.32bis
Please contact your Freescale sales
representative or our third-party providers
for further information on licensing and
commercial terms and conditions.
Video Software
Freescale offers a wide variety of video
cost-effective programmable system
codecs necessary for implementing
solutions required for winning in today’s
today’s leading media communication
competitive market place.
systems, such as videoconferencing and
media gateways. All codecs are optimized
for high quality and maximum efficiency
running on the StarCore-based MSC815x
and MSC825x high-performance DSPs.
Codecs are available in binary form for
quick download and evaluation or can be
Video Codecs
Codec
H.264/SVC
Freescale’s video codec offering includes
H.264BP
the first fully featured implementation of
H.263p3
HD H.264/scalable video coding (SVC)
standard, allowing single encode to
multiple targets and overcoming network
reliability issues.
licensed in source form open to customer
Detailed codec information and quick
edits. Freescale’s flexible software codecs
downloads can be found at
running on high-performance single- and
freescale.com/DSP.
MPEG-4SP
H.261
MPEG-2
MJPEG
JPEG2000
H.264MP/HP
multicore DSP devices enable scalable,
32 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
StarCore MSC8xxx Development Tools
Base Station Software
LTE Layer 1 Software
Real-Time Software Subsystem Features
The LTE Layer 1 software includes
Category
Specifications/Features
physical baseband channel processing
Design
approach
• Layered API software approach enables multi-level reuse and ease of integration
• Modular C software modules for all subsystems. Includes C wrapper for optimized realtime assembly modules
• Algorithm verification with floating- and fixed-point simulation system
• Multicore framework allows for efficient inter-core communication and task partitioning
Features
• Focus on high-speed shared user physical channels
Physical Downlink Shared Channel (PDSCH) (36.211 chapter 5.3)
Physical Uplink Shared Channel (PUSCH) (36.211 chapter 6.3)
Random Access Channel (RACH)
• Modular design with well-defined interfaces and module interactions
Downlink
·· IF1Tx: L1/L2 logical interface. Memory mapped over Serial RapidIO
·· IF2Tx: Transport to physical channel interface per 3GPP 36.211 and 36.212
·· IF3Tx: Transport to OFDMA processing interface. Re-maps IFFT signal
generation onto FPGA
·· IF4Tx: Baseband I/Q sample interface towards the antenna FPGA
Message-based configuration and runtime control
Includes MIMO processing
• Modulation
RTOS
support
• SmartDSP OS: Integrates real-time kernels and drivers
• Channel coding
API
• Full software abstraction through well-defined and documented APIs
SBL1 API structure for reuse on function level
Framework API for reuse of higher level, complete processing chains
Complete subsystem reuse possible for channel types
Validation/
test
• Software tested on:
Unit level (individual modules)
Integration level (module interaction)
System level (system operation, performance)
• Software test environment is part of the software delivery package
Standards
reference
[1] 3GPP TS 36.201: LTE physical layer general description (v1.0.0)
[2] 3GPP TS 36.211: Physical channels and modulation (v1.0.0)
[3] 3GPP TS 36.212: Multiplexing and channel coding (v1.3.2)
[4] 3GPP TS 36.213: Physical layer procedures (v1.0.0)
[5] 3GPP TS 36.214: Physical layer measurements (v0.1.0)
[6] 3GPP TS 36.300: E-UTRA and E-UTRAN overall description; Stage 2 (v8.0.0)
[7] 3GPP TS 25.212: UTRA multiplexing and channel coding
Layer 1
software
packages
• Signal processing library: Contains LTE Layer 1 signal processing manager and kernel
library functions. The signal processing kernels are the basic processing units and the
signal processing manager is the chain integration of a set of kernels which includes:
DL Transport Channel Package
DL Physical Channel Package
UL Transport Channel Package
UL Physical Channel Package
• Functional integration of uplink/downlink chains (PDSCH/PUSCH) on
multicore MSC8156
Uses SmartDSP OS real-time operation
and radio transport channel functions as
defined in the 3GPP standards. Freescale
provides a comprehensive set of kernel
modules covering the Layer 1 processing
for physical downlink shared channel
and physical uplink shared channels.
The kernels are further combined into
uplink and downlink chains, which run
in real time using the SmartDSP realtime operating system as a reference. All
software is developed as ANSI-C callable
and fully documented.
In brief, the physical layer processing
functions include:
• Transmission schemes
• Multiplexing
• MIMO/diversity
• Channel estimation
• Equalization (outside 3GPP scope)
WCDMA Layer 1 Software
The WCDMA Layer 1 software covers
uplink and downlink symbol rate
processing as defined in the 3GPP
standards. Freescale provides a
comprehensive, fully documented set of
kernels developed in C and ASM.
freescale.com/DSP
Next-Generation Digital Signal Processors 33
StarCore MSC8xxx Development Tools
Base Station Software
WCDMA Code
Channel
Function
DL Symbol Rate R99
DL Symbol Rate HSDPA
UL Symbol Rate R99
CRC Generation
Convolutional Coding Rate 2
Coding Rate 3 Turbo Table Generation
Turbo Coding
Turbo Puncturing
Convolutional Puncturing
Repeat
Interleaver 1
Interleaver 2
Full R99 SR DL Integrated Chain
Byte Pack
CRC Attachment
Bit Scrambling
Block Segmentation
Byte Unpack
Channel (Turbo) Coding
TurboIL
HARQ Manager
RM1
RM2 - Systematic
RM2 - P1, P2
Bit Collection
Physical Channel Seg
Interleaving
MAPLE DEPE Basic Driver
Crc Check
Channel Decoding
Rate De-Matching
First Deinterleaving
Second Deinterleaving
Channel Demapping
Full R99 SR UL Chain
Source Code
C
C
C
C
C
C
C
C
C
C
C+ASM
C+ASM
C
C+ASM
C+ASM
C+ASM
C
C+ASM
C+ASM
C+ASM
C+ASM
C+ASM
C+ASM
C+ASM
C
C
C+ASM
C+ASM
C+ASM
C+ASM
C+ASM
C+ASM
C+ASM
LTE Code
Channel Manager
TBP
DL-SCH
CBP
RBP
PDSCH
TBP
UL-SCH
CBP
DCdemux
VRB
PRB
PUSCH
RSP
NA
PRACH
PUCCH
SRS
FDP
DPP
Kernel
TB CRC Gen
CodeBlockSegmentation
CB CRC Gen
Turbo Encoder
RateMatching
BitScrambling
ModMapping
LayerMapping
Precoding
PRBMapping
TB CRC Detect
CodeBlockDesegmentation
HARQ Combining
CodeBlockDeconcatenation
Dcdemux
Channel Deinterleaving
Demodmapping
Descrambling
SNR2x2
Equalizer2x2
SNR2x4
Equalizer 2x4
Equalizer 2x4int
CE2Tx
CE1Tx
RMDecoding
sc_sel
cor_0p
Downlink Integartion
Uplink Integartion
DP_compute
DP_analyze
TBD
TBD
TBD
Real-Time Scheduling
Real-Time Scheduling
Guard Insertion
Guard Removal
iFFT/FFT
Cyclic Prefix
Insertion/Removal of the Guard Carries
Removal of the Guard Carries
Time <---> Freq Conv
Insert and Remove Cyclic Prefix
format 1
format2
34 Next-Generation Digital Signal Processors
Functions
Transport Block Processing
Transport Block CRC Generation
Code Block Segmentation
Code Block Processing
Code Block CRC Generatation
Turbo Encoding
Rate Matching
Resource Block Processing
Scrambling
Modulation Mapping
Layer Mapping
Precoding
Physical Resource Block Mapping
Transport Block Processing
Transport Block CRC Detection
Code Block Desegmentation
Code Block Processing
Hybrid Automatic Repeat Request Combing
Data and Contral Demultiplexing
Code Block Deconcatenation
Data and Contral Demultiplexing
Channel Deinterleaving
Virtual Resource Block Processing
Demodulation Mapping
Bit Descrambling
Physical Resource Block Processing
2x2 SNR Estimation
2X2 Equalizer
2x4 SNR Estimation
2x4 Equalizer
2x4 Interpolation Equalizer
Reference Signal Processing
Channel Estimation MIMO
Channel Estimation for SISO
Reed Muller Decoding
Frequency Domain Processing
RACH Subcarrier Selection
Correlation and Zero Padding
Delay Profile Processing
Delay Profile Computation
Delay Profile Analyze
PUCCH Format 1 Demodulation
PUCCH Format 2 Demodulation
SRS Metric Calculations
1. Real-Time Integration for the DLSCH and the PDSCH
1. Real-Time Integration for the ULSCH and the PUSCH
2. Support for Turbo Decoding Using MAPLE TVPE
3. Support for FFT Using MAPLE FFTPE
4. Support for DFT Using MAPLE DFTPE
MAPLE FFT for the Guard Insertion
System DMA for Guard Removal
MAPLE FFTPE for iFFT and FFT Operation
System DMA to Manage CP Insert and Remove
Source Code
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Available 1Q11
Available 1Q11
C
C
C
C
C
C
C
C
C
Beyond DSPs, November 2010
StarCore MSC8xxx Development Tools
MSC8156 Evaluation Module
For evaluation of the MSC815x or MSC825x
family of StarCore DSPs
Overview
The MSC8156 evaluation module
MSC8156EVM Block Diagram
PCIe
Reference
Clock
(MSC8156EVM) is a cost-effective ($459
USD MSRP) tool intended for engineers
evaluating the MSC815x and MSC825x
family of Freescale DSPs. The MSC815x
Diff. Clock
Generator
and MSC825x family of DSPs are
highly integrated DSP processors that
contain one, two, four or six StarCore
100 MHz
CLKIN
CLK Mux
REFCLK
RGMII1
Test Point,
Switches,
LEDS
programmable DSP performance values
RGMII2
GPIO
with each DSP core running at 1 GHz.
UART
These devices target high-bandwidth,
such as 3GPP, TD-SCDMA, 3G-LTE
and WiMAX base station applications
as well as aerospace and defense,
USB
Type B
eUTAP
Mux
12V PCIe
RJ45
RGMII
Dual
PHY
RJ45
MSC8156
ranging from eight GMACs to 48 GMACs,
highly computational DSP applications,
x4
MII
PCIe
Reference
Clock
SC3850 cores. The family supports raw
(PCIe/
SRIO/
SGMII)
PCIe
Edge
Con
JTAG
I 2C
DDR-2
RS232
to USB
USB
Mini
Type B
De-Populated
I 2C
EEPROM
EONCE
Header
medical imaging, video, voice and test
1 GB DDR3-800
SODIMM
and measurement applications. The
Non-ECC
MSC8156EVM is intended to serve as a
12V PCIe
12V
DC Input
Power Supply
1.0V/1.2V/
1.8V/2.5V/3.3V
platform for evaluating the capabilities
of the MSC815X and MSC825x family
• PCI Express mode: With the
of DSPs. On-board resources and the
MSC8156EVM plugged into a PCI
associated CodeWarrior tools help to
Express connector as provided, for
enable a variety of tasks, including:
instance, on Freescale's QorIQ enabled
• Download and run code
COM single board computer (SBC)
• Set breakpoints
environment. The EVM allows testing
• Display memory and registers
The MSC8156EVM supports two working
configurations:
• Stand-alone mode: The MSC8156EVM
of PCI Express and Serial RapidIO
interconnects and is designed to
be compatible with a standard PCI
Express interconnect.
can run in stand-alone mode with
direct connections to a development
system for debug, power supply and
other external connections.
freescale.com/DSP
Next-Generation Digital Signal Processors 35
StarCore MSC8xxx Development Tools
Features
• Supports the MSC815x and MSC825x
DSPs at 1 GHz
• A single DDR controller (DDRC2)
configured in DDR3 mode: 204-pin
SODIMM, 64-bit at 800 Mbps, no ECC,
1 GB of memory
• The DSP RGMII (at ports GE1 and
GE2) connects to a Marvell 88E1121
dual GETH PHY for regular board
configuration
• Two available debug interfaces,
including on-board USB TAP controller
(eUTAP) or on-chip emulation 14-pin
header for any external TAP controller
• 100 MHz clock oscillator for the DSP
clock in
• The EVM can operate in two main
supply configurations (configurable via
switch S1)
Stand-alone mode with external 12V
DC
PCI Express mode powered from
edge connector
• Push buttons: Main power-on-reset
(SW8), hard reset (SW7), IRQ0 (SW5),
NMI (SW6)
Development Support
Freescale supplies CodeWarrior IDE,
• C and C++ compiler with in-line
assembly
a robust and full-featured set of DSP
• Librarian
development tools. The CodeWarrior
• Multicore debugger
tool suite is an Eclipse-based integrated
• Royalty-free RTOS
development environment supporting
• Software simulator
the evaluation of many of the features of
the Freescale MSC815x and MSC825x
family of single- and multicore DSPs.
With applications ranging from base
• Profiler
• High-speed run control
• Host platform support
stations to medical imaging, aerospace
Contact your local sales office or
to advanced test and measurement,
representative for availability.
the development environment gives
designers everything they need to
exploit the advanced capabilities of the
MSC815x and MSC825x architecture.
The CodeWarrior tool suite includes:
• An Eclipse-based integrated
development environment
36 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
StarCore MSC8xxx Development Tools
MSC8156ADS
Advanced development system for the
MSC815x and MSC825x product families
Overview
test and measurement applications. The
$3,900 MSC8156ADS is intended to serve
as a platform for software and hardware
development in processor environments
using the MSC815X and MSC825x family
of DSPs. On-board resources and the
associated debugger enable developers to
perform a variety of tasks, including:
The $3,900 MSC8156 application
development system (MSC8156ADS) is a
comprehensive debugging environment
intended for engineers developing
applications for the MSC8156, MSC8154,
MSC8256, MSC8254, MSC8252 and
MSC8251 Freescale DSPs. The MSC815x
and MSC825x family of DSPs are highly
integrated DSP processors that contain
one, two, four or six StarCore SC3850 DSP
subsystems ranging from eight GMACS to
48 GMACs with each DSP core running
up to 1 GHz. These devices target highbandwidth, highly computational DSP
applications, such as 3GPP, TD-SCDMA,
3G-LTE and WiMAX base station
applications as well as aerospace and
defense, medical imaging, video, voice and
application development systems, with direct connections to debuggers, power
supply and other external connections.
• AdvancedMC mode: The MSC8156ADS
is inserted in a standard MicroTCA
backplane that allows testing of the highspeed Serial RapidIO and PCI Express
ports against other platforms. By using
a proprietary B2B adaptor card, the
AMC-X-Over, the DSP can work with a
second DSP device on an additional ADS
board. The AMC edge connector carries
all high-speed interface signals between
the devices. The ADS is compatible with
standard MicroTCA chassis, such as
a Schroff® or TUNDRA® development
platform.
• Download and run code
• Set breakpoints
• Display memory and registers
• Connect proprietary hardware via an
expansion connector
The MSC8156ADS supports two working
configurations:
• Stand-alone mode: The MSC8156ADS
can run in a stand-alone mode like other
MSC8156 Application Development System
SODIMM DDR2-72 800M ECC
100 MHz
Diff. Clock
Generator
J1
2.5 V
J3
3.3 V
Level
Shifter
DDRC1
CLKin
Clock Synth.
PTMC
REF
CLK1,2
GPIO/
TMR
SC3850
StarCore-Based
DSP:
TDM0-3/
RGMII 1,2
MSC8156
Ports 4–7
Differential
Signal MUX
Rt
Port 8–11
Port 12–15
Level
2.5 V Shifter 3.3 V
E1/T1 Framer
I2C
RJ48
3V3MP
SPI
UART
JTAG
eUTAP
Port 0
2 x Gigabit Ethernet
Port 2
1
GE1, 2:SGMIIx2
SerDes1
SRIO/
SGMII
2.5 V
2-Digit Display
SGMII Switch
SerDes2
SRIO/
PCIe/
SGMII
TDM0-3
DB9
USB
AMC
External
Clock
MII
DDRC2
SODIMM DDR3-64 800M non-ECC
FPGA
2 x Gigabit Ethernet
RGMII
RGMII PHY-2
PHY-1
SGMII Switch
RJ45
RJ45
12V
2
EEPROM
Programmable PS
SPI Boot Flash
JTAG/OnCE 14-pin
Configuration Word
freescale.com/DSP
Boot
I2C EEPROM2 Big
I2C EEPROM2 Small
RCW and BOOT
1.0/1.2/1.5/1.8/2.5/3.3 V
Next-Generation Digital Signal Processors 37
StarCore MSC8xxx Development Tools
Features
• Supports the MSC815x and
MSC825x DSPs at 1 GHz with core
voltages of 1V
• The first DDR controller (DDRC1) is
configured in DDR2 mode: 200-pin
SOCDIMM with ECC support, 64-bit at
800 Mbps, 1 GB of memory
• The second DDR controller (DDRC2)
is configured in DDR3 mode: 204-pin
SODIMM, 64-bit at 800 Mbps, No
ECC, 1 GB of memory
• The DSP RGMII (at ports GE1 and
GE2) connects to two single Marvell®
88E1111 GETH PHYs for regular board
configuration
• A Marvell 10-port SGMII switch
88E6182 links the MSC8156 SGMII
lines to 2xRJ-45 copper connectors
and to the 1000 Base-X over AMC
MicroTCA connector ports 0 and 2
• Pericom® PI2DBS212ZHE Diff Signal
Switch parts support programmable
SerDes lines multiplexing to AMC edge
connector or to the SGMII switch
• Two Dallas E1/T1 framers connect to
four DSP TDM ports
• FPGA logic: Board control and status
register (BCSR), JTAG controller allows
full board programming, multiplexing
of JTAG source signals, I2C master
and slave controllers, MII controller to
program RGMII PHY, SPI controller,
boot sequencer configures ADS
peripherals for boot over Ethernet,
generation of TDM clock and sync,
two-digit, 14-segment LED display
provides current board settings
• 100 MHz clock oscillator for the DSP
clock in
• An external pulse generator may be
used as clock source
• Can function in various main supply
configurations (configurable via DIP
switches or BCSR) in stand-alone
mode with an external power 12 VDC
at 5A when S1 switch is on, or as an
AMC card in the MicroTCA system or
interconnection with AMC-X-Over card.
If the ADS is fed outside, the S1 power
switch should be off
• On-board power system is comprised
of two regulator steps:
Primary power system is a powerone power manager with 1.0V
Development Support
Freescale supplies a comprehensive
set of CodeWarrior DSP development
tools for the DSP device. The tools
provide easier and more robust ways
for designers to develop optimized DSP
systems. With applications ranging from
base stations to medical imaging to
aerospace and defense, the development
environment gives designers everything
they need to exploit the advanced
capabilities of the MSC815x and
MSC825x architecture. In addition to the
ADS board, support tools include:
• Eclipse-based integrated development
environment (IDE)
• P1 and P3 connectors carry DSP GPIO
and TDM signals
POL regulator for MSC8156 loads,
• C and C++ compiler with in-line
assembly
including cores, MAPLE and M3,
• The DSP configuration and boot
support includes reset configuration
source three-bit set by appropriate
DIP switches, parallel load of
programmable reset configuration
word from FPGA registers sampled
previously from DIP switch array, serial
configuration and boot from a large
(64 KB) or small (1 KB) I2C EEPROM,
boot from serial 8 MB SPI flash, boot
from communications ports (from
SerDes Serial RapidIO interface or from
Ethernet SGMII or RGMII ports)
2.5V for I/O and 3.3V for on-board
• Librarian
• Two available debug interfaces,
including on-board USB TAP controller
(eUTAP) or OnCE 14-pin header for any
external TAP controller
38 Next-Generation Digital Signal Processors
peripherals, DDR switching power
supplies for DDRC1 and DDRC2
ports, LDOs for on-board peripherals
are fed from 2.5V and 3.3V POLs
• Multicore debugger
• Royalty-free RTOS
• Software simulator
• Profiler
and 12V input voltage, voltage
• High-speed run control
supervisor monitors all the ADS
• Host platform support
power supplies. Power good (PG)
Contact your local sales office or
representative for availability.
signal and dedicated LED LD14
indicate power system status. Any
failures cause nPRST signal be
continuously low
Visit freescale.com/DSP
for more information.
Push buttons: Main power-on-reset
(SW8), hard reset (SW9), soft reset
(SW11), NMI (SW10)
Beyond DSPs, November 2010
StarCore MSC8xxx Development Tools
MSC8156AMC
Advanced mezzanine card system for the
MSC815x and MSC825x product families
Overview
The Freescale MSC8156AMC is a
infrastructure applications. Developed
and two DDR controllers for high-speed,
by Freescale and integrated on chip, the
industry-standard memory interface.
MAPLE-B supports hardware acceleration
high-density, single-width, full-height
This 18 GHz of processing power,
for Turbo and Viterbi channel decoding
AdvancedMC (AMC) DSP platform based
coupled with an architecture highly
and for discrete Fourier transforms (DFT),
around three MSC8156 DSPs. The
optimized for wireless infrastructure
inverse discrete Fourier transforms (iDFT)
MSC8156 is a six-core DSP based on
applications, make this an ideal platform
and fast Fourier transforms (FFT) and
Freescale’s SC3850 StarCore technology
for developing solutions for the next
inverse fast Fourier transforms (iFFT)
and designed to advance the capabilities
generation of wireless standards such as
algorithms. An internal RISC-based
of wireless broadband equipment. It
3G_LTE, WiMAX, HSDPA+ and TDD-LTE.
QUICC Engine subsystem supports
delivers industry-leading performance
and power savings, leveraging 45 nm
process technology in a highly integrated
SoC to provide performance equivalent
to 6 GHz of a single-core device.
multiple networking protocols to help to
The AMC has been designed around a
ensure reliable data transport over packet
mezzanine concept, with three MSC8156
networks while significantly offloading
mezzanines providing the system building
processing from the DSP cores.
blocks, enabling rapid prototyping
systems to be quickly realized.
The MSC8156 embeds large internal
The MSC8156 DSP delivers a high
memory and supports a variety of
level of performance and integration,
advanced, high-speed interface types,
combining six fully programmable
including two RapidIO interfaces, two
new and enhanced SC3850 DSP
Gigabit Ethernet interfaces for network
cores, each running at 1 GHz with an
communications, a PCI Express controller
architecture highly optimized for wireless
MSC8156 AdvancedMC™ Block Diagram
RJ45
RJ45
Mezzanine
DDR III
DDR III
Mezzanine
DDR III
DDR III
DDR
DDR
GigE
GigE
PCI/sRIO
sRIO
UART
I2C
Ethernet
Transceiver
Ethernet
RGMII Switch
MSC8156
4x
4x
Serial RapidIO/
PCI Express
MUX
Serial RapidIO
DDR
Serial RapidIO
Switch
DDR III
DDR III
Mini-USB
DDR
GigE
GigE
sRIO
sRIO
UART
I2C
Serial RapidIO
Port 0
Ethernet
Port 1
Ethernet
Port 4:7
Serial RapidIO/
PCI Express
Port 8:11
Serial RapidIO
Port 12:15
Serial RapidIO
Port 17:20
Serial RapidIO
I2C
IPMB-L
MSC8156
DDR
MUX
4x
4x
4x
GigE
GigE
sRIO
sRIO
UART
I2C
FPGA
Mezzanine
4x
Serial RapidIO®/PCI Express®
MSC8156
DDR
1000 Base-X
Board Control
Module
Management
Controller
4x
4x
EEPROM
UART
freescale.com/DSP
Next-Generation Digital Signal Processors 39
StarCore MSC8xxx Development Tools
Each MSC8156 has 1 GB of associated
64-bit-wide DDR3 memory split into two
banks. For data plane applications high
throughput 3.125 GHz x4 Serial RapidIO
links connect the three MSC8156 DSPs
to each other and to the data backplane.
The RapidIO interfaces are connected
via IDT’s high-bandwidth 10 port (x4)
CPS10Q Serial RapidIO switch.
Data and control plane applications are
handled by the Gigabit Ethernet interface.
Two 1000 Base-X Gigabit interfaces
MSC8156 DSP
Headers and Debug
connect the backplane to the DSPs via
• Six StarCore DSPs SC3850s operating
• DSP JTAG/EONCE
an Ethernet switch. Each DSP has two
at 1 GHz/8000 MMACS per core and
Gigabit RGMII interfaces connected to
48000 MMACS per device
the backplane via the Ethernet switch.
Two additional Gigabit Ethernet interfaces
are provided at the front panel for test
and control.
• MAPLE-B
MMC JTAG
MMC UART
• High-speed, high-bandwidth CLASS
provided by the Pigeon Point-based
cores and other CLASS members
module management controller.
to M2 memory, M3 memory,
• Three MSC8156 DSPs
Powerful and flexible with six
SC3850 StarCore cores at 1 GHz
and up to 48000 MMACS per device
MAPLE-B
Two banks of 512 MB 64-bit DDR3800 per MSC8156 processor
Connectivity
• Serial RapidIO infrastructure (x4 3.125
Module Management
Controller
DDR controllers, MAPLE-B and
• Hot swapping
configuration registers
• FRU storage
• 32-channel DMA
• Dual RISC core QUICC Engine
• Status LEDs
subsystem operating at 500 MHz
Application Areas
providing parallel processing
• 3G-LTE
independent of the DSP cores
• TDD-LTE
• 2x 512 MB of 64-bit DDR3-800
Board I/O
• WiMAX
• 3GPP-HSPA
• TD-SCDMA
• AMC connector
2x Gigabit Ethernet interfaces (Ports
0 and 1)
3.125 GHz (x4) Serial RapidIO ports
GHz) connecting DSPs and backplane
[4:7]
via Serial RapidIO switch
3.125 GHz (x4) Serial RapidIO ports
• Gigabit Ethernet infrastructure
FPGA JTAG
decoder
fabric arbitrates between the DSP
• Single-width, full-height AMC form
factor
access to:
Programmable Turbo and Viterbi
Board control and hot swapping are
Key Features
• Expansion connector provides
[8:11]
connecting DSPs and backplane via
3.125 GHz (x4) Serial RapidIO ports
Ethernet switch
[12:15]
3.125 GHz (x4) Serial RapidIO ports
[17:20]
• Front Panel
2x Gigabit Ethernet interfaces (RJ45)
Mini USB Type B for multiplexed
access to DSPs UARTS
40 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
StarCore MSC8xxx Development Tools
P2020—MSC8156 AdvancedMC™
Reference Design
Overview
The AMC has been designed around a
GHz. This 6 GHz of processing power,
The Freescale P2020-MSC8156
mezzanine concept, with a P2020 and
coupled with an architecture highly
AdvancedMC (AMC) reference design is
MSC8156 mezzanine card providing
optimized for wireless infrastructure
a multi-standard baseband development
the system building blocks to enable
applications, make this an ideal device
platform for the next generation of
rapid prototyping systems to be quickly
for developing solutions for the next
wireless standards such as LTE, WiMAX,
realized.
generation of wireless standards.
The P2020 processor offers an excellent
For data plane applications, the P2020
This single-width, full-height AMC
combination of protocol and interface
processor, MSC8156 DSP and backplane
platform integrates Freescale’s latest
support, including dual high-performance
are connected via high throughput 3.125
generation of multicore processors,
e500v2 processor cores built on Power
GHz x4 Serial RapidIO links using the IDT
the QorIQ P2020, with the industry’s
Architecture technology, DDR2 memory,
high bandwidth CPS10Q Serial RapidIO
most powerful DSP, the award-winning
three enhanced three-speed Ethernet
switch.
MSC8156.
controllers with RGMII support, a SerDes
WCDMA and TD-SCDMA.
interface with the option of PCI Express
This offers an unprecedented
or Serial RapidIO interface, eSDHC
combination of Power Architecture and
also handled by Gigabit Ethernet links.
These connect the P2020 and MSC8156
controller and a USB 2.0 interface.
StarCore technology as well as multi-
Data and control plane applications are
interfaces to the backplane Ethernet
ports and front panel RJ45s.
protocol acceleration engines in an AMC
The MSC8156 DSP delivers a high
form factor to provide a complete Layer
level of performance and integration,
1, 2 and 3 baseband processing platform.
combining six fully programmable,
Board control and hot swapping are
SC3850 DSP cores, each running at 1
provided by the Pigeon Point based
module management controller.
P2020-MSC8156 AdvancedMCTM Block Diagram
RJ45
RJ45/USB
Mezzanine
DDR II
P2020
DDR
SOCDIMM
Flash
GigE
GigE
PCI Express®/
Serial RapidIO®
Ethernet
Transceiver
Ethernet
RGMII Switch
Port 1
4x
PCI Express/
Serial RapidIO
MUX
Serial
RapidIO
Mezzanine
DDR III
DDR III
Mini-USB
4x
PCI Express/Serial RapidIO
Serial RapidIO
Switch
LB
MUX
Serial
RapidIO
eSDHC
4x
4x
USB
Port 17:20
DDR
Ethernet
Ethernet
PCI Express/
Serial RapidIO
Serial
RapidIO
Serial
RapidIO
Serial
RapidIO
IPMB-L
FPGA
MSC8156
DDR
Port 8:11
I2C
UART
I2C
GigE
GigE
sRIO
sRIO
UART
I2C
Port 4:7
Port 12:15
4x
GigE
Memory
Card
Port 0
1000 Base-X
Board Control
4x
Module
Management
Controller
4x
EEPROM
UART
freescale.com/DSP
Next-Generation Digital Signal Processors 41
StarCore MSC8xxx Development Tools
Key Features
• Single-width, full-height AMC form
factor
• QorIQ P2020 processor
Dual e500v2 cores at 1.2 GHz
1 GB of DDR2 (SOCDIMM)
TCP/IP acceleration
eSDHC
USB
• MSC8156 DSP
Six SC3850 cores built on StarCore
technology at 1 GHz each
MSC8156 DSP
Board I/O
• Six SC3850 cores built on StarCore
• AMC connector
MAPLE-B
technology, operating at 1 GHz/8000
3.125 GHz (x4) Serial RapidIO or
Two banks of 512 MB 64-bit
MMACS per core and 48000 MMACS
2.5 GHz PCI Express ports [4:7]
DDR3-800
Connectivity
• Serial RapidIO infrastructure (x4 3.125
per device
• MAPLE-B
• Programmable Turbo and Viterbi
decoder
GHz) connecting processor, DSP and
• High-speed, high-bandwidth CLASS
backplane via Serial RapidIO switch
fabric arbitrates between the DSP
• Gigabit Ethernet infrastructure
cores and other CLASS members
connecting processor, DSP, backplane
to M2 memory, M3 memory,
and front panel via Ethernet switch
DDR controllers, MAPLE-B and
• Module management controller
Hot swapping
Board control
QorIQ P2020 Processor
• Dual high-performance e500v2 cores
built on Power Architecture technology
• 512 KB L2 cache
• Three RGMII interfaces
TCP/IP acceleration
• High-speed SerDes interface (options)
One x4 3.125 GHz Serial RapidIO
configuration registers
• Dual RISC core QUICC Engine
subsystem operating at 500 MHz,
3.125 GHz (x4) Serial RapidIO ports
[8:11]
3.125 GHz (x4) Serial RapidIO
ports [12:15]
3.125 GHz (x4) Serial RapidIO
ports [17:20]
2x Gigabit Ethernet Interfaces
(Ports 0 and1)
Front Panel
• 2x Gigabit Ethernet Interfaces (RJ45)
providing parallel processing
• Mini USB Type B for UART access
independent of the DSP cores
• USB Type B connector
• 2x 512 MB 64-bit DDR3-800
Application Areas
• 3G-LTE
• TDD-LTE
• WiMAX
• 3GPP-HSPA
• TD-SCDMA
One x4 2.5 GHz PCI Express
One x1 2.5 GHz PCI Express and
one x1 2.5 GHz Serial RapidIO
• USB interface (USB 2.0)
• Enhanced secure digital host controller
(SD/MMC)
• 1 GB 72-bit DDR2-1600 SOCDIMM
42 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
DSP56K Family
Technical Highlights
A closer look at the DSP56K families
(Including Symphony)
freescale.com/DSP
Next-Generation Digital Signal Processors 43
DSP56K Family
DSP56K Family Overview
The DSP56K family is based on the 24-bit
embedded market. The Symphony
The 24-bit Symphony DSPs consists
56300 Onyx core and is used in a vast
family of audio software enabled DPS
of single- and dual-core single MAC
array of different applications ranging
are targeted at the audio market and are
instruction architecture and are targeted
from guitar effects processors and audio
labeled in green.
at audio applications, including stereo
mixing boards to industrial controllers
The 24-bit general purpose processing
and complex networking systems. The
family consists of a single MAC instruction
family includes a multitude of memory,
architecture running up to 275 MHz with
peripheral and operating speed options
an enhanced filter coprocessor for math
ranging from single-core 150 MHz devices
intensive (FFT and DFT) acceleration
to 250 MHz dual-core devices.
and peripherals targeted at mixed signal
The family has a set of fully programmable
processing connectivity with SPI, HPI and
processors (highlighted in white in the
chip memory features.
headphones, guitar effects processors
and echo cancellation headsets. These
Symphony DSPs include multiple audio
software codecs in the ROM, including
fully certified Dolby Digital®, Pro Logic®
IIx, WMA and multiple other audio
software codecs. All available audio
codes are listed on the next page. They
also include key audio peripherals, such
roadmap below) targeted at the general
as SPDIF and audio serial ports.
DSP56K Roadmap
Dual Core
DSPA56720
• 2x 200 MIPS
• 248 kW RAM
• SPDIF/ASRC
• Ext Bus
• Dolby TrueHD,
DTS-MA, Dolby
Volume, PLIIz
DSPA56721
• 2x 200 MIPS
• 248 kW RAM
• SPDIF/ASRC
• Dolby Digital +,
DTS, PLIIz
DSPB56720
DSPB56721
• 2x 200 MIPS
• 248 kW RAM
• SPDIF/ASRC
• Ext Bus
• 144 LQFP
• 2x 250 MIPS
• 248 kW RAM
• SPDIF/ASRC
• Ext Bus
• 144/80 LQFP
Performance
Optimized
DSPB56724
DSPB56725
• 2x 250 MIPS
• 112 kW RAM
• SPDIF/ASRC
• Ext Bus
• 144 LQFP
• 2x 250 MIPS
• 112 kW RAM
• SPDIF/ASRC
• 80 LQFP
DSP56321
• 275 MIPS
• 192 kW RAM
• 196 MAPBGA
DSP56311
• 150 MIPS
• 128 kW RAM
• 196 MAPBGA
Cost
Optimized
DSPD56374
• 150 MIPS
• 18 kW RAM
• Dolby Digital,
PLIIx, Dolby
Headphone
• 80/52 LQFP
DSPC56371
DSPD56371
• 150–180 MIPS
• 88 kW RAM
• Dolby Digital,
DTS, AAC, WMA
• 80 LQFP
• 150–180 MIPS
• 88 kW RAM
• Dolby Digital,
DTS, Dolby
Headphone
• 80 LQFP
DSPB56371
DSPB56374
• 150–180 MIPS
• 88 kW RAM
• 80 LQFP
• 150 MIPS
• 18 kW RAM
• 80/52 LQFP
Including audio software in the ROM (Symphony)
General purpose processor
1
1
1
1
1
1
1
1
2
2
1
1
2
2
2
2
44 Next-Generation Digital Signal Processors
2
2
4
4
4
4
√
√
√
√
√
√
√
External
Memory
18 kW RAM
√
√
√
√
√
√
88 kW RAM
112 kW RAM
128 kW RAM
√
192 kW RAM
√
√
248 kW RAM
52LQFP
144LQFP
MAPBGA196
ESSI
ESAI
SCI
1
1
80LQFP
1
1
1
SHI
EFCOP
1
1
1
1
2
2
2
2
ASRC
Cores
56374
56371
56311
56321
56724
56725
56720
56721
SPDIF Rx/Tx
Product
Name
DSP56K Features
√
√
√
√
√
√
Beyond DSPs, November 2010
DSP56K Family
DSP56K Core
The DSP56K family uses a programmable
fixed point 24-bit 56300 core, which is a
high-performance, single clock cycle per
instruction computing engine optimized
for DSP audio processing functionality.
With the available double precision
mode, 48-bit processing is possible with
two 56-bit accumulators available to
allow for arithmetic overflow. The 5672x
devices enhance the family even further
by providing a second 56300 core which
doubles the MIPS available but at a highly
Audio Decoders Available in
Select Symphony ROMs
PCM
Multi-Channel PCM
Dolby Digital (2+5.1ch) *
Dolby Digital Extended Precision *
Dolby Digital Plus *
Dolby Consumer Encoder *
Dolby TrueHD *
DTS *
DTS-ES (Discrete/Matrix) *
DTS 96/24 *
DTS-HD (Master Audio and High
Resolution) *
MPEG-2 (5.1-ch.) *
MPEG-2 AAC (5.1-ch.) *
WMA Pro *
*Dolby or DTS license required
competitive price. Highly efficient coding
is possible via the use of the dual-core
architecture coupled with eight channel
DMAs on each core to result in one of the
most cost-efficient, highest performing
audio processing solutions on the market.
The highly configurable memory switching
options add to the flexibility of the devices
and the addition of on-board audio
peripherals, such as the S/PDIF receiver/
transmitter and asynchronous sample rate
convertor (S/PDIF and ASRC on 5672x
family only), allow for a highly integrated
• Six- or eight-channel DMA controller
• Reduced power dissipation
Very low power CMOS design
Wait and Stop low-power standby
modes
Fully-static logic
Asynchronous Sample Rate
Converter (ASRC)
• Highly parallel instruction set
The ASRC allows audio sample rate
conversion between sources with
independent clock domains. For example,
a source with an 8 kHz sample rate along
with a source with a 44.1 kHz sample rate
could be input to the ASRC and output
at a fixed sample rate of 48 kHz. It also
allows for upsampling conversion or
downsampling conversion with a range of
1/24 to eight (sampling frequency input to
output). Up to 10 channels of conversion
• Data arithmetic logic unit (Data ALU)
can occur with a maximum of three
audio system with minimal bill of
materials cost.
Key Elements of the 56300
Core
• 1 MIPS per MHz of operating speed
• Address generation unit (AGU)
sampling rates at a time.
• Program control unit (PCU)
• Phase locked loop (PLL)
• Hardware debugging support (JTAG
TAP, OnCE module and address
trace mode)
Software Architecture Post Process Phases
Freescale Developed PPPs
Freescale Developed PPPs
Third-Party Developed PPPs*
Bass Manager
Bass Boost
Fade/Balance
Compression
De-Emphasis
DC-Cut
Delay Manager
Dynamic Range Compression
Karaoke
Level Meter
Loudness
Noise Generator
Reverb
Soundfield/Concert Hall Effect
Speaker Compensation
Volume Manager
Parametric EQ
Graphic EQ
Pause Detection
Spectrum Analyzer
Tone Control
Prescaler
Beep
Chime
Dolby Headphone
Dolby Virtual Speaker
Dolby Pro Logic IIx/Pro Logic IIz
DTS Neo6
DTS-ES (matrix)
Microsoft HDCD
Neural Surround
SRS TruSurroundXT
SRS Circle Surround
SRS Circle Surround II
Waves MaxxBass
QSurround
Dolby Volume
Dolby Auto Entertainment
Gain Manager
*Dolby, DTS or other license required
freescale.com/DSP
Next-Generation Digital Signal Processors 45
DSP56K Family
SPDIF Receiver/Transmitter
Enhanced Serial Audio
Serial Host Interface (SHI)
Interface (ESAI) and
and Serial Communication
Enhanced Synchronous Serial Interface (SCI)
Interface (ESSI)
The SHI is a serial I/O interface that
The Sony/Philips Digital Interface
(SPDIF) RX/TX is an easy way to get
stereo or multi-channel into or out of the
DSP without the need for an external
transceiver chip. It allows the handling
of both SPDIF channel status (CD) and
user (U) data and includes a frequency
measurement block that allows the
precise measurement of an incoming
sampling frequency.
Enhanced Filter Coprocessor
(EFCOP)
The EFCOP module functions as a
general purpose, fully programmable filter.
It has optimized modes of operation to
perform real and complex finite impulse
response (FIR) filtering, infinite impulse
response (IIR) filtering, adaptive FIR
filtering and multi-channel FIR filtering.
The EFOP operations work in parallel
with the 56300 core operations with
minimal CPU intervention required. It has
a dedicated filter multiplier accumulator
(FMAC) and so offers dual MAC
capabilities when the 56300 core and
Both of these peripherals provide very
useful high-speed serial interfaces, ideally
suited for communication and data
transfer between the DSP and external
ADCs, DACs and other codecs. The main
difference between the two peripherals is
the number of receiver and transmitters
available. The ESSI provides one receiver
and up to three transmitters whereas the
ESAI provides six ports in total, two of
which are dedicated transmitters with the
other four configurable as transmitters
or receivers. Note that the number of
ESAI/ESSI peripherals available varies
per DSP with up to four (24 total RX/TX
pins) available on the 5672x series. Both
the ESAI and ESSI support TDM and
non-TDM modes and can be operated
in synchronous (receiver and transmitter
have the same bit clock and frame synch)
or asynchronous (one set of clocks is
generated internally and the other set is
allows communication and data transfers
between the DSP and an external host
processor such as a microcontroller,
microprocessor or serial EEPROM/
flash. Both serial peripheral interface
(SPI) and inter-integrated circuit (I2C)
control modes are supported. The SHI
can either be configured as a slave or
single-master device depending on
the system requirements and supports
8-bit, 16-bit and 24-bit data transfers.
The SCI provides a full-duplex port for
serial communication with other DSPs,
microprocessor and other peripherals
such as modems. The main difference
between the SHI and the SCI is that the
SCI can support asynchronous serial
communication (e.g. RS232) whereas the
SHI cannot. The SCI includes its own
baud rate generator which can be used as
a general purpose timer when not being
used by the SCI.
supplied externally) modes.
EFCOP are used at the same time.
56300 Core Diagram with Available Peripherals
16
Triple
Timer
Address
Generation
Unit
6/8-ch.
DMA Unit
6
Host
Interface
HI08/HDI24
6
3
ESSI/ESAI
Interface
PIO_EB
SCI/SHI
Interface
Program RAM
(or Program
RAM and
Instruction
Cache)
X Data
RAM
Y Data
RAM
PM_EB
XM_EB
YM_EB
Peripheral
Expansion Area
24-Bit
DSP56300
Core
Boot-Strap
ROM
DDB
YDB
XDB
PDB
GDB
Internal
Data Bus
Switch
EXTAL
XTAL
Clock
Generator
PLL
YAB
XAB
PAB
DAB
Program
Address
Generator
2
RESET
PINIT/NMI
Program Control
Program
Address
Generator
Program
Address
Generator
Data ALU
24 × 24 + 56-—
>56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Memory
Expansion
Area
External
Address
Bus
Switch
External
Bus
Interface
and
I-Cache
Control
External
Data Bus
Switch
External
Power
Management
JTAG
OnCE
18
Address
13
Control
24
Data
5
DE
MODA/IRQD
MODA/IRQC
MODA/IRQB
MODA/IRQA
External addressing and HI08/HDI24 is only available on select 56K DSPs
46 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
DSP56K Family
DSP563xx Single-Core Architecture
• Single 56300 DSP Core
• 6-ch. DMA
DMA
56300 DSP Core
EFCOP*
• Switchable memory configurations
• External memory available (56311/321)
• SCI (56311/321)
• SHI (56371/374)
ROM
• Complete audio software library (56371/374)
RAM
• Triple timer
• Two ESAI (56374/371)
• Two ESSI (56311/321)
ROM
• Watchdog timer (56374)
PLL
• Enhanced filter coprocessor (56371/311/321)
WDT
EMC*
SHI*
SCI*
Two ESAI
or ESSI
Triple Timer
OnCE
* Not on all devices
DSP5672x Dual-Core Architecture
• Dual 56300 DSP cores
DMA
56300
DSP Core
• 8-ch. DMA/per core
56300
DSP Core
• Switchable memory configurations
DMA
• Complete audio software library
(on specific devices)
• ASRC
ROM
RAM
Bus-I/F
Unit
ROM
RAM
• S/PDIF transmitter and receiver
• Serial host interface
• Four enhanced serial audio interfaces
• Two watchdog timers
PLL
S/PDIF
EMC*
ASRC
Shared
Internal
RAM
HDI24*
HDI24*
WDT
WDT
SHI
SHI
ICC
Two ESAI
2 ESAI
Triple Timer
OnCE
• Host data interface (56721)
OnCE
Triple Timer
* Not on all devices
freescale.com/DSP
Next-Generation Digital Signal Processors 47
Application Solutions
Application Solutions
Virtual Multi-Channel
Headphone
The DSP56374 and DSP56371 devices
are ideal for use in a virtual multi-channel
headphone solution as they offer all the
Virtual Surround Headphone
Wired
Headphone
SPDIF
Serial
EEPROM
or Flash
IS
SPDIF Rx
3.3V
necessary decoding on one chip without
Voltage 1.25V
Regulator POR
the need for mass downloading of data
I2C
2
DSPD56374
Dolby® Digital
PLIIx
Dolby Headphone
I2S
I2S
DAC
+
H/P
Amp
HDTV
to on-chip RAM. In fact, the system
Oscillator
24.576 MHz
can even forgo a host microcontroller
altogether and use the DSP for GPIO
tasks such as LED lighting and mode
selection. The DSPD56374 offers fully
certified Dolby Digital, Pro Logic IIx and
Wireless
Headphone
Serial
EEPROM
or Flash
Dolby Headphone capabilities on its
SPDIF
custom ROM as does the DSPD56371,
3.3V
Voltage 1.25V
Regulator POR
which also adds DTS decoding as well as
WMA and AAC if required. This part also
includes an integrated S/PDIF receiver
I2C
DSPD56371
Dolby Digital/DTS
AAC/WMA
PLIIx/Neo6
Dolby Headphone
I2S
Wireless
Module 2.4 GHz
BB
I2S
RF
DAC
HDTV
Oscillator
24.576 MHz
so an external device does not need to
be used, reducing overall system costs.
Boot-up can be done from a simple serial
EEPROM or flash memory, which also
helps to reduce cost.
Guitar Effects Pedal
Guitar Effects Pedal
Footswitch/
Pedal
The DSP56724 and DSP56725 devices
are perfect for cost-effective audio
SRAM/
SDRAM
instrument effects units such as guitar
footswitches or “stomp” pedals. These
DPS offer a very cost-effective solution
with substantial internal memory available
here
DAC
DSP56724/
DSP56725
(112K x 24-bit words of RAM) or an
external memory bus (DSP56724 only)
if needed. Coupled with the dual-core
architecture, this allows customers to
ADC
here
Knobs/
Switches/
LEDs
build an entire suite of effects, including
delay, chorus, distortion, sustain, flange
and reverb, into a compact module. These
devices include many standard DSP
tables in the ROM (e.g. sine, asine, atan,
dB to linear, linear to dB, log to the base
2, log to the base 10, log to the base E)
which may be useful for creating
audio effects.
48 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
DSP56K Family
DSP56K Family
Development Software,
Tools and Reference
Designs
freescale.com/DSP
Next-Generation Digital Signal Processors 49
DSP56K Family Development Tools
Development Software
A wide range of development software is
available to support the 56K DSP family,
depending on the evaluation board used
and the needs of the application.
Suite56 (For use with all
DSP56K devices)
Serial Debugger Interface (For
use with Symphony softwareenabled DSP56K devices)
Symphony Studio (For use
with all DSP56K devices)
The serial debugger interface is a serially
advanced Eclipse-based tool which is
based tool (using either I C or SPI) used
based on the Suite56 toolset but comes
to emulate a host microcontroller in
with a more user friendly graphical
a system. It should be used with the
interface. It can be used with more
DSPAUDIOEVM development tool with
advanced applications where multiple
DSPs enabled with Symphony software
files are used and dual-core debugging
(a special class of DSP with audio
may be required. It includes a basic
decoders embedded in the ROM). It
compiler, assembler and linker and can
offers a real-time interface which can
be used with assembly or C language
be used to download and install post
programs. It is recommended that for
process phases (PPPs) and run the
more complex C programs, a third-party
Symphony software architecture.
compiler should be used such as the one
2
Suite56 is the standard toolset
compatible with all 56K DSP members,
includes a basic compiler, linker and
assembler and is recommended where
basic debugging is required and
assembly language is used for code
development.
The Symphony Studio is a more
offered by Tasking .
Development Tools Quick Reference Table
EVM Board
56374
56371
56311
56321
56724
56725
56720
56721
Cost
DSPAUDIOEVM
yes
yes
no
no
yes
yes
yes
yes
$1000/$1150*
DSP563xxEVME
no
no
yes
yes
no
no
no
no
$400
Symphony Soundbite
no
yes
no
no
no
no
no
no
$150
Software
56374
56371
56311
56321
56724
56725
56720
56721
Cost
Suite56
yes
yes
yes
yes
yes
yes
yes
yes
free
Serial Debugger Interface
yes**
yes**
no
no
yes**
yes**
yes**
yes**
free
Symphony Studio
yes
yes
yes
yes
yes
yes
yes
yes
free
* Cost is quoted for motherboard and daughterboard:
Motherboard is $750, 37x daughterboard is $250, 72x daughterboard is $400
** Only used with Symphony-enabled members of the DSP56K
50 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
DSP56K Family Development Tools
DSPAUDIOEVM Evaluation Module
full speed operation and breakpoint
The $750.00 USD DSPAUDIOEVM
The $750.00 USD DSPAUDIOEVM is
evaluation module provides a hardware
designed for the following purposes:
capability and the ability to modify all
tool to allow development of applications
• To allow new users to familiarize
user-accessible registers, memory and
on the DSP5637x and DSP5672x devices.
themselves with the features of the
peripherals though the JTAG/OnCE
It consists of a generic motherboard
DSP5637x/5672x family architecture by
port.
(DSPAUDIOEVMMB1E) and a specific
exercising the product feature set.
daughterboard corresponding to your
DSP needs.
• To allow users to test and evaluate
• To serve as a platform for real-time
any audio decoders which may be
software development, software
contained in specific ROMs in the
download to on-chip or on-board RAM,
Symphony DSP family.
software running and debug with
DSPAUDIOEVMMB1(E)-Motherboard
4 x SPDIF Out, 3 x Coax, 1 x Optical/Coax 4 x SPDIF In, 2 x Coax, 2 x Optical
2-ch. Analog In Line Level
2-ch. Analog In Microphone
HC08-JB16 Debug MPU
MIC1
MultiVoltage
External
Supply
Connection
Buffer
11.2 MHz
12.0 MHz
RS-232
SPI
Debugger
Port
HC08
JB16
AK5380
2-ch. A/D
XM XM
AK5380
2-ch. A/D
AK4101
SPDIF
4 x TX
AK4114
SPDIF
4 x RX
AK4355
6-ch. D/A
XM XM XM XM
-12V
+5V
USB SPI
Debugger
Port
MIC2
+12V
Microphone
Level
Control
OP-AMP
OP-AMP
OP-AMP
OP-AMP
12-ch.
Analog
Out
Line
Level
Buffer
Buffer
Parallel
Port
High
Speed
JTAG
Debugger
System
Reset
Freescale Technology
freescale.com/DSP
AK4355
6-ch. D/A
OP-AMP
OP-AMP
9.8 MHz
Headphone
Out
HC08
GP32
HC08-GP32 Config. MPU
Gate Logic
Headphone Channel Select
Headphone Volume Control
Next-Generation Digital Signal Processors 51
DSP56K Family Development Tools
Symphony SoundBite Development Kit
Freescale’s $150 USD MSRP Symphony
High-Level Symphony SoundBite Overview
SoundBite development kit is designed
for cost-sensitive applications and
USB/External Power Supply
college laboratories, providing a costefficient entry point into high-end DSP
solutions.
The Symphony SoundBite development
Stereo Line-in
Stereo Line-out
kit brings much of the performance
of Freescale’s full-featured evaluation
module (DSPAUDIOEVMMB1E
motherboard and DSPB371DB1
daughtercard) for the Symphony
Stereo Line-in
Stereo Line-out
Symphony
SoundBite
Board
Stereo Line-in
Stereo Line-out
DSP56371 DSP to a more compact and
user-friendly design at a very manageable
price point. The Symphony SoundBite
Optical/Stereo
Line-out
Optical/Stereo
Line-in
is capable of simultaneously processing
eight independent channels of line-level
audio via four pairs of 3.5 mm stereo
jacks. One input/output pair of jacks is
shared with the AKM S/PDIF receiver and
transmitter, enabling optical digital audio
Mic
input and output. The analog processing
Note: All analog inputs and outputs are stereo
is handled by four AKM 24-bit stereo
codecs at sampling rates up to 192 kHz.
USB Communication/
Debugging Port
Pre-amp
Multiple banks of DIP switches and multi-
Documentation
colored LEDs connected to the DSP’s
• Symphony SoundBite hardware
GPIO pins allow for user interaction with
the DSP application.
The Symphony SoundBite development
kit includes the Symphony SoundBite
evaluation board, a mini USB cable and
a CD-ROM with all the software and
documentation needed to get started. An
external power supply is recommended
for optimum audio performance. The
reference guide and schematic
• Symphony DSP56300 family manual
• Symphony DSP56371 user’s guide
and data sheet
• Symphony SoundBite application
examples
Package
• 4 x 5 inch double sided PCB
Symphony Studio software is now
available for download at no charge. Go
to freescale.com/SymphonyStudio
and click on the Download tab. The
Symphony SoundBite evaluation board
includes the Symphony DSPB56371
processor on a small form-factor PCB,
256 KB serial (I2C) EEPROM memory,
mini USB interface and a DIP switches
for user inputs.
52 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
DSP56K Family Development Tools
Key Processor Features
• 24-bit Symphony DSPB56371 DSP, 180 (MIPS) at 180 MHz core clock
• Dual-Harvard architecture core (two data memory spaces in addition to
program space)
On-chip memories:
4­­–44K x 24-bit words of PRAM
28–36K x 24-bit words of XRAM
16–48K x 24-bit words of YRAM
• Two ESAIs provide up to eight channels of digital audio input and output
• SHI allows for I2C or SPI communication
Key Board Features
• Powered by USB bus voltage or external power adaptor
• On-board USB interface that provides JTAG debug, I2C and SPI serial
communication with the DSP
• 1x AK4584 24-bit 192 kHz stereo codec with integrated S/PDIF transceiver
• 3x AK4556 24-bit 192 kHz stereo codecs
• On-board microphone and pre-amplifier
• Expansion header for off-board GPIO interfacing
• 8-position DIP input switch
• Nine LED indicators
freescale.com/DSP
Next-Generation Digital Signal Processors 53
DSP56K Family Development Tools
DSP563xx Evaluation Module
(DSP563xxEVME)
The DSP563xx evaluation module is a
cost-effective platform for developing
DSP563xx Evaluation Module
real-time software and hardware products
to support wireless, telecommunications,
multimedia and other applications. It
comes supplied with a socket and samples
F SRAM
Flash
64K x 24
256K x 8
of the DSP56311 and DSP56321 DSPs.
Data Bus
25-pin Parallel
Axiom JTAG
Pod Cable
J3
Address Bus
JTAG/
OnCE Port
Host
PC
Host Port
J11
DSP563xx
RS-232
J8
SCI
Data Control
EXTAL
ESSI0
ESSI1
J2
J6
Oscillator
12.288 MHz
CS4270
CLKIN
DSP563xx EVM
54 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
StarCore MSC8xxx Development Tools
freescale.com/DSP
Next-Generation Digital Signal Processors 55
Additional Resources
Additional Resources
For additional details on the products
Support is available on the Freescale
To order samples or tools, contact your
in this brochure, including technical
Forums page at forums.freescale.com.
local Freescale Sales representative
documentation, application notes,
or your local authorized Freescale
software downloads and training, visit
distributor.
freescale.com/DSP.
Ecosystem Partners
ENEA—enea.com
OSEck RTOS, LINX message layer, network protocols. System level virtualization and debugging
environments for system development on the MSC815x and MSC825x
Adaptive Digital—adaptivedigital.com
G.PAK framework, G.168 echo cancellation, conferencing and transcoding software
GDA Technologies—gdatech.com
Hardware design services, evaluation module (AMC board)
Tata—tataelxsi.com
Media software development services
e2v—e2v.com
Extended temperature testing, ruggedized packaging for extreme environments
Nuvation—nuvation.com
Embedded system design
Altium—tasking.com/products/dsp56xxx/
Tasking compiler for DSP56xxx devices. For applications where C programming is used extensively
Domain Technologies—domaintec.com/FreescaleTools.html
DSP56xxx debugging solutions
Quadros—quadros.com/supported-processors/other-processors
Real-time OS software is available for the DSP56311 and DSP56321
Micrium—micrium.com/page/downloads/ports/freescale/dsp
Real-time OS software is available for the DSP56311 and DSP56321
Rislin—rislin.com
Media software and development services
56 Next-Generation Digital Signal Processors
Beyond DSPs, November 2010
Freescale, the Freescale logo, CodeWarrior, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S.
Pat. & Tm. Off. QUICC Engine and QorIQ are trademarks of Freescale Semiconductor, Inc. Dolby Digital, Dolby Surround,
Pro Logic and the double-D symbol are registered trademarks of Dolby Laboratories; Dolby Digital is manufactured under license from
Dolby Laboratories. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are
trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners.
© 2010 Freescale Semiconductor, Inc.
BYNDDSPBRO / Rev 1