Features • 16-channel GPS Correlator • • • • • • • • • • • • • • • • • • • – 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.5m CEP (Stand-Alone, S/A off) – Time to First Fix: 34s (Cold Start) – Acquisition Sensitivity: –142 dBm (Cold Start) – Tracking Sensitivity: –158 dBm Utilizes the ARM7TDMI® ARM® Thumb® Processor Core – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – EmbeddedICE™ (In-circuit Emulator) 128 Kbyte Internal RAM 384 Kbyte Internal ROM, Firmware Version V5.0 Position Technology Provided by µ-blox 6-channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable, Vectored Interrupt Controller – 2 External Interrupts 24 User-programmable I/O Lines 1 USB Device Port – Universal Serial Bus (USB) V2.0 Full-speed Device – Embedded USB V2.0 Full-speed Transceiver – Suspend/Resume Logic – Ping-pong Mode for Isochronous and Bulk Endpoints 2 USARTs – 2 Dedicated Peripheral Data Controller (PDC) Channels per USART Master/Slave SPI Interface – 2 Dedicated Peripheral Data Controller (PDC) Channels – 8-bit to 16-bit Programmable Data Length – 4 External Slave Chip Selects Programmable Watchdog Timer Advanced Power Management Controller (APMC) – Peripherals Can Be Deactivated Individually – Geared Master Clock to Reduce Power Consumption – Sleep State with Disabled Master Clock – Hibernate State with 32.768 kHz Master Clock Real Time Clock (RTC) 2.3V to 3.6V or 1.8V Core Supply Voltage Includes Power Supervisor 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance 4 Kbytes Battery Backup Memory 8 mm × 8 mm 56 Pin QFN56 Package RoHS-compliant, Green GPS Baseband Processor SuperSense ATR0625P1 Automotive Summary NOTE: This is a summary document. The complete document is available. For more information, please contact your local Atmel sales office. 4976BS–GPS–05/08 1. Description The GPS baseband processor ATR0625P1 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0625P1 has two USART and an USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. The ATR0625P1 includes full GPS SuperSense® firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM. The firmware supports e.g. the NMEA® protocol (2.1 and 2.3), a binary protocol for PVT data, configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS) and A-GPS (aiding). It is also possible to store the configuration settings in an optional external EEPROM. The ATR0625P1 is manufactured using Atmel®’s high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a wide range of peripheral functions on a monolithic chip, the ATR0625P1 provides a highly flexible and cost-effective solution for GPS applications. 2 ATR0625P1 4976BS–GPS–05/08 ATR0625P1 Advanced Power Management Controller XT_IN XT_OUT GPS Correlators RTC NSHDN NSLEEP GPS Accelerator ATR0625P1 Block Diagram SRAM RF_ON CLK23 SMD Generator P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0 SIGLO0 SIGHI0 Timer Counter Figure 1-1. SPI APB PIO2 Special Function USART2 P31/RXD1 USB Transceiver USB_DP USB_DM Power Supply Manager Reset Controller JTAG NTRST NRESET ROM 384K SRAM 128K DBG_EN TDI TDO TCK TMS ARM7TDMI Embedded ICE ASB Interface to Off-Chip Memory (EBI) PDC2 B R I D G E USB Watchdog P8/STATUSLED P16/NEEPROM P22/RXD2 P18/TXD1 USART1 P30/AGCOUT0 Advanced Interrupt Controller P2/BOOT_MODE P21/TXD2 PIO2 P9/EXTINT0 PIO2 Controller P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 VBAT18 VBAT LDOBAT_IN LDO_OUT LDO_IN LDO_EN 3 4976BS–GPS–05/08 2. Architectural Overview 2.1 Description The ATR0625P1 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories. The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The ATR0625P1 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address space.) The peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status, and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits, and the third address reads the value stored in the register. A bit can be set or reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0” has no effect. Individual bits can thus be modified without having to use costly read-modify-write and complex bit-manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O (PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 Controller in order to define which peripheral signals are connected with off-chip logic. The ARM7TDMI processor operates in little-endian mode on the ATR0625P1 GPS Baseband. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet. The ARM standard In-Circuit Emulator (ICE) debug interface is supported via the JTAG/ICE port of the ATR0625P1. For features of the ROM firmware (SuperSense), refer to the software documentation available from u-blox AG, Switzerland. 4 ATR0625P1 4976BS–GPS–05/08 ATR0625P1 3. Pin Configuration 3.1 Pinout Figure 3-1. Pinout QFN56 (Top View) 42 29 43 28 ATR0625P1 56 15 1 Table 3-1. 14 ATR0625P1 Pinout Pin Name QFN56 Pin Type CLK23 37 IN DBG_EN 8 IN GND (2) IN LDOBAT_IN 21 IN LDO_EN 25 IN LDO_IN 20 IN LDO_OUT 19 OUT NRESET 41 I/O NSHDN 26 OUT NSLEEP 24 OUT Pull Resistor (Reset Value)(1) PIO Bank A Firmware Label I O PD Open Drain PU NTRST 13 IN PD P0 40 I/O PD P1 47 I/O Configurable (PD) GPSMODE0 AGCOUT1 P2 46 I/O Configurable (PD) BOOT_MODE “0” P8 48 I/O Configurable (PD) STATUSLED P9 29 I/O PU to VBAT18 EXTINT0 P12 49 I/O Configurable (PU) GPSMODE2 P13 32 I/O PU to VBAT18 GPSMODE3 Notes: NANTSHORT “0” EXTINT0 NPCS2 EXTINT1 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. Ground plane 3. VBAT18 represent the internal power supply of the backup power domain. 4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. 5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required. 6. This pin is not connected 5 4976BS–GPS–05/08 Table 3-1. ATR0625P1 Pinout (Continued) Pin Type Pull Resistor (Reset Value)(1) Firmware Label P14 1 I/O Configurable (PD) NAADET1 P15 17 I/O PD ANTON I O “0” P16 6 I/O Configurable (PU) NEEPROM SIGHI1 P17 2 I/O Configurable (PD) GPSMODE5 SCK1 P18 45 I/O Configurable (PU) TXD1 P19 53 I/O Configurable (PU) GPSMODE6 SIGLO1 P20 4 I/O Configurable (PD) TIMEPULSE SCK2 P21 52 I/O Configurable (PU) TXD2 P22 30 I/O PU to VBAT18 RXD2 RXD2 P23 3 I/O Configurable (PU) GPSMODE7 SCK SCK1 TXD1 SCK2 TXD2 SCK P24 5 I/O Configurable (PU) GPSMODE8 MOSI MOSI P25 55 I/O Configurable (PD) NAADET0 MISO MISO P26 44 I/O Configurable (PU) GPSMODE10 NSS NPCS0 P27 54 I/O Configurable (PU) GPSMODE11 P29 50 I/O Configurable (PU) GPSMODE12 NPCS3 P30 16 I/O PD AGCOUT0 AGCOUT0 RXD1 P31 31 I/O PU to VBAT18 RF_ON 15 OUT PD SIGHI0 38 IN SIGLO0 39 IN TCK 9 IN PU TDI 10 IN PU TDO 11 OUT TMS 12 IN USB_DM 34 I/O USB_DP 35 I/O VBAT 22 IN VBAT18(3) 23 OUT VDD18 7, 14 IN VDD18 18, 36 IN VDD18 51 IN VDDIO (4) 43, 56 IN VDD_USB(5) 33 IN XT_IN 28 IN XT_OUT 27 OUT NC(6) 42 Notes: PIO Bank A QFN56 Pin Name NPCS1 RXD1 PU 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. Ground plane 3. VBAT18 represent the internal power supply of the backup power domain. 4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. 5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required. 6. This pin is not connected 6 ATR0625P1 4976BS–GPS–05/08 ATR0625P1 3.2 Signal Description Table 3-2. ATR0625P1 Signal Description Module Name EBI USART USB Function Type BOOT_MODE Boot Mode Input Input – PIO-controlled after reset, internal pull-down resistor TXD1 to TXD2 Transmit Data Output Output – PIO-controlled after reset RXD1 to RXD2 Receive Data Input Input – PIO-controlled after reset SCK1 to SCK2 PIO-controlled after reset External Synchronous Serial Clock I/O – USB_DP USB Data (D+) I/O – USB_DM USB Data (D-) I/O – Output – Input High/ Low/ Edge PIO-controlled after reset Automatic Gain Control Output – Interface to ATR0601 PIO-controlled after reset NSLEEP Sleep Output Output Low Interface to ATR0601 NSHDN Shutdown Output Output Low Connect to pin LDO_EN Input – APMC RF_ON AIC EXTINT0-1 AGC AGCOUT0-1 RTC XT_IN XT_OUT SPI External Interrupt Request Oscillator Input Oscillator Output Interface to ATR0601 RTC oscillator Output – RTC oscillator SCK SPI Clock I/O – PIO-controlled after reset MOSI Master Out Slave In I/O – PIO-controlled after reset MISO Master In Slave Out I/O – PIO-controlled after reset NSS/NPCS0 Slave Select I/O Low PIO-controlled after reset NPCS1 to NPCS3 Slave Select Output Low PIO-controlled after reset I/O – Input after reset Input – Interface to ATR0601 PIO P0 to P31 SIGHI0 GPS Digital IF Digital IF Input – Interface to ATR0601 SIGHI1 Digital IF Input – PIO-controlled after reset SIGLO1 Digital IF Input – PIO-controlled after reset Output – PIO-controlled after reset GPS synchronized time pulse GPSMODE0-12 GPS Mode Input – PIO-controlled after reset STATUSLED Status LED Output – PIO-controlled after reset Input Low PIO-controlled after reset Output – PIO-controlled after reset Active antenna short circuit detection Input Input Low PIO-controlled after reset Active antenna detection Input Input Low PIO-controlled after reset NEEPROM CONFIG Programmable I/O Port SIGLO0 TIMEPULSE ANTON NANTSHORT NAADET0-1 Note: Active Level Comment Enable EEPROM Support Active antenna power on Output 1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V. 7 4976BS–GPS–05/08 Table 3-2. Module ATR0625P1 Signal Description (Continued) Name TMS JTAG/ICE Function Type Test Mode Select Input TDI Test Data In TDO Test Data Out TCK NTRST DBG_EN – Internal pull-up resistor Internal pull-up resistor Input – Output – Test Clock Input – Test Reset Input Input Low Internal pull-down resistor Debug Enable Input High Internal pull-down resistor CLOCK CLK23 Clock Input Input – RESET NRESET Reset Input I/O Low POWER LDOBAT Open drain with internal pull-up resistor Power – Core voltage 1.8V Power – Variable IO voltage 1.65V to 3.6V VDD_USB Power – USB voltage 0 to 2.0V or 3.0V to 3.6V(1) GND Power – Ground LDOBAT_IN Power – 2.3V to 3.6V VBAT Power – 1.5V to 3.6V LDO_OUT LDO_EN Note: Interface to ATR0601, Schmitt trigger input VDDIO VBAT18 LDO18 Internal pull-up resistor VDD18 LDO_IN 8 Active Level Comment Out – 1.8V backup voltage LDO In Power – 2.3V to 3.6V LDO Out Power – 1.8V core voltage, max. 80 mA LDO Enable Input – 1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V. ATR0625P1 4976BS–GPS–05/08 ATR0625P1 3.3 External Connections for a Working GPS System Figure 3-2. Example of an External Connection ATR0601 SIGH SIGL SC PURF PUXTO SIGHI SIGLO CLK23 RF_ON NSLEEP NC see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 P0 - 2 P9 P12 - 17 P19 P23 - 27 P29 - 30 NC NC NC NC NC TMS TCK TDI NTRST TDO NC DBG_EN GND +3V (see Power Supply) NRESET GND NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN ATR0625P1 P8 P20 STATUS LED TIMEPULSE USB_DM USB_DP Optional USB P31 P18 Optional USART 1 P22 P21 Optional USART 2 XT_IN XT_OUT 32.368 kHz (see RTC) +3V (see Power Supply) VDDIO +3V (see Power Supply) VBAT18 VBAT VDD_USB +3V (see Power Supply) GND NC: Not connected 9 4976BS–GPS–05/08 4. Ordering Information Extended Type Number Package MPQ Remarks ATR0625P1-PYQW QFN56 2000 8 mm × 8 mm, 0.50 mm pitch, RoHS-compliant, green, automotive type ATR0625-EK1 - 1 Evaluation kit/Road test kit ATR0625-DK1 - 1 Development kit including example design information 5. Package QFN56 Package: QFN56 8 x 8 Exposed pad 6.5 x 6.5 Dimensions in mm Not indicated tolerances ±0.05 8 0.9 max. +0 6.5 0.05-0.05 43 56 1 56 1 42 Pin 1 ID technical drawings according to DIN specifications 29 14 28 0.4±0.1 0.25 14 15 0.5 nom. Drawing-No.: 6.543-5121.01-4 Issue: 1; 02.09.05 Moisture sensitivity level (MSL) = 3 10 ATR0625P1 4976BS–GPS–05/08 ATR0625P1 6. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, and not to this document. Revision No. History 4976BS-GPS-05/08 • Table 3-1 “ATR0625P1 Pinout” on page 5: Pin type of pin CLK23 changed. 11 4976BS–GPS–05/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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