ATMEL T89C51RC2

Features
• 80C52 Compatible
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•
•
•
•
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– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit timer/counters
– 256 Bytes Scratch Pad RAM
– 10 Interrupt Sources with 4 Priority Levels
– Dual Data Pointer
Variable Length MOVX for slow RAM/Peripherals
ISP (In-System Programming) using Standard VCC Power Supply
Boot ROM Contains Low Level FLASH Programming Routines and a Default Serial
Loader
High-Speed Architecture
– 40 MHz in Standard Mode
– 20 MHz in X2 Mode (6 clocks/machine cycle)
16K/32K Bytes on-chip FLASH Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 10k Write Cycles
On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 bytes)
– 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility
Keyboard Interrupt Interface on port P1
SPI Interface (Master / Slave Mode)
8-bit Clock Prescaler
Improved X2 Mode with Independent Selection for CPU and each Peripheral
Programmable Counter Array 5 Channels with:
– High Speed Output
– Compare / Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Full Duplex Enhanced UART
Dedicated Baud Rate Generator for UART
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time enabled with Reset-Out)
Power Control Modes:
– Idle Mode
– Power-down mode
– Power-off Flag
Power supply: 4.5 to 5.5V or 2.7 to 3.6V
Temperature ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
Packages: PDIL40, PLCC44, VQFP44
8-bit
Microcontroller
with 16K/
32K byte Flash
T89C51RB2
T89C51RC2
Preliminary
Description
T89C51RB2/RC2 is a high-performance FLASH version of the 80C51 8-bit microcontrollers. It contains a 16K or 32K byte Flash memory block for program and data.
The Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated
from the standard VCC pin.
The T89C51RB2/RC2 retains all features of the 80C52 with 256 bytes of internal
RAM, a 7-source 4-level interrupt controller and three timer/counters.
In addition, the T89C51RB2/RC2 has a Programmable Counter Array, an XRAM of
1024 bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface,
Rev. 4105D–8051–10/06
1
a more versatile serial channel that facilitates multiprocessor communication (EUART)
and a speed improvement mechanism (X2 mode).
Pinout is the standard 40/44 pins of the C52.
The fully static design reduces system power consumption of the T89C51RB2/RC2 by
allowing it to bring the clock frequency down to any value, even DC, without loss of data.
The T89C51RB2/RC2 has 2 software-selectable modes of reduced activity and 8-bit
clock prescaler for further reduction in power consumption. In Idle mode, the CPU is frozen while the peripherals and the interrupt system are still operating. In power-down
mode, the RAM is saved and all other functions are inoperative.
The added features of the T89C51RB2/RC2 make it more powerful for applications that
need pulse width modulation, high speed I/O and counting capabilities such as alarms,
motor control, corded phones, and smart card readers.
Table 1. Memory Size
Part Number
Flash (bytes)
XRAM (bytes)
TOTAL RAM
(bytes)
I/O
T89C51RB2
16K
1024
1280
32
T89C51RC2
32K
1024
1280
32
Block Diagram
(2) (2)
XTAL1
XTAL2
(1)
EUART
+
BRG
ALE/ PROG
RAM
256x8
C51
CORE
PSEN
Flash
32Kx8 or
16Kx8
XRAM
1Kx8
Boot
ROM
2Kx8
(1) (1)
PCA
T2
T2EX
PCA
ECI
Vss
VCC
TxD
RxD
Figure 1. Block Diagram
(1)
Timer2
IB-bus
CPU
EA
Timer 0
Timer 1
(2)
INT
Ctrl
Parallel I/O Ports & Ext. Bus
Watch Key
Dog Board
SPI
Note:
SS
MOSI
SCK
MISO
P3
P2
P1
(1) (1) (1) (1)
P0
INT1
(2) (2)
T1
(2) (2)
INT0
Port 0 Port 1 Port 2 Port 3
RESET
WR
(2)
T0
RD
1. Alternate function of Port 1
2. Alternate function of Port 3
2
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
SFR Mapping
The Special Function Registers (SFRs) of the T89C51RB2/RC2 fall into the following
categories:
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP
•
I/O port registers: P0, P1, P2, P3
•
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
•
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
•
PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 to 4)
•
Power and clock control registers: PCON
•
Hardware Watchdog Timer registers: WDTRST, WDTPRG
•
Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
•
Keyboard Interface registers: KBE, KBF, KBLS
•
SPI registers: SPCON, SPSTR, SPDAT
•
BRG (Baud Rate Generator) registers: BRL, BDRCON
•
Flash register: FCON
•
Clock Prescaler register: CKRL
•
Others: AUXR, AUXR1, CKCON0, CKCON1
3
4105D–8051–10/06
The table below shows all SFRs with their address and their reset value.
Table 2. SFR Mapping
Bit
addressable
0/8
F8h
F0h
1/9
2/A
3/B
4/C
5/D
6/E
CH
CCAP0H
CCAP1H
CCAPL2H
CCAPL3H
CCAPL4H
0000 0000
XXXX
XXXX
XXXX
XXXX
XXXX
CL
CCAP0L
CCAP1L
CCAPL2L
CCAPL3L
CCAPL4L
0000 0000
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
E7h
CMOD
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
00XX X000
X000 0000
X000 0000
X000 0000
X000 0000
X000 0000
D0h
PSW
0000 0000
FCON (a)
XXXX 0000
C8h
T2CON
0000 0000
T2MOD
XXXX XX00
A8h
A0h
98h
90h
88h
80h
IPL0
SADEN
X000 000
0000 0000
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
SPCON
SPSTA
SPDAT
0001 0100
0000 0000
XXXX XXXX
CFh
C7h
BFh
P3
IE1
IPL1
IPH1
IPH0
1111 1111
XXXXX 000
XXXXX000
XXXX X111
X000 0000
IE0
SADDR
CKCON1
0000 0000
0000 0000
XXXX XXX0
P2
AUXR1
WDTRST
WDTPRG
1111 1111
XXXXX0X0
XXXX XXXX
XXXX X000
SCON
SBUF
BRL
BDRCON
KBLS
KBE
KBF
0000 0000
XXXX XXXX
0000 0000
XXX0 0000
0000 0000
0000 0000
0000 0000
P1
CKRL
1111 1111
TCON
TMOD
TL0
TL1
TH0
TH1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
0/8
1/9
2/A
3/B
FCON access is reserved for the FLASH API and ISP software
Note:
Reserved
AUXR
XX0X 0000
CKCON0
0000 0000
PCON
00X1 0000
4/C
5/D
6/E
B7h
AFh
A7h
9Fh
1111 1111
a.
4
DFh
D7h
C0h
B0h
EFh
ACC
0000 0000
CCON
B8h
FFh
F7h
00X0 0000
D8h
7/F
B
0000 0000
E8h
E0h
Non Bit addressable
97h
8Fh
87h
7/F
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Pin Configurations
7
8
P0.5/AD5
33
9
10
P1.7/CEx4/MOSI
9
37
P0.6/AD6
32
P0.7/AD7
RST
10
36
P0.7/AD7
31
30
EA
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P3.0/RxD
35
34
EA
NIC*
11
12
P3.1/TxD
13
33
ALE/PROG
P3.2/INT0
14
15
32
31
PSEN
16
30
P2.6/A14
17
29
P2.5/A13
24
23
P2.2/A10
XTAL1
19
20
22
21
P2.1/A9
NIC*
P2.7/A15
P3.6/WR
18 19 20 21 22 23 24 25 26 27 28
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
P2.0/A8
P1.4/CEX1
VSS
P0.5/AD5
P2.3/A11
P2.4/A12
17
18
P2.2/A10
P3.7/RD
XTAL2
P2.4/A12
P2.3/A11
P2.1/A9
25
NIC*
P2.0/A8
16
P3.4/T0
P3.5/T1
VSS
P3.6/WR
P3.3/INT1
XTAL1
27
26
XTAL2
P3.5/T1
14
15
P3.4/T0
PLCC44
P3.7/RD
13
29
28
NIC*
PDIL40
P0.6/AD6
P1.0/T2
11
12
39
38
P0.4/AD4
P1.6/CEX3/SCK
7
8
P1.1/T2EX/SS
P3.2/INT0
P3.3/INT1
P1.5/CEX2/MISO
P1.2/ECI
P3.0/RxD
P3.1/TxD
P0.3/AD3
P0.4/AD4
P1.3/CEX0
P1.7CEX4/MOSI
RST
6 5 4 3 2 1 44 43 42 41 40
36
35
34
5
P0.2/AD2
P0.3/AD3
6
P0.1/AD1
P0.2/AD2
P0.1/AD1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
37
P0.0/AD0
3
4
VCC
P1.2/ECI
P1.3CEX0
P1.4/CEX1
NIC*
P0.0/AD0
P1.0/T2
VCC
39
38
P1.1/T2EX/SS
40
2
P1.2/ECI
1
P1.3/CEX0
P1.0/T2
P1.1/T2EX/SS
P1.4/CEX1
Figure 2. Pin Configurations
44 43 42 41 40 39 38 37 36 35 34
P1.5/CEX2/MISO
1
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
2
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
3
4
5
6
7
8
VQFP44 1.4
33
32
P0.4/AD4
31
30
P0.6/AD6
P0.7/AD7
29
28
EA
NIC*
27
ALE/PROG
PSEN
26
25
9
24
10
11
23
P0.5/AD5
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
NIC*
VSS
XTAL1
XTAL2
P3.7/RD
P3.6/WR
12 13 14 15 16 17 18 19 20 21 22
*NIC: No Internal Connection
5
4105D–8051–10/06
Table 3. Pin Description for 40 - 44 Pin Packages
Pin Number
Mnemonic
DIL
LCC
VQFP44 1.4
Type
Name and Function
VSS
20
22
16
I
Ground: 0V reference
VCC
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle and power - down
operation
P0.0 - P0.7
39 - 32
43 - 36
37 - 30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 must be
polarized to VCC or V SS in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low - order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull - up when
emitting 1s. Port 0 also inputs the code bytes during FLASH programming. External
pull - ups are required during program verification during which P0 outputs the code
bytes.
P1.0 - P1.7
1-8
2-9
40 - 44
1-3
I/O
Port 1: Port 1 is an 8 - bit bidirectional I/O port with internal pull - ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull - ups and can be
used as inputs. As inputs, Port 1 pins that are externally pulled low will source
current because of the internal pull - ups. Port 1 also receives the low - order
address byte during memory programming and verification.
Alternate functions for T89C51RB2/RC2 Port 1 include:
1
2
3
2
3
4
40
41
42
I/O
P1.0: Input / Output
I/O
T2 (P1.0): Timer/Counter 2 external count input/Clockout
I/O
P1.1: Input / Output
I
T2EX: Timer/Counter 2 Reload/Capture/Direction Control
I
SS: SPI Slave Select
I/O
I
4
5
6
5
6
7
43
44
1
P1.2: Input / Output
ECI: External Clock for the PCA
I/O
P1.3: Input / Output
I/O
CEX0: Capture/Compare External I/O for PCA module 0
I/O
P1.4: Input / Output
I/O
CEX1: Capture/Compare External I/O for PCA module 1
I/O
P1.5: Input / Output
I/O
CEX2: Capture/Compare External I/O for PCA module 2
I/O
MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When
SPI is in slave mode, MISO outputs data to the master controller.
7
8
2
I/O
P1.6: Input / Output
I/O
CEX3: Capture/Compare External I/O for PCA module 3
I/O
SCK: SPI Serial Clock
SCK outputs clock to the slave peripheral
8
6
9
3
I/O
P1.7: Input / Output:
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Table 3. Pin Description for 40 - 44 Pin Packages (Continued)
Pin Number
Mnemonic
DIL
LCC
VQFP44 1.4
P1.0 - P1.7
Type
Name and Function
I/O
CEX4: Capture/Compare External I/O for PCA module 4
I/O
MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI
is in slave mode, MOSI receives data from the master controller.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier
21 - 28
24 - 31
18 - 25
I/O
Port 2: Port 2 is an 8 - bit bidirectional I/O port with internal pull - ups. Port 2 pins
that have 1s written to them are pulled high by the internal pull - ups and can be
used as inputs. As inputs, Port 2 pins that are externally pulled low will source
current because of the internal pull - ups. Port 2 emits the high - order address byte
during fetches from external program memory and during accesses to external data
memory that use 16 - bit addresses (MOVX @DPTR). In this application, it uses
strong internal pull - ups emitting 1s. During accesses to external data memory that
use 8 - bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some
Port 2 pins receive the high order address bits during EPROM programming and
verification:
P2.0 - P2.7
P2.0 to P2.5 for 16 KB devices
P2.0 to P2.6 for 32KB devices
P3.0 - P3.7
10 - 17
11,
13 - 19
5,
7 - 13
I/O
Port 3: Port 3 is an 8 - bit bidirectional I/O port with internal pull - ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull - ups and can be
used as inputs. As inputs, Port 3 pins that are externally pulled low will source
current because of the internal pull - ups. Port 3 also serves the special features of
the 80C51 family, as listed below.
10
11
5
I
RXD (P3.0): Serial input port
11
13
7
O
TXD (P3.1): Serial output port
12
14
8
I
INT0 (P3.2): External interrupt 0
13
15
9
I
INT1 (P3.3): External interrupt 1
14
16
10
I
T0 (P3.4): Timer 0 external input
15
17
11
I
T1 (P3.5): Timer 1 external input
16
18
12
O
WR (P3.6): External data memory write strobe
17
19
13
O
RD (P3.7): External data memory read strobe
RST
9
10
4
I/O
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power - on reset
using only an external capacitor to VCC. This pin is an output when the hardware
watchdog forces a system reset.
ALE/PROG
30
33
27
O (I)
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of
the address during an access to external memory. In normal operation, ALE is
emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can
be used for external timing or clocking. Note that one ALE pulse is skipped during
each access to external data memory. This pin is also the program pulse input
(PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR. 0
bit. With this bit set, ALE will be inactive during internal fetches.
7
4105D–8051–10/06
Table 3. Pin Description for 40 - 44 Pin Packages (Continued)
Pin Number
Mnemonic
DIL
LCC
VQFP44 1.4
Type
Name and Function
PSEN
29
32
26
O
Program Strobe ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
EA
31
35
29
I
External Access Enable: EA must be externally held low to enable the device to
fetch code from external program memory locations 0000H to FFFFH (RD). If
security level 1 is programmed, EA will be internally latched on Reset.
8
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Oscillator
In order to optimize the power consumption and execution time needed for a specific
task, an internal, prescaler feature has been implemented between oscillator and the
CPU and peripherals.
Registers
Table 4. CKRL Register
CKRL – Clock Reload Register (97h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit Number
Mnemonic
7:0
CKRL
Description
Clock Reload Register:
Prescaler value
Reset Value = 1111 1111b
Not bit addressable
Table 5. PCON Register
PCON – Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit Number
Bit Mnemonic
Description
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can
also be set by software.
3
GF1
General Purpose Flag
Cleared by software for general purpose usage.
Set by software for general purpose usage.
2
GF0
General Purpose Flag
Cleared by software for general purpose usage.
Set by software for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b Not bit addressable
9
4105D–8051–10/06
Functional Block
Diagram
Figure 3. Functional Oscillator Block Diagram
Reload
Reset
CKRL
FOSC
Xtal1
Osc
1
Xtal2
:2
0
8-bit
Prescaler-Divider
CLK
PERIPH
CLK
CPU
X2
•
A hardware RESET puts the prescaler divider in the following state:
•
•
CPU clock
Idle
CKCON0
Prescaler Divider
Peripheral Clock
CKRL = FFh: FCLK CPU = FCLK PERIPH = F OSC/2 (Standard C51 feature)
Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
•
CKRL = 00h: minimum frequency
FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode)
•
CKRL = FFh: maximum frequency
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X2 Mode:
F OSC
F CPU = F CLKPER IPH = ----------------------------------------------
2 × ( 255 – CKRL )
In X1 Mode:
F OSC
F CPU = F CLKPER IPH = ----------------------------------------------
4 × ( 255 – CKRL )
10
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Enhanced Features
X2 Feature
In comparison to the original 80C52, the T89C51RB2/RC2 implements some new features, which are:
•
the X2 option
•
the Dual Data Pointer
•
the extended RAM
•
the Programmable Counter Array (PCA)
•
the Hardware Watchdog
•
the SPI interface
•
the 4-level interrupt priority system
•
the power-off flag
•
the ONCE mode
•
the ALE disabling
•
some enhanced features are also located in the UART and the timer 2
The T89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages:
•
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
•
Save power consumption while keeping same CPU power (oscillator power saving).
•
Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
•
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description
The clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 4 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1÷2 to avoid glitches when switching from X2 to STD mode. Figure 5 shows
the switching mode waveforms.
Figure 4. Clock Generation Diagram
CKRL
2
XTAL1
FXTAL
FOSC
XTAL1:2
0
1
8 bit Prescaler
FCLK CPU
FCLK PERIPH
X2
CKCON0
11
4105D–8051–10/06
Figure 5. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 bit
FOSC
CPU clock
STD Mode
X2 Mode
STD Mode
The X2 bit in the CKCON0 register (see Table 6) allows a switch from 12 clock periods
per instruction to 6 clock periods and vice versa. At reset, the speed is set according to
X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (See
Table 6.) and SPIX2 bit in the CKCON1 register (see Table 7) allows a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral
speed (6 clock periods per peripheral clock cycle). These bits are active only in X2
mode.
12
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Table 6. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
7
Bit
Mnemonic Description
Reserved
Watchdog Clock
6
WDX2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
5
PCAX2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
4
SIX2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Timer2 Clock
3
T2X2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 Clock
2
T1X2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Timer0 Clock
1
T0X2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this
bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
CPU Clock
0
X2
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and
to enable the individual peripherals’X2’ bits. Programmed by hardware after
Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is
cleared.
Reset Value = 0000 000’HSB. X2’b (See Table 70 “Hardware Security Byte”)
Not bit addressable
13
4105D–8051–10/06
Table 7. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
SPIX2
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
6
-
Reserved
5
-
Reserved
4
-
Reserved
3
-
Reserved
2
-
Reserved
1
-
Reserved
0
SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset Value = XXXX XXX0b
Not bit addressable
14
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Dual Data Pointer
Register DPTR
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 8) that allows the program
code to switch between them (Refer to Figure 6).
Figure 6. Use of Dual Pointer
External Data Memory
7
0
DPS
AUXR1(A2H)
DPTR1
DPTR0
DPH(83H) DPL(82H)
15
4105D–8051–10/06
Table 8. AUXR1 register
AUXR1- Auxiliary Register 1(0A2h)
7
6
5
4
3
2
1
0
-
-
ENBOOT
-
GF3
0
-
DPS
Bit
Bit
Number
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
ENBOOT
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
3
GF3
2
0
Always cleared.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
DPS
This bit is a general purpose user flag. *
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
Reset Value: XXXX XX0X0b
Not bit addressable
Note:
*Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
16
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
17
4105D–8051–10/06
Expanded RAM
(XRAM)
The T89C51RB2/RC2 provides additional Bytes of random access memory (RAM)
space for increased data parameter handling and high level language usage.
T89C51RB2/RC2 devices have expanded RAM in external data space; maximum size
and location are described in Table 9.
Table 9. Expanded RAM
Address
Part Number
T89C51RB2/RC2
XRAM size
Start
End
1024
00h
3FFh
The T89C51RB2/RC2 has internal data memory that is mapped into four separate
segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register (see Table 9).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
Figure 7. Internal and External Data Memory Address
0FFh or 3FFh
0FFh
0FFh
Upper
128 bytes
Internal
Ram
indirect accesses
80h
XRAM
0FFFFh
Special
Function
Register
direct accesses
External
Data
Memory
80h
7Fh
Lower
128 bytes
Internal
Ram
direct or indirect
accesses
00
00
00FFh up to 03FFh
0000
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•
18
Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
•
Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
•
The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 9. This can be
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
•
With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done by the use of
DPTR.
•
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-order eight address bits (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and
MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7
(RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
19
4105D–8051–10/06
Registers
Table 10. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
-
-
M0
-
XRS1
XRS0
EXTRAM
AO
Bit
Number
Bit
Mnemonic Description
7
-
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Pulse length
5
M0
Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock
periods.
4
-
3
XRS1
2
XRS0
Reserved
The value read from this bit is indeterminate. Do not set this bit.
XRAM Size
XRS1
0
XRS0
0
XRAM size
256 bytes (default)
0
1
512 bytes
1
0
768 bytes
1
1
1024 bytes
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
1
EXTRAM
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
0
AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
Reset Value = XX0X 00’HSB. XRAM’0b (See Table 70)
Not bit addressable
20
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Timer 2
The Timer 2 in the T89C51RB2/RC2 is the standard C52 Timer 2.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2 are cascaded. It is controlled by T2CON (Table 11) and T2MOD (Table 12)
registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects F OSC/12
(timer operation) or external pin T2 (counter operation) as the timer clock input. Setting
TR2 allows TL2 to increment by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
Auto-Reload Mode
•
Auto-reload mode with up or down counter
•
Programmable clock-output
The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to
the Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as
an Up/down timer/counter as shown in Figure 8. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of
the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit
resolution.
21
4105D–8051–10/06
Figure 8. Auto-Reload Mode Up/Down Counter (DCEN = 1)
FCLK PERIPH
:6
0
1
T2
C/T2
TR2
T2CON
T2CON
T2EX:
(DOWN COUNTING RELOAD VALUE)
if DCEN=1, 1=UP
FFh
FFh
if DCEN=1, 0=DOWN
(8-bit)
(8-bit)
if DCEN = 0, up counting
TOGGLE
T2CON
EXF2
TL2
TH2
(8-bit)
(8-bit)
TIMER 2
INTERRUPT
TF2
T2CON
RCAP2L
(8-bit)
RCAP2H
(8-bit)
(UP COUNTING RELOAD VALUE)
Programmable ClockOutput
In the clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 9). The input clock increments TL2 at frequency FCLK PERIPH/2.The
timer repeatedly counts to overflow from a loaded value. At overflow, the contents of
RCAP2H and RCAP2L registers are loaded into TH2 and TL2.In this mode, Timer 2
overflows do not generate interrupts. The formula gives the clock-out frequency as a
function of the system oscillator frequency and the value in the RCAP2H and RCAP2L
registers:
Clock –O utFrequency
F CLKPERIPH
= --------------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L )
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(FCLK PERIPH/216) to 4 MHz (FCLK PERIPH/4). The generated clock signal is brought out to
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
•
Set T2OE bit in T2MOD register.
•
Clear C/T2 bit in T2CON register.
•
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•
Enter a 16-bit initial value in timer registers TH2/TL2.It can be the same as the
reload value or a different one depending on the application.
•
To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
22
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Figure 9. Clock-Out Mode C/T2 = 0
FCLK PERIPH
:6
TR2
T2CON
TL2
(8-bit)
TH 2
(8-bit)
OVERFLOW
RCAP2L RCAP2H
(8-bit) (8-bit)
Toggle
T2
Q
D
T2OE
T2MOD
T2EX
EXF2
EXEN2
T2CON
T2CON
TIMER 2
INTERRUPT
23
4105D–8051–10/06
Registers
Table 11. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
7
Bit
Mnemonic Description
TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1).
5
RCLK
Receive Clock bit
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
2
TR2
1
0
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0
for clock out mode.
CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
24
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Table 12. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
T2OE
DCEN
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
T2OE
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0
DCEN
Down Counter Enable bit
Cleared to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
Reset Value = XXXX XX00b
Not bit addressable
25
4105D–8051–10/06
Programmable
Counter Array PCA
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture modules. Its clock input can be programmed to count
any one of the following signals:
•
÷6
Peripheral clock frequency (FCLK PERIPH) ÷ 2
•
Timer 0 overflow
•
External input on ECI (P1.2)
•
Peripheral clock frequency (FCLK PERIPH)
Each compare/capture modules can be programmed in any one of the following modes:
•
rising and/or falling edge capture
•
software timer
•
high-speed output
•
pulse width modulator
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog
Timer", page 37).
When the compare/capture modules are programmed in the capture mode, software
timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If the port is not used for the PCA, it can still be used for
standard I/O.
PCA component
External I/O Pin
16-bit Counter
P1.2 / ECI
16-bit Module 0
P1.3 / CEX0
16-bit Module 1
P1.4 / CEX1
16-bit Module 2
P1.5 / CEX2
16-bit Module 3
P1.6 / CEX3
The PCA timer is a common time base for all five modules (See Figure 10). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 13) and can be programmed to run at:
26
•
1/6 the peripheral clock frequency (FCLK PERIPH)
•
1/2 the peripheral clock frequency (FCLK PERIPH)
•
The Timer 0 overflow
•
The input on the ECI pin (P1.2)
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Figure 10. PCA Timer/Counter
To PCA
modules
Fclk periph /6
overflow
Fclk periph / 2
CH
T0 OVF
It
CL
16 bit up/down counter
P1.2
CIDL
WDTE
CF
CR
CPS1
CPS0
ECF
CCF2
CCF1 CCF0
CMOD
0xD9
Idle
CCF4 CCF3
CCON
0xD8
27
4105D–8051–10/06
Registers
Table 13. CMOD Register
CMOD - PCA Counter Mode Register (D9h)
7
6
5
4
3
2
1
0
CIDL
WDTE
-
-
-
CPS1
CPS0
ECF
Bit
Number
Bit
Mnemonic Description
Counter Idle Control
7
CIDL
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
Watchdog Timer Enable
6
WDTE
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
CPS1
PCA Count Pulse Select
CPS1 CPS0 Selected PCA input
0
0
Internal clock fCLK PERIPH/6
1
0
CPS0
ECF
0
1
1
0
Internal clock fCLK PERIPH/2
Timer 0 Overflow
1
1
External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4)
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
Reset Value = 00XX X000b
Not bit addressable
The CMOD register includes three additional bits associated with the PCA (See
Figure 10 and Table 13).
•
The CIDL bit which allows the PCA to stop during idle mode.
•
The WDTE bit which enables or disables the watchdog function on module 4.
•
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and each module (Refer to Table 14).
28
•
Bit CR (CCON. 6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
•
Bit CF: The CF bit (CCON. 7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
•
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc. ) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Table 14. CCON Register
CCON - PCA Counter Control Register (D8h)
7
6
5
4
3
2
1
0
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Number
Bit
Mnemonic Description
PCA Counter Overflow flag
7
CF
6
CR
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF may be set by either hardware or software but can only be
cleared by software.
PCA Counter Run control bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
5
-
4
CCF4
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Module 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 3 interrupt flag
3
CCF3
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 2 interrupt flag
2
CCF2
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 1 interrupt flag
1
CCF1
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 0 interrupt flag
0
CCF0
Must be cleared by software.
Set by hardware when a match or capture occurs.
Reset Value = 000X 0000b
Not bit addressable
The watchdog timer function is implemented in module 4 (See Figure 13).
The PCA interrupt system is shown in Figure 11.
29
4105D–8051–10/06
Figure 11. PCA Interrupt System
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
CCON
0xD8
PCA Timer/Counter
Module 0
Module 1
To Interrupt
priority decoder
Module 2
Module 3
Module 4
CMOD. 0 ECF
ECCFn CCAPMn. 0
IE. 6
EC
IE. 7
EA
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:
•
16-bit Capture, positive-edge triggered
•
16-bit Capture, negative-edge triggered
•
16-bit Capture, both positive and negative-edge triggered
•
16-bit Software Timer
•
16-bit High Speed Output
•
8-bit Pulse Width Modulator
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 15). The
registers contain the bits that control the mode that each module will operate in.
•
The ECCF bit (CCAPMn. 0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module.
•
PWM (CCAPMn. 1) enables the pulse width modulation mode.
•
The TOG bit (CCAPMn. 2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the module's
capture/compare register.
•
The match bit MAT (CCAPMn. 3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the module's
capture/compare register.
•
The next two bits CAPN (CCAPMn. 4) and CAPP (CCAPMn. 5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
•
The last bit in the register ECOM (CCAPMn. 6) when set enables the comparator
function.
Table 15 shows the CCAPMn settings for the various PCA functions.
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T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Table 15. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
7
6
5
4
3
2
1
0
-
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Bit
Number
Bit
Mnemonic Description
7
-
6
ECOMn
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
Capture Positive
5
CAPPn
4
CAPNn
Cleared to disable positive edge capture.
Set to enable positive edge capture.
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
Match
3
MATn
2
TOGn
1
PWMn
When MATn = 1, a match of the PCA counter with this module's
compare/capture register causes the CCFn bit in CCON to be set, flagging an
interrupt.
Toggle
When TOGn = 1, a match of the PCA counter with this module's
compare/capture register causes theCEXn pin to toggle.
Pulse Width Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
Enable CCF interrupt
0
CCF0
Cleared to disable compare/capture flag CCFn in the CCON register to generate
an interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Reset Value = X000 0000b
Not bit addressable
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4105D–8051–10/06
Table 16. PCA Module Modes (CCAPMn Registers)
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMm
ECCFn
Module Function
0
0
0
0
0
0
0
No Operation
X
1
0
0
0
0
X
16-bit capture by a positive-edge
trigger on CEXn
X
0
1
0
0
0
X
16-bit capture by a negative trigger
on CEXn
X
1
1
0
0
0
X
16-bit capture by a transition on
CEXn
1
0
0
1
0
0
X
16-bit Software Timer / Compare
mode.
1
0
0
1
1
0
X
16-bit High Speed Output
1
0
0
0
0
1
0
8-bit PWM
1
0
0
1
X
0
X
Watchdog Timer (module 4 only)
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output (See Table 17 &
Table 18).
Table 17. CCAPnH Registers (n = 0-4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
7-0
Bit
Mnemonic Description
-
PCA Module n Compare/Capture Control
CCAPnH Value
Reset Value = 0000 0000b
Not bit addressable
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4105D–8051–10/06
T89C51RB2/RC2
Table 18. CCAPnL Registers (n = 0-4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
7-0
Bit
Mnemonic Description
-
PCA Module n Compare/Capture Control
CCAPnL Value
Reset Value = 0000 0000b
Not bit addressable
Table 19. CH Register
CH - PCA Counter Register High (0F9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
7-0
Bit
Mnemonic Description
-
PCA counter
CH Value
Reset Value = 0000 0000b
Not bit addressable
Table 20. CL Register
CL - PCA Counter Register Low (0E9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
7-0
Bit
Mnemonic Description
-
PCA Counter
CL Value
Reset Value = 0000 0000b
Not bit addressable
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4105D–8051–10/06
PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM
bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module's
capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(Refer to Figure 12).
Figure 12. PCA Capture Mode
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0 CCON
0xD8
PCA IT
PCA Counter/Timer
Cex. n
CH
CL
CCAPnH
CCAPnL
Capture
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4
0xDA to 0xDE
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T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
16-bit Software Timer/
Compare Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT
bits in the modules CCAPMn register. The PCA timer will be compared to the module's
capture registers and when a match occurs, an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 13).
Figure 13. PCA Compare Mode and PCA Watchdog Timer
CCON
CF
Write to
CCAPnL
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Reset
PCA IT
Write to
CCAPnH
1
CCAPnH
0
CCAPnL
Enable
Match
16 bit comparator
CH
RESET *
CL
PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CIDL
WDTE
CPS1 CPS0
ECF
CCAPMn, n = 0 to 4
0xDA to 0xDE
CMOD
0xD9
* Only for Module 4
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
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4105D–8051–10/06
High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (See Figure 14).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
Figure 14. PCA High Speed Output Mode
CCON
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Write to
CCAPnL Reset
PCA IT
Write to
CCAPnH
1
CCAPnH
0
CCAPnL
Enable
16 bit comparator
CH
Match
CL
CEXn
PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4
0xDA to 0xDE
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
36
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Pulse Width Modulator
Mode
All of the PCA modules can be used as PWM outputs. Figure 15 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the
modules will have the same frequency of output because they all share the PCA timer.
The duty cycle of each module is independently variable using the module's capture
register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output
will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in
the module's CCAPMn register must be set to enable the PWM mode.
Figure 15. PCA PWM Mode
CCAPnH
Overflow
CCAPnL
“0”
CEXn
Enable
8 bit comparator
“1”
CL
PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n= 0 to 4
0xDA to 0xDE
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA module that can be programmed as a watchdog. However, this module can still be
used for other modes if the watchdog is not needed. Figure 13 shows a diagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven high.
In order to hold off the reset, the user has three options:
•
periodically change the compare value so it will never match the PCA timer,
•
periodically change the PCA timer value so it will never match the compare values,
or
•
disable the watchdog by clearing the WDTE bit before a match occurs and then reenable it.
The first two options are more reliable because the watchdog timer is never disabled as
in option #3.If the program counter ever goes astray, a match will eventually occur and
37
4105D–8051–10/06
cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
38
T89C51RB2/RC2
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T89C51RB2/RC2
Serial I/O Port
The serial I/O port in the T89C51RB2/RC2 is compatible with the serial I/O port in the
80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
Framing Error Detection
•
Framing error detection
•
Automatic address recognition
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 16).
Figure 16. Framing Error Block Diagram
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD0 = 0)
SMOD1SMOD0
-
POF
GF1
GF0
PD
IDL
PCON (87h)
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 24.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 17. and Figure 18.).
Figure 17. UART Timings in Mode 1
RXD
D0
Start
bit
D1
D2
D3
D4
Data byte
D5
D6
D7
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
39
4105D–8051–10/06
Figure 18. UART Timings in Modes 2 and 3
RXD
D0
Start
bit
D1
D2
D3
D4
Data byte
D5
D6
D7
D8
Ninth Stop
bit
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, the user may enable the automatic address recognition feature in mode 1.In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the device’s address and is terminated
by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Given Address
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t-care bits (defined by zeros) to form the
device’s given address. The don’t-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
40
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To communicate with slave A only, the master must send an address where bit 0 is clear (e. g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e. g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e. g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e. g. :
SADDR0101 0110b
SADEN1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and
broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
41
4105D–8051–10/06
Registers
Table 21. SADEN Register
SADEN - Slave Address Mask Register (B9h)
7
6
5
4
3
2
1
0
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
Table 22. SADDR Register
SADDR - Slave Address Register (A9h)
7
6
5
4
Reset Value = 0000 0000b
Not bit addressable
Baud Rate Selection for
UART for Mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
Figure 19. Baud Rate Selection
TIMER1
TIMER2
0
TIMER_BRG_RX
0
1
/ 16
Rx Clock
1
RCLK
RBCK
INT_BRG
TIMER1
TIMER2
0
1
TIMER_BRG_TX
0
1
/ 16
Tx Clock
TCLK
INT_BRG
42
TBCK
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Table 23. Baud Rate Selection Table UART
Internal Baud Rate Generator
(BRG)
TCLK
RCLK
TBCK
RBCK
Clock Source
Clock Source
(T2CON)
(T2CON)
(BDRCON)
(BDRCON)
UART Tx
UART Rx
0
0
0
0
Timer 1
Timer 1
1
0
0
0
Timer 2
Timer 1
0
1
0
0
Timer 1
Timer 2
1
1
0
0
Timer 2
Timer 2
X
0
1
0
INT_BRG
Timer 1
X
1
1
0
INT_BRG
Timer 2
0
X
0
1
Timer 1
INT_BRG
1
X
0
1
Timer 2
INT_BRG
X
X
1
1
INT_BRG
INT_BRG
When the internal Baud Rate Generator is used, the Baud Rates are determined by the
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
Figure 20. Internal Baud Rate
CLK PERIPH
0
/6
auto reload counter
overflow
BRG
/2
1
SPD
0
INT_BRG
1
BRL
SMOD1
BRR
•
The baud rate for UART is token by formula:
Baud_Rate
=
2SMOD1 x FCLK PERIPH
2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)]
(BRL) = 256 -
2SMOD1 x FCLK PERIPH
2 x 2 x 6(1-SPD) x 16 x Baud_Rate
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4105D–8051–10/06
Table 24. SCON Register
SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic
Description
Framing Error bit (SMOD0=1)
7
FE
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
6
SM1
Serial port Mode bit 1
SM0 SM1 Mode Description
Baud Rate
0
0
1
0
1
0
0
1
2
Shift Register
8-bit UART
9-bit UART
FCPU PERIPH/6
Variable
FCPU PERIPH /32 or /16
1
1
3
9-bit UART
Variable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
5
SM2
4
REN
3
TB8
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
2
RB8
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
1
0
TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning
of the stop bit in the other modes.
RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 17.
and Figure 18. in the other modes.
Reset Value = 0000 0000b
Bit addressable
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T89C51RB2/RC2
Table 25. Example of Computed Value When X2=1, SMOD1=1, SPD=1
Baud Rates
FOSC = 16. 384 MHz
FOSC = 24MHz
BRL
Error (%)
BRL
Error (%)
115200
247
1.23
243
0.16
57600
238
1.23
230
0.16
38400
229
1.23
217
0.16
28800
220
1.23
204
0.16
19200
203
0.63
178
0.16
9600
149
0.31
100
0.16
4800
43
1.23
-
-
Table 26. Example of Computed Value When X2=0, SMOD1=0, SPD=0
Baud Rates
FOSC = 16. 384 MHz
FOSC = 24MHz
BRL
Error (%)
BRL
Error (%)
4800
247
1.23
243
0.16
2400
238
1.23
230
0.16
1200
220
1.23
202
3.55
600
185
0.16
152
0.16
The baud rate generator can be used for mode 1 or 3 (refer to Figure 19.), but also for
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 33.)
UART Registers
Table 27. SADEN Register
SADEN - Slave Address Mask Register for UART (B9h)
7
6
5
4
3
2
1
0
2
1
0
Reset Value = 0000 0000b
Table 28. SADDR Register
SADDR - Slave Address Register for UART (A9h)
7
6
5
4
3
Reset Value = 0000 0000b
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4105D–8051–10/06
Table 29. SBUF Register
SBUF - Serial Buffer Register for UART (99h)
7
6
5
4
3
2
1
0
Reset Value = XXXX XXXXb
Table 30. BRL Register
BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
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T89C51RB2/RC2
Table 31. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic
7
TF2
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
5
RCLK
Receive Clock bit for UART
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
2
TR2
1
0
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH ).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
timer 2 overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
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4105D–8051–10/06
Table 32. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic
7
SMOD1
6
SMOD0
5
-
4
POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Description
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
48
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T89C51RB2/RC2
Table 33. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
6
5
4
3
2
1
0
-
-
-
BRR
TBCK
RBCK
SPD
SRC
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3
TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2
RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1
SPD
Description
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART
0
SRC
Cleared to select FOSC /12 as the Baud Rate Generator (FCLK PERIPH/6 in X2
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = XXX0 0000b
Not bit addressablef
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Interrupt System
The T89C51RB2/RC2 has a total of 10 interrupt vectors: two external interrupts (INT0
and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in
Figure 21.
Figure 21. Interrupt Control System
High priority
interrupt
IPH, IPL
3
INT0
IE0
0
3
TF0
0
3
INT1
IE1
0
3
Interrupt
polling
sequence, decreasing from
high to low priority
TF1
0
3
PCA IT
0
RI
TI
3
TF2
EXF2
3
0
0
3
KBD IT
0
3
SPI IT
0
Individual Enable
Global Disable
Low priority
interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 38 and Table 36). This register also
contains a global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 39) and in the
Interrupt Priority High register (Table 37 and Table 38) shows the bit values and priority
levels associated with each combination.
50
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Registers
The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located
at address 0043H and Keyboard interrupt vector is located at address 004BH. All other
vectors addresses are the same as standard C52 devices.
Table 34. Priority Level Bit Values
IPH. x
IPL. x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
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4105D–8051–10/06
Table 35. IEO Register
IE0 - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic Description
7
EA
6
EC
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
PCA interrupt enable bit
Cleared to disable.
Set to enable.
5
ET2
Timer 2 overflow interrupt Enable bit
Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4
ES
Serial port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
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T89C51RB2/RC2
Table 36. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
7
6
5
4
3
2
1
0
-
PPCL
PT2L
PSL
PT1L
PX1L
PT0L
PX0L
Bit
Number
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
-
6
PPCL
PCA interrupt Priority bit
Refer to PPCH for priority level.
5
PT2L
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4
PSL
Serial port Priority bit
Refer to PSH for priority level.
3
PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2
PX1L
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1
PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0
PX0L
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = X000 0000b
Bit addressable
53
4105D–8051–10/06
Table 37. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PPCH
PCA interrupt Priority high bit.
PPCH PPCL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT2H
Timer 2 overflow interrupt Priority High bit
PT2H PT2L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PSH
Serial port Priority High bit
PSH
PSL
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX1H
External interrupt 1 Priority High bit
PX1H PX1L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX0H
External interrupt 0 Priority High bit
PX0H PX0L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = X000 0000b
Not bit addressable
54
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T89C51RB2/RC2
Table 38. IE1 Register
IE1 - Interrupt Enable Register (B1h)
7
6
5
4
3
2
1
0
-
-
-
-
-
SPI
-
KBD
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
6
-
Reserved
5
-
Reserved
4
-
Reserved
3
-
Reserved
2
SPI
SPI interrupt Enable bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1
-
0
KBD
Reserved
Keyboard interrupt Enable bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
Reset Value = XXXX X000b
Bit addressable
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Table 39. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
7
6
5
4
3
2
1
0
-
-
-
-
-
SPIL
-
KBDL
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
SPIL
1
-
0
KBDL
SPI interrupt Priority bit
Refer to SPIH for priority level.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Keyboard interrupt Priority bit
Refer to KBDH for priority level.
Reset Value = XXXX X000b
Bit addressable
56
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T89C51RB2/RC2
Table 40. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
7
6
5
4
3
2
1
0
-
-
-
-
-
SPIH
-
KBDH
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
SPIH
1
-
0
KBDH
SPI interrupt Priority High bit
SPIH
SPIL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Keyboard interrupt Priority High bit
KB DH KBDL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = XXXX X000b
Not bit addressable
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Interrupt Sources and
Vector Addresses
58
Table 41. Interrupt Sources and Vector Addresses
Interrupt
Request
Vector
Number
Polling Priority
Interrupt Source
Address
0
0
Reset
1
1
INT0
IE0
0003h
2
2
Timer 0
TF0
000Bh
3
3
INT1
IE1
0013h
4
4
Timer 1
IF1
001Bh
5
6
UART
RI+TI
0023h
6
7
Timer 2
TF2+EXF2
002Bh
7
5
PCA
CF + CCFn (n = 0-4)
0033h
8
8
Keyboard
KBDIT
003Bh
9
9
SPI
SPIIT
004Bh
0000h
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Keyboard Interface
The T89C51RB2/RC2 implements a keyboard interface allowing the connection of a
8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on
both high or low level. These inputs are available as alternate function of P1 and allow to
exit from idle and power down modes.
The keyboard interface interfaces with the C51 core through 3 special function registers:
KBLS, the Keyboard Level Selection register (Table 44), KBE, The Keyboard interrupt
Enable register (Table 43), and KBF, the Keyboard Flag register (Table 42).
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard interrupt (see Figure 22). As detailed in Figure 23 each keyboard
input has the capability to detect a programmable level according to KBLS. x bit value.
Level detection is then reported in interrupt flags KBF. x that can be masked by software
using KBE. x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage
of P1 inputs for other purpose.
Figure 22. Keyboard Interface Block Diagram
Vcc
0
P1:x
KBF. x
1
Internal Pullup
KBE. x
KBLS. x
Figure 23. Keyboard Input Circuitry
P1.0
Input Circuitry
P1.1
Input Circuitry
P1.2
Input Circuitry
P1.3
Input Circuitry
P1.4
Input Circuitry
P1.5
Input Circuitry
P1.6
Input Circuitry
P1.7
Input Circuitry
KBDIT
Power Reduction Mode
KBD
IE1
Keyboard Interface
Interrupt Request
P1 inputs allow exit from idle and power down modes as detailed in Section “Powerdown Mode”, page 76.
59
4105D–8051–10/06
Registers
Table 42. KBF Register
KBF-Keyboard Flag Register (9Eh)
7
6
5
4
3
2
1
0
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
KBF7
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set.
Must be cleared by software.
KBF6
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set.
Must be cleared by software.
KBF5
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 5 bit in KBIE register is set.
Must be cleared by software.
KBF4
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 4 bit in KBIE register is set.
Must be cleared by software.
KBF3
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 3 bit in KBIE register is set.
Must be cleared by software.
KBF2
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 2 bit in KBIE register is set.
Must be cleared by software.
KBF1
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set.
Must be cleared by software.
KBF0
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set.
Must be cleared by software.
Reset Value= 0000 0000b
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T89C51RB2/RC2
Table 43. KBE Register
KBE-Keyboard Input Enable Register (9Dh)
7
6
5
4
3
2
1
0
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
Bit
Number
Bit
Mnemonic Description
7
KBE7
Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 7 bit in KBF register to generate an interrupt request.
6
KBE6
Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 6 bit in KBF register to generate an interrupt request.
5
KBE5
Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 5 bit in KBF register to generate an interrupt request.
4
KBE4
Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 4 bit in KBF register to generate an interrupt request.
3
KBE3
Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 3 bit in KBF register to generate an interrupt request.
2
KBE2
Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 2 bit in KBF register to generate an interrupt request.
1
KBE1
Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 1 bit in KBF register to generate an interrupt request.
0
KBE0
Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 0 bit in KBF register to generate an interrupt request.
Reset Value= 0000 0000b
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4105D–8051–10/06
Table 44. KBLS Register
KBLS-Keyboard Level Selector Register (9Ch)
7
6
5
4
3
2
1
0
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
Bit
Number
Bit
Mnemonic Description
7
KBLS7
Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
6
KBLS6
Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
5
KBLS5
Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
4
KBLS4
Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
3
KBLS3
Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
2
KBLS2
Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
1
KBLS1
Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0
KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Reset Value= 0000 0000b
62
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T89C51RB2/RC2
Serial Port Interface
(SPI)
The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial
communication between the MCU and peripheral devices, including other MCUs.
Features
Features of the SPI module include the following:
Signal Description
•
Full-duplex, three-wire synchronous transfers
•
Master or Slave operation
•
Eight programmable Master clock rates
•
Serial clock with programmable polarity and phase
•
Master Mode fault error flag with MCU interrupt capability
•
Write collision flag protection
Figure 20 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices:
Figure 24. SPI Master/Slaves interconnection
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
VDD
Slave 4
Slave 3
MISO
MOSI
SCK
SS
0
1
2
3
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
Master
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
Master Output Slave Input
(MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output
(MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out the devices
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one byte on the serial lines.
Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
low for any message for a Slave. It is obvious that only one Master (SS high level) can
63
4105D–8051–10/06
drive the network. The Master may select each Slave device by software through port
pins (Figure 20). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (See Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general purpose if the following conditions are met:
•
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set(1).
•
The Device is configured as a Slave with CPHA and SSDIS control bits set (2) This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Note:
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in
this mode, the SS is used to start the transmission.
Baud rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is
chosen from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 45 gives the different clock rates selected by SPR2:SPR1:SPR0:
Table 45. SPI Master Baud Rate Selection
64
SPR2
SPR1
SPR0
Clock Rate
Baud rate divisor (BD)
0
0
0
FCLK PERIPH /2
2
0
0
1
FCLK PERIPH /4
4
0
1
0
FCLK PERIPH / 8
8
0
1
1
FCLK PERIPH /16
16
1
0
0
FCLK PERIPH /32
32
1
0
1
FCLK PERIPH /64
64
1
1
0
FCLK PERIPH /128
128
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T89C51RB2/RC2
Functional Description
Figure 25 shows a detailed structure of the SPI module.
Figure 25. SPI Module Block Diagram
Internal Bus
SPDAT
FCLK PERIPH
Clock
Divider
/2
/4
/8
/16
/32
/64
/128
Shift Register
7
6
5
4
3
2
1
0
Receive Data Register
Pin
Control
Logic
Clock
Logic
MOSI
MISO
M
S
Clock
Select
SCK
SS
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI Interrupt Request
SPI
Control
8-bit bus
1-bit signal
SPSTA
SPIF WCOL
Operating Modes
-
MODF
-
-
-
-
The Serial Peripheral Interface can be configured as one of the two modes: Master
mode or Slave mode. The configuration and initialization of the SPI module is made
through one register:
•
The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
•
SPCON
•
The Serial Peripheral STAtus register (SPSTA)
•
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 26).
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Figure 26. Full-Duplex Master-Slave Interconnection
8-bit Shift register
SPI
Clock Generator
MISO
MISO
MOSI
MOSI
SCK
SS
Master MCU
8-bit Shift register
SCK
VDD
SS
VSS
Slave MCU
Master mode
The SPI operates in Master mode when the Master bit, MSTR (1) , in the SPCON register
is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the byte is immediately transferred to the shift
register. The byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin.
The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA
becomes set. At the same time that SPIF becomes set, the received byte from the Slave
is transferred to the receive data register in SPDAT. Software clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
Slave mode
The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to’0’. SS must remain low until the transmission is complete.
In a Slave SPI module, data enters the shift register under the control of the SCK from
the Master SPI module. After a byte enters the shift register, it is immediately transferred
to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow
condition, Slave software must then read the SPDAT before another byte enters the
shift register (3). A Slave SPI must complete the write to the SPDAT (shift register) at
least one bus cycle before the Master SPI starts a transmission. If the write to the data
register is late, the SPI transmits the data already in the shift register from the previous
transmission.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock POLarity (CPOL (4) ) and the Clock PHAse
(CPHA4). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 22 and Figure 23).
The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
1.
The SPI module should be configured as a Master before it is enabled (SPEN set). Also
the Master SPI should be configured before the Slave SPI.
2.
3.
The SPI module should be configured as a Slave before it is enabled (SPEN set).
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).
4.
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T89C51RB2/RC2
Figure 27. Data Transmission Format (CPHA = 0)
SCK cycle number
1
2
3
4
5
6
7
8
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MISO (from Slave)
MSB
SS (to Slave)
Capture point
Figure 28. Data Transmission Format (CPHA = 1)
1
2
3
4
5
6
7
8
MOSI (from Master)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
MISO (from Slave)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
SCK cycle number
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
LSB
SS (to Slave)
Capture point
Figure 29. CPHA/SS Timing
MISO/MOSI
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA = 0)
Slave SS
(CPHA = 1)
As shown in Figure 28, the first SCK edge is the MSB capture strobe. Therefore the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each byte transmitted (Figure 25).
Figure 29 shows an SPI transmission in which CPHA is’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 24). This format may be preferable in systems having only one Master and
only one Slave driving the MISO data line.
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Error conditions
The following flags in the SPSTA signal SPI error conditions:
Mode Fault (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)
pin is inconsistent with the actual mode of the device. MODF is set to warn that there
may have a multi-master conflict for system control. In this case, the SPI system is
affected in the following ways:
•
An SPI receiver/error CPU interrupt request is generated,
•
The SPEN bit in SPCON is cleared. This disable the SPI,
•
The MSTR bit in SPCON is cleared
When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal becomes’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master
device is pulled low, there is no way that another Master attempt to drive the network. In
this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the
SPCON register and therefore making the SS pin as a general purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set,
followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.
Write Collision (WCOL)
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA
and an access to SPDAT.
Overrun Condition
An overrun condition occurs when the Master device tries to send several data bytes
and the Slave devise has not cleared the SPIF bit issuing from the previous data byte
transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
Interrupts
Two SPI status flags can generate a CPU interrupt requests:
Table 46. SPI Interrupts
Flag
Request
SPIF (SP data transfer)
SPI Transmitter Interrupt request
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (if SSDIS =’0’)
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests.
Figure 30 gives a logical view of the above statements.
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T89C51RB2/RC2
Figure 30. SPI Interrupt Requests Generation
SPIF
SPI Transmitter
CPU Interrupt Request
SPI
CPU Interrupt Request
MODF
SPI Receiver/error
CPU Interrupt Request
SSDIS
Registers
There are three registers in the module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
Serial Peripheral Control
register (SPCON)
•
The Serial Peripheral Control Register does the following:
•
Selects one of the Master clock rates,
•
Configure the SPI module as Master or Slave,
•
Selects serial clock polarity and phase,
•
Enables the SPI module,
•
Frees the SS pin for a general purpose
Table 47 describes this register and explains the use of each bit.
Table 47. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit Number
Bit Mnemonic
7
SPR2
6
SPEN
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
5
SSDIS
5
MSTR
Cleared to enable SS# in both Master and Slave modes.
Set to disable SS# in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
4
CPOL
Cleared to have the SCK set to’0’ in idle state.
Set to have the SCK set to’1’ in idle low.
Clock Phase
3
CPHA
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
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Bit Number
Bit Mnemonic
2
SPR1
1
SPR0
Description
SPR2
SPR1
0
0
0
FCLK PERIPH /2
0
0
1
FCLK PERIPH /4
0
1
0
FCLK PERIPH /8
0
1
1
FCLK PERIPH /16
1
0
0
FCLK PERIPH /32
1
0
1
FCLK PERIPH /64
1
1
0
FCLK PERIPH /128
1
1
1
Invalid
SPR0 Serial Peripheral Rate
Reset Value= 0001 0100b
Not bit addressable
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
•
Data transfer complete
•
Write collision
•
Inconsistent logic level on SS pin (mode fault error)
Table 48 describes the SPSTA register and explains the use of every bit in the register.
Table 48. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
7
6
5
4
3
2
1
0
SPIF
WCOL
-
MODF
-
-
-
-
Bit
Number
Bit
Mnemonic Description
Serial Peripheral data transfer flag
7
SPIF
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision flag
6
WCOL
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Mode Fault
4
MODF
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
70
3
-
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Bit
Number
Bit
Mnemonic Description
1
-
0
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value= 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa register
(SPDAT)
The Serial Peripheral Data Register (Table 49) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 49. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
Reset Value= Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there
is no on-going exchange. However, special care should be taken when writing to them
while a transmission is on-going:
•
Do not change SPR2, SPR1 and SPR0
•
Do not change CPHA and CPOL
•
Do not change MSTR
•
Clearing SPEN would immediately disable the peripheral
•
Writing to the SPDAT will cause an overflow
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Hardware Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where T CLK PERIPH= 1/FCLK
PERIPH. To make the best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out
capability, ranking from 16ms to 2s @ FOSCA = 12MHz. To manage this feature, refer to
WDTPRG register description, Table 50.
Table 50. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
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Table 51. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
7
6
5
4
3
2
1
0
-
-
-
-
-
S2
S1
S0
Bit
Number
Bit
Mnemonic Description
7
-
6
-
5
-
4
-
3
-
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Selected Time-out
(214 - 1) machine cycles, 16. 3 ms @ FOSCA =12 MHz
(215 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
(216 - 1) machine cycles, 65. 5 ms @ FOSCA =12 MHz
(217 - 1) machine cycles, 131 ms @ FOSCA=12 MHz
(218 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
(219 - 1) machine cycles, 542 ms @ FOSCA=12 MHz
(220 - 1) machine cycles, 1.05 s @ FOSCA =12 MHz
(221 - 1) machine cycles, 2.09 s @ FOSCA =12 MHz
Reset value XXXX X000
WDT During Power Down In Power Down mode the oscillator stops, which means the WDT also stops. While in
Power Down mode the user does not need to service the WDT. There are 2 methods of
and Idle
exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited
with hardware reset, servicing the WDT should occur as it normally should whenever the
T89C51RB2/RC2 is reset. Exiting Power Down with an interrupt is significantly different.
The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is better to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
T89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
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ONCE™ Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using T89C51RB2/RC2
without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the T89C51RB2/RC2; the following sequence must be exercised:
•
Pull ALE low while the device is in reset (RST high) and PSEN is high.
•
Hold ALE low as RST is deactivated.
While the T89C51RB2/RC2 is in ONCE mode, an emulator or test CPU can be used to
drive the circuit. The following table shows the status of the port pins during ONCE
mode.
Normal operation is restored when normal reset is applied.
Table 52. External Pin Status during ONCE Mode
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
XTAL1/2
Weak pull-up
Weak pull-up
Float
Weak pull-up
Weak pull-up
Weak pull-up
Active
"Once" is a registered trademark of Intel Corporation.
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T89C51RB2/RC2
Power Management
Two power reduction modes are implemented in the T89C51RB2/RC2: the Idle mode
and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be
dynamically divided by 2 using the X2 mode detailed in Section “Clock”.
Reset
A reset is required after applying power at turn-on. To achieve a valid reset, the reset
signal must be maintained for at least 2 machine cycles (24 oscillator clock periods)
while the oscillator is running and stabilized and VCC established within the specified
operating ranges. A device reset initializes the T89C51RB2/RC2 and vectors the CPU
to address 0000h. RST input has a pull-down resistor allowing power-on reset by simply
connecting an external capacitor to VDD as shown in Figure 31. Resistor value and input
c h a r a c t e r i s ti c s a r e d i s c u s s e d i n t h e S e c t i o n “ D C C h a r a c t e r i s t ic s ” o f th e
T89C51RB2/RC2 datasheet. The status of the Port pins during reset is detailed in
Table 53.
Figure 31. Reset Circuitry and Power-On Reset
VDD
To CPU core
and peripherals
+
R
RST
RST
RST
VSS
a. RST input circuitry
b. Power-on Reset
Table 53. Pin Conditions in Special Operating Modes
Reset Recommendation
to Prevent Flash
Corruption
Mode
Port 0
Port 1
Port 2
Port 3
Port 4
ALE
PSEN#
Reset
Floating
High
High
High
High
High
High
Idle
Data
Data
Data
Data
Data
High
High
PowerDown
Data
Data
Data
Data
Data
Low
Low
A bad reset sequence will lead to bad microcontroller initialization and system registers
like SFR’s, Program Counter, etc. will not be correctly initialized. A bad initialization may
lead to unpredictable behaviour of the C51 microcontroller.
An example of this situation may occur in an instance where the bit ENBOOT in AUXR1
register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared inorder to unmap the boot from the code area (yet
due to a bad reset) the bit ENBOOT in SFR’s may be set. If the value of Program
Counter is accidently in the range of the boot memory addresses then a flash access
(write or erase) may corrupt the Flash on-chip memory .
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage(power
supply failure, power supply switched off).
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Idle Mode
An instruction that sets PCON. 0 indicates that it is the last instruction to be executed
before going into Idle mode. In Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logical states they had at the time Idle was activated. ALE and PSEN hold at logic high
level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will
cause PCON. 0 to be cleared by hardware, terminating the Idle mode. The interrupt will
be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during idle. For example, an instruction that activates idle can
also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a power-down mode can be invoked by software (refer to
Table 5, PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked powerdown mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from powerdown. To properly terminate power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from
power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power down mode, 1024
clocks are necessary to exit to power down mode and enter in operating mode.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 32. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the first
input will be released. In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will
be the one following the instruction that put T89C51RB2/RC2 into power-down mode.
76
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4105D–8051–10/06
T89C51RB2/RC2
Figure 32. Power-down Exit Waveform
INT0
INT1
XTALA
or
XTALB
Active phase
Power-down phase
Oscillator restart phase
Active phase
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:
If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table shows the state of ports during idle and power-down modes.
Table 54. State of Ports
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Port Data*
Port Data
Port Data
Port Data
Idle
External
1
1
Floating
Port Data
Address
Port Data
Power Down
Internal
0
0
Port Dat*
Port Data
Port Data
Port Data
Power Down
External
0
0
Floating
Port Data
Port Data
Port Data
* Port 0 can force a 0 level. A "one" will leave port floating.
77
4105D–8051–10/06
Power-off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a
“warm start” reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while
VCC is still applied to the device and could be generated for example by an exit from
power-down.
The power-off flag (POF) is located in PCON register (Table 55). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by
software allowing the user to determine the type of reset.
Table 55. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic Description
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
78
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with
external program or data memory. Nevertheless, during internal code execution, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0.As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 56. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
-
-
M0
-
XRS1
XRS0
EXTRAM
AO
Bit
Number
Bit
Mnemonic Description
7
-
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Pulse length
5
M0
Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock
periods.
4
-
3
XRS1
2
XRS0
Reserved
The value read from this bit is indeterminate. Do not set this bit
XRAM Size
XRS1
0
XRS0
0
XRAM size
256 bytes (default)
0
1
512 bytes
1
0
768 bytes
1
1
1024 bytes
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
1
EXTRAM
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
0
AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
79
4105D–8051–10/06
Electrical Characteristics
Absolute Maximum Ratings(*)
Operating Temperature Range ...... 0°C to 70°C (Commercial)
................................................... -40°C to 85°C (Industrial)
Storage Temperature ................................... -65°C to +150°C
Voltage on VCC to VSS...................................-0.5V to + 6. 5V
Note:
*Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Voltage on Any Pin to VSS ...................... -0.5V to VCC + 0.5V
Power Dissipation ........................................................... 1 W(1)
Note:
80
1. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
DC Parameters for Standard Voltage
TA = 0°C to +70°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 40 MHz.
TA = -40°C to +85°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 40 MHz.
Table 57. DC Parameters in Standard Voltage
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except RST, XTAL1,
VIH1
Input High Voltage RST, XTAL1
VOL
VOL1
VOH
VOH1
RRST
Output Low Voltage, ports 1, 2, 3, 4 and 5
Typ
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.3
V
IOL = 100 μA(4)
0.45
V
IOL = 1.6 mA(4)
1.0
V
IOL = 3.5 mA(4)
0.3
V
IOL = 200 μA(4)
0.45
V
IOL = 3.2 mA(4)
1.0
V
IOL = 7. 0 mA(4)
(6)
(6)
Output Low Voltage, port 0, ALE, PSEN
Output High Voltage, ports 1, 2, 3, 4 and 5
Output High Voltage, port 0, ALE, PSEN
RST Pulldown Resistor
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
50
90 (5)
200
kΩ
Test Conditions
IOH = -10 μA
IOH = -30 μA
IOH = -60 μA
VCC = 5V ± 10%
IOH = -200 μA
IOH = -3.2 mA
IOH = -7. 0 mA
VCC = 5V ± 10%
IIL
Logical 0 Input Current ports 1, 2, 3, 4 and 5
-50
μA
Vin = 0.45 V
ILI
Input Leakage Current
±10
μA
0.45V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
and 5
-650
μA
Vin = 2.0 V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
TA = 25°C
IPD
Power Down Current
150
μA
4. 5V < VCC < 5. 5 V(3)
TBD
mA
0.4 Freq (Mhz)
+ 3 mA
mA
0.4 Freq (Mhz)
+ 20 mA
mA
ICCIDLE
ICC
ICCOP1
Power Supply Current on idle mode
100
(7)
Power Supply Current on normal mode
(7)
Power Supply Current Flash programming
(7)
Note: 3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC. ; RST = VSS
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3.The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
81
4105D–8051–10/06
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than
the listed test conditions.
7. For other values, please contact your sales office.
DC Parameters for Low Voltage
TA = 0°C to +70°C; VSS = 0V; VCC = 2.7V to 3.3V; F = 0 to 20 MHz.
TA = -40°C to +85°C; VSS = 0V; VCC = 2.7V to 3.3V; F = 0 to 20 MHz.
Table 58. DC Parameters for Low Voltage
Symbol
Parameter
Min
Typ
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
Test Conditions
VIL
Input Low Voltage
VIH
Input High Voltage except RST, XTAL1
VIH1
Input High Voltage, RST, XTAL1
VOL
Output Low Voltage, ports 1, 2, 3, 4 and 5 (6)
0.45
V
IOL = 0.8 mA(4)
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
0.45
V
IOL = 1.6 mA(4)
VOH
Output High Voltage, ports 1, 2, 3, 4 and 5
0.9 VCC
V
IOH = -10 μA
VOH1
Output High Voltage, port 0, ALE, PSEN
0.9 VCC
V
IOH = -40 μA
IIL
Logical 0 Input Current ports 1, 2, 3
-50
μA
Vin = 0.45 V
ILI
Input Leakage Current
±10
μA
0.45V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3,
-650
μA
Vin = 2.0 V
200
kΩ
10
pF
Fc = 1 MHz
TA = 25°C
50
μA
VCC = 2.5V to 3.5 V(3)
mA
mA
V CC = 3.3 V(1)
VCC = 3.3 V(2)
(5)
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
IPD
Power Down Current
10
ICC
Power Supply Current (7)
TBD
Note:
50
90
(5)
1. Operating ICC is measured with all output pins disconnected; XTALA1 driven with TCLCH, TCHCL = 5 ns (see Figure 36.), VIL =
VSS + 0.5 V,
VIH = V CC - 0.5V; XTAL2 N. C. ; EA = RST = Port 0 = V CC. ICC would be slightly higher if a crystal oscillator used.
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = V CC 0.5V; XTAL2 N. C; Port 0 = VCC; EA = RST = VSS (see Figure 33).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC. ; RST = VSS
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3.The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
82
T89C51RB2/RC2
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T89C51RB2/RC2
7. For other values, please contact your sales office.
Figure 33. ICC Test Condition, Idle Mode
VCC
ICC
VCC
VCC
P0
VCC
RST
(NC)
CLOCK
SIGNAL
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 34. ICC Test Condition, Operating Mode
VCC
ICC
VCC
VCC
P0
RST
EA
XTAL2
XTAL1
VSS
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
Figure 35. ICC Test Condition, Power-Down Mode
VCC
ICC
VCC
VCC
P0
RST
(NC)
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
83
4105D–8051–10/06
Figure 36. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
0.7VCC
0.2VCC-0.1
AC Parameters
Explanation of the AC
Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example: TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA
TA
TA
TA
= 0 to +70°C; VSS = 0V; VCC = 5V ± 10%; M range.
= -40°C to +85°C; VSS = 0V; V CC = 5V ± 10%; M range.
= 0 to +70°C; VSS = 0V; 2.7V < VCC < 3.3V; L range.
= -40°C to +85°C; VSS = 0V; 2.7V < V CC < 3.3V; L range.
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other
outputs = 80 pF. )
Table 59, Table 62 and Table 65 give the description of each AC symbols.
Table 68, Table 65 and Table 67 give for each range the AC parameter.
Table 68, Table 67 and Table 66 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value in
the corresponding column (-M or -L) and use this value in the formula.
Example: TLLIU for -M and 20 MHz, Standard clock.
x = 35 ns
T 50 ns
TCCIV = 4T - x = 165 ns
84
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
External Program Memory
Characteristics
Table 59. Symbol Description
Symbol
T
Parameter
Oscillator clock period
TLHLL
ALE pulse width
TAVLL
Address Valid to ALE
TLLAX
Address Hold After ALE
TLLIV
ALE to Valid Instruction In
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
Table 60. AC Parameters for a Fix Clock
Symbol
-M
Min
-L
Max
Min
Units
Max
T
25
25
ns
TLHLL
35
35
ns
TAVLL
5
5
ns
TLLAX
5
5
ns
TLLIV
65
65
ns
TLLPL
5
5
ns
TPLPH
50
50
ns
TPLIV
TPXIX
30
0
30
0
ns
ns
TPXIZ
10
10
ns
TAVIV
80
80
ns
TPLAZ
10
10
ns
85
4105D–8051–10/06
Table 61. AC Parameters for a Variable Clock
Symbol
Type
Standard Clock
X2 Clock
X parameter
for -M range
X parameter
for -L range
Units
TLHLL
Min
2T-x
T-x
15
15
ns
TAVLL
Min
T-x
0.5 T - x
20
20
ns
TLLAX
Min
T-x
0.5 T - x
20
20
ns
TLLIV
Max
4T-x
2T-x
35
35
ns
TLLPL
Min
T-x
0.5 T - x
15
15
ns
TPLPH
Min
3T-x
1.5 T - x
25
25
ns
TPLIV
Max
3T-x
1.5 T - x
45
45
ns
TPXIX
Min
x
x
0
0
ns
TPXIZ
Max
T-x
0.5 T - x
15
15
ns
TAVIV
Max
5T-x
2.5 T - x
45
45
ns
TPLAZ
Max
x
x
10
10
ns
External Program Memory
Read Cycle
Figure 37. External Program Memory Read Cycle
12 TCLCL
TLHLL
TLLIV
ALE
TLLPL
TPLPH
PSEN
TLLAX
TAVLL
PORT 0
INSTR IN
TPLIV
TPLAZ
A0-A7
TPXAV
TPXIZ
TPXIX
INSTR IN
A0-A7
INSTR IN
TAVIV
PORT 2
86
ADDRESS
OR SFR-P2
ADDRESS A8-A15
ADDRESS A8-A15
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
External Data Memory
Characteristics
Table 62. Symbol Description
Symbol
Parameter
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data set-up to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE high
Table 63. AC Parameters for a Fix Clock
-M
-L
Symbol
Min
TRLRH
125
125
ns
TWLWH
125
125
ns
TRLDV
TRHDX
Max
Min
95
0
Max
95
0
Units
ns
ns
TRHDZ
25
25
ns
TLLDV
155
155
ns
TAVDV
160
160
ns
105
ns
TLLWL
45
TAVWL
70
70
ns
TQVWX
5
5
ns
TQVWH
155
155
ns
TWHQX
10
10
ns
TRLAZ
0
0
ns
TWHLH
5
105
45
45
5
45
ns
87
4105D–8051–10/06
Table 64. AC Parameters for a Variable Clock
X parameter for - X parameter for M range
L range
Symbol
Type
Standard Clock
X2 Clock
Units
TRLRH
Min
6T-x
3T-x
25
25
ns
TWLWH
Min
6T-x
3T-x
25
25
ns
TRLDV
Max
5T-x
2.5 T - x
30
30
ns
TRHDX
Min
x
x
0
0
ns
TRHDZ
Max
2T-x
T-x
25
25
ns
TLLDV
Max
8T-x
4T -x
45
45
ns
TAVDV
Max
9T-x
4. 5 T - x
65
65
ns
TLLWL
Min
3T-x
1.5 T - x
30
30
ns
TLLWL
Max
3T+x
1.5 T + x
30
30
ns
TAVWL
Min
4T-x
2T-x
30
30
ns
TQVWX
Min
T-x
0.5 T - x
20
20
ns
TQVWH
Min
7T-x
3.5 T - x
20
20
ns
TWHQX
Min
T-x
0.5 T - x
15
15
ns
TRLAZ
Max
x
x
0
0
ns
TWHLH
Min
T-x
0.5 T - x
20
20
ns
TWHLH
Max
T+x
0.5 T + x
20
20
ns
External Data Memory Write
Cycle
Figure 38. External Data Memory Write Cycle
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TLLAX
PORT 0
A0-A7
TQVWX
TQVWH
TWHQX
DATA OUT
TAVWL
PORT 2
88
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
External Data Memory Read
Cycle
Figure 39. External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
TLLWL
TRLRH
RD
TRHDZ
TAVDV
TLLAX
PORT 0
TRHDX
A0-A7
DATA IN
TRLAZ
TAVWL
PORT 2
ADDRESS
OR SFR-P2
Serial Port Timing – Shift
Register Mode
ADDRESS A8-A15 OR SFR P2
Table 65. Symbol Description
Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output data set-up to clock rising edge
TXHQX
Output data hold after clock rising edge
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
Table 66. AC Parameters for a Fix Clock
-M
-L
Symbol
Min
TXLXL
300
300
ns
TQVHX
200
200
ns
TXHQX
30
30
ns
TXHDX
0
0
ns
TXHDV
Max
117
Min
Max
117
Units
ns
89
4105D–8051–10/06
Table 67. AC Parameters for a Variable Clock
Symbol
Type
Standard
Clock
X2 Clock
X parameter
for -M range
X parameter
for -L range
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
50
ns
TXHQX
Min
2T-x
T-x
20
20
ns
TXHDX
Min
x
x
0
0
ns
TXHDV
Max
10 T - x
5 T- x
133
133
ns
Units
ns
Shift Register Timing
Waveforms
Figure 40. Shift Register Timing Waveforms
0
INSTRUCTION
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
INPUT DATA
0
1
3
4
5
6
7
TXHDX
TXHDV
VALID
WRITE to SBUF
2
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
Flash EEPROM Programming
and Verification
Characteristics
Table 68. Flash Programming Parameters
TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10%.
Symbol
1/TCLCL
90
VALID
Parameter
Oscillator Frequency
Min
Max
Units
4
6
MHz
TEHAZ
Control to address float
TAVGL
Address Setup to PROG
Low
48 TCLCL
TGHAX
Address Hold after PROG
48 TCLCL
TDVGL
Data Setup to PROG Low
48 TCLCL
TGHDX
Data Hold after PROG
48 TCLCL
TGLGH
PROG Width for PGMC and
PGXC*
TGLGH
PROG Width for PGML
TAVQV
Address to Valid Data
48 TCLCL
TELQV
ENABLE Low to Data Valid
48 TCLCL
TEHQZ
Data Float after ENABLE
48 TCLCL
10
20
ms
48 TCLCL
0
48 TCLCL
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Flash EEPROM Programming
and Verification Waveforms
Figure 41. Flash EEPROM Programming and Verification Waveforms
PROGRAMMING
P1.0-P1.7
P2.0-P2.4
P3.4-P3.5
VERIFICATION
ADDRESS
ADDRESS
TAVQV
P0
DATA OUT
DATA IN
TGHDX
TGHAX
TDVGL
TAVGL
ALE/PROG
TGLGH
TEHAZ
CONTROL
SIGNALS
(ENABLE)
External Clock Drive
Characteristics (XTAL1)
Table 69. External Clock Drive Characteristics (XTAL1)
Symbol
Parameter
Min
Max
Units
TCLCL
Oscillator Period
25
ns
TCHCX
High Time
3
ns
TCLCX
Low Time
3
ns
TCLCH
Rise Time
3
ns
TCHCL
Fall Time
3
ns
60
%
TCHCX/TCLCX
External Clock Drive
Waveforms
TEHQZ
TELQV
Cyclic ratio in X2 mode
40
Figure 42. External Clock Drive Waveforms
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCX
TCLCH
TCLCX
TCHCL
TCLCL
AC Testing Input/Output
Waveforms
Figure 43. AC Testing Input/Output Waveforms
VCC -0.5V
INPUT/OUTPUT
0.45V
0.2 VCC + 0.9
0.2 VCC - 0.1
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at VIH min. for a logic “1” and V IL max for a logic “0”.
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Float Waveforms
Figure 44. Float Waveforms
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD
VLOAD + 0.1 V
VLOAD - 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/V OL level
occurs. IOL/IOH ≥ ± 20 mA.
Clock Waveforms
92
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
T89C51RB2/RC2
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T89C51RB2/RC2
Figure 45. Clock Waveforms
INTERNAL
CLOCK
STATE4
STATE5
STATE6
STATE1
STATE2
STATE3
STATE4
STATE5
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
SAMPLED
PCL OUT
DATA
SAMPLED
FLOAT
P2 (EXT)
PCL OUT
FLOAT
DATA
SAMPLED
PCL OUT
FLOAT
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
DATA
SAMPLED
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
WRITE CYCLE
WR
P0
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DPL OR Rt OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DATA OUT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
MOV PORT SRC
OLD DATA NEW DATA
P0 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1.P2.P3)
(INCLUDES INTO. INT1.TO T1)
SERIAL PORT SHIFT CLOCK
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded) RD and WR propagation
delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
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Flash EEPROM
Memory
The Flash memory increases EPROM and ROM functionality with in-circuit electrical
erasure and programming. It contains 16K or 32K bytes of program memory organized
respectively in 128 or 256 pages of 128 bytes. This memory is both parallel and serial
In-System Programmable (ISP). ISP allows devices to alter their own program memory
in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash.
The programming does not require 12V external programming voltage. The necessary
high programming voltage is generated on-chip using the standard V CC pins of the
microcontroller.
Features
Flash Programming and
Erasure
•
Flash E2PROM internal program memory.
•
Boot vector allows user provided Flash loader code to reside anywhere in the Flash
memory space. This configuration provides flexibility to the user.
•
Default loader in Boot ROM allows programming via the serial port without the need
of a user provided loader.
•
Up to 64K byte external program memory if the internal program memory is disabled
(EA = 0).
•
Programming and erase voltage with standard 5V or 3V V CC supply.
•
Read/Programming/Erase:
•
Byte-wise read without wait state
•
Byte or page erase and programming (10 ms)
•
Typical programming time (32K bytes) in 10s
•
Parallel programming with 87C51 compatible hardware interface to programmer
•
Programmable security for the code in the Flash
•
10k write cycles
•
10 years data retention
The 16K or 32K bytes Flash is programmed by bytes or by pages of 128 bytes. It is not
necessary to erase a byte or a page before programming. The programming of a byte or
a page includes a self erase before programming.
There are three methods of programming the Flash memory:
94
•
First, the on-chip ISP bootloader may be invoked which will use low level routines to
program the pages. The interface used for serial downloading of Flash is the UART.
•
Second, the Flash may be programmed or erased in the end-user application by
calling low-level routines through a common entry point in the Boot ROM.
•
Third, the Flash may be programmed using the parallel method by using a
conventional EPROM programmer. The parallel programming method used by
these devices is similar to that used by EPROM 87C51 but it is not identical and the
commercially available programmers need to have support for the
T89C51RB2/RC2. The bootloader and the Application Programming Interface (API)
routines are located in the BOOT ROM.
T89C51RB2/RC2
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T89C51RB2/RC2
Flash Registers and
Memory Map
Hardware Register
The T89C51RB2/RC2 Flash memory uses several registers for his management:
•
Hardware registers can only be accessed through the parallel programming modes
which are handled by the parallel programmer.
•
Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flash program memory
addressing space.
The only hardware register of the T89C51RB2/RC2 is called Hardware Security Byte
(HSB).
Table 70. Hardware Security Byte (HSB)
7
6
5
4
3
2
1
0
X2
BLJB
-
-
XRAM
LB2
LB1
LB0
Bit
Number
Bit
Mnemonic
7
X2
Description
X2 Mode
Programmed to force X2 mode (6 clocks per instruction)
Unprogrammed to force X1 mode, Standard Mode. (Default)
Boot Loader Jump Bit
6
BLJB
Unprogrammed this bit to start the user’s application on next reset at address
0000h.
Programmed this bit to start the boot loader at address F800h (Default).
5
-
Reserved
4
-
Reserved
3
XRAM
XRAM config bit (only programmable by programmer tools)
Programmed to inhibit XRAM
Unprogrammed, this bit to valid XRAM (Default)
2-0
LB2-0
User Memory Lock Bits (only programmable by programmer tools)
See Table 71
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
Flash Memory Lock Bits
•
When this bit is set the boot address is 0000h.
•
When this bit is reset the boot address is F800h. By default, this bit is cleared and
the ISP is enabled.
The three lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 71.
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Table 71. Program Lock Bits
Program Lock Bits
Security
level
LB0
LB1
LB2
1
U
U
U
No program lock features enabled.
Protection description
2
P
U
U
MOVC instruction executed from external program memory is disabled
from fetching code bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the Flash is
disabled. ISP and software programming with API are still allowed.
3
X
P
U
Same as 2, also verify through parallel programming interface is
disabled.
4
X
X
P
Same as 3, also external execution is disabled. (Default)
Note:
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X: do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the "software security bits" which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will set the HSB in its inactive state and will erase the Flash memory. The part reference can always be read using Flash parallel programming modes.
Default Values
Software Registers
The default value of the HSB provides parts ready to be programmed with ISP:
•
BLJB: Programmed force ISP operation.
•
X2: Unprogrammed to force X1 mode (Standard Mode).
•
XRAM: Unprogrammed to valid XRAM
•
LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Several registers are used, in factory and by parallel programmers, to make copies of
hardware registers contents. These values are used by Atmel ISP (see Section "In-System Programming (ISP)", page 101).
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
•
Commands issued by the parallel memory programmer.
•
Commands issued by the ISP software.
•
Calls of API issued by the application software.
Several software registers described in Table 72.
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Table 72. Default Values
Mnemonic
Definition
Default value
Description
SBV
Software Boot Vector
FCh
HSB
Copy of the Hardware security byte
BSB
Boot Status Byte
SSB
Software Security Byte
FFh
Copy of the Manufacturer Code
58h
ATMEL
Copy of the Device ID #1: Family Code
D7h
C51 X2, Electrically Erasable
Copy of the Device ID #2: memories
F7h
T89C51RB2/RC2 32KB
size and type
FBh
T89C51RB2/RC2 16 KB
Copy of the Device ID #3: name and
revision
EFh
T89C51RB2/RC2 32KB,
Revision 0
FFh
T89C51RB2/RC2 16 KB,
Revision 0
101x 1011b
0FFh
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 72 and Table 74.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 73. Software Security Byte
7
6
5
4
3
2
1
0
-
-
-
-
-
-
LB1
LB0
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
Do not clear this bit.
6
-
Reserved
Do not clear this bit.
5
-
Reserved
Do not clear this bit.
4
-
Reserved
Do not clear this bit.
3
-
Reserved
Do not clear this bit.
2
-
Reserved
Do not clear this bit.
1-0
LB1-0
User Memory Lock Bits
See Table 74
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown to Table 74.
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Table 74. Program Lock bits of the SSB
Program Lock Bits
Security
level
LB0
LB1
1
U
U
No program lock features enabled.
2
P
U
ISP programming of the Flash is disabled.
3
X
P
Same as 2, also verify through ISP programming interface is disabled.
Note:
Flash Memory Status
Protection description
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X: do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
T89C51RB2/RC2 parts are delivered in standard with the ISP boot in the Flash memory.
After ISP or parallel programming, the possible contents of the Flash memory are summarized on the figure below:
Figure 46. Flash memory possible contents
7FFFh T89C51RC2 32KB
3FFFh T89C51RB2 16KB
Virgin
Application
Virgin
or
application
Application
Dedicated
ISP
Virgin
or
application
Virgin
or
application
Dedicated
ISP
0000h
Default
Memory Organization
After ISP
After ISP
After parallel
programming
After parallel
programming
After parallel
programming
In the T89C51RB2/RC2, the lowest 16K or 32K of the 64Kb program memory address
space is filled by internal Flash.
When the EA pin high, the processor fetches instructions from internal program Flash.
Bus expansion for accessing program memory from 16K or 32K upward automatic since
external instruction fetches occur automatically when the program counter exceeds
3FFFh (16K) or 7FFFh (32K). If the EA pin is tied low, all program memory fetches are
from external memory.
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T89C51RB2/RC2
Boot process
Boot Flash
When the user application programs its own Flash memory, all of the low level details
are handled by a code that is permanently contained in a 2k byte “Boot ROM”. A user
program simply calls the common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation. Boot ROM operations include: erase block,
program byte or page, verify byte or page, program security lock bit, etc. The Boot ROM
is placed in the program memory space at the top of the address space from F800h to
FFFFh.
Figure 47. Boot ROM loader memory map
FFF0
Entry point for API
F800
ISP start
Reset Code Execution
At the falling edge of reset (unless the hardware conditions on PSEN, EA and ALE are
set as described below), the T89C51RB2/RC2 reads the BLJB bit in the HSB byte. If this
bit is set, it jumps to 0000h and if not, it jumps to F800h. At this address, the boot software reads a special Flash register: the Software Boot Vector (SBV). If the BSB is set to
zero, power-up execution starts at location 0000h, which is the normal start address of
the user’s application code. When the Boot Status Bit is set, the contents of the Boot
Vector is used as the high byte of the execution address and the low byte is set to 00h.
The factory default setting is FCh, corresponding to default ROM ISP boot loader. A
custom boot loader can be written with the Boot Vector set to the custom boot loader
address.
Hardware Activation of the
Boot Loader
The default boot loader can also be executed by holding PSEN LOW, EA HIGH, and
ALE HIGH (or not connected) at the falling edge of RESET. This allows an application to
be built that will normally execute the end user’s code but can be manually forced into
default ISP operation.
As PSEN has the same structure as P1-P3, the current to force PSEN to 0 as I TL is
defined in the DC parameters.
User application should take care to release hardware conditions (PSEN LOW, EA
HIGH) 24 clock cycles after falling edge of reset signal.
If the factory default setting for the Boot Vector (FCh) is changed, it will no longer point
to the ISP default Flash boot loader code. It can be restored:
•
With the default ISP activated with hardware conditions on PSEN, EA and ALE.
•
With a customized loader (in the end user application) that provides features for
erasing and reprogramming of the Software Boot Vector and BSB.
•
Through the parallel programming method.
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After programming the Flash, the status byte should be programmed to zero in order to
allow execution of the user’s application code beginning at address 0000h.
Boot Process Summary
The boot process is summarized on the following flowchart:
Figure 48. Boot process flowchart
RESET
If BLJB=0 then ENBOOT bit (AUXR1) is set
else ENBOOT bit (AUXR1) is cleared
Yes (PSEN = 0, EA = 1, and ALE =1 or not connected)
Hardware
Hardware
condition?
FCON = 00h
FCON = F0h
BLJB=1
ENBOOT=0
BLJB!= 0
?
BLJB=0
ENBOOT=1
F800h
Software
FCON = 00h
?
yes = hardware boot conditions
BSB = 00h
?
PC=0000h
USER APPLICATION
SBV = FCh
?
USER BOOT LOADER
Atmel BOOT LOADER
PC= [SBV]00h
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T89C51RB2/RC2
In-System Programming
(ISP)
The In-System Programming (ISP) is performed without removing the microcontroller
from the system. The ISP facility consists of a series of internal hardware resources
coupled with internal firmware to facilitate remote programming of theT89C51RB2/RC2
through the serial port.
The Atmel ISP facility has made in-circuit programming in an embedded application
possible with a minimum of additional expense in components and circuit board area.
The ISP function through UART uses four pins: TxD, RxD, VSS, VCC. Only a small connector needs to be available to interface the application to an external circuit in order to
use this feature.
Using In-System
Programming (ISP)
The ISP feature allows a wide range of baud rates in the user application. It is also
adaptable to a wide range of oscillator frequencies. This is accomplished by measuring
the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP
f e a tu r e r e q u ir e s th a t a n in itia l c h a ra c te r (a n u p p e rc a s e U ) b e se n t t o t h e
T89C51RB2/RC2 to establish the baud rate. The ISP firmware provides auto-echo of
received characters.
Once baud rate initialization has been performed, the ISP firmware will only accept Intel
Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below:
:NNAAAARRDD. DDCC
T89C51RB2/RC2 will accept up to 16 (10h) data bytes. The “AAAA” string represents
the address of the first byte in the record. If there are zero bytes in the record, this field
is often set to ‘‘0000’’. The “RR” string indicates the record type. A record type of “00” is
a data record. A record type of “01” indicates the end-of-file mark. In this application,
additional record types will be added to indicate either commands or data for the ISP
facility. The “DD” string represents the data bytes. The maximum number of data bytes
in a record is limited to 16 (decimal). The “CC” string represents the checksum byte. ISP
commands are summarized in Table 75.
As a record is received by the T89C51RB2/RC2, the information in the record is stored
internally and a checksum calculation is performed and compared to ‘‘CC’’.
The operation indicated by the record type is not performed until the entire record has
been received. Should an error occur in the checksum, the T89C51RB2/RC2 will send
an “X” out the serial port indicating a checksum error. If the checksum calculation is
found to match the checksum in the record, then the command will be executed. In most
cases, successful reception of the record will be indicated by transmitting a “. ” character
out the serial port (displaying the contents of the internal program memory is an exception). In the case of a Data Record (record type ‘‘00’’), an additional check is made. A “.
” character will NOT be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully programmed. For a data record,
an “X” indicates that the checksum failed to match, and an “R” character indicates that
one of the bytes did not properly program.
FLIP, a software utility to implement ISP programming with a PC, is available from the
Atmel the web site.
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Table 75. Intel-Hex Records Used by In-system Programming
RECORD TYPE
COMMAND/DATA FUNCTION
Data Record
:nnaaaa00dd. . . . ddcc
Where:
Nn = number of bytes (hex) in record
00
aaaa = memory address of first byte in record
dd. . . . dd = data bytes
cc = checksum
Example:
:05008000AF5F67F060B6
End of File (EOF), no operation
:xxxxxx01cc
Where:
01
xxxxxx = required field, but value is a “don’t care”
cc = checksum
Example:
:00000001FF
Specify Oscillator Frequency (Not required, left for Philips compatibility)
:01xxxx02ddcc
Where:
02
xxxx = required field, but value is a “don’t care”
dd = required field, but value is a “don’t care”
cc = checksum
Example:
:0100000210ED
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RECORD TYPE
COMMAND/DATA FUNCTION
Miscellaneous Write Functions
:nnxxxx03ffssddcc
Where:
nn = number of bytes (hex) in record
xxxx = required field, but value is a “don’t care”
03 = Write Function
ff = subfunction code
ss = selection code
dd = data input (as needed)
cc = checksum
Subfunction Code = 01 (Erase Block)
ff = 01
ss = block number in bits 7:5, Bits 4:0 = zeros
Example:
:0200000301A05A erase block 5
Subfunction Code = 04 (Reset Boot Vector and Status Byte)
ff = 04
ss = don’t care
dd = don’t care
Example:
:020000034500F8 Reset boot vector (FCh) and status byte (FFh)
03
Subfunction Code = 05 (Program Software Security Bits)
ff = 05
ss = 00 program software security bit 1 (Level 2 inhibit writing to Flash)
ss = 01 program software security bit 2 (Level 3 inhibit Flash verify)
ss = 02 program security bit 3 (No effect, left for Philips compatibility; disable external
memory is already set in the default hardware security byte)
Example:
:020000030501F6 program security bit 2
Subfunction Code = 06 (Program Boot Status Byte, Boot Vector,X2 bit,Osc bit or BLJB
fuse bit)
ff = 06
ss = 00 program Boot Status byte
ss = 01 program Software Boot vector
ss = 02 program X2 bit
ss = 04 program BLJB
Example:
:03000003060100F5 program boot vector with 00
Subfunction Code = 07 (Full chip erase)
ff = 07
ss = don’t care
dd = don’t care
Example:
:03000007F5 program boot vector with 00
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RECORD TYPE
COMMAND/DATA FUNCTION
Display Device Data or Blank Check
Record type 04 causes the contents of the entire Flash array to be sent out the serial
port in a formatted display. This display consists of an address and the contents of 16
bytes starting with that address. No display of the device contents will occur if security
bit 2 has been programmed. The dumping of the device data to the serial port is
terminated by the reception of any character.
General Format of Function 04
:05xxxx04sssseeeeffcc
Where:
05 = number of bytes (hex) in record
04
xxxx = required field, but value is a “don’t care”
04 = “Display Device Data or Blank Check” function code
ssss = starting address
eeee = ending address
ff = subfunction
00 = display data
01 = blank check
cc = checksum
Example:
:0500000440004FFF0069 (display 4000–4FFF)
Miscellaneous Read Functions
General Format of Function 05
:02xxxx05ffsscc
Where:
02 = number of bytes (hex) in record
xxxx = required field, but value is a “don’t care”
05= “Miscellaneous Read” function code
ffss = subfunction and selection code
05
0000 = read copy of the signature byte – manufacturer id (58H)
0001 = read copy of the signature byte – device ID# 1 (Family code)
0002 = read copy of the signature byte – device ID # 2 (Memories size and type)
0003 = read copy of the signature byte – device ID # 3 (Product name and revision)
0700 = read the software security bits
0701 = read BSB
0702 = read SBV
0704 = read HSB
cc = checksum
Example:
:020000050001F0 read copy of the signature byte – device id # 1
In-application
Programming Method
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a common interface, PGM_MTP. The programming functions are selected by
setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0h.
Results are returned in the registers. The API calls are shown in Table .
A set of Philips® compatible API calls is provided.
When several bytes have to be programmed, it is highly recommended to use the Atmel
API “PROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 bytes in a single command.
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Table 76. API Calls
API Call
Parameter
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
R1 = 02h
PROGRAM DATA
BYTE
DPTR = address of byte to program
ACC = byte to program
Return Parameter
ACC = 00 if pass,!00 if fail
Input Parameters:
R0 = osc freq (integer Not required)
R1 = 09h
DPTR0 = address of the first byte to program in the Flash memory
PROGRAM DATA
PAGE
DPTR1 = address in XRAM of the first data to program (second data pointer)
ACC = number of bytes to program
Return Parameter
ACC = 00 if pass,!00 if fail
Remark: number of bytes to program is limited such as the Flash write remains in a
single 128bytes page. Hence, when ACC is 128, valid values of DPL are 00h, or,
80h.
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
R1 = 01h
DPH = block number
ERASE BLOCK
Number
0
DPTR
0
Block
00h256 bytes (default)
1
20h
512 bytes
2
40h
768 bytes
DPL = 00h
Return Parameter
None
Remark: Command for Philips compatibility, as no erase is needed; the ISP
firmware write FFh in the corresponding block.
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
ERASE BOOT
VECTOR
R1 = 04h
DPH = 00h
DPL = don’t care
Return Parameter
none
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Table 76. API Calls (Continued)
API Call
Parameter
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
R1 = 05h
DPH = 00h
PROGRAM
SOFTWARE
SECURITY BIT
DPL = 00h – security bit # 1 (inhibit writing to Flash)
01h – security bit # 2 (inhibit Flash verify)
10h - allows ISP writing to Flash (see Note 1)
11h - allows ISP Flash verify (see Note 1)
Return Parameter
none
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
R1 = 06h
PROGRAM BOOT
STATUS BYTE
DPH = 00h
DPL = 00h
ACC = status byte
Return Parameter
ACC = status byte
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
R1 = 06h
PROGRAM BOOT
VECTOR
DPH = 00h
DPL = 01h
ACC = boot vector
Return Parameter
ACC = boot vector
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
R1 = 0Ah
PROGRAM X2
MODE
DPH = 00h
DPL = 08h
ACC = value (00 or 01h)
Return Parameter
ACC = boot vector
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
R1 = 0Ah
PROGRAM BLJB
DPH = 00h
DPL = 04h
ACC = value (00 or 01h)
Return Parameter
ACC = boot vector
Input Parameters:
R1 = 03h
READ DEVICE DATA DPTR = address of byte to read
Return Parameter
ACC = value of byte read
106
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Table 76. API Calls (Continued)
API Call
Parameter
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
R1 = 00h
READ copy of the
DPH = 00h
MANUFACTURER ID
DPL = 00h (manufacturer ID)
Return Parameter
ACC = value of byte read
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
READ copy of the
device ID # 1
R1 = 00h
DPH = 00h
DPL = 01h (device ID # 1)
Return Parameter
ACC = value of byte read
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
READ copy of the
device ID # 2
R1 = 00h
DPH = 00h
DPL = 02h (device ID # 2)
Return Parameter
ACC = value of byte read
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
READ copy of the
device ID # 3
R1 = 00h
DPH = 00h
DPL = 03h (device ID # 2)
Return Parameter
ACC = value of byte read
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
READ SOFTWARE
SECURITY BITS
R1 = 07h
DPH = 00h
DPL = 00h (Software security bits)
Return Parameter
ACC = value of byte read
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
READ HARDWARE
SECURITY BITS
R1 = 07h -> OBh
DPH = 00h
DPL = 04h (Hardware security bits)
Return Parameter
ACC = value of byte read
107
4105D–8051–10/06
Table 76. API Calls (Continued)
API Call
Parameter
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
READ BOOT
STATUS BYTE
R1 = 07h
DPH = 00h
DPL = 01h (status byte)
Return Parameter
ACC = value of byte read
Input Parameters:
R0 = osc freq (integer Not required, left for Philips compatibility)
READ BOOT
VECTOR
R1 = 07h
DPH = 00h
DPL = 02h (boot vector)
Return Parameter
ACC = value of byte read
Note:
108
These functions can only be called by user’s code. The standard boot loader cannot
decrease the security level.
Number
DPTR
Block
0
00h
0 - 8 KB
1
20h
8 - 16 KB
2
40h
16 - 32 KB (Only on T89C51RC2)
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Ordering Information
Table 77. Possible Order Entries
Part-number
Memory size
Supply voltage
Temperature range
Package
Packing
T89C51RB2-3CSCM
16 K bytes
5V
Commercial
PDIL40
Stick
T89C51RB2-3CSIM
16 K bytes
5V
Industrial
PDIL40
Stick
T89C51RB2-SLSCM
16 K bytes
5V
Commercial
PLCC44
Stick
T89C51RB2-SLSIM
16 K bytes
5V
Industrial
PLCC44
Stick
T89C51RB2-SLSIL
16 K bytes
3V
Industrial
PLCC44
Stick
T89C51RB2-RLTIM
16 K bytes
5V
Industrial
VQFP44
Tray
T89C51RB2-RLTIL
16 K bytes
3V
Commercial
VQFP44
Tray
T89C51RC2-3CSCM
32 K bytes
5V
Commercial
PDIL40
Stick
T89C51RC2-3CSIM
32 K bytes
5V
Industrial
PDIL40
Stick
T89C51RC2-SLSCM
32 K bytes
5V
Commercial
PLCC44
Stick
T89C51RC2-SLSIM
32 K bytes
5V
Industrial
PLCC44
Stick
T89C51RC2-SLSIL
32 K bytes
3V
Industrial
PLCC44
Stick
T89C51RC2-RLTIM
32 K bytes
5V
Industrial
VQFP44
Tray
T89C51RC2-RLTIL
32 K bytes
3V
Commercial
VQFP44
Tray
109
4105D–8051–10/06
Package Information
PDIL40
110
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Package Information
VQFP44
Package Information
PLC44
111
4105D–8051–10/06
112
T89C51RB2/RC2
4105D–8051–10/06
T89C51RB2/RC2
Document Revision History
Changes from 4105C 02/02 to 4105D - 10-06
1. Correction to PDIL40 figure on page 5.
113
4105D–8051–10/06
Table of Contents
Features ................................................................................................. 1
Description ............................................................................................ 1
Block Diagram ....................................................................................... 2
SFR Mapping ......................................................................................... 3
Pin Configurations ................................................................................ 5
Oscillator ............................................................................................... 9
Registers............................................................................................................... 9
Functional Block Diagram................................................................................... 10
Enhanced Features ............................................................................. 11
X2 Feature .......................................................................................................... 11
Dual Data Pointer Register DPTR ...................................................... 15
Expanded RAM (XRAM) ..................................................................... 18
Registers............................................................................................................. 20
Timer 2 ................................................................................................. 21
Auto-Reload Mode.............................................................................................. 21
Programmable Clock-Output .............................................................................. 22
Registers............................................................................................................. 24
Programmable Counter Array PCA ................................................... 26
Registers.............................................................................................................
PCA Capture Mode.............................................................................................
16-bit Software Timer/ Compare Mode...............................................................
High Speed Output Mode ...................................................................................
Pulse Width Modulator Mode..............................................................................
PCA Watchdog Timer .........................................................................................
28
34
35
36
37
37
Serial I/O Port ...................................................................................... 39
Framing Error Detection .....................................................................................
Automatic Address Recognition..........................................................................
Registers.............................................................................................................
Baud Rate Selection for UART for Mode 1 and 3...............................................
UART Registers..................................................................................................
39
40
42
42
45
Interrupt System ................................................................................. 50
Registers............................................................................................................. 51
i
4105D–8051–10/06
Interrupt Sources and Vector Addresses............................................................ 58
Keyboard Interface ............................................................................. 59
Registers............................................................................................................. 60
Serial Port Interface (SPI) ................................................................... 63
Features.............................................................................................................. 63
Signal Description............................................................................................... 63
Functional Description ........................................................................................ 65
Hardware Watchdog Timer ................................................................ 72
Using the WDT ................................................................................................... 72
WDT During Power Down and Idle..................................................................... 73
ONCE™ Mode (ON Chip Emulation) .................................................. 74
Power Management ............................................................................ 75
Reset ..................................................................................................................
Reset Recommendation to Prevent Flash Corruption ........................................
Idle Mode ............................................................................................................
Power-down Mode..............................................................................................
75
75
76
76
Power-off Flag ..................................................................................... 78
Reduced EMI Mode ............................................................................. 79
Electrical Characteristics ................................................................... 80
Absolute Maximum Ratings(*) ................................................................................................................. 80
DC Parameters for Standard Voltage ................................................................. 81
DC Parameters for Low Voltage .........................................................................82
AC Parameters ................................................................................................... 84
Flash EEPROM Memory ..................................................................... 94
Features.............................................................................................................. 94
Flash Programming and Erasure ........................................................................ 94
Flash Registers and Memory Map...................................................................... 95
Flash Memory Status.......................................................................................... 98
Memory Organization ......................................................................................... 98
Boot process....................................................................................................... 99
In-System Programming (ISP).......................................................................... 101
In-application Programming Method................................................................. 104
Ordering Information ........................................................................ 109
Package Information ........................................................................ 110
PDIL40.............................................................................................................. 110
ii
4105D–8051–10/06
Package Information ........................................................................ 111
VQFP44 ............................................................................................................ 111
Package Information ........................................................................ 111
PLC44............................................................................................................... 111
Document Revision History ............................................................. 113
Changes from 4105C - 02/02 to 4105D - 10-06 ............................................... 113
Table of Contents .................................................................................. i
iii
4105D–8051–10/06
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