ATMEL AT86RF212-ZU

Features
• Fully Integrated 800/900 MHz-Band Transceiver
- European ISM Band from 863 to 870 MHz
- North American ISM Band from 902 to 928 MHz
• Direct Sequence Spread Spectrum with Different Modulation and Data Rates
- BPSK with 20 and 40 kbit/s (compliant to IEEE 802.15.4-2006)
- O-QPSK with 100 and 250 kbit/s (compliant to IEEE 802.15.4-2006)
- O-QPSK with 200, 400, 500, and 1000 kbit/s PSDU Data Rate
• Flexible Combination of Frequency Bands and Data Rates
• Industry Leading Link Budget
- Receiver Sensitivity up to -110 dBm
- Programmable TX Output Power up to +10 dBm
• Low Power Supply Voltage from 1.8 V to 3.6 V
- Internal Voltage Regulators and Battery Monitor
• Low Current Consumption
- SLEEP
= 0.2 µA
- TRX_OFF = 0.4 mA
- RX_ON = 9 mA
- TX_ACTIVE = 19 mA (at PTX = 5 dBm)
• Digital Interface
- Registers, Frame Buffer, and AES Accessible through SPI
- Clock Output with Configurable Rate
• Radio Transceiver Features
- Adjustable Receiver Sensitivity
- Integrated TX/RX Switch, LNA, and PLL Loop Filter
- Fast Settling PLL Supporting Frequency Hopping
- Automatic VCO and Filter Calibration
- Integrated 16 MHz Crystal Oscillator
- 128 byte FIFO for Transmit/Receive
• IEEE 802.15.4-2006 Hardware Support
- FCS Computation and Check
- Clear Channel Assessment
- Received Signal Strength Indicator, Energy Detection, and Link Quality
Indication
• MAC Hardware Accelerator
- Automatic Acknowledgement, CSMA-CA, and Retransmission
- Automatic Frame Filtering
• AES 128 bit Hardware Accelerator (ECB and CBC modes)
• Extended Feature Set Hardware Support
- True Random Number Generation for Security Applications
- TX/RX Indication (External RF Front End Control)
- MAC based Antenna Diversity
• Optimized for Low BoM Cost and Ease of Production
- Low External Component Count: Antenna, Reference Crystal, and Bypass
Capacitors
- Excellent ESD Robustness
• Industrial Temperature Range from -40°C to +85°C
3
• 32-pin Low-profile Lead-free Plastic QFN Package, 5.0 x 5.0 x 0.9 mm
• Compliant to IEEE 802.15.4-2003 and IEEE 802.15.4-2006, ETSI EN 300 220-1,
and FCC 47 CFR Section 15.247
AT86RF212
Low Power
800/900 MHz
Transceiver for
IEEE 802.15.42006, ZigbeeTM,
and ISM
Applications
PRELIMINARY
8168A-AVR-06/08
Disclaimer
Values contained in this datasheet are based on simulations and characterization of
other transceivers manufactured on a similar process technology. Final values will be
available after the device is characterized.
1 Overview
The AT86RF212 is a low-power, low-voltage 800/900 MHz transceiver specially
designed for low-cost IEEE 802.15.4, ZigBeeTM, and high data rate ISM applications.
For the sub-1 GHz bands, it supports low data rates (20 and 40 kbit/s) of the IEEE
802.15.4-2003 standard [2] and provides optional data rates (100 and 250 kbit/s) using
O-QPSK, according to IEEE 802.15.4-2006 [1]. Furthermore, proprietary High Data
Rates Modes up to 1000 kbit/s can be employed.
The AT86RF212 is a true SPI-to-antenna solution. RF-critical components except the
antenna, crystal, and de-coupling capacitors are integrated on-chip. MAC and AES
hardware accelerators improve overall system power efficiency and timing.
1.1 General Circuit Description
The AT86RF212 single-chip RF transceiver provides a complete radio interface
between the antenna and the microcontroller. It comprises the analog radio part, digital
modulation and demodulation including time and frequency synchronization, as well as
data buffering. The number of external components is minimized so that only the
antenna, a filter (at high output power levels), the crystal, and four bypass capacitors
are required. The bidirectional differential antenna pins are used in common for RX and
TX, i.e. no external antenna switch is needed. Control of an external power amplifier is
supported by two digital control signals (differential operation). The transceiver block
diagram is shown in Figure 1-1.
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AT86RF212
8168A-AVR-06/08
AT86RF212
TX Power
XTAL2
XTAL1
Figure 1-1. AT86RF212 Block Diagram
Voltage
Regulator
XOSC
PA
Mixer
RFP
RFN
LPF
Frequency
Synthesis
LNA
PPF
Mixer
DAC
FTN,
BATMON
BPF
ADC
AGC
Analog Domain
Configuration Registers
TX BBP
TRX Buffer
RX BBP
Control Logic
SPI
(Slave)
/SEL
MISO
MOSI
SCLK
AES
IRQ
CLKM
DIG1
DIG2
/RST
SLP_TR
DIG3/4
Digital Domain
The receiver path is based on a low-IF architecture. After channel filtering and downconversion the low-IF signal is sampled and applied to the digital signal processing part.
Communication between transmitter and receiver is based on direct sequence spread
spectrum with different modulation schemes and spreading codes. The AT86RF212
supports the IEEE 802.15.4-2006 standard mandatory BPSK modulation and optional
O-QPSK modulation in the 800 and 900 MHz band. For applications not necessarily
targeting IEEE compliant networks the radio transceiver supports proprietary High Data
Rate Modes based on O-QPSK.
A single 128 byte TRX buffer stores receive or transmit data.
The AT86RF212 features hardware supported 128 bit security operation. The
standalone AES encryption/decryption engine can be accessed in parallel to all PHY
operational modes. Configuration of the AT86RF212, reading, and writing of data
memory as well as the AES hardware engine are controlled by the SPI interface and
additional control signals.
On-chip low-dropout voltage regulators provide the analog and digital 1.8 V power
supply. Control registers retain their settings in SLEEP mode when the regulators are
turned off. The RX and TX signal processing paths are highly integrated and optimized
for low power consumption.
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8168A-AVR-06/08
2 Pin Configuration
2.1 Pin-out Diagram
XTAL2
XTAL1
AVSS
EVDD
AVDD
AVSS
AVSS
AVSS
Figure 2-1. AT86RF212 Pin-out Diagram
DIG3
32 31 30 29 28 27 26 25
24
1
exposed paddle
DIG4
2
AVSS
3
RFP
4
RFN
5
AVSS
IRQ
/SEL
22
MOSI
21
DVSS
20
MISO
6
19
SCLK
DVSS
7
18
DVSS
/RST
8
17
9 10 11 12 13 14 15 16
CLKM
Note:
DEVDD
DVDD
DVDD
DVSS
SLP_TR
DIG2
DIG1
AT86RF212
DVSS
23
AVSS
The exposed paddle is electrically connected to the die inside the package. It shall be
soldered to the board to ensure electrical and thermal contact and good mechanical
stability.
2.2 Pin Description
Table 2-1. Pin Description
4
Pins
Name
Type
Description
1
DIG3
Digital output
RX/TX Indication, see section 9.4;
if disabled, internally pulled to AVSS
2
DIG4
Digital output
RX/TX Indication (DIG3 inverted), see section 9.4;
if disabled, internally pulled to AVSS
3
AVSS
Ground
Ground for RF signals
4
RFP
RF I/O
Differential RF signal
5
RFN
RF I/O
Differential RF signal
6
AVSS
Ground
Ground for RF signals
7
DVSS
Ground
Digital ground
8
/RST
Digital input
Chip reset; active low
9
DIG1
Digital output
Antenna Diversity RF switch control, see section 9.3;
if disabled, internally pulled to DVSS
AT86RF212
8168A-AVR-06/08
AT86RF212
Pins
Name
Type
Description
10
DIG2
Digital output
1. Antenna Diversity RF switch control (DIG1 inverted), see section 9.3
2. Signal IRQ_2 (RX_START) for RX Frame Time Stamping, see section 9.5
If disabled, internally pulled to DVSS
11
SLP_TR
Digital input
Controls sleep, transmit start, receive states; active high, see section 4.6
12
DVSS
Ground
Digital ground
13
DVDD
Analog
Regulated 1.8 V internal supply voltage; digital domain, see section 7.5
14
DVDD
Analog
Regulated 1.8 V internal supply voltage; digital domain, see section 7.5
15
DEVDD
Supply
External supply voltage; digital domain
16
DVSS
Ground
Digital ground
17
CLKM
Digital output
Master clock signal output; low if disabled, see section 7.7
18
DVSS
Ground
Digital ground
19
SCLK
Digital input
SPI clock
20
MISO
Digital output
SPI data output (master input slave output)
21
DVSS
Ground
Digital ground
22
MOSI
Digital input
SPI data input (master output slave input)
23
/SEL
Digital input
SPI select, active low
24
IRQ
Digital output
1. Interrupt request signal; active high or active low, see section 4.7
2. Buffer-level mode indicator; active high
25
XTAL2
Analog
Crystal pin, see sections 2.2.1.3 and 7.7
26
XTAL1
Analog
Crystal pin or external clock supply, see section 2.2.1.3 and 7.7
27
AVSS
Ground
Analog ground
28
EVDD
Supply
External supply voltage, analog domain
29
AVDD
Analog
Regulated 1.8 V internal supply voltage; analog domain, see section 7.5
30
AVSS
Ground
Analog ground
31
AVSS
Ground
Analog ground
32
AVSS
Ground
Analog ground
Paddle
AVSS
Ground
Analog ground; exposed paddle of QFN package
2.2.1 Analog and RF Pins
2.2.1.1 Supply and Ground Pins
EVDD, DEVDD
EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF212 radio
transceiver.
AVDD, DVDD
AVDD and DVDD are outputs of the internal voltage regulators and require bypass
capacitors for stable operation. The voltage regulators are controlled independently by
the radio transceivers state machine and are activated depending on the current radio
transceiver state. The voltage regulators can be configured for external supply. For
details refer to section 7.5.
AVSS, DVSS
AVSS and DVSS are analog and digital ground pins respectively.
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8168A-AVR-06/08
2.2.1.2 RF Pins
RFN, RFP
A differential RF port (RFP/RFN) provides common-mode rejection to suppress the
switching noise of the internal digital signal processing blocks. At board-level, the
differential RF layout ensures high receiver sensitivity by reducing spurious emissions
originated from other digital ICs such as a microcontroller.
The RF port is designed for a 100 Ω differential load. A DC path between the RF pins is
allowed. A DC path to ground or supply voltage is not allowed. Therefore when
connecting a RF-load providing a DC path to the power supply or ground, AC-coupling
is required as indicated in Table 2-2.
A simplified schematic of the RF front end is shown in Figure 2-2.
Figure 2-2. Simplified RF Front-end Schematic
PCB
AT86RF212
LNA
RX
PA
TX
RFP
RFN
MC
0.9V
M0
RXTX
CM
Feedback
RF port DC values depend on the operating state, refer to section 5. In TRX_OFF state,
when the analog front-end is disabled (see section 5.1.2.3), the RF pins are pulled to
ground, preventing a floating voltage larger than 1.8 V, which is not allowed for the
internal circuitry.
In transmit mode, a control loop provides a common-mode voltage of 0.9 V. Transistor
M0 is off, allowing the PA to set the common-mode voltage. The common-mode
capacitance at each pin to ground shall be < 100 pF to ensure the stability of this
common-mode feedback loop.
In receive mode, the RF port provides a low-impedance path to ground when transistor
M0, see Figure 2-2, pulls the inductor center tap to ground. A DC voltage drop of 20 mV
across the on-chip inductor can be measured at the RF pins.
Matching control (MC) is implemented by an adjustable capacitances to ground at each
RF pin as shown in Figure 2-2. The input capacitance can be changed within 15 steps
by setting a 4-bit control word (register 0x19, RF_CTRL_1).
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AT86RF212
8168A-AVR-06/08
AT86RF212
2.2.1.3 Crystal Oscillator Pins
XTAL1, XTAL2
The pin XTAL1 is the input of the reference oscillator amplifier (XOSC), XTAL2 the
output. A detailed description of the crystal oscillator setup and the related
XTAL1/XTAL2 pin configuration can be found in section 7.7.
When using an external clock reference signal, XTAL1 shall be used as input pin. For
further details refer to section 7.7.3.
2.2.1.4 Analog Pin Summary
Table 2-2. Analog Pin Behavior – DC values
Pin
Values and Conditions
Comments
RFP/RFN
VDC = 0.9 V (BUSY_TX)
VDC = 20 mV (receive states)
VDC = 0 mV (otherwise)
DC level at pins RFP/RFN for various transceiver states
AC-coupling is required if an antenna with a DC path to ground is
used. Serial capacitance and capacitance of each pin to ground
must be < 100 pF.
XTAL1/XTAL2
VDC = 0.9 V at both pins
CPAR = 3 pF
VAC ≤ 1.0 Vpp
DC level at pins XTAL1/XTAL2 for various transceiver states
Parasitic capacitance (Cpar) of the pins must be considered as
additional load capacitance to the crystal.
DVDD
VDC = 1.8 V (all states, except P_ON, SLEEP,
and RESET)
VDC = 0 mV (otherwise)
DC level at pin DVDD for various transceiver states
Supply pins (voltage regulator output) for the digital 1.8 V voltage
domain. The outputs shall be bypassed by 1 µF.
AVDD
VDC = 1.8 V (all states, except P_ON, SLEEP,
RESET, and TRX_OFF)
VDC = 0 mV (otherwise)
DC level at pin AVDD for various transceiver states
Supply pin (voltage regulator output) for the analog 1.8 V voltage
domain. The outputs shall be bypassed by 1 µF.
2.2.2 Digital Pins
The AT86RF212 provides a digital microcontroller interface. The interface comprises a
slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ,
SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in chapter
4.
Additional digital output signals DIG1 … DIG4 are provided to control external blocks,
i.e. for Antenna Diversity RF switch control or as an RX/TX Indicator, see sections 9.3
and 9.4, respectively. After reset, these pins are connected to digital ground
(DIG1/DIG2) or analog ground (DIG3/DIG4).
2.2.2.1 Driver Strength Settings
The driver strength of all digital output pins (MISO, IRQ, DIG1, …, DIG4) and CLKM pin
can be configured using register 0x03 (TRX_CTRL_0), see Table 2-3.
Table 2-3. Digital Output Driver Configuration
Pin
Default Driver Strength
Comment
MISO, IRQ, DIG1, …, DIG4
2 mA
Adjustable to 2 mA, 4 mA, 6 mA, and 8 mA
CLKM
4 mA
Adjustable to 2 mA, 4 mA, 6 mA, and 8 mA
The capacitive load should be as small as possible and not larger than 50 pF when
using the 2 mA minimum driver strength setting. Generally, the output driver strength
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8168A-AVR-06/08
should be adjusted to the lowest possible value in order to keep the current
consumption and the emission of digital signal harmonics low.
2.2.2.2 Pull-up and Pull-down Configuration
Pulling resistors are internally connected to all digital input pins in radio transceiver
state P_ON, see section 5.1.2.1. Table 2-4 summarizes the pull-up and pull-down
configuration.
Table 2-4. Pull-up / Pull-Down Configuration of Digital Input Pins in P_ON State
Pins
H
=ˆ
pull-up, L
/RST
H
/SEL
H
SCLK
L
MOSI
L
SLP_TR
L
=ˆ
pull-down
In all other states including RESET, no pull-up or pull-down resistors are connected to
any of the digital input pins.
2.2.2.3 Register Description
Register 0x03 (TRX_CTRL_0):
The TRX_CTRL_0 register controls the drive current of the digital output pads and the
CLKM clock rate.
Table 2-5. Register 0x03 (TRX_CTRL_0)
Bit
7
6
5
4
Name
PAD_IO
PAD_IO
PAD_IO_CLKM
PAD_IO_CLKM
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
1
Bit
3
2
1
0
Name
CLKM_SHA_SEL
CLK_CTRL
CLKM_CTRL
CLKM_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
1
0
0
1
• Bit 7:6 – PAD_IO
These register bits set the output driver current of digital output pads, except CLKM.
Table 2-6. Digital Output Driver Strength
Register Bits
PAD_IO
Note:
8
Value
(1)
Description
0
2 mA
1
4 mA
2
6 mA
3
8 mA
1. Underlined values indicate reset settings.
AT86RF212
8168A-AVR-06/08
AT86RF212
• Bit 5:4 – PAD_IO_CLKM
These register bits set the output driver current of pin CLKM. Refer also to section 7.7.
Table 2-7. CLKM Driver Strength
Register Bits
Value
Description
PAD_IO_CLKM
0
2 mA
1
4 mA
2
6 mA
3
8 mA
• Bit 3 – CLKM_SHA_SEL
Refer to section 7.7.
• Bit 2:0 – CLKM_CTRL
Refer to section 7.7.
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8168A-AVR-06/08
3 Application Circuits
3.1 Basic Application Schematic
A basic application schematic of the AT86RF212 with a single-ended RF connector is
shown in Figure 3-1. The 50 Ω single-ended RF input is transformed to the 100 Ω
differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC
coupling of the RF input to the RF port. Regulatory rules like FCC 47 section 15.247,
ERC/REC 70-03 or ETSI EN 300 220 may require an external filter F1, depending on
used transmit power levels.
Figure 3-1. Basic Application Schematic
VCC
CB2
CX1
CX2
XTAL
30 29
28
27
26
25
AVSS
AVDD
EVDD
AVSS
XTAL1
XTAL2
2 DIG4
/SEL 23
3 AVSS
MOSI 22
4 RFP
B1
5 RFN
MISO 20
DVDD
DEVDD
DVSS
DVSS 18
DVDD
7 DVSS
DVSS
SCLK 19
SLP_TR
6 AVSS
DIG2
C2
DVSS 21
AT86RF212
DIG1
F1
IRQ 24
9
10
11
12
13
14
15
16
8 /RST
CB3
Digital Interface
C1
RF
31
AVSS
1 DIG3
32
AVSS
CB1
CLKM 17
R1
C3
CB4
The power supply bypass capacitors (CB2, CB4) are connected to the external analog
supply pin (EVDD, pin 28) and external digital supply pin (DEVDD, pin 15). Capacitors
CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage
regulators to ensure stable operation. All bypass capacitors should be placed as close
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AT86RF212
8168A-AVR-06/08
AT86RF212
as possible to the pins and should have a low-resistance and low-inductance
connection to ground to achieve the best performance.
The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry
connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best
accuracy and stability of the reference frequency, large parasitic capacitances should
be avoided. Crystal lines should be routed as short as possible and not in proximity of
digital I/O signals. This is especially required for the High Data Rate Modes, refer to
chapter 7.1.4. Crosstalk from digital signals on the crystal pins or the RF pins can
degrade the system performance. Therefore, a low-pass filter (C3, R1) is placed close
to the CLKM output pin to reduce the emission of CLKM signal harmonics. This is not
needed if the CLKM pin is not used as a microcontroller clock source. In that case, the
output should be turned off during device initialization.
The ground plane of the application board should be separated into four independent
fragments, the analog, the digital, the antenna and the XTAL ground plane. The
exposed paddle shall act as the reference point of the individual grounds.
Table 3-1. Example Bill of Materials (BoM) for Basic Application Schematic
Designator
Description
Value
Manufacturer
Part Number
B1
SMD balun
F1
SMD low pass filter
CB1, CB3
900 MHz
Wuerth
JTI
748431090
0900BL18B100
900 MHz
Wuerth
JTI
748131009
0898LP18A035
LDO VREG
bypass capacitor
1 μF
AVX
Murata
0603YD105KAT2A
GRM188R61C105KA12D
X5R
(0603)
10%
16 V
CB2, CB4
Power supply bypass
capacitor
1 μF
CX1, CX2
Crystal load capacitor
12 pF
AVX
Murata
06035A120JA
GRP1886C1H120JA01
COG
(0603)
5%
50 V
C1, C2
RF coupling capacitor
68 pF
Epcos
Epcos
AVX
B37930
B37920
06035A680JAT2A
C0G
5%
50 V
AVX
Murata
06035A229DA
GRP1886C1H2R0DA01
COG
(0603)
C3
CLKM low-pass
filter capacitor
2.2 pF
Comment
(0402 or 0603)
±0.5 pF
50 V
Designed for fCLKM = 1 MHz
R1
CLKM low-pass
filter resistor
XTAL
Crystal
680 Ω
CX-4025 16 MHz ACAL Taitien
SX-4025 16 MHz Siward
Designed for fCLKM = 1 MHz
XWBBPL-F-1
A207-011
3.2 Extended Feature Set Application Schematic
For using the extended features
• Antenna Diversity
uses pins DIG1/DIG2 (1)
section 9.3
• RX/TX Indicator
uses pins DIG3/DIG4
section 9.4
• RX Frame Time Stamping
uses pin DIG2
section 9.5
an extended application schematic is required.
All other extended features (see section 9) do not need an extended schematic.
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8168A-AVR-06/08
An extended feature set application schematic illustrating the use of the AT86RF212
Extended Feature Set is shown in Figure 3-2. Although this example shows all
additional hardware features combined, it is possible to use all features separately or in
various combinations.
Figure 3-2. Extended Feature Application Schematic
VCC
CB2
CX1
CX2
XTAL
AVDD
EVDD
AVSS
XTAL1
XTAL2
2 DIG4
/SEL 23
3 AVSS
MOSI 22
4 RFP
B1
MISO 20
DVSS 18
DVSS
7 DVSS
DEVDD
SCLK 19
DVDD
6 AVSS
9
10
11
12
13
14
15
16
8 /RST
ANT1
DVSS 21
AT86RF212
5 RFN
C2
IRQ 24
CB3
Digital Interface
25
DVDD
SW1
26
DVSS
N1
27
SLP_TR
F1
28
DIG2
PA
C1
30 29
DIG1
LNA
RFSwitch
SW2
RFSwitch
N2
31
AVSS
1 DIG3
32
AVSS
ANT0
AVSS
CB1
CLKM 17
R1
C3
CB4
In this example, a balun (B1) transforms the differential radio transceiver RF pins
(RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic;
refer to Figure 3-1. The RF-Switches (SW1, SW2) separate between receive and
transmit path in an external RF front-end.
These switches are controlled by the RX/TX Indicator, represented by the differential
pin pair DIG3/DIG4, refer to 9.4.
During receive the corresponding microcontroller may search for the most reliable RF
signal path using an Antenna Diversity algorithm or stored statistic data of link signal
quality. One antenna is selected (SW2) by the Antenna Diversity RF switch control pin
DIG1 (1), the RF signal is amplified by an optional low-noise amplifier (N2) and fed to the
radio transceiver using the second RX/TX switch (SW1).
During transmit the AT86RF212 TX signal is amplified using an external PA (N1), low
pass filtered to suppress spurious harmonics emission and fed to the antennas via an
RF switch (SW2). In this example RF switch SW2 further supports Antenna Diversity
controlled by pin DIG1 (1).
Note:
12
1. DIG1/DIG2 can be used as a differential pin pair to control an RF switch if RX
Frame Time Stamping is not used, refer to sections 9.3 and 9.5, respectively.
AT86RF212
8168A-AVR-06/08
AT86RF212
4 Microcontroller Interface
4.1 Overview
This section describes the AT86RF212 to microcontroller interface. The interface
comprises a slave SPI and additional control signals; see Figure 4-1. The SPI timing
and protocol are described below.
Figure 4-1. Microcontroller to AT86RF212 Interface
AT86RF212
/SEL
/SEL
/SEL
MOSI
MOSI
MOSI
MISO
MISO
MISO
SCLK
SCLK
SCLK
GPIO1/CLK
CLKM
CLKM
GPIO2/IRQ
IRQ
SPI - Master
SPI - Slave
SPI
Microcontroller
IRQ
SLP_TR
GPIO3
SLP_TR
GPIO4
/RST
/RST
GPIO5
DIG2
DIG2
Microcontrollers with a master SPI such as Atmel’s AVR family interface directly to the
AT86RF212. The SPI is used for register, Frame Buffer, SRAM, and AES access. The
additional control signals are connected to the GPIO/IRQ interface of the
microcontroller.
Table 4-1 introduces the radio transceiver I/O signals and their functionality.
Table 4-1. Signal Description of Microcontroller Interface
Signal
Description
/SEL
SPI select signal, active low
MOSI
SPI data (Master Output Slave Input) signal
MISO
SPI data (Master Input Slave Output) signal
SCLK
SPI clock signal
CLKM
Clock output, refer to section 7.7.4, usable as:
- microcontroller clock source
- high precision timing reference
- MAC timer reference
IRQ
Interrupt request signal, further used as:
- Frame Buffer Empty indicator, refer to section 9.6.
SLP_TR
Multi purpose control signal, see section 4.6:
- Sleep/Wakeup
- TX start
- disable/enable CLKM
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8168A-AVR-06/08
Signal
Description
/RST
AT86RF212 reset signal, active low
4.2 SPI Timing Description
Pin 17 (CLKM) can be used as a microcontroller master clock source. If the
microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI
operates in synchronous mode, otherwise in asynchronous mode.
In synchronous mode, the maximum SCLK frequency is 8 MHz.
In asynchronous mode, the maximum SCLK frequency is limited to 7.5 MHz. The signal
at pin CLKM is not required to derive SCLK and may be disabled to reduce power
consumption and spurious emissions.
Figure 4-2 and Figure 4-3 illustrate the SPI timing and introduces its parameters. The
corresponding timing parameter definitions t1 – t9 are defined in section 10.4.
Figure 4-2. SPI Timing, Global Map, and Definition of Timing Parameters t5, t6, t8 and t9
t8
t9
/SEL
SCLK
MOSI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
t5
MISO
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
t6
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 4-3. SPI Timing, Detailed Drawing of Timing Parameter t1 to t4
/SEL
SCLK
t3
MOSI
t4
Bit 7
Bit 6
t1
MISO
Bit 5
t2
Bit 7
Bit 6
Bit 5
The SPI is based on a byte-oriented protocol and is always a bidirectional
communication between master and slave. The SPI master starts the transfer by
asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one
byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte
to the master (via MISO). When the master wants to receive one byte of data from the
slave it must also transmit one byte to the slave. All bytes are transferred with MSB first.
An SPI transaction is finished by releasing /SEL = H.
/SEL = L enables the MISO output driver of the AT86RF212. The MSB of MISO is valid
after t1 (see section 10.4, parameter 10.4.3) and is updated at each falling edge of
SCLK. If the driver is disabled, there is no internal pull-up resistor connected to it.
5
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Driving the appropriate signal level must be ensured by the master device or an
external pull-up resistor. Note, when both /SEL and /RST are active, the MISO output
driver is also enabled.
Referring to Figure 4-2 and Figure 4-3 MOSI is sampled at the rising edge of the SCLK
signal and the output is set at the falling edge of SCLK. The signal must be stable
before and after the rising edge of SCLK as specified by t3 and t4, refer to section 10.4,
parameters 10.4.5 and 10.4.6.
5
5
This SPI operational mode is commonly known as “SPI mode 0”.
4.3 SPI Protocol
Each SPI sequence starts with transferring a command byte from the SPI master via
MOSI (see Table 4-2) with MSB first. This command byte defines the SPI access mode
and additional mode-dependent information.
Table 4-2. SPI Command Byte Definition
Bit 7
Bit 6
1
0
Register address [5:0]
1
1
Register address [5:0]
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
1
Reserved
1
1
Reserved
0
0
Reserved
1
0
Reserved
Bit 1
Bit 0
Access Mode
Access Type
Register access
Read access
Write access
Frame Buffer access
Read access
Write access
SRAM access
Read access
Write access
Each SPI transfer returns bytes back to the SPI master on MISO. The content of the
first byte is the PHY_STATUS field, see section 4.4.
In Figure 4-4 to Figure 4-14 and the following chapters logic values stated with XX on
MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return
values on MISO stated as XX shall be ignored by the microcontroller.
The different access modes are described within the following sections.
4.3.1 Register Access Mode
A register access mode is a two-byte read/write operation initiated by /SEL = L. The first
transferred byte on MOSI is the command byte including an identifier bit (bit7 = 1), a
read/write select bit (bit 6), and a 6-bit register address.
On read access, the content of the selected register address is returned in the second
byte on MISO (see Figure 4-4).
Figure 4-4. Register Access Mode – Read Access
byte 1 (command byte)
MOSI
MISO
Note:
1
0
ADDRESS[5:0]
PHY_STATUS
(1)
byte 2 (data byte)
XX
READ DATA[7:0]
1. Each SPI access can be configured to return PHY status information
(PHY_STATUS) on MISO, refer to section 4.4.
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On write access, the second byte transferred on MOSI contains the write data to the
selected address (see Figure 4-6).
Figure 4-5. Register Access Mode – Write Access
byte 1 (command byte)
MOSI
1
1
MISO
byte 2 (data byte)
ADDRESS[5:0]
WRITE DATA[7:0]
PHY_STATUS
XX
Each register access must be terminated by setting /SEL = H.
Figure 4-6 illustrates a typical SPI sequence for a register access sequence for write
and read respectively.
Figure 4-6. Example SPI Sequence – Register Access Mode
Register Write Access
Register Read Access
/SEL
SCLK
MOSI
WRITE COMMAND
MISO
PHY_STATUS
WRITE DATA
READ COMMAND
XX
XX
PHY_STATUS
READ DATA
4.3.2 Frame Buffer Access Mode
The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one
IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed
description of the Frame Buffer can be found in section 7.4. An introduction to the
IEEE 802.15.4 frame format can be found in section 6.1.
Frame Buffer read and write accesses are used to read or write frame data (PSDU and
additional information) from or to the Frame Buffer. Each access starts with /SEL = L
followed by a command byte on MOSI. If this byte indicates a frame read or write
access, the next byte PHR indicates the frame length followed by the PSDU data, see
Figure 4-7 and Figure 4-8.
On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO
starting with the second byte. After the PSDU data, three more bytes are transferred
containing the link quality indication (LQI) value, the energy detection (ED) value and
the status information (RX_STATUS) of the received frame. Figure 4-7 illustrates the
packet structure of a Frame Buffer read access. The structure of RX_STATUS is
described in Table 4-3.
Figure 4-7. Packet Structure - Frame Read Access
byte 1 (command byte)
byte 2 (data byte)
byte 3 (data byte)
byte n-1 (data byte)
byte n (data byte)
MOSI
0 0 1 reserved[5:0]
XX
XX
XX
XX
MISO
PHY_STATUS
PHR[7:0]
PSDU[7:0]
ED[7:0]
RX_STATUS[7:0]
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Table 4-3. RX_STATUS
Bit
7
6
Register
0x06, PHY_RSSI[7]
0x02, TRX_STATE[7:5]
Name
RX_CRC_VALID
TRAC_STATUS
Section
6.3.5
5.2.6
Bit
3
2
Register
0x0c, TRX_CTRL_2[3:0]
Name
BPSK_OQPSK
Section
7.1.5
5
4
1
SUB_MODE
0
OQPSK_DATA_RATE
Note, the Frame Buffer read access can be terminated at any time without any
consequences by setting /SEL = H, e.g. after reading the frame length byte only. A
successive Frame Buffer read operation starts again at the PHR field.
On Frame Buffer write access the second byte transferred on MOSI contains the frame
length (PHR field) followed by the payload data (PSDU) as shown by Figure 4-8.
Figure 4-8. Packet Structure - Frame Write Access
byte 1 (command byte)
byte 2 (data byte)
byte 3 (data byte)
byte n-1 (data byte)
byte n (data byte)
MOSI
0 1 1 reserved[5:0]
PHR[7:0]
PSDU[7:0]
PSDU[7:0]
PSDU[7:0]
MISO
PHY_STATUS
XX
XX
XX
XX
The number of bytes n for one frame buffer access is calculated as follows:
Read Access: n = 5 + frame_length
[PHY_STATUS, PHR, PSDU data, LQI, ED, and RX_STATUS]
Write Access: n = 2 + frame_length
[command byte, PHR, and PSDU data]
The maximum value of frame_length is 127 bytes. That means that n ≤ 132 for Frame
Buffer read and n ≤ 129 for Frame Buffer write accesses.
Each read or write of a data byte automatically increments the address counter of the
Frame Buffer until the access is terminated by setting /SEL = H.
Figure 4-9 and Figure 4-10 illustrate an example SPI sequence of a Frame Buffer
access to read a frame with 2-byte PSDU and write a frame with 4-byte PSDU.
Figure 4-9. Example SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU
/SEL
SCLK
MOSI
COMMAND
XX
MISO
PHY_STATUS
PHR
XX
PSDU 1
XX
PSDU 2
XX
LQI
XX
ED
XX
RX_STATUS
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Figure 4-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4-byte PSDU
/SEL
SCLK
MOSI
COMMAND
MISO
PHY_STATUS
PHR
PSDU 1
XX
XX
PSDU 2
XX
PSDU 3
PSDU 4
XX
XX
Access violations during a Frame Buffer read or write access are indicated by interrupt
IRQ_6 (TRX_UR). For further details, refer to section 7.4.
Notes
• The Frame Buffer is shared between RX and TX; therefore, the frame data are
overwritten by new incoming frames. If the TX frame data are to be retransmitted, it
must be ensured that no frame was received in the meanwhile.
• To avoid overwriting during receive Dynamic Frame Buffer Protection can be
enabled, refer to section 9.7.
• For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode
(TX_ARET) refer to section 5.2.4.
4.3.3 SRAM Access Mode
The SRAM access mode allows accessing dedicated bytes within the Frame Buffer.
This may reduce the SPI traffic.
During frame receive after occurrence of IRQ_2 (RX_START) an SRAM access can be
used to upload the PHR field while preserving Dynamic Frame Buffer Protection, see
9.7.
Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the
command byte and must indicate an SRAM access mode according to the definition in
Table 4-2. The following byte indicates the start address of the write or read access.
The address space is 0x00 to 0x7F for radio transceiver receive or transmit operations.
The security module (AES) uses an address space from 0x82 to 0x94, refer to
section 9.1.
On SRAM read access, one or more bytes of read data are transferred on MISO
starting with the third byte of the access sequence (see Figure 4-11).
Figure 4-11. Packet Structure – SRAM Read Access
byte 1 (command byte)
byte 2 (address)
byte 3 (data byte)
byte n-1 (data byte)
byte n (data byte)
MOSI
0 0 0 reserved[5:0]
ADDRESS[7:0]
XX
XX
XX
MISO
PHY_STATUS
XX
DATA[7:0]
DATA[7:0]
DATA[7:0]
On SRAM write access, one or more bytes of write data are transferred on MOSI
starting with the third byte of the access sequence (see Figure 4-12). Do not attempt to
read or write bytes beyond the SRAM buffer size.
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Figure 4-12. Packet Structure – SRAM Write Access
byte 1 (command byte)
byte 2 (address)
byte 3 (data byte)
byte n-1 (data byte)
byte n (data byte)
MOSI
0 1 0 reserved[5:0]
ADDRESS[7:0]
DATA[7:0]
DATA[7:0]
DATA[7:0]
MISO
PHY_STATUS
XX
XX
XX
XX
As long as /SEL = L, every subsequent byte read or byte write increments the address
counter of the Frame Buffer until the SRAM access is terminated by /SEL = H.
Figure 4-13 and Figure 4-14 illustrate an example SPI sequence of a SRAM access to
read and write a data package of 5-byte length respectively.
Figure 4-13. Example SPI Sequence – SRAM Read Access of a 5-byte Data Package
/SEL
SCLK
MOSI
COMMAND
MISO
PHY_STATUS
ADDRESS
XX
XX
DATA 1
XX
DATA 2
XX
DATA 3
XX
XX
DATA 4
DATA 5
DATA 4
DATA 5
Figure 4-14. Example SPI Sequence – SRAM Write Access of a 5-byte Data Package
/SEL
SCLK
MOSI
COMMAND
MISO
PHY_STATUS
ADDRESS
XX
DATA 1
XX
DATA 2
XX
DATA 3
XX
XX
XX
Notes
• The SRAM access mode is not intended to be used as an alternative to the Frame
Buffer access modes (see section 4.3.2).
• Frame Buffer access violations are not indicated by a TRX_UR interrupt when using
the SRAM access mode, for further details refer to section 7.4.3.
4.4 PHY Status Information
Each SPI access can be configured to return status information of the radio transceiver
(PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO.
The content of the radio transceiver status information can be configured using register
bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the
first byte send on MISO to the microcontroller is set to 0x00.
4.4.1 Register Description – SPI Control
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating
modes and settings of the radio transceiver.
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Table 4-4. Register 0x04 (TRX_CTRL_1)
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
SPI_CMD_MODE
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – PA_EXT_EN
Refer to section 9.4.3.
• Bit 6 – IRQ2_EXT_EN
Refer to section 9.5.2.
• Bit 5 – TX_AUTO_CRC_ON
Refer to section 6.3.5.
• Bit 4 – RX_BL_CTRL
Refer to section 9.6.2.
• Bit 3:2 – SPI_CMD_MODE
Each SPI transfer returns bytes back to the SPI master. The content of the first byte can
be configured using register bits SPI_CMD_MODE. The transfer of the following status
information can be configured as follows:
Table 4-5. PHY Status Information
Register Bits
Value
SPI_CMD_MODE
Description
0
default (empty, all bits 0x00)
1
monitor TRX_STATUS register
see 5.1.5
2
monitor PHY_RSSI register
see 6.4
3
monitor IRQ_STATUS register
see 4.7
• Bit 1 – IRQ_MASK_MODE
Refer to section 4.7.2.
• Bit 0 – IRQ_POLARITY
Refer to section 4.7.2.
4.5 Radio Transceiver Identification
The AT86RF212 can be identified by four registers. One register contains a unique part
number and one register the corresponding version number. Additional two registers
contain the JEDEC manufacture ID.
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4.5.1 Register Description
Register 0x1C (PART_NUM):
Table 4-6. Register 0x1C (PART_NUM)
Bit
7
6
5
4
Name
3
1
0
1
1
1
2
1
0
0
0
1
2
1
0
1
1
1
PART_NUM[7:0]
Read/Write
Reset Value
2
R
0
0
0
0
0
• Bit 7:0 – PART_NUM
This register contains the radio transceiver part number.
Table 4-7. Radio Transceiver Part Number
Register Bits
Value
PART_NUM
State Description
7
AT86RF212 part number
Register 0x1D (VERSION_NUM):
Table 4-8. Register 0x1D (VERSION_NUM)
Bit
7
6
5
4
Name
3
VERSION_NUM[7:0]
Read/Write
Reset Value
R
0
0
0
0
0
• Bit 7:0 – VERSION_NUM
This register contains the radio transceiver version number.
Table 4-9. Radio Transceiver Version Number
Register Bits
Value
VERSION_NUM
State Description
1
Revision A
Register 0x1E (MAN_ID_0):
Table 4-10. Register 0x1E (MAN_ID_0)
Bit
7
6
5
4
Name
3
MAN_ID_0[7:0]
Read/Write
Reset Value
R
0
0
0
1
1
• Bit 7:0 – MAN_ID_0
Bits [7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0.
Bits [15:8] are stored in register 0x1F (MAN_ID_1). The highest 16 bits of the ID are not
stored in registers.
Table 4-11. JEDEC Manufacturer ID – Bits [7:0]
Register Bits
MAN_ID_0
Value
0x1F
State Description
Atmel JEDEC manufacturer ID,
Bits [7:0] of 32 bit manufacturer ID: 00 00 00 1F
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Register 0x1F (MAN_ID_1):
Table 4-12. Register 0x1F (MAN_ID_1)
Bit
7
6
5
4
Name
3
2
1
0
0
0
0
MAN_ID_1[7:0]
Read/Write
Reset Value
R
0
0
0
0
0
• Bit 7:0 – MAN_ID_1
Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1.
Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not
stored in registers.
Table 4-13. JEDEC Manufacturer ID – Bits [15:8]
Register Bits
MAN_ID_1
Value
0x00
State Description
Atmel JEDEC manufacturer ID
Bits [15:8] of 32 bit manufacturer ID: 00 00 00 1F
4.6 Sleep/Wake-up and Transmit Signal (SLP_TR)
Pin 11 (SLP_TR) is a multi-functional pin. Its function relates to the current state of the
AT86RF212 and is summarized in Table 4-14. The radio transceiver states are
explained in detail in section 5.
Table 4-14. SLP_TR Multi-functional Pin
Transceiver Status
Function
PLL_ON
TX start
Transition Description
LÆH
Starts frame transmission
TX_ARET_ON
TX start
LÆH
Starts TX_ARET transaction
BUSY_RX_AACK
TX start
LÆH
Starts ACK transmission during RX_AACK slotted operation, see section
5.2.3.5.
TRX_OFF
Sleep
LÆH
Takes the radio transceiver into SLEEP state, CLKM disabled
SLEEP
Wakeup
HÆL
Takes the radio transceiver back into TRX_OFF state, level sensitive
RX_ON
Disable CLKM
LÆH
Takes the radio transceiver into RX_ON_NOCLK state and disables CLKM
RX_ON_NOCLK
Enable CLKM
HÆL
Takes the radio transceiver into RX_ON state and enables CLKM
RX_AACK_ON
Disable CLKM
LÆH
Takes the radio transceiver into RX_AACK_ON_NOCLK state and
disables CLKM
RX_AACK_ON_NOCLK
Enable CLKM
HÆL
Takes the radio transceiver into RX_AACK_ON state and enables CLKM
In states PLL_ON and TX_ARET_ON, pin SLP_TR is used as trigger input to initiate a
TX transaction. Here pin SLP_TR is sensitive on rising edge only.
After initiating a state change by a rising edge at pin SLP_TR in radio transceiver states
TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the new state as
long as the pin is logical high and returns to the preceding state with the falling edge.
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SLEEP state
The SLEEP state is used when radio transceiver functionality is not required, and thus
the AT86RF212 can be powered down to reduce the overall power consumption.
A power-down scenario is shown in Figure 4-15. When the radio transceiver is in
TRX_OFF state the microcontroller forces the AT86RF212 to SLEEP by setting
SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is
switched off after 35 clock cycles. This enables a microcontroller in a synchronous
system to complete its power-down routine and prevent deadlock situations. The
AT86RF212 awakes when the microcontroller releases pin SLP_TR. This concept
provides the lowest possible power consumption.
The CLKM clock frequency settings for CLKM_CTRL values 6 and 7 are not intended to
directly clock the microcontroller. When using these clock rates, CLKM is turned off
immediately when entering SLEEP state.
Figure 4-15. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer
SLP_TR
tTR2
CLKM
35 CLKM clock cycles
CLKM off
async timer elapses
(microcontroller)
Note:
Timing figure tTR2 refer to Table 5-1.
RX_ON and RX_AACK_ON states
For synchronous systems, where CLKM is used as a microcontroller clock source and
the SPI master clock (SCLK) is directly derived from CLKM, the AT86RF212 supports
an additional power-down mode for receive operating states (RX_ON and
RX_AACK_ON).
If an incoming frame is expected and no other applications are running on the
microcontroller, it can be powered down without missing incoming frames.
This can be achieved by a rising edge on pin SLP_TR that turns off the CLKM. Then
the radio transceiver state changes from RX_ON or RX_AACK_ON (Extended
Operating Mode) to RX_ON_NOCLK or RX_AACK_ON_NOCLK respectively.
In case that a frame is received (e.g. indicated by an IRQ_2 (RX_START) interrupt) the
clock output CLKM is automatically switched on again.
This scenario is shown in Figure 4-16. In RX_ON state, the clock at pin 17 (CLKM) is
switched off after 35 clock cycles when setting the pin SLP_TR = H.
The CLKM clock frequency settings for CLKM_CTRL values 6 and 7 are not intended to
directly clock the microcontroller. When using these clock rates, CLKM is turned off
immediately when entering RX_ON_NOCLK and RX_AACK_ON_NOCLK respectively.
In states RX_(AACK)_ON_NOCLK and RX_(AACK)_ON, the radio transceiver current
consumptions are equivalent. However, the RX_(AACK)_ON_NOCLK current
consumption is reduced by the current required for driving pin 17 (CLKM).
23
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Figure 4-16. Wake-Up Initiated by Radio Transceiver Interrupt
radio transceiver
IRQ issued
IRQ
typ. 5 µs
SLP_TR
CLKM
35 CLKM clock cycles
CLKM off
4.7 Interrupt Logic
4.7.1 Overview
The AT86RF212 supports 8 interrupt requests as listed in Table 4-15. Each interrupt is
enabled by setting the corresponding bit in the interrupt mask register
0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the
interrupt status register. All interrupt events are OR-combined to a single external
interrupt signal (IRQ, pin 24). If an interrupt is issued (pin IRQ = H), the microcontroller
shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of
the interrupt. A read access to this register clears the interrupt status register and thus
the IRQ pin, too.
Interrupts are not cleared automatically when the event that caused them vanishes.
Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) because the
occurrence of one clears the other.
The supported interrupts for the Basic Operating Mode are summarized in Table 4-15.
Table 4-15. Interrupt Description in Basic Operating Mode
IRQ Name
Description
Section
IRQ_7 (BAT_LOW)
Indicates a supply voltage below the programmed threshold.
7.6.4
IRQ_6 (TRX_UR)
Indicates a Frame Buffer access violation.
7.4.3
IRQ_5 (AMI)
Indicates address matching.
IRQ_4 (CCA_ED_READY)
Multi-functional interrupt:
1. AWAKE_END:
•
Indicates radio transceiver reached TRX_OFF state at the end of P_ON Ö
TRX_OFF and SLEEP Ö TRX_OFF state transition
2. CCA_ED_READY:
•
Indicates the end of a CCA or ED measurement
6.2
o
5.1.2.3
6.6.4
IRQ_3 (TRX_END)
RX: Indicates the completion of a frame reception.
TX: Indicates the completion of a frame transmission.
5.1.3
IRQ_2 (RX_START)
Indicates the start of a PSDU reception. The TRX_STATE changes to BUSY_RX, the
PHR is valid to be read from Frame Buffer.
5.1.3
IRQ_1 (PLL_UNLOCK)
Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state,
the PA is turned off immediately.
7.8.5
IRQ_0 (PLL_LOCK)
Indicates PLL lock.
7.8.5
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The interrupt IRQ_4 has two meanings, depending on the current radio transceiver
state, refer to register 0x01 (TRX_STATUS).
After P_ON, SLEEP, or RESET, the radio transceiver issues an interrupt
IRQ_4 (AWAKE_END) when it enters state TRX_OFF.
The second meaning is only valid for receive states. If the microcontroller initiates an
ED or CCA measurement, the completion of the measurement is indicated by interrupt
IRQ_4 (CCA_ED_READY), refer to sections 6.5.4 and 6.6.4 for details.
After P_ON or RESET all interrupts are disabled. During radio transceiver initialization it
is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF
state is entered. Note that AWAKE_END interrupt can usually not be seen when the
transceiver enters TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is
reset to mask all interrupts. In this case, state TRX_OFF is normally entered before the
microcontroller could modify the register.
The interrupt handling in Extended Operating Mode is described in section 5.2.5.
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt
event can be read from IRQ_STATUS register even if the interrupt itself is masked.
However, in that case no timing information for this interrupt is provided.
The IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04,
TRX_CTRL_1). The default behavior is active high, which means that pin IRQ = H
issues an interrupt request.
If “Frame Buffer Empty Indicator” is enabled during Frame Buffer read access the IRQ
pin has an alternative functionality, refer to section 9.6 for details.
4.7.2 Register Description
Register 0x0E (IRQ_MASK):
The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is
enabled if the corresponding bit is set to 1. All interrupts are disabled after power up
sequence (P_ON state) or reset (RESET state).
Table 4-16. Register 0x0E (IRQ_MASK)
Bit
7
6
5
4
Name
MASK_BAT_LOW
MASK_TRX_UR
MASK_AMI
MASK_
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
MASK_TRX_END
MASK_RX_START
MASK_
MASK_PLL_LOCK
CCA_ED_READY
PLL_UNLOCK
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
If an interrupt is enabled it is recommended to read the interrupt status register 0x0F
(IRQ_STATUS) first to clear the history.
Register 0x0F (IRQ_STATUS):
The IRQ_STATUS register contains the status of the pending interrupt requests.
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8168A-AVR-06/08
Table 4-17. Register 0x0F (IRQ_STATUS)
Bit
7
6
5
4
Name
BAT_LOW
TRX_UR
AMI
CCA_ED_READY
Read/Write
R
R
R
R
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
TRX_END
RX_START
PLL_UNLOCK
PLL_LOCK
Read/Write
R
R
R
R
Reset Value
0
0
0
0
By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the
issued interrupt can be identified. A read access to this register resets all interrupt bits,
and so clears the IRQ_STATUS register.
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt
event can be read from IRQ_STATUS register even if the interrupt itself is masked.
However in that case no timing information for this interrupt is provided.
If register bit IRQ_MASK_MODE is set, it is recommended to read the interrupt status
register 0x0F (IRQ_STATUS) first to clear the history.
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating
modes and settings of the radio transceiver.
Table 4-18. Register 0x04 (TRX_CTRL_1)
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
SPI_CMD_MODE
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – PA_EXT_EN
RX/TX Indicator, refer to section 9.4.3.
• Bit 6 – IRQ2_EXT_EN
The timing of a received frame can be determined by a separate pin. If register bit
IRQ_2_EXT_EN is set to 1, the reception of a PHR field is directly issued on
pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START). Note that this pin is also active
even if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register
0x0E (IRQ_MASK) is set to 0. The pin remains at high level until the end of the frame
receive procedure.
For further details refer to section 9.5.
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AT86RF212
• Bit 5 – TX_AUTO_CRC_ON
Refer to section 6.3.5.
• Bit 4 – RX_BL_CTRL
Refer to section 9.6.2.
• Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
• Bit 1 – IRQ_MASK_MODE
The AT86RF212 supports polling of interrupt events. Interrupt polling can be enabled by
register bit IRQ_MASK_MODE. Even if an interrupt request is masked by the
corresponding bit in register 0x0E (IRQ_MASK), the event is indicated in register
0x0F (IRQ_STATUS).
Table 4-19. Interrupt Polling Configuration
Register Bit
IRQ_MASK_MODE
Value
Description
0
Interrupt polling disabled
1
Interrupt polling enabled
• Bit 0 – IRQ_POLARITY
The default polarity of the IRQ pin is active high. The polarity can be configured to
active low via register bit IRQ_POLARITY, see Table 4-20.
Table 4-20. Configuration of Pin 24 (IRQ)
Register Bit
IRQ_POLARITY
Value
Description
0
pin IRQ high active
1
pin IRQ low active
This setting does not affect the polarity of the Frame Buffer Empty Indicator, refer to
section 9.6. The Frame Buffer Empty Indicator is always active high.
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8168A-AVR-06/08
5 Operating Modes
5.1 Basic Operating Mode
This section summarizes all states to provide the basic functionality of the AT86RF212,
such as receiving and transmitting frames, the power up sequence and sleep. The
Basic Operating Mode is designed for IEEE 802.15.4 and ISM applications; the
corresponding radio transceiver states are shown in Figure 5-1.
Figure 5-1. Basic Operating Mode State Diagram (for timing refer to Table 5-1)
SLEEP
(Sleep State)
XOSC=ON
Pull=ON
XOSC=OFF
Pull=OFF
=
L
P_ON
(Power-on after EVDD)
H
=
11
_O
N
_O
FF
RX
TR
X
RX_ON
PLL_ON
(PLL State)
PLL_ON 9
Frame
End
10
BUSY_TX
(Transmit State)
=
H
SLP_TR = H
or
TX_START
FORCE_PLL_ON
TR
14
SL
P_
TR
=
L
SL
P_
SHR
Detected
Frame
End
N
F
RX_ON
O
L_
PL
RX_ON_NOCLK
8
(Rx Listen State)
4
OF
BUSY_RX
(Receive State)
SHR
Detected
5
X_
TR
6
RESET
(all states except P_ON)
XOSC=ON
Pull=OFF
7
/RST = H
13
(Clock State)
(all states except SLEEP)
/RST = L
TR
TRX_OFF
12
(from all states)
SL
P_
FF
O
X_
TR
FORCE_TRX_OFF
2
1
SL
P_
TR
3
(Rx Listen State)
(all states except SLEEP,
P_ON, TRX_OFF, RX_ON_NOCLK)
Legend:
Blue: SPI Write to Register TRX_STATE (0x02)
Red: Control signals via IC Pin
Green: Event
Basic Operating Mode States
CLKM=OFF
X
State transition number, see Table 7-1
5.1.1 State Control
The radio transceiver states are controlled either by writing commands to register bits
TRX_CMD (register 0x02, TRX_STATE), or directly by two signal pins:
pin 11 (SLP_TR) and pin 8 (/RST). A successful state change can be verified by
reading the radio transceiver status from register 0x01 (TRX_STATUS).
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AT86RF212
If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF212 is in
a state transition. Do not try to initiate a further state change while the radio transceiver
is in STATE_TRANSITION_IN_PROGRESS.
Pin SLP_TR is a multifunctional pin, refer to section 4.6. Depending on the radio
transceiver state, a rising edge of pin SLP_TR causes the following state transitions:
• TRX_OFF
→
SLEEP
• RX_ON
→
RX_ON_NOCLK
• PLL_ON
→
BUSY_TX
whereas the falling edge of pin SLP_TR causes the following state transitions:
• SLEEP
• RX_ON_NOCLK
→
→
TRX_OFF
RX_ON
Pin 8 (/RST) causes a reset of all registers (register bits CLKM_CTRL are shadowed,
for details refer to section 7.7.4), and the content of the SRAM it deleted. It forces the
radio transceiver into TRX_OFF state. However, if the device was in P_ON state it
remains in P_ON state.
For all states except SLEEP, the state change commands FORCE_TRX_OFF or
TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active
receive or transmit states (BUSY_*), the command FORCE_TRX_OFF interrupts these
active processes, and forces an immediate transition to TRX_OFF. By contrast a
TRX_OFF command is stored until an active state (receiving or transmitting) has been
finished. After that the transition to TRX_OFF is performed.
For a fast transition from receive or active transmit states to PLL_ON state the
command FORCE_PLL_ON is provided. Active processes are interrupted. In contrast
to FORCE_TRX_OFF this command does not disable the PLL and the analog voltage
regulator AVREG. It is not available in states SLEEP, RESET, and all *_NOCLK states.
The completion of each requested state change shall always be confirmed by reading
the register bits TRX_STATUS (register 0x01, TRX_STATUS).
5.1.2 Description
5.1.2.1 P_ON – Power-On after EVDD
When the external supply voltage (EVDD) is applied first to the AT86RF212 the radio
transceiver goes into P_ON state performing an on-chip reset. The crystal oscillator is
activated and the default 1 MHz master clock is provided at pin 17 (CLKM) after the
crystal oscillator has stabilized. CLKM can be used as a clock source to the
microcontroller. The SPI interface and digital voltage regulator are enabled.
The on-chip power-on-reset sets all registers to their default values. A dedicated reset
signal from the microcontroller at pin 8 (/RST) is not necessary, but recommended for
hardware/software synchronization reasons.
All digital inputs have pull-up or pull-down resistors during P_ON state, refer to section
2.2.2.2. This is necessary to support microcontrollers where GPIO signals are floating
after power on or reset. The input pull-up and pull-down resistors are disabled when the
radio transceiver leaves P_ON state. Leaving P_ON state, outputs pins DIG1/DIG2 are
internally connected to digital ground, whereas pins DIG3/DIG4 are internally connected
to analog ground, unless their configuration is changed. A reset at pin 8 (/RST) does
not enable the pull-up or pull-down resistors.
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8168A-AVR-06/08
Prior to leaving P_ON, the microcontroller must set the input pins to the default
operating values: SLP_TR = L, /RST = H and /SEL = H.
All interrupts are disabled by default. Thus, interrupts for state transition control are to
be enabled first, e.g. enable IRQ_4 (AWAKE_END) to indicate a state transition to
TRX_OFF state. In P_ON state a first access to the radio transceiver registers is
possible after a default 1 MHz master clock is provided at pin 17 (CLKM), refer to tTR1 in
Table 5-1.
Once the supply voltage has stabilized and the crystal oscillator has settled (see section
10.5, parameter tXTAL),. the interrupt mask for the AWAKE_END should be set. A valid
SPI write access to register bits TRX_CMD (register 0x02, TRX_STATE) with the
command TRX_OFF or FORCE_TRX_OFF initiates a state change from P_ON towards
TRX_OFF state, which is then indicated by an AWAKE_END interrupt if enabled.
5.1.2.2 SLEEP – Sleep State
In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating. The
radio transceiver current consumption is reduced to leakage current and the current of a
low power voltage regulator (typ. 100 nA), which provides the supply voltage for the
registers such that the contents of them remains valid. This state can only be entered
from state TRX_OFF, by setting SLP_TR = H.
If CLKM is enabled, the SLEEP state is entered 35 CLKM cycles after the rising edge at
pin 11 (SLP_TR). At that time CLKM is turned off. If the CLKM output is already turned
off (bits CLKM_CTRL = 0 in register 0x03), the SLEEP state is entered immediately.
At clock rates of 250 kHz and symbol clock rate (CLKM_CTRL values 6 and 7, register
0x03, TRX_CTRL_0), the main clock at pin 17 (CLKM) is turned off immediately.
Setting SLP_TR = L returns the radio transceiver back to the TRX_OFF state. During
SLEEP the register contents remains valid while the content of the Frame Buffer and
the security engine (AES) are cleared.
/RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby
sets all registers to their default values. Exceptions are register bits CLKM_CTRL
(register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for
details see section 7.7.4.
5.1.2.3 TRX_OFF – Clock State
In TRX_OFF, the crystal oscillator is running and the master clock is available at
pin 17 (CLKM). The SPI interface and digital voltage regulator are enabled, thus the
radio transceiver registers, the Frame Buffer and security engine (AES) are accessible
(see sections 7.4 and 9.1).
In contrast to P_ON state, pull-up and pull-down resistors are disabled.
Note that the analog front-end is disabled during TRX_OFF. If TRX_OFF_AVDD_EN
(register 0x0C, TRX_CTRL_2) is set, the analog voltage regulator is turned on, enabling
faster switch to any transmit/receive state.
Entering the TRX_OFF state from P_ON, SLEEP, or RESET state, the state change is
indicated by interrupt IRQ_4 (AWAKE_END) if enabled.
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AT86RF212
5.1.2.4 PLL_ON – PLL State
Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator
(AVREG) first, unless the AVREG is already switched on (register 0x0C,
TRX_OFF_AVDD_EN). After the voltage regulator has been settled (see
Table 5-2), the PLL frequency synthesizer is enabled. When the PLL has been settled
at the receive frequency to a channel defined by register bits CHANNEL (register 0x08,
PHY_CC_CCA), CC_NUMBER (register 0x013, CC_CTRL_0), and CC_BAND (register
0x014, CC_CTRL_1), a successful PLL lock is indicated by issuing an interrupt IRQ_0
(PLL_LOCK).
After the RX_ON command is issued in PLL_ON state, register bits TRX_STATUS
(register 0x01, TRX_STATUS) immediately indicate the radio being in RX_ON state.
However, frame reception can only start, once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
5.1.2.5 RX_ON and BUSY_RX – RX Listen and Receive State
The AT86RF212 receive mode is internally separated into RX_ON state and BUSY_RX
state. There is no difference between these states with respect to the analog radio
transceiver circuitry, which is always turned on. In both states the receiver and the PLL
frequency synthesizer are enabled.
During RX_ON state the receiver listens for incoming frames. After detecting a valid
synchronization header (SHR), the AT86RF212 automatically enters the BUSY_RX
state. The reception of a non-zero PHR field generates an IRQ_2 (RX_START), if
enabled.
During PSDU reception the frame data are stored continuously in the Frame Buffer until
the last byte was received. The completion of the frame reception is indicated by an
interrupt IRQ_3 (TRX_END) and the radio transceiver returns the state RX_ON. At the
same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with
the result of the FCS check (see section 6.3).
Received frames are passed to the address match filter, refer to section 6.2. If the
content of the MAC addressing fields (refer to IEEE 802.15.4 section 7.2.1) of a frame
matches to the expected addresses, which is further dependent on the addressing
mode, an address match interrupt IRQ_5 (AMI) is issued, refer to 4.7. The expected
address values are to be stored in registers 0x20 – 0x2B (Short address, PAN ID and
IEEE address). Frame filtering is available in Basic and Extended Operating Mode,
refer to section 6.2.
Leaving state RX_ON is only possible by writing a state change command to register
bits TRX_CMD in register 0x02 (TRX_STATE).
5.1.2.6 RX_ON_NOCLK – RX Listen State without CLKM
If the radio transceiver is listening for an incoming frame and the microcontroller is not
running an application, the microcontroller may be powered down to decrease the total
system power consumption. This specific power-down scenario for systems running in
clock synchronous mode (see section 4), is supported by the AT86RF212 using the
state RX_ON_NOCLK.
This state can only be entered by setting pin 11 (SLP_TR) = H while the radio
transceiver is in RX_ON state, refer to chapter 0. Pin 17 (CLKM) is disabled 35 clock
cycles after the rising edge at the SLP_TR pin, see Figure 4-16. This allows the
microcontroller to complete its power-down sequence.
31
8168A-AVR-06/08
Note that for CLKM clock rates 250 kHz and symbol clock rates (CLKM_CTRL values 6
and 7; register 0x03, TRX_CTRL_0) the master clock signal CLKM is switched off
immediately after rising edge of SLP_TR.
The reception of a frame shall be indicated to the microcontroller by an interrupt
indicating the receive status. CLKM is turned on again, and the radio transceiver enters
the BUSY_RX state (see section 4.6 and Figure 4-16). When using RX_ON_NOCLK, it
is essential to enable at least one interrupt request indicating the reception status.
After the receive transaction has been completed, the radio transceiver enters the
RX_ON state. The radio transceiver only reenters the RX_ON_NOCLK state, when the
next rising edge of pin SLP_TR pin occurs.
If the AT86RF212 is in the RX_ON_NOCLK state, and pin SLP_TR is reset to logic low,
it enters the RX_ON state, and it starts to supply clock on the CLKM pin again.
A reset in state RX_ON_NOCLK further requires to reset pin SLP_TR to logic low,
otherwise the radio transceiver enters directly the SLEEP state.
Note
• A reset in state RX_ON_NOCLK further requires to reset pin SLP_TR to logic low,
otherwise the radio transceiver enters directly the SLEEP state.
5.1.2.7 BUSY_TX – Transmit State
A transmission can only be initiated in state PLL_ON. There are two ways to start a
transmission::
• Rising edge of pin 11 (SLP_TR)
• TX_START command written
TRX_STATE).
to
register
bits
TRX_CMD
(register
0x02,
Either of these forces the radio transceiver into the BUSY_TX state.
During the transition to BUSY_TX state, the PLL frequency shifts to the transmit
frequency. The actual transmission of the first data chip of the SHR starts after 1
symbol period (refer to section 7.1.3) in order to allow PLL settling and PA ramp-up, see
Figure 5-6. After transmission of the SHR, the Frame Buffer content is transmitted. In
case the PHR indicates a frame length of zero, the transmission is aborted immediately
after the PHR field.
After the frame transmission has been completed, the AT86RF212 automatically turns
off the power amplifier, generates an IRQ_3 (TRX_END) interrupt and returns into
PLL_ON state.
5.1.2.8 RESET State
The RESET state is used to set back the state machine and to reset all registers of the
AT86RF212 to their default values, exception are register bits CLKM_CTRL (register
0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see
section 7.7.4.
A reset forces the radio transceiver into TRX_OFF state. If, however, the device is in
P_ON state it remains in P_ON state.
A reset is initiated with pin /RST = L and the state returns after setting /RST = H. The
reset pulse should have a minimum length as specified in section 10.4, parameter
10.4.13.
5
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AT86RF212
During reset, the microcontroller has to set the radio transceiver control pins SLP_TR
and /SEL to their default values.
An overview of the register reset values is provided in Table 12-2.
5.1.3 Interrupt Handling
All interrupts provided by the AT86RF212 (see Table 4-15) are supported in Basic
Operating Mode.
For example, interrupts are provided to observe the status of radio transceiver RX and
TX operations.
When being in receive mode, IRQ_2 (RX_START) indicates the detection of a non-zero
PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the
frame reception.
During transmission IRQ_3 (TRX_END) indicates the completion of the frame
transmission.
Figure 5-2 shows an example for a transmit/receive transaction between two devices
and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame
containing a MAC header, MAC payload and a valid FCS. The end of the frame
transmission is indicated by IRQ_3 (TRX_END).
The frame is received by Device 2. Interrupt IRQ_2 (RX_START) indicates the
detection of a valid PHR field, and IRQ_3 (TRX_END) the completion of the frame
reception. If the frame passes the Frame Filter, refer to 6.2, an address match interrupt
IRQ_5 (AMI) is issued after the reception of the MAC header (MHR).
Processing delay tIRQ is a typical value, refer to 0.
Figure 5-2. Timing of RX_START, AMI, and TRX_END Interrupts in Basic Operating Mode for O-QPSK 250 kbit/s Mode
128
160
192
PLL_ON
192+(9+m)*32
BUSY_TX
Time [µs]
PLL_ON
TX
(Device1)
TRX_STATE
0
SLP_TR
IRQ
Number of Octets
Frame Content
TRX_STATE
IRQ
Interrupt latency
tTR10
4
1
1
7
m
2
Preamble
SFD
PHR
MHR
MSDU
FCS
RX_ON
BUSY_RX
IRQ_2 (RX_START)
tIRQ
IRQ_5 (AMI)
tIRQ
Frame
on Air
Processing Delay
IRQ_3 (TRX_END)
RX_ON
TRX_END
tIRQ
RX
(Device 2)
-tTR10
5.1.4 Timing
The following paragraphs depict state transitions and their timing properties. Timings
are explained in Table 5-1 and section 10.4.
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5.1.4.1 Power_on Procedure
The power-on procedure during P_ON state is shown in Figure 5-3.
Figure 5-3. Power-on Procedure during P_ON State
100
0
Event
EVDD on
State
P_ON
Block
XOSC, DVREG
Time [µs]
400
CLKM on
tTR1
Time
When the external supply voltage (EVDD) is supplied to the AT86RF212, the radio
transceiver enables the crystal oscillator (XOSC) and the internal 1.8 V voltage
regulator for the digital domain (DVREG). After tTR1, the master clock signal is available
at pin 17 (CLKM) at default rate of 1 MHz. If CLKM is available, the SPI has already
been enabled and can be used to control the transceiver.
5.1.4.2 Wake-up Procedure
The wake-up procedure from SLEEP state is shown in Figure 5-4.
Figure 5-4. Wake-up Procedure from SLEEP State
0
SLP_TR = L
Event
State
Block
100
400
200
CLKM on
Time [µs]
IRQ_4 (AWAKE_END)
TRX_OFF
SLEEP
XOSC, DVREG
Time
FTN XOSC, DVREG
tTR2
The radio transceiver’s SLEEP state is left by releasing pin SLP_TR to logic low. This
restarts the XOSC and DVREG. After tTR2, the radio transceiver enters TRX_OFF state.
The internal clock signal is available and provided to pin 17 (CLKM), if enabled.
This procedure is similar to Power-On, however, the radio transceiver automatically
ends in TRX_OFF state. During this the filter-tuning network (FTN) calibration is
performed. Entering TRX_OFF state is signaled by IRQ_4 (AWAKE_END), if this
interrupt was enabled by the appropriate mask register bit.
5.1.4.3 State Change from TRX_OFF to PLL_ON / RX_ON
The transition from TRX_OFF to PLL_ON or RX_ON mode and further to RX_ON or
PLL_ON is shown in Figure 5-5.
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AT86RF212
Figure 5-5. Transition from TRX_OFF to PLL_ON/RX_ON State and further to
RX_ON/PLL_ON
0
IRQ_0 (PLL_LOCK)
Event
State
RX_ON /
PLL_ON
PLL_ON / RX_ON
TRX_OFF
Block
AVREG
Command
PLL_ON / RX_ON
PLL
RX_ON /
PLL_ON
tTR8/tTR9
tTR4 / tTR6
Time
Note:
Time [µs]
100
If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately, even
if the PLL has not settled.
In TRX_OFF state, entering the commands PLL_ON or RX_ON initiates a ramp-up
sequence of the internal 1.8 V voltage regulator for the analog domain (AVREG).
RX_ON state can be entered any time from PLL_ON state, regardless whether the PLL
has already locked, which is indicated by IRQ_0 (PLL_LOCK). Likewise, PLL_ON state
can be entered any time from RX_ON state.
When TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is already set in TRX_OFF
state the analog voltage regulator is turned on immediately and the ramp up sequence
to PLL_ON or RX_ON can be accelerated.
5.1.4.4 State Change from PLL_ON via BUSY_TX to RX_ON States
The transition from PLL_ON to BUSY_TX state and subsequently to RX_ON state is
shown in Figure 5-6.
Figure 5-6. PLL_ON to BUSY_TX to RX_ON Timing for O-QPSK 250 kbit/s Mode
0
SLP_TR=H or
TRX_CMD =TX_START
Event
State
16
PLL_ON
Time
TRX_CMD=RX_ON
BUSY_TX
tTR10
IRQ_3 (TRX_END)
RX_ON
TX
Block
x + 32 Time [µs]
x
PLL
RX
tTR11
Starting from PLL_ON, it is further assumed that the PLL has already been locked. A
transmission is initiated either by a rising edge of pin 11 (SLP_TR) or by command
TX_START. The PLL settles to the transmit frequency and the PA is enabled.
After the duration of tTR10 (1 symbol period), the AT86RF212 changes into BUSY_TX
state, transmitting the internally generated SHR and the PSDU data of the Frame
Buffer.
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8168A-AVR-06/08
After completing the frame transmission, indicated by IRQ_3 (TRX_END), the PLL
settles back to the receive frequency within tTR11 and returns to state PLL_ON.
If during BUSY_TX the radio transmitter is requested to change to a receive state, it
automatically proceeds to state RX_ON upon completion of the transmission, refer to
Figure 5-6.
5.1.4.5 Reset Procedure
The radio transceiver reset procedure is shown in Figure 5-7.
Figure 5-7. Reset Procedure
x
0
[IRQ_4 (AWAKE_END)]
Event
State
Time [µs]
x + 40
x + 10
any
undefined
TRX_OFF
FTN
Block
Pin /RST
Time
t10
t11
tTR13
/RST = L sets all registers to their default values. Exceptions are register bits
CLKM_CTRL (register 0x03, TRX_CTRL_0), refer to section 7.7.4.
After releasing the reset pin (/RST = H) the wake-up sequence including an FTN
calibration cycle is performed, refer to section 7.9. After that the TRX_OFF state is
entered.
Figure 5-7 illustrates the reset procedure once P_ON state was left and the radio
transceiver was not in SLEEP state.
The reset procedure is identical for all originating radio transceiver states except of
state P_ON and SLEEP state. Instead, the procedures described in section 5.1.2.1 and
5.1.2.2 must be followed to enter the TRX_OFF state.
If the radio transceiver was in SLEEP state, the XOSC and DVREG are enabled before
entering TRX_OFF state.
Notes
• The reset impulse should have a minimum length t10 as specified in section 10.4,
see parameter 10.4.13.
• An access to the device should not occur earlier than t11 after releasing the pin
/RST; refer to section 10.4, parameter 10.4.14.
• A reset overrides an SPI command that might be queued.
5
5
5.1.4.6 State Transition Timing Summary
Transition timings are listed in Table 5-1 and do not include SPI access time if not
otherwise stated. See measurement setup in Figure 3-1.
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Table 5-1. State Transition Timing
No
Symbol
Transition
Time [µs], typ.
Comments
1
tTR1
P_ON
Ö
until CLKM
available
380
Depends on crystal oscillator setup (CL = 10 pF) and external
capacitor at DVDD (1 µF nom.)
2
tTR2
SLEEP
Ö
TRX_OFF
240
Depends on crystal oscillator setup (CL = 10 pF) and external
capacitor at DVDD (1 µF nom.)
TRX_OFF state indicated by IRQ_4 (AWAKE_END)
3
tTR3
TRX_OFF
Ö
SLEEP
35 cycles
of CLKM
For fCLKM > 250 kHz
4
tTR4
TRX_OFF
Ö
PLL_ON
110
Depends on external capacitor at AVDD (1 µF nom.), if register
bit TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is not
set
If register bit TRX_OFF_AVDD_EN was set in a state where
the PLL has locked at the same frequency
20
5
tTR5
PLL_ON
Ö
TRX_OFF
1
6
tTR6
TRX_OFF
Ö
RX_ON
110
7
tTR7
RX_ON
Ö
TRX_OFF
1
8
tTR8
PLL_ON
Ö
RX_ON
1
9
tTR9
RX_ON
Ö
PLL_ON
1
Transition time is also valid for TX_ARET_ON, RX_AACK_ON
10
tTR10
PLL_ON
Ö
BUSY_TX
1 symbol
When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START
first symbol transmission is delayed by 1 symbol period (PLL
settling and PA ramp up), refer to section 7.1.3.
11
tTR11
BUSY_TX
Ö
PLL_ON
32
PLL settling time
12
tTR12
All modes
Ö
TRX_OFF
1
Using TRX_CMD = FORCE_TRX_OFF (see register 0x02,
TRX_STATE); not valid for SLEEP state
13
tTR13
RESET
Ö
TRX_OFF
26
Not valid for P_ON or SLEEP state
14
tTR14
Various
states
Ö
PLL_ON
1
Using TRX_CMD = FORCE_PLL_ON (see register 0x02,
TRX_STATE); not valid for SLEEP, P_ON, RESET,
TRX_OFF, and *_NO_CLK
Depends on external capacitor at AVDD (1 µF nom.), if register
bit TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is not
set
The state transition timing is calculated based on the timing of the individual blocks
shown in Figure 5-3 to Figure 5-7. The worst case values include maximum operating
temperature, minimum supply voltage, and device parameter variations, see
Table 5-2.
Table 5-2. Analog Block Initialization and Settling Times
Block
Time [µs], typ.
Time [µs], max.
XOSC
215
1000
FTN
25
Comments
Leaving SLEEP state, depends on crystal Q factor and load
capacitor
Filter tuning time
DVREG
60
1000
Depends on external bypass capacitor at DVDD
(CB3 = 1 µF nom., 10 µF worst case), and on EVDD voltage
AVREG
60
1000
Depends on external bypass capacitor at AVDD
(CB1 = 1 µF nom., 10 µF worst case) , and on EVDD voltage
37
8168A-AVR-06/08
Block
Time [µs], typ.
Time [µs], max.
Comments
PLL, initial
96
276
PLL settling time TRX_OFF > PLL_ON, including 60 µs
AVREG settling time
PLL, settling
11
21
Duration of channel switch within frequency band
PLL, CF cal.
8
270
PLL center frequency calibration, refer to section 7.8.4
PLL, DCU cal.
10
PLL DCU calibration, refer to section 7.8.4
PLL, RX Ö TX
16
PLL settling time RX Ö TX
PLL, TX Ö RX
32
PLL settling time TX Ö RX
5.1.5 Register Description
Register 0x01 (TRX_STATUS):
A read access to TRX_STATUS register signals the current radio transceiver state. A
state change is initiated by writing a state transition command to register bits
TRX_CMD (register 0x02, TRX_STATE). Alternatively, a state transition can be initiated
by the rising edge of pin 11 (SLP_TR) in the appropriate state.
This register is used for Basic and Extended Operating Mode, refer to section 5.2.
Table 5-3. Register 0x01 (TRX_STATUS)
Bit
7
6
5
4
Name
CCA_DONE
CCA_STATUS
Reserved
TRX_STATUS
Read/Write
R
R
R
R
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
TRX_STATUS
TRX_STATUS
TRX_STATUS
TRX_STATUS
Read/Write
R
R
R
R
Reset Value
0
0
0
0
• Bit 7 – CCA_DONE
Refer to section 6.6
• Bit 6 – CCA_STATUS
Refer to section 6.6
• Bit 5 – Reserved
• Bit 4:0 – TRX_STATUS
The register bits TRX_STATUS signal the current radio transceiver status. If the
requested state transition is not completed yet, the TRX_STATUS returns
STATE_TRANSITION_IN_PROGRESS. Do not try to initiate a further state change
while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. State transition
timings are defined in Table 5-1.
Table 5-4. Radio Transceiver Status, Register Bits TRX_STATUS
38
Register Bits
Value
State Description
TRX_STATUS
0x00
P_ON
0x01
BUSY_RX
0x02
BUSY_TX
AT86RF212
8168A-AVR-06/08
AT86RF212
Register Bits
Value
State Description
0x06
RX_ON
0x08
TRX_OFF (CLK Mode)
0x09
PLL_ON (TX_ON)
(3)
SLEEP
0x11
(1)
BUSY_RX_AACK
0x12
(1)
BUSY_TX_ARET
0x16
(1)
RX_AACK_ON
0x19
(1)
TX_ARET_ON
0x0F
0x1C
RX_ON_NOCLK
(1)
RX_AACK_ON_NOCLK
(1)
BUSY_RX_AACK_NOCLK
(2)
STATE_TRANSITION_IN_PROGRESS
0x1D
0x1E
0x1F
All other values are reserved
Notes:
1. Extended Operating Mode only, refer to section 5.2.
2. Do not try to initiate a further state change while the radio transceiver is in
STATE_TRANSITION_IN_PROGRESS state.
3. In SLEEP state register not accessible.
Register 0x02 (TRX_STATE):
Radio transceiver state changes can be initiated by writing register bits TRX_CMD. This
register is used for Basic and Extended Operating Mode, refer to section 5.2.
Table 5-5. Register 0x02 (TRX_STATE)
Bit
7
6
5
4
Name
TRAC_STATUS
TRAC_STATUS
TRAC_STATUS
TRX_CMD
Read/Write
R
R
R
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
TRX_CMD
TRX_CMD
TRX_CMD
TRX_CMD
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7:5 – TRAC_STATUS
Refer to section 5.2.6.
• Bit 4:0 – TRX_CMD
A write access to register bits TRX_CMD initiates a radio transceiver state transition.
Table 5-6. State Control Command, Register Bits TRX_CMD
Register Bits
Value
State Transition towards
TRX_CMD
0x00
NOP
0x02
TX_START
0x03
0x04
FORCE_TRX_OFF
(1)
FORCE_PLL_ON
39
8168A-AVR-06/08
Register Bits
Value
State Transition towards
0x06
RX_ON
0x08
TRX_OFF (CLK Mode)
0x09
PLL_ON (TX_ON)
0x16
(2)
RX_AACK_ON
0x19
(2)
TX_ARET_ON
All other values are reserved and mapped to NOP
Notes:
1. FORCE_PLL_ON is not valid for states SLEEP, RESET, and all *_NOCLK states,
as well as STATE_TRANSITION_IN_PROGRESS towards these states.
2. Extended Operating Mode only, refers to section 5.2.6.
5.2 Extended Operating Mode
The Extended Operating Mode is a hardware MAC accelerator and goes beyond the
basic radio transceiver functionality provided by the Basic Operating Mode. It handles
time critical MAC tasks, requested by the IEEE 802.15.4-2003/2006 standard, such as
automatic acknowledgement, automatic CSMA-CA, and retransmission. This results in
a more efficient IEEE 802.15.4-2003/2006 software MAC implementation including
reduced code size and may allow the use of a smaller microcontroller.
The Extended Operating Mode is designed to support IEEE 802.15.4-2003/2006
standard compliant frames and comprises the following procedures:
Automatic acknowledgement (RX_AACK transaction) divides into the tasks:
•
•
•
•
•
•
Frame reception and automatic FCS check
Configurable addressing fields check
Interrupt indicating address match
Interrupt indicating frame reception, if it passes frame filtering and FCS check
Automatic acknowledgment (ACK) frame transmission, if applicable
Support of slotted acknowledgment using SLP_TR pin (used for beacon-enabled
operation)
Automatic CSMA-CA and Retransmission (TX_ARET transaction) divides into the
tasks:
•
•
•
•
•
CSMA-CA including automatic CCA retry and random back-off
Frame transmission and automatic FCS field generation
Reception of ACK frame (if ACK was requested)
Automatic retry of transmissions if ACK was expected but not received or accepted
Interrupt signaling with transaction status
An AT86RF212 state diagram including the Extended Operating Mode states is shown
in Figure 5-8. Yellow marked states represent the Basic Operating Mode; blue marked
states represent the Extended Operating Mode.
40
AT86RF212
8168A-AVR-06/08
AT86RF212
Figure 5-8. Extended Operating Mode State Diagram
SLEEP
(Sleep State)
XOSC=ON
Pull=ON
XOSC=OFF
Pull=OFF
H
/RST = L
13
(Clock State)
(all modes except SLEEP)
(from all states)
P_
TR
=
TRX_OFF
12
FORCE_TRX_OFF
2
3
SL
F
OF
X_
TR
1
SL
P_
TR
=L
P_ON
(Power-on after EVDD)
/RST = H
RESET
(all modes except P_ON)
X_
OF
F
RX
(Rx Listen State)
Frame
End
SLP_TR=H
or
TX_START
11
RX_ON
PLL_ON
PLL_ON
(PLL State)
10
9
see notes
N
From
TRX_OFF
TX
_A
R
ET
_O
PLL_ON
AC
FORCE_PLL_ON
TX_ARET_ON
RX
_A
AC
K_
O
CLKM=OFF
K_
ON
ON
L_
N
(Rx Listen State)
RX
_A
From
TRX_OFF
PL
RX_ON_NOCLK
SHR
Detected
BUSY_RX_
AACK_NOCLK
CLKM=OFF
SHR
Detected
Frame
Rejected
SLP_TR=H
RX_AACK_ON
SLP_TR=L
Transaction
Finished
Frame
Accepted
BUSY_RX_AACK
Frame
End
14
=H
BUSY_TX
(Transmit State)
R
=L
P
SL
R
_T
SL
P_
T
SHR
Detected
(Receive State)
8
RX_ON
4
F
BUSY_RX
SHR
Detected
TR
6
5
OF
X_
TR
_O
7
ON
L_
PL
N
XOSC=ON
Pull=OFF
RX_AACK_
ON_NOCLK
CLKM=OFF
TX_ARET_ON
SLP_TR=H
or
TX_START
Frame
End
BUSY_TX_ARET
Legend:
Blue: SPI Write to Register TRX_STATE (0x02)
Red: Control signals via IC Pin
Green: Event
Basic Operating Mode States
Extended Operating Mode States
41
8168A-AVR-06/08
5.2.1 State Control
The Extended Operating Modes RX_AACK and TX_ARET are controlled via register
bits TRX_CMD (register 0x02, TRX_STATE), which receives the state transition
commands. The corresponding states, RX_AACK_ON and TX_ARET_ON,
respectively, are to be entered from states TRX_OFF or PLL_ON as illustrated by
Figure 5-8. The success of the state change shall be confirmed by reading register
0x01 (TRX_STATUS).
RX_AACK - Receive with Automatic ACK
A state transition to RX_AACK_ON from PLL_ON or TRX_OFF is initiated by writing the
command RX_AACK_ON to register bits TRX_CMD (register 0x02, TRX_STATE). On
success reading register 0x01 (TRX_STATUS) returns RX_AACK_ON or
BUSY_RX_AACK. The latter one is returned if a frame is currently about being
received.
The RX_AACK Extended Operating Mode is terminated by writing command PLL_ON
to the register bits TRX_CMD. If the AT86RF212 is within a frame receive or
acknowledgment procedure (BUSY_RX_AACK) the state change is executed after
finish. Alternatively, the commands FORCE_TRX_OFF or FORCE_PLL_ON can be
used to cancel the RX_AACK transaction and change into transceiver state TRX_OFF
or PLL_ON, respectively.
TX_ARET - Transmit with Automatic Retry and CSMA-CA Retry
Similarly, a state transition to TX_ARET_ON from PLL_ON or TRX_OFF is initiated by
writing command TX_ARET_ON to register bits TRX_CMD (register 0x02,
TRX_STATE). The radio transceiver is in the TX_ARET_ON state when register 0x01
(TRX_STATUS) returns TX_ARET_ON. The TX_ARET transaction is actually started
with a rising edge of pin 11 (SLP_TR) or by writing the command TX_START to register
bits TRX_CMD.
The TX_ARET Extended Operating Mode is terminated by writing the command
PLL_ON to the register bits TRX_CMD. If the AT86RF212 is within a CSMA-CA, a
frame-transmit or an acknowledgment procedure (BUSY_TX_ARET) the state change
is executed after finish. Alternatively the command FORCE_PLL_ON can be used to
instantly terminate the TX_ARET transaction and change into transceiver state
PLL_ON.
Notes
• A state change request from TRX_OFF to RX_AACK_ON or TX_ARET_ON
internally passes the state PLL_ON to initiate the radio transceiver front end. Thus
the readiness to receive or transmit data is delayed accordingly (see Table 5-1). In
that case it is recommended to use interrupt IRQ_0 (PLL_LOCK) as an indicator.
5.2.2 Configuration
As the usage of the Extended Operating Mode is based on Basic Operating Mode
functionality only features beyond the basic radio transceiver functionality are described
in the following sections. For details of the Basic Operating Mode refer to section 5.1.
When using the RX_AACK or TX_ARET modes, the following registers need to be
configured.
42
AT86RF212
8168A-AVR-06/08
AT86RF212
RX_AACK configuration steps:
• Setup Frame Filter:
registers 0x20 – 0x2B
o Short address, PAN ID and IEEE address
• Configure acknowledgement generation
registers 0x2C, 0x2E
o Handling of Frame Version Subfield
o Handling of Pending Data
o Automatic or slotted ACK generation
• Additional Frame Filtering Properties
register 0x17
o Frame Filter Version Control
o Characterize the device as PAN coordinator, if required
o Promiscuous Mode
o Handling of reserved frame types
The configuration of Frame Filter is described in section 6.2.1. The addresses for the
address match algorithm are to be stored in the appropriate address registers.
Additional control of the RX_AACK mode is done with register 0x17 (XAH_CTRL_1)
and register 0x2E (CSMA_SEED_1).
Configuration examples for different device operating modes and handling of various
frame types can be found in section 5.2.3.1.
TX_ARET configuration steps:
• Enable automatic FCS handling
• Configure CSMA-CA
o MAX_FRAME_RETRIES
o MAX_CSMA_RETRIES
o CSMA_SEED
o MAX_BE, MIN_BE
• Configure CCA (see section 6.6)
register 0x04
register 0x2C
register 0x2C
registers 0x2D, 0x2E
register 0x2F
MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) defines the maximum number
of frame retransmissions.
The register bits MAX_CSMA_RETRIES (register 0x2C) configure the maximum
number of CSMA-CA retries after a busy channel is detected.
The CSMA_SEED_0 and CSMA_SEED_1 register bits (registers 0x2D, 0x2E) define a
random seed for the backoff time random-number generator in the AT86RF212.
The register bits MAX_BE and MIN_BE (register 0x2F) define the maximum and
minimum CSMA backoff exponent, respectively.
5.2.3 RX_AACK_ON – Receive with Automatic ACK
The RX_AACK Extended Operating Mode handles reception and automatic
acknowledgement of IEEE 802.15.4 compliant frames.
The general flow of the RX_AACK algorithm is shown in Figure 5-9. Here the gray
shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4
compliant frames, refer to 5.2.3.2. All other procedures are exceptions for specific
operating modes or frame formats, refer to section 5.2.3.3.
43
8168A-AVR-06/08
In RX_AACK_ON state, the AT86RF212 listens for incoming frames. After detecting a
non-zero PHR, the AT86RF212 changes into BUSY_RX_AACK state and parses the
frame content of the MAC header (MHR), refer to section 6.1.2.
If the content of the MAC addressing fields of the received frame (refer to
IEEE 802.15.4 frame format, section 7.2.1) passes the frame filter, an address match
interrupt IRQ_5 (AMI) is issued. The reference address values are to be stored in
registers 0x20 – 0x2B (Short address, PAN ID and IEEE address). The Frame Filter
operations are described in detail in section 6.2.
Generally, at nodes, configured as a normal device or PAN coordinator, a frame is
indicated by interrupt IRQ_3 (TRX_END) if the frame passes the Frame Filter and the
FCS is valid. The interrupt is issued after the completion of the frame reception. The
microcontroller can then read the frame data. An exception applies if promiscuous
mode is enabled; see section 5.2.3.2. In that case, an interrupt IRQ_3 is issued for all
frames.
During reception, the AT86RF212 parses bit 5 (ACK Request) of the frame control field
of the received data or MAC command frame to check if an acknowledgement (ACK)
response is expected. In that case and if the frame matches the third level filtering rules
(see IEEE 802.15.4-2006, section 7.5.6.2) the radio transceiver automatically generates
and transmits an ACK frame and proceeds back to RX_AACK_ON state.
By default, the acknowledgment frame is transmitted aTurnaroundTime (12 symbols,
see IEEE 802.15.4, section 6.4.1) after the reception of the last symbol of a data or
MAC command frame. Optionally, for non-compliant networks this delay can be
reduced to 2 symbols by register bit AACK_ACK_TIME (register 0x2E, XAH_CTRL_1).
The content of the frame pending subfield of the ACK response is set according to
register bit AACK_SET_PD (register 0x2E, CSMA_SEED_1). The sequence number is
copied from the received frame accordingly.
If the register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) is set, no
acknowledgement frame is sent, even if requested.
For slotted operation, the start of the transmission of acknowledgement frames is
controlled by pin 11 (SLP_TR), refer to 5.2.3.5.
The status of the RX_AACK transaction is indicated by register subfield
TRAC_STATUS (register 0x02, TRX_STATE). Table 5-7 lists corresponding values.
Table 5-7. RX_AACK interpretation of TRAC_STATUS register bits
Value
Name
Description
0
SUCCESS
The transaction has finished with success
2
SUCCESS_WAIT_FOR_ACK
The transaction either waits aTurnaroundTime
symbols until the ACK is transmitted or
expects the rising edge on pin 11 (SLP_TR) to
start the transmission (slotted operation)
7
INVALID
Default value, when RX_AACK transaction is
invoked
Note that generally the AT86RF212 PHY modes as well as the Extended Feature Set
work independent from RX_AACK Extended Operating Mode.
44
AT86RF212
8168A-AVR-06/08
AT86RF212
Figure 5-9. Flow Diagram of RX_AACK
TRX_STATE = RX_AACK_ON,
TRAC_STATUS =
INVALID
Detect SHR
TRX_STATE =
BUSY_RX_AACK
Issue IRQ_2
(RX_START)
Scan MHR
Note 1:
Address match, Promiscuous Mode and
Reserved Frames:
- A radio transceiver in promiscuous
mode or configured to receive reserved
frames handles received frames passing
the third level of filtering
- for details refer to the descritption of
Promiscuous Mode and Reserved
Frame Types
Address match?
Promiscuous Mode
Reserved Frames
N
Y
Îssue IRQ_5
(AMI)
AACK_PROM_MODE
== 1 ?
N
FCF[2:0]
>3?
Y
Y
Receive PSDU
N
Receive PSDU
FCS valid ||
AACK_PROM_MODE
?
N
N
FCS valid ?
Y
ACK requested ?
(see Note 2)
Note 2:
Additional conditions:
- ACK requested &
- ACK_DIS_ACK==0 &
- frame_version<=AACK_FVN_MODE
AACK_UPLD_RES_FT
== 1 ?
Y
Y
Issue IRQ_3
(TRX_END)
N
Receive PSDU
Y
Issue IRQ_3
(TRX_END)
Issue IRQ_3
(TRX_END)
TRAC_STATUS =
SUCCESS_WAIT_FOR_ACK
N
No
Slotted Operation
?
Y
Wait
(AACK_ACK_TIME)
Wait
(AACK_ACK_TIME)
Wait
(pin 11, (SLP_TR),
rising edge)
Transmit ACK
TRX_STATE = RX_AACK_ON, TRAC_STATUS = SUCCESS
45
8168A-AVR-06/08
5.2.3.1 Configuration Registers
Overview
RX_AACK configuration as described below shall be done prior to switching the
AT86RF212 into state RX_AACK_ON, refer to 5.2.1.
Table 5-8 summarizes all register bits which affect the behavior of an RX_AACK
transaction. For frame filtering it is further required to setup address registers to match
to the expected address.
Table 5-8. Overview of RX_AACK Configuration Bits
Register
Address
Register
Bits
0x20,0x21
0x22,0x23
0x24
…
0x2B
Register Name
Description
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Setup Frame Filter, see 6.2.1
0x0C
7
RX_SAFE_MODE
Dynamic frame buffer protection, see 9.7
0x17
1
AACK_PROM_MODE
Enable promiscuous mode
0x17
2
AACK_ACK_TIME
Modify auto acknowledge start time
0x17
4
AACK_UPLD_RES_FT
Enable reserved frame type reception,
needed to receive non-standard compliant
frames, see 5.2.3.3
0x17
5
AACK_FLTR_RES_FT
Filter reserved frame types like data frame
type, needed for filtering of non-standard
compliant frames, see 5.2.3.3
0x2C
0
SLOTTED_OPERATION
If set, acknowledgment transmission has
to be triggered by pin 11 (SLP_TR),
see 4.6
0x2E
3
AACK_I_AM_COORD
Define device as PAN coordinator, see
5.2.3.2
0x2E
4
AACK_DIS_ACK
Disable generation of acknowledgment
0x2E
5
AACK_SET_PD
Signal pending data in Frame Control
Field (FCF) of acknowledgement
0x2E
7:6
AACK_FVN_MODE
Control the ACK generation, depending
on FCF frame version number
The usage of the RX_AACK configuration bits for various device types or operating
modes is explained in the following sections. Configuration bits not mentioned in the
following two sections should be set to their reset values according to Table 12-2.
All registers mentioned in Table 5-8 are described in section 5.2.6.
5.2.3.2 Configuration of IEEE Compliant Scenarios
Device not operating as a PAN Coordinator
Table 5-9 shows the RX_AACK configuration registers, required to setup a typical
IEEE 802.15.4 compliant device.
46
AT86RF212
8168A-AVR-06/08
AT86RF212
Table 5-9. Configuration of IEEE 802.15.4 Devices
Register
Address
Register
Bits
0x20,0x21
0x22,0x23
0x24
…
0x2B
Register Name
Description
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Setup Frame Filter, see section 6.2.1
0x0C
7
RX_SAFE_MODE
0: disable frame protection
1: enable frame protection
0x2C
0
SLOTTED_OPERATION
0: Transceiver operates in unslotted
mode.
1: Transceiver operates in slotted mode,
see section 5.2.3.5.
0x2E
7:6
AACK_FVN_MODE
Controls the ACK behavior, depending on
FCF frame version number
b00 : acknowledges only frames with
version number 0, i.e. according to
IEEE 802.15.4-2003 frames
b01 : acknowledges only frames with
version number 0 or 1, i.e. frames
according to IEEE 802.15.4-2003/2006
b10 : acknowledges only frames with
version number 0 or 1 or 2
b11 : acknowledges all frames,
independent of the FCF frame version
number
Notes
• The default value of the short address is 0xFFFF. Thus, if no short address has been
configured, only frames with either the broadcast address or the IEEE address are
accepted by the frame filter.
• In the IEEE 802.15.4-2003 standard, the frame version subfield does not yet exist,
but is marked as reserved. According to this standard, reserved fields have to be set
to zero. At the same time, the IEEE 802.15.4-2003 standard requires ignoring
reserved bits upon reception. Thus, there is a contradiction in the standard which can
be interpreted in two ways:
1. If a network should only allow access to nodes compliant to IEEE 802.15.4-2003,
then AACK_FVN_MODE should be set to 0.
2. If a device should acknowledge all frames independent of its frame version,
AACK_FVN_MODE should be set to 3. However, this may result in conflicts with
co-existing IEEE 802.15.4-2006 standard compliant networks.
The same holds for PAN coordinators, see below.
PAN Coordinator
Table 5-10 shows the RX_AACK configuration registers, required to setup a PAN
coordinator device.
47
8168A-AVR-06/08
Table 5-10. Configuration of a PAN Coordinator
Register
Address
Register
Bits
0x20,0x21
0x22,0x23
0x24
…
0x2B
Register Name
Description
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Setup Frame Filter, see section 6.2.1
0x0C
7
RX_SAFE_MODE
0: disable frame protection
1: enable frame protection
0x2C
0
SLOTTED_OPERATION
0: Transceiver operates in unslotted
mode.
1: Transceiver operates in slotted mode,
see section 5.2.3.5.
0x2E
3
AACK_I_AM_COORD
1: device is PAN coordinator
0x2E
5
AACK_SET_PD
0: frame pending subfield is 0 in FCF
1: frame pending subfield is 1 in FCF
0x2E
7:6
AACK_FVN_MODE
Controls the ACK behavior depending on
FCF frame version number
b00 : acknowledges only frames with
version number 0, i.e. according to
IEEE 802.15.4-2003 frames
b01 : acknowledges only frames with
version number 0 or 1, i.e. frames
according to IEEE 802.15.4-2003/2006
b10 : acknowledges only frames with
version number 0 or 1 or 2
b11 : acknowledges all frames,
independent of the FCF frame version
number
Promiscuous Mode or Sniffer
The promiscuous mode is described in IEEE 802.15.4-2006, section 7.5.6.5. This mode
is further illustrated in Figure 5-9. According to IEEE 802.15.4-2006 in promiscuous
mode, the MAC sub layer shall pass received frames with correct FCS to the next
higher layer without further processing. This implies that received frames should never
be automatically acknowledged.
In order to support sniffer application and promiscuous mode, only second level filter
rules as defined by IEEE 802.15.4-2006, section 7.5.6.2, are applied to the received
frame.
Table 5-11 shows the RX_AACK configuration registers, required to setup a typical
IEEE 802.15.4 compliant device, which operates in promiscuous mode.
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Table 5-11. Configuration of Promiscuous Mode
Register
Address
Register
Bits
0x20,0x21
0x22,0x23
0x24
…
0x2B
Register Name
Description
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
each address shall be set: 0x00
0x17
1
AACK_PROM_MODE
1: Enable promiscuous mode
0x2E
4
AACK_DIS_ACK
1: Disable acknowledgment generation
To signal the availability of frame data, an IRQ_3 (TRX_END) is issued even if the FCS
is invalid. Thus, it is necessary to read register bit RX_CRC_VALID (register 0x06,
PHY_RSSI) after IRQ_3 (TRX_END) in order to verify the reception of a frame with a
valid FCS.
If a device, operating in promiscuous mode, received a frame with a valid FCS that
furthermore passed the third level of filtering (according to IEEE 802.15.4-2006, section
7.5.6.2), an acknowledgement (ACK) frame would be transmitted. But, according to the
definition of the promiscuous mode a received frame shall not be acknowledged, even if
requested. Thus register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) must be
set to 1, to disable ACK generation.
In all receive modes, interrupt IRQ_5 (AMI) is issued, if the received frame matches the
node’s address according to the filter rules described in 6.2.
Promiscuous mode could also be implemented using state RX_ON (Basic Operating
Mode), refer to section 5.1. However, the RX_AACK transaction additionally enables
extended functionality like automatic acknowledgement and non-destructive frame
filtering.
5.2.3.3 Configuration of non IEEE Compliant Scenarios
Reserved Frame Types
In RX_AACK mode, frames with reserved frame types, refer to section 6.1.2.2, Table 62, can also be handled. This might be required when implementing proprietary, nonstandard compliant protocols. The reception of reserved frame types is an extension of
the AT86RF212 Frame Filter, see section 6.2. Received frames are either handled like
data frames, or may be allowed to completely bypass the Frame Filter. The flow chart in
Figure 5-9 shows the corresponding state machine.
In addition to Table 5-9 or Table 5-10, the following Table 5-12 shows RX_AACK
configuration registers, required to setup a node to receive reserved frame types.
Table 5-12. RX_AACK Configuration to Receive Reserved Frame Types
Register
Address
Register
Bits
0x17
0x17
Register Name
Description
4
AACK_UPLD_RES_FT
1 : Enable reserved frame type reception
5
AACK_FLTR_RES_FT
Filter reserved frame types like data frame
type, see note below
0 : disable
1 : enable
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There are two different options for handling reserved frame types.
1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0:
Any non-corrupted frame with a reserved frame type is indicated by the interrupt
IRQ_3 (TRX_END). No further frame filtering is applied on those frames. The
interrupt IRQ_5 (AMI) is never generated and no acknowledgment is sent.
2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1:
Any frame with a reserved frame type is treated like an IEEE 802.15.4 compliant data
frame. This implies the generation of the interrupt IRQ_5 (AMI) upon address
matches. The IRQ_3 (TRX_END) interrupt is only generated if the address matches
and the frame is correct (FCS valid). Then an acknowledgment is sent, if the ACK
request subfield of the received frame is set accordingly.
Short Acknowledgment Frame (ACK) Start Timing
Register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1), see Table 5-13, defines
the delay between the end of the frame reception and the start of the transmission of an
acknowledgment frame.
Table 5-13. ACK start timing for unslotted operation
Register
Address
Register
Bit
0x17
2
Register Name
Description
AACK_ACK_TIME
0: Standard compliant acknowledgement
delay of 12 symbol periods
1: Reduced acknowledgment delay of 2
symbol periods (BPSK-20, O-QPSK{100,200,400}) or 3 symbol periods
(BPSK-40, O-QPSK-{250,500,1000}).
Note that this feature can be used in all scenarios, independent of other configurations.
However, shorter acknowledgment timing is especially useful when using High Data
Rate Modes to increase battery lifetime and to improve the overall data throughput;
refer to section 7.1.4.3.
In slotted operation mode, the acknowledgment transmission is actually started by pin
11 (SLP_TR). Table 5-14 shows that the AT86RF212 enables the trigger pin with an
appropriate delay. Thus a transmission cannot be started earlier.
Table 5-14. ACK start timing for slotted operation
Register
Address
Register
Bit
0x17
2
Register Name
Description
AACK_ACK_TIME
0: Acknowledgment frame transmission
can be triggered after 6 symbol periods.
1: Acknowledgment frame transmission
can be triggered after 3 symbol periods.
5.2.3.4 RX_AACK_NOCLK – RX_AACK_ON without CLKM
If the AT86RF212 is listening for an incoming frame and the microcontroller is not
running an application, the microcontroller can be powered down to decrease the total
system power consumption. This special power-down scenario for systems running in
clock synchronous mode (see section 4.2) is supported by the AT86RF212 using the
states RX_AACK_ON_NOCLK and BUSY_RX_AACK_NOCLK, see Figure 5-8. They
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achieve the same functionality as the states RX_AACK_ON and BUSY_RX_AACK with
pin 17 (CLKM) disabled.
The RX_AACK_NOCLK state is entered from RX_AACK_ON by a rising edge at
pin 11 (SLP_TR). The return to RX_AACK_ON state automatically results either from
the reception of a valid frame, indicated by interrupt IRQ_3 (TRX_END), or a falling
edge on pin SLP_TR.
A received frame is considered valid if it passes frame filtering and has a correct FCS. If
an ACK was requested, the radio transceiver enters BUSY_RX_AACK state and follows
the procedure described in section 5.2.3.
After the RX_AACK transaction has been completed, the radio transceiver remains in
RX_AACK_ON state. The AT86RF212 re-enters the RX_AACK_ON_NOCLK state only
by the next rising edge on pin 11 (SLP_TR).
The timing and behavior when CLKM is disabled or enabled are described in section
4.6.
Note that RX_AACK_NOCLK is not available for slotted operation mode (see 5.2.3.5).
5.2.3.5 Slotted Operation – Slotted Acknowledgement
In networks using slotted operation the start of the acknowledgment frame, and thus the
exact timing, must be provided by the microcontroller. Exact timing requirements for the
transmission of acknowledgments in beacon-enabled networks are explained in
IEEE 802.15.4-2006, section 7.5.6.4.2. In conjunction with the microcontroller the
AT86RF212 supports slotted acknowledgement operation. This mode is invoked by
setting register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) to 1.
If an acknowledgment (ACK) frame is to be transmitted in RX_AACK mode, the radio
transceiver expects a rising edge on pin 11 (SLP_TR) to actually start the transmission.
During this waiting period the transceiver reports SUCCESS_WAIT_FOR_ACK through
register bits TRAC_STATUS (register 0x02, XAH_CTRL_0), see Figure 5-9. The
minimum delay between the occurrence of interrupt IRQ_3 (TRX_END) and pin start of
the ACK frame in slotted operation is 3 symbol periods.
Figure 5-10 illustrates the timing of an RX_AACK transaction in slotted operation. The
acknowledgement frame is ready to transmit 3 symbol times after the reception of the
last symbol of a data or MAC command frame, indicated by IRQ_3. The transmission of
the acknowledgement frame is initiated by the microcontroller with the rising edge of pin
11 (SLP_TR) and starts tTR10 later.
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Figure 5-10. Example Timing of an RX_AACK Transaction for Slotted Operation
Frame Type
SFD
TRX_STATE
Data Frame (ACK=1)
RX_AACK_ON
ACK Frame (Frame Pending = 0)
BUSY_RX_AACK
RX/TX
Frame
on Air
time
BUSY_RX_AACK
RX
TX
IRQ
RX_AACK_ON
RX
TRX_END
tIRQ
SLP_TR accepted
3 symbols
SLP_TR
tTR10
...
TRAC_STATUS
SUCCESS_WAIT_FOR_ACK
SUCCESS
5.2.3.6 Timing
A general timing example of an RX_AACK transaction is shown in Figure 5-11. In this
example a data frame with an ACK request is received. The AT86RF212 changes to
state BUSY_RX_AACK after SFD detection. The completion of the frame reception is
indicated by a TRX_END interrupt. The interrupts IRQ_2 (TX_START) and IRQ_5 (AMI)
are disabled in this example. The ACK frame is automatically transmitted after
aTurnaroundTime (12 symbols), assuming default acknowledgment frame start timing.
The interrupt latency t9 is specified in section 10.4.
Figure 5-11. Example Timing of an RX_AACK Transaction
Frame Type
SFD
TRX_STATE
Data Frame (ACK=1)
ACK Frame (Frame Pending = 0)
RX_AACK_ON
BUSY_RX_AACK
RX
RX/TX
Frame
on Air
time
RX_AACK_ON
TX
RX
TRX_END
IRQ
tIRQ
aTurnaroundTime
(AACK_ACK_TIME)
TRAC_STATUS
...
SUCCESS_WAIT_FOR_ACK
SUCCESS
5.2.4 TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA Retry
The TX_ARET Extended Operating Mode supports the frame transmission process as
defined by IEEE 802.15.4–2006. It is invoked as described in 5.2.1 by writing
TX_ARET_ON to register subfield TRX_CMD (register 0x02, TRX_STATE).
If a transmission is initiated in TX_ARET mode, the AT86RF212 executes the
CSMA-CA algorithm, as defined by IEEE 802.15.4–2006, section 7.5.1.4. If the CCA
reports IDLE, the frame is transmitted from the Frame Buffer.
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If an acknowledgement frame is requested, the radio transceiver checks for an ACK
reply automatically. The CSMA-CA based transmission process is repeated as long as
no valid acknowledgement is received or the number of frame retransmissions
(MAX_FRAME_RETRIES) is exceeded.
The completion of the TX_ARET transaction is indicated by the IRQ_3 (TRX_END)
interrupt, see section 5.2.5.
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Figure 5-12. Flow Diagram of TX_ARET
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Description
The implemented TX_ARET algorithm is shown in Figure 5-12.
Prior to invoking TX_ARET mode, see section 5.2.1, the basic configuration steps as
described in 5.2.2 shall be executed. It is further recommended to write the PSDU
transmit data to the Frame Buffer in advance.
The transmit start event may either come from a rising edge on pin 11 (SLP_TR) or by
writing a TX_START command to register subfield TRX_CMD (register 0x02,
TRX_STATE).
If the CSMA-CA algorithm detects a busy channel, this process is repeated up to
MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0). In case that CSMA-CA does
not detect a clear channel after MAX_CSMA_RETRIES, it aborts the TX_ARET
transaction,
issues
interrupt
IRQ_3
(TRX_END),
and
returns
CHANNEL_ACCESS_FAILURE in register bits TRAC_STATUS (register 0x02,
TRX_STATE).
During transmission of a frame, the radio transceiver parses bit 5 (ACK Request) of the
MAC header (MHR) frame to check whether an ACK reply is expected.
If no ACK is expected, the radio transceiver issues IRQ_3 (TRX_END) directly after the
frame transmission has been completed. The register bits TRAC_STATUS (register
0x02, TRX_STATE) are set to SUCCESS.
If an ACK is expected, after transmission the radio transceiver automatically switches to
receive mode waiting for a valid ACK reply (i.e. matching sequence number and correct
FCS). After receiving a valid ACK frame the Frame Pending subfield of this frame is
parsed and the status register bits TRAC_STATUS are updated to SUCCESS or
SUCCESS_DATA_PENDING accordingly, refer to Table 5-15. At the same time, the
entire TX_ARET transaction is terminated and interrupt IRQ_3 (TRX_END) is issued.
If no valid ACK is received within the timeout period, refer to section 5.2.4.1, the radio
transceiver retries the entire transaction, (CSMA-CA based frame transmission) until
the maximum number of frame retransmissions is exceeded, see register bits
MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0). In that case, the
TRAC_STATUS is set to NO_ACK, the TX_ARET transaction is terminated, and
interrupt IRQ_3 (TRX_END) is issued.
Table 5-15 summarizes the Extended Operating Mode result codes in register subfield
TRAC_STATUS (register 0x02, TRX_STATE) with respect to the TX_ARET
transaction.
Table 5-15. TX_ARET Interpretation of TRAC_STATUS register bits
Value
Name
Description
0
SUCCESS
The transaction was responded by a valid
ACK, or, if no ACK is requested, after a
successful frame transmission.
1
SUCCESS_DATA_PENDING
Equivalent to SUCCESS and indicating that
the Frame Pending bit (see section 6.1.2.2) of
the received acknowledgment frame was set.
3
CHANNEL_ACCESS_FAILURE
Channel is still busy after
MAX_CSMA_RETRIES of CSMA-CA.
5
NO_ACK
No acknowledgement frame was received
during all retry attempts.
7
INVALID
Entering TX_ARET mode until IRQ_3
(TRX_END).
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A value of MAX_CSMA_RETRIES = 7 initiates an immediate TX_ARET transaction
without performing CSMA-CA. This supports beacon-enabled network operation.
Furthermore by ignoring the value of MAX_FRAME_RETRIES only a single attempt is
made to transmit the frame.
Note that the acknowledgment receive procedure does not overwrite the Frame Buffer
content. Transmit data in the Frame Buffer is not modified during the entire TX_ARET
transaction. Received frames other than the expected ACK frame are discarded
automatically.
5.2.4.1 Acknowledgment Timeout
If an acknowledgment (ACK) frame is expected after frame transmission, the
AT86RF212 sets a timeout until which a valid ACK frame must have been arrived. This
timeout macAckWaitDuration is defined according to [1] as follows:
macAckWaitDuration [symbol periods] =
aUnitBackoffPeriod + aTurnaroundTime + phySHRDuration + 6 · phySymbolsPerOctet,
where 6 represents the number of PHY header octets plus the number of PSDU octets
in an acknowledgment frame.
Specifically for the implemented PHY Modes (see section 7.1), this formula results in
the following values:
•
BPSK:
macAckWaitDuration = 120 symbol periods
•
O-QPSK:
macAckWaitDuration = 54 symbol periods
Note that for any PHY Mode the unit [symbol period] refers to the symbol duration of the
appropriate synchronization header, see section 7.1.3 for further information regarding
symbol period.
5.2.4.2 Timing
A timing example of a TX_ARET transaction is shown in Figure 5-13. In the example
shown, a data frame with an acknowledgment request is to be transmitted. The frame
transmission is started by pin 11 (SLP_TR). As MIN_BE is set to zero, the initial CSMACA backoff period has length zero too. Thus the CSMA-CA duration time tCSMA-CA only
consists of 8 symbols of CCA measurement period. If CCA returns IDLE (assumed
here), the frame is transmitted.
After that, the AT86RF212 switches to receive mode and expects an acknowledgement
response, which is indicated by register subfield TRAC_STATUS (register 0x02,
TRX_STATE) set to SUCCESS_WAIT_FOR_ACK. After a period of aTurnaroundTime
+ aUnitBackoff the transmission of the ACK frame must have started. During the entire
transaction including frame transmit, wait for ACK and ACK receive, the radio
transceiver status register TRX_STATUS (register 0x01, TRX_STATUS) signals
BUSY_TX_ARET.
A successful reception of the acknowledgment frame is indicated by interrupt IRQ_3
(TRX_END). The status register TRX_STATUS (register 0x01, TRX_STATUS) changes
back to TX_ARET_ON. At the same time, register TRAC_STATUS changes to
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SUCCESS or to SUCCESS_DATA_PENDING, if the frame pending subfield of the
acknowledgment frame was set to 1.
Figure 5-13. Example Timing of a TX_ARET Transaction
FrameType
Data Frame (ACK=1)
Frame
on Air
time
ACK Frame
ACK start timeout
20 symbols
TRX_STATE
TX_ARET_ON
RX/TX
BUSY_TX_ARET
TX_ARET_ON
RX
RX
TX
CSMA-CA
32 µs
SLP_TR
IRQ
TRX_END
tCSMA-CA
(8 symbols)
Typ. Delays
TRAC_STATUS
SUCC. / INVALID
Register settings:
16 µs
INVALID
0x2C: MAX_FRAME_RETRIES=0
aTurnaroundTime
(12 symbols)
tIRQ
SUCCESS_WAIT_FOR_ACK
0x2C: MAX_CSMA_RETRIES=0
SUCCESS
0x2E: MIN_BE=0
5.2.5 Interrupt Handling
The interrupt handling in the Extended Operating Mode is similar to the Basic Operating
Mode. Interrupts can be enabled by setting the appropriate bit in register 0x0E
(IRQ_MASK).
For RX_AACK and TX_ARET the following interrupts inform about the status of a frame
reception and transmission:
• IRQ_2 (RX_START)
• IRQ_3 (TRX_END)
• IRQ_5 (AMI)
For RX_AACK mode, it is recommended to enable only interrupt IRQ_3 (TRX_END).
This interrupt is issued only if the Frame Filter (see section 6.2) reports a matching
address and the FCS is valid (see section 6.3). The usage of other interrupts is
optional.
On reception of a frame, the RX_START interrupt indicates that a correct
synchronization header (SHR) was found. This interrupt is issued after the PHR.
Interrupt AMI interrupt indicates address match, refer to filter rules in section 6.2.
The TRX_END interrupt is always generated after completing a TX_ARET transaction.
After that, the return code can be read from subfield TRAC_STATUS (register 0x02,
TRX_STATE).
Several interrupts are automatically suppressed by the radio transceiver during
TX_ARET transaction. In contrast to section 6.6, the CCA algorithm (part of CSMA-CA)
does not generate interrupt IRQ_4 (CCA_ED_READY). Furthermore, the interrupts
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RX_START and AMI are not generated during the TX_ARET acknowledgment receive
process.
5.2.6 Register Description
Register Summary
The following registers control the Extended Operating Mode:
Table 5-16. Register Summary
Reg.-Addr.
Register Name
Description
0x01
TRX_STATUS
Radio transceiver status, CCA result
0x02
TRX_STATE
Radio transceiver state control, TX_ARET status
0x04
TRX_CTRL_1
TX_AUTO_CRC_ON
0x08
PHY_CC_CCA
CCA mode control, see section 6.6.6
0x09
CCA_THRES
CCA ED threshold settings, see section 6.6.6
0x17
XAH_CTRL_1
RX_AACK control
0x20 – 0x2B
Frame Filter configuration
- Short address, PAN ID and IEEE address
- See section 6.2.3
0x2C
XAH_CTRL_0
TX_ARET control, retries value control
0x2D
CSMA_SEED_0
CSMA-CA seed value
0x2E
CSMA_SEED_1
CSMA-CA seed value, RX_AACK control
0x2F
CSMA_BE
CSMA-CA back-off exponent control
Register 0x01 (TRX_STATUS):
The read-only register TRX_STATUS provides the current state of the radio transceiver.
A state change is initiated by writing a state transition command to register bits
TRX_CMD (register 0x02, TRX_STATE).
Table 5-17. Register 0x01 (TRX_STATUS)
Bit
7
6
5
4
Name
CCA_DONE
CCA_STATUS
Reserved
TRX_STATUS
Read/Write
R
R
R
R
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
TRX_STATUS
TRX_STATUS
TRX_STATUS
TRX_STATUS
Read/Write
R
R
R
R
Reset Value
0
0
0
0
• Bit 7 – CCA_DONE
Refer to section 6.6, not updated in Extended Operating Mode
• Bit 6 – CCA_STATUS
Refer to section 6.6, not updated in Extended Operating Mode
• Bit 5 – Reserved
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• Bit 4:0 – TRX_STATUS
The register bits TRX_STATUS signals the current radio transceiver status.
Table 5-18. Radio Transceiver Status
Register Bits
Value
State Description
TRX_STATUS
0x00
P_ON
0x01
BUSY_RX
0x02
BUSY_TX
0x06
RX_ON
0x08
TRX_OFF (CLK Mode)
0x09
0x0F
PLL_ON (TX_ON)
(1)
SLEEP
0x11
BUSY_RX_AACK
0x12
BUSY_TX_ARET
0x16
RX_AACK_ON
0x19
TX_ARET_ON
0x1C
RX_ON_NOCLK
0x1D
RX_AACK_ON_NOCLK
0x1E
BUSY_RX_AACK_NOCLK
0x1F
(2)
STATE_TRANSITION_IN_PROGRESS
All other values are reserved
Notes:
1. In SLEEP state registers are not accessible.
2. Do not try to initiate a further state change while the radio transceiver is in
STATE_TRANSITION_IN_PROGRESS state.
Register 0x02 (TRX_STATE):
The AT86RF212 radio transceiver states are controlled via register TRX_STATE using
register bits TRX_CMD. A successful state transition shall be confirmed by reading
register bits TRX_STATUS (register 0x01, TRX_STATUS).
The read-only register bits TRAC_STATUS indicate the status or result of an Extended
Operating Mode transaction.
Table 5-19. Register 0x02 (TRX_STATE)
Bit
7
6
5
4
Name
TRAC_STATUS
TRAC_STATUS
TRAC_STATUS
TRX_CMD
Read/Write
R
R
R
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
TRX_CMD
TRX_CMD
TRX_CMD
TRX_CMD
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
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• Bit 7:5 – TRAC_STATUS
The status of the RX_AACK and TX_ARET procedure is indicated by register bits
TRAC_STATUS. Details of the algorithm and a description of the status information are
given in sections 5.2.3 and 5.2.4.
Table 5-20. TRAC_STATUS Transaction Status
Register Bits
Value
TRAC_STATUS
Description
(1)
RX_AACK
TX_ARET
X
X
0
SUCCESS
1
SUCCESS_DATA_PENDING
2
SUCCESS_WAIT_FOR_ACK
3
CHANNEL_ACCESS_FAILURE
X
NO_ACK
X
5
(1)
7
INVALID
X
X
X
X
All other values are reserved
Note:
1. Even though the reset value for register bits TRAC_STATUS is 0, the RX_AACK
and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID)
when it is started.
• Bit 4:0 – TRX_CMD
A write access to register bits TRX_CMD initiates a radio transceiver state transition:
Table 5-21. State Control Register
Register Bits
Value
State Description
TRX_CMD
0x00
NOP
0x02
TX_START
0x03
FORCE_TRX_OFF
0x04(1)
FORCE_PLL_ON
0x06
RX_ON
0x08
TRX_OFF (CLK Mode)
0x09
PLL_ON (TX_ON)
0x16
RX_AACK_ON
0x19
TX_ARET_ON
All other values are reserved and mapped to NOP
Note:
1. FORCE_PLL_ON is not valid for states SLEEP, P_ON, RESET, TRX_OFF, and all
*_NOCLK states, as well as STATE_TRANSITION_IN_PROGRESS towards
these states.
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi-purpose register to control various operating
modes and settings of the radio transceiver.
Table 5-22. Register 0x04 (TRX_CTRL_1)
60
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
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8168A-AVR-06/08
AT86RF212
Bit
3
2
1
0
Name
SPI_CMD_MODE
SPI_CMD_MODE
SPI_CMD_MODE
IRQ_POLARITY
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – PA_EXT_EN
Refer to section 9.4.
• Bit 6 – IRQ_2_EXT_EN
Refer to section 9.5.
• Bit 5 – TX_AUTO_CRC_ON
If set, register bit TX_AUTO_CRC_ON enables the automatic FCS generation. For
further details refer to section 6.3.
• Bit 4 – RX_BL_CTRL
Refer to section 9.6.
• Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
• Bit 1 – IRQ_MASK_MODE
Refer to section 4.7.
• Bit 0 – IRQ_POLARITY
Refer to section 4.7.
Register 0x17 (XAH_CTRL_1):
The XAH_CTRL_1 register is a control register for Extended Operating Mode.
Table 5-23. Register 0x17 (XAH_CTRL_1)
Bit
7
6
5
4
Name
Reserved
CSMA_LBT_MODE
AACK_FLTR_RES_FT
AACK_UPLD_RES_FT
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
Reserved
AACK_ACK_TIME
AACK_PROM_MODE
Reserved
Read/Write
R
R/W
R/W
R
Reset Value
0
0
0
0
• Bit 7 – Reserved
• Bit 6 – CSMA_LBT_MODE
Refer to section 6.7.3.
• Bit 5 – AACK_FLTR_RES_FT
This register bit shall only be set if AACK_UPLD_RES_FT = 1.
If AACK_FLTR_RES_FT = 1, reserved frame types are filtered like data frames as
specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4
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section 7.2.1.1.1. Interrupt IRQ_5 (AMI) is issued upon passing the frame filter, see
section 6.2.
If AACK_FLTR_RES_FT = 0, the received reserved frame is only checked for a valid
FCS.
• Bit 4 – AACK_UPLD_RES_FT
If AACK_UPLD_RES_FT = 1, received frames marked as reserved frames are further
processed. For these frames, interrupt IRQ_3 (TRX_END) is generated, if the FCS is
valid.
In conjunction with the configuration bit AACK_FLTR_RES_FT set, these frames are
handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction.
Otherwise, if AACK_UPLD_RES_FT = 0, frames with a reserved frame type are
blocked.
• Bit 3 – Reserved
• Bit 2 – AACK_ACK_TIME
According to IEEE 802.15.4, section 7.5.6.4.2 the transmission of an acknowledgment
frame shall commence 12 symbol periods (aTurnaroundTime) after the reception of the
last symbol of a data or MAC command frame. This is achieved with the reset value of
the register bit AACK_ACK_TIME.
Alternatively, if AACK_ACK_TIME = 1, the acknowledgment response time is reduced
according to Table 5-24.
Table 5-24. Short ACK response time (AACK_ACK_TIME = 1)
PHY Mode
ACK response time [symbol periods]
BPSK-20, OQPSK-{100,200,400}
2
BPSK-40, OQPSK-{250,500,1000}
3
The reduced ACK response time is particularly useful for the High Data Rate Modes,
refer to section 7.1.4.
• Bit 1 – AACK_PROM_MODE
Register bit AACK_PROM_MODE enables the promiscuous mode, within the
RX_AACK mode; refer to IEEE 802.15.4-2006 section 7.5.6.5.
If this bit is set, incoming frames with a valid PHR generate interrupt IRQ_3 (TRX_END)
even if the third level filter rules do not match or the FCS is not valid. However, register
bit RX_CRC_VALID (register 0x06) is set accordingly.
If a frame passes the third level filter rules, an acknowledgement frame is generated
and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E,
CSMA_SEED_1).
• Bit 0 – Reserved
Register 0x2C (XAH_CTRL_0):
Register 0x2C (XAH_CTRL_0) is a control register for Extended Operating Mode.
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Table 5-25. Register 0x2C (XAH_CTRL_0)
Bit
7
6
Name
5
4
MAX_FRAME_RETRIES
Read/Write
R/W
Reset Value
0
0
1
1
Bit
3
2
1
0
Name
Read/Write
Reset Value
SLOTTED_OPERATION
MAX_CSMA_RETRIES
R/W
1
0
R/W
0
0
• Bit 7:4 – MAX_FRAME_RETRIES
The setting of MAX_FRAME_RETRIES specifies the number of attempts in TX_ARET
mode to automatically retransmit a frame, when it was not acknowledged by the
recipient.
• Bit 3:1 – MAX_CSMA_RETRIES
MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the
CSMA-CA procedure before the transaction gets cancelled. According IEEE 802.15.4
the valid range of MAX_CSMA_RETRIES is [0, 1, …, 5].
A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission
without performing CSMA-CA. This may especially be required for slotted
acknowledgement operation. MAX_CSMA_RETRIES = 6 is reserved.
• Bit 0 – SLOTTED_OPERATION
If set, register bit SLOTTED_OPERATION enables RX_AACK acknowledgment
generation in slotted operation mode, refer to section 5.2.3.5.
Using RX_AACK mode in networks operating in beacon or slotted mode, refer to
IEEE 802.15.4-2006, section 5.5.1, register bit SLOTTED_OPERATION indicates that
acknowledgement frames are to be sent on back-off slot boundaries (slotted
acknowledgement).
If this register bit is set the acknowledgement frame transmission is initiated by the
microcontroller, using the rising edge of pin 11 (SLP_TR).
Register 0x2D (CSMA_SEED_0):
The CSMA_SEED_0 register is a control register for RX_AACK and contains a part of
the CSMA seed for the CSMA-CA algorithm.
Table 5-26. Register 0x2D (CSMA_SEED_0)
Bit
7
6
5
Name
4
2
1
0
0
1
0
CSMA_SEED_0[7:0]
Read/Write
Reset Value
3
R/W
1
1
1
0
1
• Bit 7:0 – CSMA_SEED_0
This register contains the lower 8 bit of the CSMA_SEED, bits [7:0]. The higher 3 bit are
part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is
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the seed for the random number generation that determines the length of the back-off
period in the CSMA-CA algorithm.
It is recommended to initialize registers CSMA_SEED with random values. This can be
done using register bits RND_VALUE (register 0x06, PHY_RSSI), refer to section 9.2.
Register 0x2E (CSMA_SEED_1):
The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of
the CSMA seed for the CSMA-CA algorithm, as well as control bits for the Frame Filter
and RX_AACK transaction.
Table 5-27. Register 0x2E (CSMA_SEED_1)
Bit
7
6
5
4
Name
AACK_FVN_MODE
AACK_FVN_MODE
AACK_SET_PD
AACK_DIS_ACK
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
0
Bit
3
2
1
0
Name
AACK_I_AM_COORD
CSMA_SEED_1
CSMA_SEED_1
CSMA_SEED_1
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
• Bit 7:6 – AACK_FVN_MODE
The frame control field of the MAC header (MHR) contains a frame version subfield.
The setting of AACK_FVN_MODE specifies the frame filtering and acknowledgement
behavior of the AT86RF212. According to the content of these register bits the radio
transceiver passes frames with a specific frame version number, number group, or
independent of the frame version number.
Thus the register bit AACK_FVN_MODE defines the maximum acceptable frame
version. Received frames with a higher frame version number than configured do not
pass the Frame Filter and thus are not acknowledged.
Table 5-28. Frame Version Subfield dependent Frame Acknowledgment
Register Bits
AACK_FVN_MODE
Value
Description
0
Acknowledge frames with version number 0
1
Acknowledge frames with version number 0 or 1
2
Acknowledge frames with version number 0 or 1 or 2
3
Acknowledge independent of frame version number
Note that the frame version field of the acknowledgment frame is set to 0x00 according
to IEEE 802.15.4-2006, section 7.2.2.3.1 Acknowledgment frame MHR fields.
• Bit 5 – AACK_SET_PD
The content of AACK_SET_PD bit is copied into the frame pending subfield of the
acknowledgment frame if the ACK is the answer to a data request MAC command
frame.
In addition, if register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) are
configured to accept frames with a frame version other than 0 or 1, the content of
register bit AACK_SET_PD is also copied into the frame pending subfield of the
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acknowledgment frame for any MAC command frame with a frame version of 2 or 3 that
have the security enabled subfield set to 1. This is done in the assumption that a future
version of the standard [1] might change the length or structure of the auxiliary security
header, so it would not possible to safely detect whether the MAC command frame is
actually a data request command or not.
• Bit 4 – AACK_DIS_ACK
If this bit is set no acknowledgment frames are transmitted in RX_AACK Extended
Operating Mode, even if requested.
• Bit 3 – AACK_I_AM_COORD
This register bit has to be set if the node is a PAN coordinator. It is used for frame
filtering in RX_AACK.
If I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC
command frame, the frame shall be accepted only if the device is the PAN coordinator
and the source PAN identifier matches macPANId, for details refer to IEEE 802.15.4,
section 7.5.6.2 (third-level filter rule 6).
• Bit 2:0 – CSMA_SEED_1
These register bits are the higher 3-bit of the CSMA_SEED, bits [10:8]. The lower part
is in register 0x2D (CSMA_SEED_0), see register CSMA_SEED_0 for details.
Register 0x2F (CSMA_BE):
Table 5-29. Register 0x2F (CSMA_BE)
Bit
7
6
5
4
Name
MAX_BE
MAX_BE
MAX_BE
MAX_BE
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
1
Bit
3
2
1
0
Name
MIN_BE
MIN_BE
MIN_BE
MIN_BE
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
1
• Bit 7:4 – MAX_BE
Register bits MAX_BE defines the maximum value of the backoff exponent in the
CSMA-CA algorithm. It equals macMaxBE, refer to [1], section 7.5.1.4, Table 71. Valid
values are [4’d8, 4’d7, … , 4’d3].
• Bit 3:0 – MIN_BE
Register bits MIN_BE defines the minimum value of the backoff exponent in the CSMACA algorithm. It quals to macMinBE, refer to [1], section 7.5.1.4, Table 71.
Valid values are [MAX_BE, (MAX_BE – 1), … , 4’d0].
Note
• If MIN_BE = 0 and MAX_BE = 0 the CCA backoff period is always set to 0.
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6 Functional Description
6.1 Introduction – IEEE 802.15.4-2006 Frame Format
Figure 6-1 provides an overview of the physical layer (PHY) frame structure as defined
by the IEEE 802.15.4-2006 standard. Figure 6-2 shows the medium access control
layer (MAC) frame structure.
Figure 6-1. IEEE 802.15.4 Frame Format – PHY Layer Frame Structure
PHY Protocol Data Unit (PPDU)
Preamble Sequence
SFD
5 octets
Synchronization Header (SHR)
Frame
Length
1 octet
(PHR)
PHY Payload
max. 127 octets PHY Payload
PHY Service Data Unit (PSDU)
MAC Protocol Data Unit (MPDU)
6.1.1 PHY Protocol Data Unit (PPDU)
6.1.1.1 Synchronization Header (SHR)
The SHR consists of a four-octet preamble field (all zero), followed by a single octet
start-of-frame delimiter (SFD). During transmit, the SHR is automatically generated by
the AT86RF212, thus the Frame Buffer shall contain PHR and PSDU only, see section
4.3.2.
The transmission of the SHR requires 40 symbols for a transmission with BPSK
modulation and 10 symbols for a transmission with O-QPSK modulation, respectively.
Table 6-1 illustrates the SHR duration depending on the selected data rate, see also
section 10.5.
As the SPI data rate is usually higher than the over-the-air data rate, this allows the
microcontroller to initiate a transmission before the frame buffer write access is
completed.
During frame reception, the SHR is used for synchronization purposes. The matching
SFD determines the beginning of the PHR and the following PSDU payload data.
6.1.1.2 PHY Header (PHR)
The PHY header is a single octet following the SHR. The least significant 7 bits denote
the frame length of the following PSDU, while the most significant bit of that octet is
reserved, and shall be set to 0 for IEEE 802.15.4 compliant frames.
In transmit mode, the PHR needs to be supplied as the first octet during Frame Buffer
write access, see section 4.3.2.
In receive mode, the PHR is returned as the first octet during Frame Buffer read
access, see section 4.3.2.
6.1.1.3 PHY Payload (PHY Service Data Unit, PSDU)
The PSDU has a variable length between one and 127 octets. The PSDU contains the
MAC protocol data unit (MPDU), where the last two octets are used for the Frame
Check Sequence (FCS), see section 6.3.
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6.1.1.4 Timing Summary
Table 6-1 shows timing information for the above mentioned frame structure depending
on the selected data rate.
Table 6-1. PPDU Timing
PHY Mode
BPSK
(1)
O-QPSK (1)
O-QPSK
(2)
Notes:
PSDU
Bit Rate
[kbit/s]
Header
Bit Rate
[kbit/s]
Duration
SHR [µs]
PHR [µs]
Max. PSDU [ms]
20
20
2000
400
50.8
40
40
1000
200
25.4
100
100
300
80
10.16
250
250
160
32
4.064
200
100
300
80
5.08
400
100
300
80
2.54
500
250
160
32
2.032
1000
250
160
32
1.016
1. Compliant to IEEE 802.15.4-2006, see [1]
2. High Data Rate Modes, see chapter 7.1.4
6.1.2 MAC Protocol Data Unit (MPDU)
Figure 6-2 shows the frame structure of the MAC layer.
Figure 6-2. IEEE 802.15.4-2006 Frame Format – MAC Layer Frame Structure
MAC Protocol Data Unit (MPDU)
Sequence
Number
FCF
Addressing Fields
MAC Payload
MAC Header (MHR)
Destination
PAN ID
0
1
Frame Type
2
MAC Service Data Unit (MSDU)
Destination
Source
address
PAN ID
0/4/6/8/10/12/14/16/18/20 octets
3
4
5
Security
Enabled
Frame
Pending
ACK
Request
FCS
6
7
Source
address
8
PAN ID
Reserved
Compr.
Frame Control Field 2 octets
9
(MFR)
Auxiliary Security Header
CRC-16
0/5/6/10/14 octets
2 octets
10
11
Destination
Addressing Mode
12
13
Frame Version
14
15
Source
Addressing Mode
6.1.2.1 MAC Header (MHR)
The MAC header consists of the Frame Control Field (FCF), a sequence number, and
the addressing fields of variable length.
6.1.2.2 Frame Control Field (FCF)
The FCF occupies the first two octets of the MPDU.
Bit [2:0]: describe the “Frame Type”. Table 6-2 summarizes frame types defined by [1],
section 7.2.1.1.1.
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Table 6-2. Frame Type Field
Frame Type Value
Description
b2 b1 b0
Value
000
0
Beacon
001
1
Data
010
2
Acknowledge
011
3
MAC command
100 – 111
4–7
Reserved
These bits are used for frame filtering by the third level filter rules, refer to section
7.2.1.1.1 of [1].
Bit 3 indicates whether security processing applies to this frame. This field is evaluated
by the Frame Filter.
Bit 4 is the “Frame Pending” subfield. This field can be set in an acknowledgment frame
to indicate to the node receiving the acknowledgment frame that the node sent the
acknowledgment frame has more data to send.
Bit 5 forms the “Acknowledgment Request” subfield. If this bit is set within a data or
MAC command frame that is not broadcast, the recipient shall acknowledge the
reception of the frame within the time specified by IEEE 802.15.4 (i.e. within 12 symbols
for nonbeacon-enabled networks).
Bit 6: The “PAN ID Compression” subfield indicates that in a frame where both the
destination and source addresses are present, the PAN ID is omitted from the source
addressing field. This bit is evaluated by the Frame Filter of the AT86RF212.
Bit [9:7]: Reserved
Bit [11:10]: The “Destination Addressing Mode” subfield describes the format of the
destination address of the frame. The values of the address modes are summarized in
Table 6-3, according to IEEE 802.15.4:
Table 6-3. Destination and Source Addressing Mode
Addressing Mode Value
Description
b11 b10
Value
00
0
PAN identifier and address fields are not present.
01
1
Reserved
10
2
Address field contains a 16-bit short address.
11
3
Address field contains a 64-bit extended address.
If the destination address mode is either 2 or 3, i.e. if the destination address is present,
the addressing field consists of a 16-bit PAN ID first, followed by either the 16-bit or 64bit address as defined by the mode.
Bit [13:12]: The “Frame Version” subfield specifies the version number corresponding
to the frame, see Table 6-4. These bits are reserved in IEEE-802.15.4-2003.
This subfield shall be set to 0x00 to indicate a frame compatible with
IEEE 802.15.4-2003 and 0x01 to indicate an IEEE 802.15.4 frame. All other subfield
values shall be reserved for future use. See [1], section 7.2.3 for details on frame
compatibility.
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Table 6-4. Frame Version Field
Frame Version Value
Description
b13 b12
Value
00
0
Frames are compatible with IEEE 802.15.4-2003
01
1
Frames are compatible with IEEE 802.15.4-2006
10
2
Reserved
11
3
Reserved
Bit [15:14] is the “Source Addressing Mode” subfield, with similar meaning as
“Destination Addressing Mode”.
The addressing field description bits of the FCF (Bits 0–2, 3, 6, 10–15) affect the
AT86RF212 Frame Filter, see section 6.2.
6.1.2.3 Frame Compatibility between IEEE 802.15.4 Rev. 2003 and 2006
All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured
frames compliant with IEEE 802.15.4-2003, with two exceptions: a coordinator
realignment command frame with the Channel Page field present (see [1], section
7.3.8) and any frame with a MAC Payload field larger than aMaxMACSafePayloadSize
octets.
Compatibility for secured frames is shown in Table 6-5, which identifies the security
operating modes for IEEE 802.15.4-2003 and IEEE 802.15.4-2006.
Table 6-5. Frame Compatibility
Frame Control Field Bit Assignments
Description
Security Enabled
b3
Frame Version
b13 b12
0
00
No security. Frames are compatible between
IEEE 802.15.4-2003 and IEEE 802.15.4-2006.
0
01
No security. Frames are not compatible between
IEEE 802.15.4-2003 and IEEE 802.15.4-2006.
1
00
Secured frame formatted according to
IEEE 802.15.4-2003. This type of frame is not
supported in IEEE 802.15.4-2006.
1
01
Secured frame formatted according to
IEEE 802.15.4-2006
6.1.2.4 Sequence Number
The one-octet sequence number following the FCF identifies a particular frame, so that
duplicated frame transmissions can be detected. While operating in RX_AACK states,
the received frame content of this field is copied into the acknowledgment frame.
6.1.2.5 Addressing Fields
The addressing field carries several addresses used for address matching indication.
The destination address (if present) is always first, followed by the source address (if
present). Each address field consists of the PAN ID and a device address. If both
addresses are present, and the “PAN ID compression” subfield in the FCF is set to one,
the source PAN ID is omitted.
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Note that in addition to these general rules, IEEE 802.15.4 further restricts the valid
address combinations for the different MAC frame types. For example, the situation
where both addresses are omitted (source addressing mode = 0 and destination
addressing mode = 0) is only allowed for acknowledgment frames. The Frame Filter in
the AT86RF212 has been designed to apply to IEEE 802.15.4 compliant frames. It can
be configured to handle other frame formats and exceptions.
6.1.2.6 Auxiliary Security Header
The Auxiliary Security Header terminates the MHR. This field has a variable length and
specifies information required for security processing, including how the frame is
actually protected (security level) and which keying material from the MAC security PIB
is used (see [1], section 7.6.1). This field shall be present only if the Security Enabled
subfield b3, see 6.1.2.3, is set to one. For details on formatting, see 7.6.2 of [1].
6.1.2.7 MAC Service Data Unit (MSDU)
This is the actual MAC payload. It is usually structured according to the individual frame
type descriptions in IEEE 802.15.4 standard.
6.1.2.8 MAC Footer (MFR)
The MAC footer consists of a two-octet Frame Checksum (FCS), for details refer to
section 6.3.
6.2 Frame Filter
Frame Filtering is a procedure that evaluates whether or not a received frame matches
predefined criteria, like source or destination address or frame types. A filtering
procedure as described in IEEE 802.15.4-2006 chapter 7.5.6.2 (third level of filtering) is
applied to the frame to accept a received frame and to generate the address match
interrupt IRQ_5 (AMI).
The AT86RF212 Frame Filter passes only frames that satisfy all of the following
requirements/rules (quote from IEEE 802.15.4-2006, 7.5.6.2):
1. The Frame Type subfield shall not contain a reserved frame type.
2. The Frame Version subfield shall not contain a reserved value.
3. If a destination PAN identifier is included in the frame, it shall match macPANId or
shall be the broadcast PAN identifier (0xFFFF).
4. If a short destination address is included in the frame, it shall match either
macShortAddress or the broadcast address (0xFFFF). Otherwise, if an extended
destination address is included in the frame, it shall match aExtendedAddress.
5. If the frame type indicates that the frame is a beacon frame, the source PAN identifier
shall match macPANId unless macPANId is equal to 0xffff, in which case the beacon
frame shall be accepted regardless of the source PAN identifier.
6. If only source addressing fields are included in a data or MAC command frame, the
frame shall be accepted only if the device is the PAN coordinator and the source
PAN identifier matches macPANId.
Moreover the AT86RF212 has two additional requirements:
7. The frame type shall indicate that the frame is not an acknowledgment (ACK) frame.
8. At least one address field must be configured.
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Address matching, indicated by interrupt IRQ_5 (AMI), is furthermore controlled by the
FCF of a received frame according to the following rule:
If Destination Addressing Mode is 0/1 and Source Addressing Mode is 0, see section
6.1.2.2, no interrupt IRQ_5 is generated. This causes that no acknowledgement frame
is announced.
For backward compatibility with IEEE 802.15.4-2003, the third level filter rule 2 (Frame
Version) can be disabled by register bits AACK_FVN_MODE (register 0x2E,
CSMA_SEED_1).
Frame filtering is available in Extended and Basic Operating Modes. A frame that
passes the Frame Filter generates the interrupt IRQ_5 (AMI), if not masked.
Notes
• Filter rule 1 is affected by register bits AACK_FLTR_RES_FT
AACK_UPLD_RES_FT, see section 6.2.3.
• Filter rule 2 is affected by register bits AACK_FVN_MODE, see section 6.2.3.
and
6.2.1 Configuration
The Frame Filter is configured by setting the appropriate address variables and several
additional properties as described in Table 6-6.
Table 6-6. Frame Filter Configuration
Register
Address
Register
Bits
0x20,0x21
0x22,0x23
0x24
…
0x2B
7:0
0x17
Name
Description
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Set macShortAddress, macPANId
aExtendedAddress as described in [1]
1
AACK_PROM_MODE
0: disable promiscuous mode
1: enable promiscuous mode
0x17
4
AACK_UPLD_RES_FT
0: disable reserved frame type reception
1: enable reserved frame type reception
0x17
5
AACK_FLTR_RES_FT
Filter reserved frame types like data frame
type, see section 6.2.2
0: disable
1: enable
0x2E
7:6
AACK_FVN_MODE
Frame acceptance criteria depending on
FCF frame version number
b00: accept only frames with version
number 0, i.e. according to
IEEE 802.15.4-2003 frames
b01: accept only frames with version
number 0 or 1, i.e. frames according to
IEEE 802.15.4-2006
b10: accept only frames with version
number 0 or 1 or 2
b11: accept all frames, independent of the
FCF frame version number
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6.2.2 Handling of Reserved Frame Types
Reserved frame types as described in 5.2.3.3 are treated according to bits
AACK_UPLD_RES_FT and AACK_FLTR_RES_FT of register 0x17 (XAH_CTRL_1)
with 3 options:
1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0:
Frames of reserved frame type with correct FCS are indicated by the interrupt IRQ_3
(TRX_END). No further frame filtering is applied on these frames. Interrupt IRQ_5
(AMI) is never generated and no acknowledgment is sent.
2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1:
If AACK_FLTR_RES_FT = 1, any frame with a reserved frame type is treated by the
RX_AACK Frame Filter as an IEEE 802.15.4 compliant data frame. This implies the
generation of the interrupt IRQ_5 (AMI) upon address matches.
3. AACK_UPLD_RES_FT = 0
Any frame with a reserved frame type is blocked.
6.2.3 Register Description
Register 0x17 (XAH_CTRL_1):
The XAH_CTRL_1 register is a control register for Extended Operating Mode.
Table 6-7. Register 0x17 (XAH_CTRL_1)
Bit
7
6
5
4
Name
Reserved
CSMA_LBT_MODE
AACK_FLTR_RES_FT
AACK_UPLD_RES_FT
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
Reserved
AACK_ACK_TIME
AACK_PROM_MODE
Reserved
Read/Write
R
R/W
R/W
R
Reset Value
0
0
0
0
• Bit 7 – Reserved
• Bit 6 – CSMA_LBT_MODE
Refer to section 6.7.3.
• Bit 5 – AACK_FLTR_RES_FT
This register bit shall only be set if AACK_UPLD_RES_FT = 1.
If AACK_FLTR_RES_FT = 1, any frame with a reserved frame type is treated by the
RX_AACK Frame Filter as an IEEE 802.15.4 compliant data frame.
If AACK_FLTR_RES_FT = 0, the received reserved frame is only checked for a valid
FCS.
See 6.2.2 for details.
• Bit 4 – AACK_UPLD_RES_FT
If AACK_UPLD_RES_FT = 1, received frames which are identified as reserved frames
will not be blocked.
See 6.2.2 for details.
• Bit 3 – Reserved
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• Bit 2 – AACK_ACK_TIME
Refer to section 5.2.3.3.
• Bit 1 – AACK_PROM_MODE
Refer to section 5.2.6.
• Bit 0 – Reserved
Register 0x20 (SHORT_ADDR_0):
This register contains the lower 8 bit of the 16-bit short address for Frame Filter address
recognition, bits [7:0].
Table 6-8. Register 0x20 (SHORT_ADDR_0)
Bit
7
6
5
Name
4
3
1
0
1
1
SHORT_ADDRESS_0[7:0]
Read/Write
Reset Value
2
R/W
1
1
1
1
1
1
Register 0x21 (SHORT_ADDR_1):
This register contains the higher 8 bit of the 16-bit short address for Frame Filter
address recognition, bits [15:8].
Table 6-9. Register 0x21 (SHORT_ADDR_1)
Bit
7
6
5
Name
4
2
1
0
1
1
SHORT_ADDRESS_1[7:0]
Read/Write
Reset Value
3
R/W
1
1
1
1
1
1
Register 0x22 (PAN_ID_0):
This register contains the lower 8 bit of the MAC PAN ID for Frame Filter address
recognition, bits [7:0].
Table 6-10. Register 0x22 (PAN_ID_0)
Bit
7
6
5
4
Name
2
1
0
1
1
1
PAN_ID_0[7:0]
Read/Write
Reset Value
3
R/W
1
1
1
1
1
Register 0x23 (PAN_ID_1):
This register contains the higher 8 bit of the MAC PAN ID for Frame Filter address
recognition, bits [15:8].
Table 6-11. Register 0x23 (PAN_ID_1)
Bit
7
6
5
4
Name
2
1
0
1
1
1
PAN_ID_1[7:0]
Read/Write
Reset Value
3
R/W
1
1
1
1
1
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Register 0x24 (IEEE_ADDR_0):
This register contains bits [7:0] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-12. Register 0x24 (IEEE_ADDR_0)
Bit
7
6
5
Name
4
2
1
0
0
0
0
IEEE_ADDR_0[7:0]
Read/Write
Reset Value
3
R/W
0
0
0
0
0
Register 0x25 (IEEE_ADDR_1):
This register contains bits [15:8] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-13. Register 0x25 (IEEE_ADDR_1)
Bit
7
6
5
Name
4
2
1
0
0
0
0
IEEE_ADDR_1[7:0]
Read/Write
Reset Value
3
R/W
0
0
0
0
0
Register 0x26 (IEEE_ADDR_2):
This register contains bits [23:16] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-14. Register 0x26 (IEEE_ADDR_2)
Bit
7
6
5
Name
4
2
1
0
0
0
0
IEEE_ADDR_2[7:0]
Read/Write
Reset Value
3
R/W
0
0
0
0
0
Register 0x27 (IEEE_ADDR_3):
This register contains bits [31:24] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-15. Register 0x27 (IEEE_ADDR_3)
Bit
7
6
5
Name
4
Read/Write
Reset Value
3
2
1
0
0
0
0
IEEE_ADDR_3[7:0]
R/W
0
0
0
0
0
Register 0x28 (IEEE_ADDR_4):
This register contains bits [39:32] of the 64-bit IEEE extended address for Frame Filter
address recognition.
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Table 6-16. Register 0x28 (IEEE_ADDR_4)
Bit
7
6
5
Name
4
2
1
0
0
0
0
IEEE_ADDR_4[7:0]
Read/Write
Reset Value
3
R/W
0
0
0
0
0
Register 0x29 (IEEE_ADDR_5):
This register contains bits [47:40] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-17. Register 0x29 (IEEE_ADDR_5)
Bit
7
6
5
Name
4
2
1
0
0
0
0
IEEE_ADDR_5[7:0]
Read/Write
Reset Value
3
R/W
0
0
0
0
0
Register 0x2A (IEEE_ADDR_6):
This register contains bits [55:48] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-18. Register 0x2A (IEEE_ADDR_6)
Bit
7
6
5
Name
4
2
1
0
0
0
0
IEEE_ADDR_6[7:0]
Read/Write
Reset Value
3
R/W
0
0
0
0
0
Register 0x2B (IEEE_ADDR_7):
This register contains bits [63:56] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-19. Register 0x2B (IEEE_ADDR_7)
Bit
7
6
5
Name
4
Read/Write
Reset Value
3
2
1
0
0
0
0
IEEE_ADDR_7[7:0]
R/W
0
0
0
0
0
Register 0x2E (CSMA_SEED_1):
The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of
the CSMA seed for the CSMA-CA algorithm, as well as control bits for the Frame Filter
and RX_AACK transaction.
Table 6-20. Register 0x2E (CSMA_SEED_1)
Bit
7
6
5
4
Name
AACK_FVN_MODE
AACK_FVN_MODE
AACK_SET_PD
AACK_DIS_ACK
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
0
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Bit
3
2
1
0
Name
AACK_I_AM_COORD
CSMA_SEED_1
CSMA_SEED_1
CSMA_SEED_1
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
• Bit 7:6 – AACK_FVN_MODE
The frame control field of the MAC header (MHR) contains a frame version subfield.
The setting of AACK_FVN_MODE specifies the frame filtering and acknowledgement
behavior of the AT86RF212. According to the content of these register bits the radio
transceiver passes frames with a specific set of frame version numbers.
Thus the register bit AACK_FVN_MODE defines the maximum acceptable frame
version. Received frames with a higher frame version number than configured do not
pass the Frame Filter and thus are not acknowledged.
Table 6-21. Frame Version Subfield dependent Frame Acceptance
Register Bits
Value
AACK_FVN_MODE
Description
0
Accept frames with version number 0
1
Accept frames with version number 0 or 1
2
Accept frames with version number 0 or 1 or 2
3
Accept independent of frame version number
• Bit 5 – AACK_SET_PD
Refer to section 5.2.6.
• Bit 4 – AACK_ DIS_ACK
Refer to section 5.2.6.
• Bit 3 – AACK_I_AM_COORD
Refer to section 5.2.6.
• Bit 2:0 – CSMA_SEED_1
Refer to section 5.2.6.
6.3 Frame Check Sequence (FCS)
A FCS mechanism employing a 16-bit International Telecommunication Union Telecommunication Standardization Sector (ITU-T) cyclic redundancy check (CRC) can
be used to detect errors in frames.
6.3.1 Overview
The FCS is intended for use at the MAC layer in order to detect corrupted frames. It is
computed by applying an ITU-T CRC polynomial to all transmitted/received bytes
following the length field (MHR and MSDU fields). The FCS has a length of 16 bit and is
located in the last two octets of the PSDU.
By default, the AT86RF212 generates and inserts the FCS octets autonomously during
transmit process. This behavior can be disabled by setting register bit
TX_AUTO_CRC_ON = 0 (register 0x04, TRX_CTRL_1).
An automatic FCS check is always performed during frame reception.
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6.3.2 CRC Calculation
The CRC polynomial used in IEEE 802.15.4 networks is defined by
G16 ( x) = x 16 + x 12 + x 5 + 1 .
The FCS shall be calculated for transmission using the following algorithm:
Let
M ( x) = b0 x k −1 + b1 x k −2 + K + bk −2 x + bk −1
be the polynomial representing the sequence of bits for which the checksum is to be
16
computed. Multiply M(x) by x , giving the polynomial
N ( x) = M ( x) ⋅ x16 .
Divide N (x) modulo 2 by the generator polynomial, G16 ( x ) , to obtain the remainder
polynomial,
R ( x) = r0 x15 + r1 x14 + ... + r14 x + r15
The FCS field is given by the coefficients of the remainder polynomial, R (x) .
Example:
Considering a 5-octet ACK frame, the MHR field consists of
0100 0000 0000 0000 0101 0110 .
The leftmost bit (b0) is transmitted first in time. The FCS would be
0010 0111 1001 1110 .
The leftmost bit (r0) is transmitted first in time.
6.3.3 Automatic FCS Generation
The automatic FCS generation is enabled with register bit TX_AUTO_CRC_ON = 1.
This allows the AT86RF212 to compute the FCS autonomously. For a frame with a
frame length field specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2
octets in the Frame Buffer, and the resulting FCS octets are transmitted in place of the
last two octets of the Frame Buffer.
6.3.4 Automatic FCS Check
Basic and Extended Operating Modes are provided with an automatic FCS check for
received frames. Register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set to one,
if the FCS of a received frame is valid.
In Extended Operating Mode, the RX_AACK procedure does not accept a frame, if the
corresponding FCS is not valid, and no TRX_END interrupt is issued. When operating
in TX_ARET mode, the FCS of a received ACK is automatically checked. If it is not
correct, the ACK is not accepted, refer to section 5.2.4 for automated retries.
6.3.5 Register Description
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi-purpose register to control various operating
modes and settings of the radio transceiver, see Table 6-22.
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Table 6-22. Register 0x04 (TRX_CTRL_1)
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
SPI_CMD_MODE
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – PA_EXT_EN
Refer to section 9.4.3.
• Bit 6 – IRQ2_EXT_EN
Refer to section 9.5.2.
• Bit 5 – TX_AUTO_CRC_ON
The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1,
which is the reset value.
• Bit 4 – RX_BL_CTRL
Refer to section 9.6.2.
• Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
• Bit 1 – IRQ_MASK_MODE
Refer to section 4.7.2.
• Bit 0 – IRQ_POLARITY
Refer to section 4.7.2.
Register 0x06 (PHY_RSSI):
The PHY_RSSI register is a multi-purpose register to indicate FCS validity, to provide
random numbers, and a RSSI value.
Table 6-23. Register 0x06 (PHY_RSSI)
78
Bit
7
6
5
4
Name
RX_CRC_VALID
RND_VALUE
RND_VALUE
RSSI[4]
Read/Write
R
R
R
R
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
RSSI[3]
RSSI[2]
RSSI[1]
RSSI[0]
Read/Write
R
R
R
R
Reset Value
0
0
0
0
AT86RF212
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AT86RF212
• Bit 7 – RX_CRC_VALID
Reading this register bit indicates whether the last received frame has a valid FCS or
not. The register bit is updated at the same time the IRQ_3 (TRX_END) is issued and
remains valid until the next SHR detection. A value of “1” corresponds to a valid FCS, a
value of “0” corresponds to an invalid FCS.
• Bit 6:5 – RND_VALUE
Refer to register description in section 9.1.8.
• Bit 4:0 – RSSI
Refer to register description in section 6.4.4.
6.4 Received Signal Strength Indicator (RSSI)
The Received Signal Strength Indicator is characterized by:
• a dynamic range of 81 dB
• a minimum RSSI value of 0
• a maximum RSSI value of 28
6.4.1 Overview
The RSSI is a 5-bit value indicating the received signal power in the selected channel,
in steps of 3 dB. No attempt is made to distinguish IEEE 802.15.4 signals from others,
only the received signal strength is evaluated. The RSSI provides the basis for an ED
measurement, see 6.5.
6.4.2 Reading RSSI
In Basic Operating Modes, the RSSI value is valid in any receive state, and is updated
at time intervals according to Table 6-24. The current RSSI value can be accessed by
reading register bits RSSI of register 0x06 (PHY_RSSI).
Table 6-24. RSSI Update Interval
PHY Mode
Update Interval [µs]
BPSK-20
32
BPSK-40
24
O-QPSK
8
It is not recommended reading the RSSI value when using the Extended Operating
Modes. Instead, the automatically generated ED value should be used, see section 6.5.
6.4.3 Data Interpretation
The RSSI value is a 5-bit value, indicating the receiver input power, in steps of 3 dB and
with a range of 0 - 28.
A RSSI value of 0 indicates a receiver input power less than RSSI_BASE_VAL [dBm].
The value RSSI_BASE_VAL itself depends on the PHY mode, refer to section 7.1. For
typical conditions, it is shown in Table 6-25.
Due to environmental conditions (temperature, voltage, semiconductor parameters,
etc.), RSSI_BASE_VAL has a maximum tolerance of ±5 dB. This should be considered
as a constant offset over the measurement range.
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Table 6-25. RSSI_BASE_VAL
PHY Mode
RSSI_BASE_VAL [dBm]
Maximum Tolerance [dB]
BPSK with 300 kchip/s
-100
±5
BPSK with 600 kchip/s
-99
±5
O-QPSK with 400 kchip/s
-98
±5
O-QPSK with 1000 kchip/s,
sine shaping (SIN)
-97
±5
O-QPSK with 1000 kchip/s,
raised cosine shaping (RC-0.8)
-97
±5
For a RSSI value in the range of 1 to 28, the receiver input power can be calculated as
follows:
PRF = RSSI_BASE_VAL[dBm] + 3 (RSSI - 1) [dBm]
Figure 6-3. Mapping between RSSI Value and Receiver Input Power
-5
-15
[dBm]
-25
Received Input Power P
RF
-35
-45
-55
-65
BPSK with 300 kchip/s
BPSK with 600 kchip/s
O-QPSK with 400 kchip/s
O-QPSK with 1000 kchip/s (SIN)
O-QPSK with 1000 kchip/s (RC-0.8)
-75
-85
-95
-105
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
RSSI
6.4.4 Register Description
Register 0x06 (PHY_RSSI)
Table 6-26. Register 0x06 (PHY_RSSI)
80
Bit
7
6
5
4
Name
RX_CRC_VALID
RND_VALUE
RND_VALUE
RSSI
Read/Write
R
R
R
R
Reset Value
0
0
0
0
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AT86RF212
Bit
3
2
1
0
Name
RSSI
RSSI
RSSI
RSSI
Read/Write
R
R
R
R
Reset Value
0
0
0
0
• Bit 7 – RX_CRC_VALID
Refer to register description in section 6.3.5.
• Bit 6:5 – RND_VALUE
Refer to register description in section 9.1.8.
• Bit 4:0 – RSSI
The result of the automated RSSI measurement is stored in register bits RSSI. The
value is updated at time intervals according to Table 6-24 at any receive state.
The value is a number between 0 and 28, indicating the received signal strength as a
linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. A RSSI
value of 0 indicates a receiver input power less than RSSI_BASE_VAL [dBm] (see
Table 6-25), a value of 28 an input power equal or larger than (RSSI_BASE_VAL + 81)
[dBm].
6.5 Energy Detection (ED)
The Energy Detection (ED) module is characterized by:
• 85 unique energy levels defined
• 1 dB resolution
6.5.1 Overview
The receiver ED measurement (ED scan procedure) can be used as a part of a channel
selection algorithm. It is an estimation of the received signal power within the bandwidth
of an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on the
channel. The ED value is calculated by averaging RSSI values over 8 symbol periods,
with the exception of the High Data Rate Modes, refer to 7.1.4.
6.5.2 Measurement Description
There are two ways to initiate an ED measurement:
• Manually, by writing an arbitrary value to register 0x07 (PHY_ED_LEVEL), or
• Automatically, after detection of a valid SHR of an incoming frame.
For manually initiated ED measurements, the radio transceiver needs to be either in the
state RX_ON or BUSY_RX. The end of the ED measurement time (8 symbol periods) is
indicated by the interrupt IRQ_4 (CCA_ED_READY) and the measurement result is
stored in register 0x07 (PHY_ED_LEVEL).
In order to avoid interference with an automatically initiated ED measurement, the SHR
detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN),
refer to section 7.2.
Note that it is not recommended to manually initiate an ED measurement when using
the Extended Operating Mode.
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An automated ED measurement is started upon SHR detection. The end of the
automated measurement is not signaled by an interrupt.
When using the Basic Operating Mode, a valid ED value (register 0x07,
PHY_ED_LEVEL) of the currently received frame is accessible not later than 8 symbol
periods after IRQ_2 (RX_START) and remains valid until a new RX_START interrupt is
generated by the next incoming frame or until another ED measurement is initiated.
When using the Extended Operating Mode, it is recommended to mask IRQ_2
(RX_START), thus the interrupt cannot be used as timing reference. A successful frame
reception is signalized by interrupt IRQ_3 (TRX_END). In this case, the value needs to
be read within the time span of a next SHR detection plus the ED measurement time in
order to avoid overwrite of the current ED value. This is important for time critical
applications or if the interrupt IRQ_2 (RX_START) is not used to indicate the reception
of a frame.
The values of the register 0x07 (PHY_ED_LEVEL) are:
Table 6-27. Register Bit PHY_ED_LEVEL Interpretation
PHY_ED_LEVEL
Description
0xFF
Reset value
0x00 … 0x54
ED measurement result of the last ED measurement
6.5.3 Data Interpretation
The PHY_ED_LEVEL is an 8-bit register. The ED value of the AT86RF212 has a valid
range from 0x00 to 0x54 (0 to 84) with a resolution of 1 dB. Values 0x55 to 0xFE do not
occur and a value of 0xFF indicates the reset value. A value of PHY_ED_LEVEL = 0
indicates that the measured receiver input power is less than or equal to
RSSI_BASE_VAL [dBm] (refer to Table 6-25).
For an ED value in the range of 0 to 84, the receiver input power can be calculated as
follows:
PRF = RSSI_BASE_VAL[dBm] + ED [dBm]
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Figure 6-4. Mapping between Receiver Input Power and ED Value
-5
-15
[dBm]
-25
Received Input Power P
RF
-35
-45
-55
-65
BPSK with 300 kchip/s
BPSK with 600 kchip/s
O-QPSK with 400 kchip/s
O-QPSK with 1000 kchip/s (SIN)
O-QPSK with 1000 kchip/s (RC-0.8)
-75
-85
-95
-105
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
PHY_ED_LEVEL (register 0x07)
6.5.4 Interrupt Handling
Interrupt IRQ_4 (CCA_ED_READY) is issued at the end of a manually initiated ED
measurement.
Note that an ED measurement should only be initiated in RX states. Otherwise, the
radio transceiver generates an IRQ_4 (CCA_ED_READY) without actually performing
an ED measurement.
6.5.5 Register Description
Register 0x07 (PHY_ED_LEVEL)
The ED_LEVEL register contains the result of an ED measurement.
Table 6-28. Register 0x07 (PHY_ED_LEVEL)
Bit
7
6
5
4
Name
3
2
1
0
1
1
1
ED_LEVEL[7:0]
(1)
Read/Write
R
Reset Value
1
1
1
1
1
Note:
1. A write access is required for initiation of a manual ED measurement.
Bit 7:0 – ED_LEVEL
The minimum ED value (ED_LEVEL = 0) indicates a receiver input power less than or
equal to RSSI_BASE_VAL [dBm]. The range is 84 dB with a resolution of 1 dB and an
absolute accuracy of ±5 dB.
A manual ED measurement can be initiated by a write access to the register. A value
0xFF indicates that a measurement has never been started yet (reset value).
The measurement duration is 8 symbol periods, see section 7.1.3.
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For High Data Rate Modes, the automated measurement duration is reduced to 2
symbol periods, refer to 7.1.4. For manually initiated ED measurements in these
modes, the measurement time is still 8 symbol periods as long as the receiver is in
RX_ON state.
A value out of {0x00,..,0x54} indicates the result of the last ED measurement.
6.6 Clear Channel Assessment (CCA)
The main features of the Clear Channel Assessment (CCA) module are:
• All four CCA modes are provided as defined in IEEE 802.15.4-2006
• Adjustable threshold for energy detection algorithm
6.6.1 Overview
A CCA measurement is used to detect a clear channel. Four CCA modes are specified
by IEEE 802.15.4-2006:
Table 6-29. CCA Mode Overview
CCA Mode
Description
1
Energy above threshold.
CCA shall report a busy medium upon detecting any energy above the ED
threshold.
2
Carrier sense only.
CCA shall report a busy medium only upon the detection of a signal with the
modulation and spreading characteristics of an IEEE 802.15.4 compliant signal.
The signal strength may be above or below the ED threshold.
0, 3
Carrier sense with energy above threshold.
CCA shall report a busy medium using a logical combination of
- Detection of a signal with the modulation and spreading characteristics of
this standard and/or
- Energy above the ED threshold.
Where the logical operator may be configured as either OR (mode 0) or
AND (mode 3).
6.6.2 Configuration and Request
The CCA modes are configurable via register 0x08 (PHY_CC_CCA).
When being in Basic Operating Mode, a CCA request can be initiated manually by
setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the AT86RF212 is in any
RX state. The current channel status (CCA_STATUS) and the CCA completion status
(CCA_DONE) are accessible through register 0x01 (TRX_STATUS).
The end of a manually initiated CCA (8 symbol periods plus processing delay), is
indicated by the interrupt IRQ_4 (CCA_ED_READY).
The sub-register CCA_ED_THRES of register 0x09 (CCA_THRES) defines the receive
power threshold of the “Energy above threshold” algorithm. The threshold is calculated
by
V_THRES = (RSSI_BASE_VAL + 2 • CCA_ED_THRES) [dBm].
Any received power above this level is interpreted as a busy channel.
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Note that it is not recommended to manually initiate a CCA request when using the
Extended Operating Mode.
6.6.3 Data Interpretation
The current channel status (CCA_STATUS) and the CCA completion status
(CCA_DONE) are accessible through register 0x01 (TRX_STATUS). Note that register
bits CCA_DONE and CCA_STATUS are cleared in response to a CCA_REQUEST.
The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radio
transceiver detected no signal (idle channel) during the CCA evaluation period, the
CCA_STATUS bit is set to 1, otherwise, it is set to 0.
When using the “Energy above threshold” algorithm, a received power above
V_THRES level is interpreted as a busy channel.
When using the “carrier sense” algorithm (i.e. CCA_MODE = 0, 2, and 3), the
AT86RF212 reports a busy channel upon detection of a (PHY mode specific)
IEEE 802.15.4 signal above the RSSI_BASE_VAL (see Table 6-25). The AT86RF212 is
also capable of detecting signals below this value, but the detection probability
decreases with decreasing signal power. It is almost zero at the radio transceivers
sensitivity level (see chapter 0).
6.6.4 Interrupt Handling
Interrupt IRQ_4 (CCA_ED_READY) is issued at the end of a manually initiated CCA
measurement.
Notes
• A CCA request should only be initiated in Basic Operating Mode RX states.
Otherwise, the radio transceiver generates IRQ_4 (CCA_ED_READY) and sets the
register bit CCA_DONE = 1, without actually performing a CCA measurement.
• Requesting a CCA measurement during BUSY_RX state and during an ED
measurement, the interrupt IRQ_4 (CCA_ED_READY) may be issued immediately
after the request. If in this case the register bit CCA_DONE is equal to 0, an
additional interrupt CCA_ED_READY is issued after finishing the CCA measurement
and register bit CCA_DONE is set to 1.
6.6.5 Measurement Time
The response time of a manually initiated CCA measurement depends on the receiver
state.
In RX_ON state, the CCA measurement is done over eight symbol periods and the
result is accessible upon the event IRQ_4 (CCA_ED_READY) or upon CCA_DONE=1
(register 0x01, TRX_STATUS).
In BUSY_RX state, the CCA measurement duration depends on the CCA mode and the
CCA request relative to the detection of the SHR. The end of the CCA measurement is
indicated by IRQ_4 (CCA_ED_READY). The variation of a CCA measurement period in
BUSY_RX state is described in Table 6-30.
Table 6-30. CCA Measurement Period and Access in BUSY_RX state
CCA Mode
1
Request within ED Measurement(1)
Request after ED Measurement
Energy above threshold.
CCA result is available after finishing
automated ED measurement period.
CCA result is immediately available
after request.
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CCA Mode
2
Request within ED Measurement(1)
Request after ED Measurement
Carrier sense only.
CCA result is immediately available after request.
3
Carrier sense with Energy above threshold (AND).
CCA result is immediately available
after request.
CCA result is available after finishing
automated ED measurement period.
0
Carrier sense with Energy above threshold (OR).
CCA result is immediately available
after request.
CCA result is available after finishing
automated ED measurement period.
Note:
1. After detecting the SHR, an automated ED measurement is started with a length of
8 symbol periods (2 symbol periods for high rate PHY modes), refer to 7.1.3. This
automated ED measurement must be finished to provide a result for the CCA
measurement. Only one automated ED measurement per frame is performed.
It is recommended to perform CCA measurements in RX_ON state only. To avoid
switching accidentally to BUSY_RX state, the SHR detection can be disabled by setting
register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to section 7.2. The receiver
remains in RX_ON state to perform a CCA measurement until the register bit
RX_PDT_DIS is set back to continue the frame reception. In this case, the CCA
measurement duration is 8 symbol periods.
6.6.6 Register Description
Register 0x01 (TRX_STATUS):
Two register bits of register 0x01 (TRX_STATUS) indicate the status of the CCA
measurement.
Table 6-31. Register 0x01 (TRX_STATUS)
Bit
7
6
5
4
Name
CCA_DONE
CCA_STATUS
Reserved
TRX_STATUS
Read/Write
R
R
R
R
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
TRX_STATUS
TRX_STATUS
TRX_STATUS
TRX_STATUS
Read/Write
R
R
R
R
Reset Value
0
0
0
0
• Bit 7 – CCA_DONE
This register indicates completion a CCA measurement, which is additionally indicated
by the interrupt IRQ_4 (CCA_ED_READY). Note that register bit CCA_DONE is cleared
in response to a CCA_REQUEST.
Table 6-32. CCA Algorithm Status
86
Register Bit
Value
Description
CCA_DONE
0
CCA calculation not finished
1
CCA calculation finished
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• Bit 6 – CCA_STATUS
After a CCA request is completed, the result of the CCA measurement is available in
register bit CCA_STATUS. Note that register bit CCA_STATUS is cleared in response
to a CCA_REQUEST.
Table 6-33. CCA Status Result
Register Bit
Value
CCA_STATUS
Description
0
Channel indicated as busy
1
Channel indicated as idle
• Bit 5 – Reserved
• Bit 4:0 – TRX_STATUS
Refer to section 5.1.5 and 5.2.6.
Register 0x08 (PHY_CC_CCA):
This register is provided to initiate and control a CCA measurement.
Table 6-34. Register 0x08 (PHY_CC_CCA)
Bit
7
6
5
4
Name
CCA_REQUEST
CCA_MODE
CCA_MODE
CHANNEL
Read/Write
W
R
R
R
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
CHANNEL
CHANNEL
CHANNEL
CHANNEL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
1
• Bit 7 – CCA_REQUEST
A manual CCA measurement is initiated by setting CCA_REQUEST = 1. The register
bit is automatically cleared after requesting a CCA measurement with
CCA_REQUEST = 1.
• Bit 6:5 – CCA_MODE
The CCA mode can be selected using register bits CCA_MODE.
Table 6-35. CCA Mode
Register Bits
Value
Description
CCA_MODE
0
Carrier sense OR Energy above threshold
1
Energy above threshold
2
Carrier sense only
3
Carrier sense AND Energy above threshold
Note that IEEE 802.15.4–2006 CCA mode 3 defines the logical combination of CCA
mode 1 and 2 with the logical operators AND or OR. This can be selected with:
• CCA_MODE = 0
• CCA_MODE = 3
for logical operation OR, and
for logical operation AND.
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• Bit 4:0 – CHANNEL
Refer to section 7.8.
Register 0x09 (CCA_THRES):
This register sets the ED threshold level for CCA.
Table 6-36. Register 0x09 (CCA_THRES)
Bit
7
6
5
4
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
1
1
0
0
Bit
3
2
1
0
Name
CCA_ED_THRES
CCA_ED_THRES
CCA_ED_THRES
CCA_ED_THRES
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
1
1
• Bit 7:5 – Reserved
• Bit 4:0 – CCA_ED_THRES
The CCA mode 1 request indicates a busy channel if the measured received power is
above (RSSI_BASE_VAL + 2 • CCA_ED_THRES) [dBm]. CCA modes 0 and 3 are
logically related to this result.
6.7 Listen Before Talk (LBT)
6.7.1 Overview
Equipment using the AT86RF212 shall conform to the established regulations. With
respect to the regulations in Europe, CSMA-CA based transmission according to IEEE
802.15.4 is not appropriate. In principle, transmission is subject to low duty cycles (0.1
to 1 %). However, according to ETSI EN 300 220-1-V2.1.1, equipment employing listen
before talk (LBT) and adaptive frequency agility (AFA) does not have to comply with
duty cycle conditions.
Hence, LBT can be attractive in order to reduce network latency.
Minimum Listening Time
A device with LBT needs to comply with a minimum listening time, refer to chapter
8.11.1.2.2 of ETSI EN 300 220-1-V2.1.1. Prior transmission, the device must listen for a
receive signal at or above the LBT threshold level to determine whether the intended
channel is available for use, unless transmission is pursuing acknowledgement.
A device using LBT needs to listen for a fixed period of 5 ms. If after this period the
channel is free, transmission may immediately commence (i.e. no CSMA is required).
Otherwise, a new listening period of a randomly selected time span between 5 and 10
ms is required. The time resolution shall be approximately 0.5 ms. The last step needs
to be repeated until a free channel is available.
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LBT Threshold
According to ETSI EN 300 220-1-V2.1.1, the maximum LBT threshold for an IEEE
802.15.4 signal is presumably -82 dBm, assuming a channel spacing of 1 MHz.
6.7.2 LBT Mode
The AT86RF212 supports the previously described LBT specific listening mode when
operating in the Extended Operating Mode.
In particular, during TX_ARET (see section 5.2.4), the CSMA-CA algorithm can be
replaced by the LBT listening mode, when setting register bit CSMA_LBT_MODE
(register 0x17, XAH_CTRL_1). In this case, however, the register bits
MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0) as well as MIN_BE and
MAX_BE (register 0x2F, CSMA_BE) are ignored, implying that the listening mode will
sustain, unless a clear channel has been found or the TX_ARET transaction will be
canceled. The latter can be achieved by setting TRX_CMD to either FORCE_PLL_ON
or FORCE_TRX_OFF (register 0x02, TRX_STATE). All other aspects of TX_ARET
remain unchanged; refer to section 5.2.4.
The LBT threshold can be configured in the same way as for CCA, i. e. via register bits
CCA_MODE (register 0x08, PHY_CCA) and register bits CCA_ED_THRES (register
0x09, CCA_ED_THRES), refer to section 6.6.
6.7.3 Register Description
Register 0x08 (PHY_CC_CCA):
This register is relevant for the measurement mode when using LBT, i.e. selecting
Energy above threshold or Carrier sense (CS) or combination of both.
Table 6-37. Register 0x08 (PHY_CC_CCA)
Bit
7
6
5
4
Name
CCA_REQUEST
CCA_MODE
CCA_MODE
CHANNEL
Read/Write
W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
CHANNEL
CHANNEL
CHANNEL
CHANNEL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
1
• Bit 7 – CCA_REQUEST
Not applicable for LBT, see section 6.6.6.
• Bit 6:5 – CCA_MODE
The CCA mode can be used in order to select the appropriate LBT measurement mode
by using register bits CCA_MODE, refer to section 6.6.
• Bit 4:0 – CHANNEL
Refer to section 7.8.
Register 0x09 (CCA_THRES):
This register is relevant for the ED threshold when using LBT.
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Table 6-38. Register 0x09 (CCA_THRES)
Bit
7
6
5
4
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
1
1
0
0
Bit
3
2
1
0
Name
CCA_ED_THRES
CCA_ED_THRES
CCA_ED_THRES
CCA_ED_THRES
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
1
1
• Bit 7:5 – Reserved
• Bit 4:0 – CCA_ED_THRES
For CCA_MODE = 1, a busy channel is indicated if the measured received power is
above (RSSI_BASE_VAL + 2 • CCA_ED_THRES) [dBm]. CCA_MODE = 0 and 3 are
logically related to this result.
Register 0x17 (XAH_CTRL_1):
This register is relevant for enabling or disabling the LBT mode.
Table 6-39. Register 0x17 (XAH_CTRL_1)
Bit
7
6
5
4
Name
Reserved
CSMA_LBT_MODE
AACK_FLTR_RES_FT
AACK_UPLD_RES_FT
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
Reserved
AACK_ACK_TIME
AACK_PROM_MODE
Reserved
Read/Write
R
R/W
R/W
R
Reset Value
0
0
0
0
• Bit 7 – Reserved
• Bit 6 – CSMA_LBT_MODE
If set to 0 (default), CSMA-CA algorithm is used during TX_ARET for clear channel
assessment. Otherwise, the LBT specific listening mode is applied.
• Bit 5 – AACK_FLTR_RES_FT
Refer to section 5.2.6.
• Bit 4 – AACK_UPLD_RES_FT
Refer to section 5.2.6.
• Bit 3 – Reserved
• Bit 2 – AACK_ACK_TIME
Refer to section 5.2.6.
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• Bit 1 – AACK_PROM_MODE
Refer to section 5.2.6.
• Bit 0 – Reserved
6.8 Link Quality Indication (LQI)
6.8.1 Requirements
The IEEE 802.15.4 standard defines the LQI as a characterization of the strength
and/or quality of a received frame. The use of the LQI result by the network or
application layer is not specified in this standard. The LQI value shall be an integer
ranging from 0 to 255, with at least 8 unique values. The minimum and maximum LQI
values (0 and 255) should be associated with the lowest and highest quality compliant
signals, respectively, and LQI values in between should be uniformly distributed
between these two limits.
6.8.2 Implementation
During symbol detection within frame reception, the AT86RF212 uses correlation
results of multiple symbols in order to compute an estimate of the LQI value. This is
motivated by the fact, that the mean value of the correlation result is inversely related to
the probability of a detection error.
LQI computation is automatically performed for each received frame, once the SHR has
been detected. LQI values are integers ranging from 0 to 255 as required by the IEEE
802.15.4 standard.
6.8.3 Obtaining the LQI Value
The LQI value is available, once the corresponding frame has been completely
received. This is indicated by the interrupt IRQ_3 (TRX_END). The value can be
obtained by means of a frame buffer read access, see section 4.3.2.
6.8.4 Remarks
The reason for a low LQI value can be twofold: a low signal strength and/or high signal
distortions, e.g. by interference and/or multipath propagation. High LQI values,
however, indicate a sufficient signal strength and low signal distortions.
Note that the LQI value is almost always 255 for scenarios with very low signal
distortions and a signal strength much greater than the sensitivity level. In this case, the
packet error rate tends towards zero and increase of the signal strength, i.e. by
increasing the transmission power, cannot decrease the error rate any further.
Received signal strength indication (RSSI) or energy detection (ED) can be used to
evaluate the signal strength and the link margin.
ZigBee networks often require identification of the “best” routing between two nodes.
LQI and RSSI/ED can be applied, depending on the optimization criteria. If a low frame
error rate (corresponding to a high throughput) is the optimization criteria, then the LQI
value should be taken into consideration. If, however, the target is a low transmission
power, then the RSSI/ED value is also helpful.
Various combinations of LQI and RSSI/ED are possible for routing decisions. As a rule
of thumb, information on RSSI/ED is useful in order to differentiate between links with
high LQI values. However, transmission links with low LQI values should be discarded
for routing decisions even if the RSSI/ED values are high, since it is merely an
information about the received signal strength whereas the source can be an interferer.
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7 Module Description
7.1 Physical Layer Modes
7.1.1 Spreading, Modulation and Pulse Shaping
The AT86RF212 supports various physical layer (PHY) modes independent of the RF
channel selection. Symbol mapping along with chip spreading, modulation and pulse
shaping is part of the digital base band processor, see Figure 7-1.
Figure 7-1. Base Band Transmitter Architecture
PPDU
Symbol Mapping
&
Chip Spreading
Modulation
BPSK/O-QPSK
Pulse Shaping
DAC
The combination of spreading, modulation and pulse shaping are restricted to several
combinations as shown in Table 7-1.
The AT86RF212 is fully compliant to the IEEE 802.15.4 low data rate modes of 20
kbit/s or 40 kbit/s, employing binary phase-shift keying (BPSK) and spreading with a
fixed chip rate of 300 kchip/s or 600 kchip/s, respectively. The symbol rate is 20
ksymbol/s or 40 ksymbol/s, respectively. In both cases, pulse shaping is approximating
a raised cosine filter with roll-off factor 1.0 (RC-1.0).
For optional data rates according to IEEE 802.15.4-2006, offset quadrature phase-shift
keying (O-QPSK) is supported by the AT86RF212 with a fixed chip rate of either 400
kchip/s or 1000 kchip/s.
At a chip rate of 400 kchip/s, pulse shaping is always a combination of both, half-sine
shaping (SIN) and raised cosine filtering with roll-off factor 0.2 (RC-0.2), according to
IEEE 802.15.4-2006 for the 868.3 MHz band. At a chip rate of 1000 kchip/s, pulse
shaping is either half-sine filtering (SIN) as specified in IEEE 802.15.4-2006, or,
alternatively, raised cosine filtering with roll-off factor 0.8 (RC-0.8).
For O-QPSK, the AT86RF212 supports spreading according to IEEE 802.15.4-2006
with data rates of either 100 kbit/s or 250 kbit/s depending on the chip rate, leading to a
symbol rate of either 25 ksymbol/s or 62.5 ksymbol/s, respectively.
Additionally, the AT86RF212 supports two more spreading codes for O-QPSK with
shortened code lengths. This leads to higher but non IEEE 802.15.4-2006 compliant
data rates during the PSDU part of the frame with 200, 400, 500, and 1000 kbit/s. The
proprietary High Data Rate Modes are outlined in more detail in section 7.1.4.
Table 7-1. Modulation and Pulse Shaping
Modulation
Chip Rate
[kchip/s]
Supported Data
Rate for PPDU
Header [kbit/s]
Supported Data
Rates for PSDU
[kbit/s]
Pulse Shaping
BPSK
300
20
20
RC-1.0
600
40
40
RC-1.0
400
100
100/200/400
SIN and RC-0.2
1000
250
250/500/1000
SIN or RC-0.8
O-QPSK
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7.1.2 Configuration
The PHY mode can be selected by setting appropriate register bits of register 0x0C
(TRX_CTRL_2), refer to section 7.1.5. During configuration, the transceiver needs to
be in state TRX_OFF.
7.1.3 Symbol Period
Within IEEE 802.15.4 and, accordingly, within this document, time references are often
specified in units of symbol periods, leading to a PHY mode independent description.
Table 7-2 shows the duration of the symbol period. Note that for the proprietary High
Data Rate Modes, the symbol period is (by definition) the same as the symbol period of
the corresponding base mode.
Table 7-2. Duration of the Symbol Period
Modulation
PSDU Data Rate [kbit/s]
Duration of Symbol Period
[µs]
BPSK
20
50
40
25
O-QPSK
100, 200, 400
40
250, 500, 1000
16
7.1.4 Proprietary High Data Rate Modes
The main features are:
• High Data Rates up to 1000 kbit/s
• Support of Basic and Extended Operating Mode
7.1.4.1 Overview
The AT86RF212 supports alternative data rates higher than 250 kbit/s for applications
not necessarily targeting IEEE 802.15.4 compliant networks.
The High Data Rate Modes utilize the same RF channel bandwidth as the
IEEE 802.15.4-2006 sub-1 GHz O-QPSK modes. Higher data rates are achieved by
modified O-QPSK spreading codes having reduced code lengths. The lengths are
reduced by the factor 2 or by the factor 4.
For O-QPSK with 400 kchip/s, this leads to a data rate of 200 kbit/s (2-fold) and 400
kbit/s (4-fold), respectively.
For O-QPSK with 1000 kchip/s, the resulting data rate is 500 kbit/s (2-fold) and 1000
kbit/s (4-fold), respectively.
Due to the decreased spreading factor, the sensitivity of the receiver is reduced.
Section 10.7, parameter 10.7.1, shows typical values of the sensitivity for different data
rates. Note that the sensitivity values of the High Data Rate Modes are provided for a
maximum PSDU length of 127 octets.
7.1.4.2 High Data Rate Frame Structure
In order to allow robust frame synchronization, high data rate modulation is restricted to
the PSDU part only. The PPDU header (the preamble, the SFD and the PHR field) are
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transmitted with the IEEE 802.15.4 O-QPSK rate of either 100 kbit/s or 250 kbit/s (basic
rates), see Figure 7-2.
Figure 7-2. High Date Rate Frame Structure
Basic Rate Transmission:
100 kbit/s
250 kbit/s
Preamble
High Rate Transmission:
{200, 400} kbit/s
{500, 1000} kbit/s
SFD
PHR
PSDU
Due to the overhead caused by the PPDU header and the FCS, the effective data rate
is less than the selected data rate, depending on the length of the PSDU. A graphical
representation of the effective data rate is shown in Figure 7-3.
Figure 7-3. Effective Data Rate of the O-QPSK Modes
Netto bit rate B
900
1000 kbit/s
800
700
B [kbit/s]
600
500 kbit/s
500
400 kbit/s
250 kbit/s
400
200 kbit/s
300
100 kbit/s
200
100
0
0
20
40
60
80
PSDU length in octets
100
120
Consequently, high data rate transmission is useful for large PSDU lengths due to the
higher effective data rate, or in order to reduce the power consumption of the system.
7.1.4.3 High Date Rate Mode Options
Reduced Acknowledgment Time
If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, the
acknowledgment time is reduced to the duration of 2 symbol periods for 200 and 400
kbit/s, and to 3 symbol periods for 500 and 1000 kbit/s, refer to Table 5-24. Otherwise, it
defaults to 12 symbol periods according to IEEE 802.15.4.
Receiver Sensitivity Control
The different data rates between PPDU header (SHR and PHR) and PHY payload
(PSDU) cause a different sensitivity between header and payload. This can be adjusted
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by defining sensitivity threshold levels of the receiver. With a sensitivity threshold level
set, the AT86RF212 does not synchronize to frames with an RSSI level below that
threshold. Refer to section 7.2.3 for a configuration of the sensitivity threshold with
register 0x15 (RX_SYN).
Scrambler
For data rates 1000 kbit/s and 400 kbit/s, additional chip scrambling is applied per
default, in order to mitigate data dependent spectral properties. Scrambling can be
disabled if bit OQPSK_SCRAM_EN (register 0x0C, TRX_CTRL_2) is set to 0.
Energy Detection
The ED measurement time span is 8 symbol periods according to IEEE 802.15.4, see
section 7.1.3. For frames operated at a higher data rate, the ED measurement period is
reduced to 2 symbol periods taking reduced frame durations into account. This means,
the ED measurement time is 80 µs for modes 200 kbit/s and 400 kbit/s, and 32 µs for
modes 500 kbit/s and 1000 kbit/s.
Carrier Sense
For clear channel assessment, IEEE 802.15.4-2006 specifies several modes which may
either apply Energy above threshold or Carrier sense (CS) or a combination of both.
Since signals of the High Data Rate Modes are not compliant to IEEE802.15.4-2006,
CS is not supported, when the AT86RF212 is operating in these modes. However,
“Energy above threshold” is supported.
Link Quality Indicator (LQI)
For the High Data Rate Modes, the link quality value does not contain useful
information and should be discarded.
7.1.5 Register Description
Register 0x0C (TRX_CTRL_2):
The TRX_CTRL_2 register controls the PHY mode settings. Note that during
configuration, the transceiver needs to be in state TRX_OFF.
Table 7-3. Register 0x0C (TRX_CTRL_2)
Bit
7
6
5
4
Name
RX_SAFE_MODE
TRX_OFF_AVDD_EN
OQPSK_SCRAM_EN
OQPSK_SUB1_RC_EN
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
BPSK_OQPSK
SUB_MODE
OQPSK_DATA_RATE
OQPSK_DATA_RATE
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
0
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• Bit 7 – RX_SAFE_MODE
Refer to section 9.7.2.
• Bit 6 – TXR_OFF_AVDD_EN
Refer to section 5.1.4.3.
• Bit 5 – OQPSK_SCRAM_EN
If set to 1 (reset value), the scrambler is enabled for OQPSK_DATA_RATE = 2 and
BPSK_OQPSK = 1 (O-QPSK is active). Otherwise, the scrambler is disabled.
Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly
required to align different transceivers with OQPSK_SCRAM_EN in order to assure
interoperability.
• Bit 4 – OQPSK_SUB1_RC_EN
The bit is only relevant for SUB_MODE = 1 and BPSK_OQPSK = 1.
If set to 0 (reset value), pulse shaping is half-sine filtering for O-QPSK transmission.
If set to 1, pulse shaping is RC-0.8 filtering for O-QPSK transmission. Compared with
half-sine filtering, side-lobes are reduced at the expense of an increased peak to
average ratio (~ 1 dB).
Note that during reception, this bit is not evaluated within the AT86RF212, so it is not
explicitly required to align different transceivers with OQPSK_SUB1_RC_EN in order to
assure interoperability. It is very likely, that this also holds for any 915 MHz IEEE
802.15.4-2006 compliant O-QPSK transceiver, since the IEEE Std 802.15.4-2006
requirements are fulfilled for both types of shaping.
• Bit 3 – BPSK_OQPSK
If set to 0 (reset value), BPSK transmission and reception is applied.
If set to 1, O-QPSK transmission and reception is applied.
Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly
required to align different transceivers with BPSK_OQPSK in order to assure
interoperability.
• Bit 2 – SUB_MODE
If set to 1 (reset value), the chip rate is 1000 kchip/s for BPSK_OQPSK = 1 and 600
kchip/s for BPSK_OQPSK = 0. It permits data rates out of {250, 500, 1000} kbit/s, or 40
kbit/s, respectively. This mode is particularly suitable for the 915 MHz band. For OQPSK transmission, pulse shaping is either half-sine shaping or RC-0.8 shaping,
depending on OQPSK_SUB1_RC_EN.
If set to 0, the chip rate is 400 kchip/s for BPSK_OQPSK = 1 and 300 kchip/s for
BPSK_OQPSK = 0. It permits data rates out of {100, 200, 400} kbit/s, or 20 kbit/s,
respectively. This mode is particularly suitable for the 868.3 MHz band. For O-QPSK
transmission, pulse shaping is always the combination of half-sine shaping and RC-0.2
shaping.
Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly
required to align different transceivers with SUB_MODE in order to assure
interoperability.
• Bit 1:0 – OQPSK_DATA_RATE
These register bits control the O-QPSK data rate during the PSDU part of the frame, as
depicted by Table 7-4. The reset value is OQPSK_DATA_RATE = 0.
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Note that during reception, these bits are evaluated within the AT86RF212, so it is
explicitly required to align different transceivers with OQPSK_DATA_RATE in order to
assure interoperability.
Table 7-4. O-QPSK Data Rate during PSDU
Register Bits
Value
OQPSK_DATA_RATE
O-QPSK Data Rate
[kbit/s]
SUB_MODE = 0
O-QPSK Data Rate
[kbit/s]
SUB_MODE = 1
0
100
250
1
200
500
2, 3
400
1000
In Table 7-5, all PHY modes supported by the AT86RF212 are summarized with the
relevant setting for each bit of register TRX_CTRL_2. The character ‘-‘ means, the bit
entry is not relevant for the particular PHY mode.
Table 7-5. Register 0x0C (TRX_CTRL_2) Bit Alignment
PHY Mode
Register 0x0C, Bit
Comment
7
6
5
4
3
2
1
0
BPSK-20
-
-
-
-
0
0
-
-
IEEE 802.15.4
BPSK-40
-
-
-
-
0
1
-
-
IEEE 802.15.4
OQPSK-SIN-RC-100
-
-
-
-
1
0
0
0
IEEE 802.15.4-2006
OQPSK-SIN-RC-200
-
-
-
-
1
0
0
1
proprietary
OQPSK-SIN-RC-400-SCR-ON
-
-
1
-
1
0
1
-
proprietary, scrambler on
OQPSK-SIN-RC-400-SCR-OFF
-
-
0
-
1
0
1
-
proprietary, scrambler off
OQPSK-SIN-250
-
-
-
0
1
1
0
0
IEEE 802.15.4-2006
OQPSK-SIN-500
-
-
-
0
1
1
0
1
proprietary
OQPSK-SIN-1000-SCR-ON
-
-
1
0
1
1
1
-
proprietary, scrambler on
OQPSK-SIN-1000-SCR-OFF
-
-
0
0
1
1
1
-
proprietary, scrambler off
OQPSK-RC-250
-
-
-
1
1
1
0
0
IEEE 802.15.4-2006
OQPSK-RC-500
-
-
-
1
1
1
0
1
proprietary
OQPSK-RC-1000-SCR-ON
-
-
1
1
1
1
1
-
proprietary, scrambler on
OQPSK-RC-1000-SCR-OFF
-
-
0
1
1
1
1
-
proprietary, scrambler off
Note:
(1)
1. not strictly compliant to IEEE 802.15.4-2006 but most likely being interoperable
7.2 Receiver (RX)
7.2.1 Overview
The AT86RF212 transceiver is split into an analog radio front-end and a digital domain,
see Figure 1-1.
Referring to the receiver part of the analog section, the differential RF signal is amplified
by a low noise amplifier (LNA) and split into quadrature signals by a poly-phase filter
(PPF). Two mixer circuits convert the quadrature signal down to an intermediate
frequency. Channel selectivity is achieved by an integrated band-pass filter (BPF). The
subsequent analog-to-digital converter (ADC) samples the receive signal and
additionally generates a digital RSSI signal, see section 6.4. The ADC output is then
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further processed by the digital baseband receiver (RX BBP) which is part of the digital
domain.
The BBP performs further filtering and signal processing. In RX_ON state the receiver
searches for the synchronization header. Once the synchronization is established and
the SFD is found the received signal is demodulated and provided to the Frame Buffer.
The receiver performs a state change indicated by register bits TRX_STATUS (register
0x01, TRX_STATUS) to BUSY_RX. Once the whole frame is received, the receiver
switches back to RX_ON to listen on the channel. A similar scheme applies to the
Extended Operating Mode.
The receiver is designed to handle frequency and symbol rate errors up to ±60 ppm,
refer to section 10.5, parameter 549H10.5.7.
Several status information are generated during the receive process: LQI, ED, and
RX_STATUS. They are automatically appended during Frame Read Access, refer to
section 4.3.2. Some information is also available through register access, e.g. ED value
(register 0x07, PHY_ED_LEVEL) and FCS correctness (register 0x06, PHY_RSSI).
The Extended Operating Mode of the AT86RF212 supports frame filtering and pending
data indication.
The frame receive procedure including the radio transceiver setup for reception and
reading PSDU data from the Frame Buffer is described in section 8.1.
7.2.2 Configuration
In Basic Operating Mode, the receiver is enabled by writing command RX_ON to
register bits TRX_CMD (register 0x02, TRX_STATE) in states TRX_OFF or PLL_ON. In
Extended Operating Mode, the receiver is enabled for RX_AACK operation from state
PLL_ON by writing the command RX_AACK_ON.
There is no additional configuration required to receive IEEE 802.15.4 compliant frames
when using the Basic Operating Mode. However, the frame reception in the Extended
Operating Mode requires further register configurations. For details refer to section
5.2.2.
For specific applications the receiver can be configured to handle critical environments,
to simplify the interaction with the microcontroller or to operate different data rates.
The AT86RF212 receiver has an outstanding sensitivity performance. At certain
conditions (interference floor, High Data Rate Modes, refer to section 7.1.4), it may be
useful to manually decrease this sensitivity. This is achieved by adjusting the
synchronization header detector threshold using register bits RX_PDT_LEVEL (register
0x15, RX_SYN). Received signals with a RSSI value below the threshold do not
activate the demodulation process.
Furthermore, it may be useful to protect a received frame against overwriting by
subsequent received frames. A Dynamic Frame Buffer Protection is enabled with
register bit RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) set, see section 9.7. The
receiver remains in RX_ON or RX_AACK_ON state until the whole frame is uploaded
by the microcontroller, indicated by /SEL = H during the SPI Frame Receive Mode. The
Frame Buffer content is only protected if the FCS is valid.
A Static Frame Buffer Protection is enabled with register bit RX_PDT_DIS (register
0x15, RX_SYN) set. The receiver remains in RX_ON or RX_AACK_ON state and no
further SHR is detected until the register bit RX_PDT_DIS is set back.
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7.2.3 Register Description
Table 7-6. Register 0x19 (RF_CTRL_1)
Bit
7
6
5
4
Name
RF_MC
RF_MC
RF_MC
RF_MC
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7:4 – RF_MC
These register bits provide the matching control of the differential RF pins (RFN, RFP)
by switching capacitances to ground, see Figure 2-2. Each step increases the
capacitance by 36 fF at each pin. The capacitance setting at the RF pins is valid for
both RX and TX operation.
Table 7-7. RF Pin Matching Control
Register Bits
Value
Capacitance at RF Pins [fF]
0
0
1
36
2
72
3
108
RF_MC
…
15
540
• Bit 3:0 – Reserved
Register 0x15 (RX_SYN):
This register controls the sensitivity threshold of the receiver.
Table 7-8. Register 0x15 (RX_SYN)
Bit
7
6
5
4
Name
RX_PDT_DIS
Reserved
Reserved
Reserved
Read/Write
R/W
R
R
R
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
RX_PDT_LEVEL
RX_PDT_LEVEL
RX_PDT_LEVEL
RX_PDT_LEVEL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – RX_PDT_DIS
RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in
receive mode. An ongoing frame reception is not affected.
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• Bit 6:4 – Reserved
• Bit 3:0 – RX_ PDT_LEVEL
With these register bits, the receiver can be desensitized such that frames with an RSSI
level below the threshold level (if RX_PDT_LEVEL > 0) are not received. The threshold
level can be calculated according to the following formula:
RX_THRES = RSSI_BASE_VAL + RX_PDT_LEVEL * 3, for RX_PDT_LEVEL > 0
The RSSI_BASE_VALUE is described in section 6.4.3.
If register bits RX_PDT_LEVEL = 0 (reset value), this feature is disabled which
corresponds to the highest sensitivity.
7.3 Transmitter (TX)
7.3.1 Overview
The AT86RF212 transmitter utilizes a direct up-conversion topology. The digital
transmitter (TX BBP) generates the in-phase (I) and quadrature (Q) component of the
modulation signal. A digital-to-analog converter (DAC) forms the analog modulation
signal. A quadrature mixer pair converts the analog modulation signal to the RF
domain. The power amplifier (PA) provides signal power delivered to the differential
antenna pins (RFP, RFN). Both, the LNA the PA are internally connected to the
bidirectional differential antenna pins so that no external antenna switch is needed.
Using the default settings, the PA incorporates an equalizer to improve its linearity. The
enhanced linearity keeps the spectral side lobes of the transmit spectrum low in order to
meet the requirements of the European 868.3 MHz band.
If the PA boost mode is turned on, the equalizer is disabled. This allows to deliver a
higher transmit power of up to 10 dBm at the cost of higher spectral side lobes and
higher harmonic power.
In Basic Operating Mode a transmission is started from PLL_ON state by either writing
TX_START to register bits TRX_CMD (register 0x02, TRX_STATE) or by a rising edge
of SLP_TR.
In Extended Operating Modes, a transmission might be started automatically depending
on the transaction phase of either RX_AACK or TX_ARET, refer to section 5.2.
7.3.2 Frame Transmit Procedure
The frame transmit procedure including writing PSDU data into the Frame Buffer and
initiating a transmission is described in section 8.2.
7.3.3 Spectrum Masks
The AT86RF212 can be operated in different frequency bands, using different power
levels, modulation schemes, chip rates, and pulse shaping filters. The occupied
bandwidth of transmit signals depends on the chosen mode of operation, refer to Table
7-9. Knowledge of modulation bandwidth, power spectrum, and side lobes is essential
for proper system setup, i.e. non-overlapping channel spacing.
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Table 7-9. Modulation, Pulse Shaping, and Occupied Bandwidth
Modulation
Chip Rate
[kchip/s]
Pulse Shaping
99% Occupied
Bandwidth
[kHz]
20 dB
Bandwidth
[kHz]
BPSK
300
RC-1.0
385
430
600
RC-1.0
750
825
400
SIN and RC-0.2
370
400
1000
SIN
1210
1230
RC-0.8
1210
1300
O-QPSK
Figure 7-4 to Figure 7-8 show power spectra for different parameter combinations listed
in Table 7-9. Note that not all combinations are compliant with IEEE 802.15.4-2006.
The spectra were captured using default settings of AT86RF212. The resolution
bandwidth of the spectrum analyzer was set to 30 kHz. The video bandwidth was set to
10 kHz.
Figure 7-4. Spectrum of BPSK with Chip Rate of 300 kchip/s
0
-10
Power [dBm]
-20
-30
-40
-50
-60
-70
912
913
914
915
916
Frequency [MHz]
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Figure 7-5. Spectrum of BPSK with Chip Rate of 600 kchip/s
0
-10
Power [dBm]
-20
-30
-40
-50
-60
-70
912
913
914
915
916
Frequency [MHz]
Figure 7-6. Spectrum of O-QPSK with Chip Rate of 400 kchip/s
0
-10
Power [dBm]
-20
-30
-40
-50
-60
-70
912
913
914
915
916
Frequency [MHz]
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AT86RF212
Figure 7-7. Spectrum of O-QPSK with Chip Rate of 1000 kchip/s and Sinewave Pulse
Shaping
0
-10
Power [dBm]
-20
-30
-40
-50
-60
-70
910
912
914
916
918
Frequency [MHz]
Figure 7-8. Spectrum of O-QPSK with Chip Rate of 1000 kchip/s and Raised Cosine
Pulse Shaping
0
-10
Power [dBm]
-20
-30
-40
-50
-60
-70
910
912
914
916
918
Frequency [MHz]
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Figure 7-4 to Figure 7-8 illustrate typical spectra of the transmitted signals of the
AT86RF212 and do not claim any limits.
Refer to the local authority bodies (FCC, ETSI etc.) for further details about definition of
power spectral density masks, definition of spurious emission, allowed modulation
bandwidth, transmit power, and its limits.
7.3.4 TX Output Power
The maximum output power of the transmitter is typically 5 dBm in normal mode and 10
dBm in boost mode. The TX output power can be set via register bits TX_PWR (register
0x05, PHY_TX_PWR). The output power of the transmitter can be controlled down to 11 dBm dB with 1 dB resolution.
To meet the spectral requirements of the European 868.3 MHz band it is necessary to
limit the TX power by appropriate setting of TX_PWR, GC_PA (register 0x05,
PHY_TX_PWR) and GC_TX_OFFS (register 0x16, TX_CTRL_0), see Table 7-15 and
Table 7-16.
7.3.5 TX Power Ramping
To optimize the output power spectral density (PSD), individual transmitter blocks are
enabled sequentially. A transmit action is started by either the rising edge of pin
SLP_TR or the command TX_START in register 0x02. One symbol period later the data
transmission begins. During this time period, the PLL settles to the frequency used for
transmission. The PA is enabled prior to the data transmission start. This PA lead time
can be adjusted with the value PA_LT in register 0x16 (RF_CTRL_0).The PA is always
enabled at the lowest gain value corresponding to GC_PA=0. Then the PA gain is
increased automatically to the value set by GC_PA in register 0x16 (RF_CTRL_0). After
transmission is completed, TX power ramping down is performed in an inverse order.
The control signals associated with TX power ramping are shown in Figure 7-9. In this
example, the transmission is initiated with the rising edge of pin 11 (SLP_TR). The radio
transceiver state changes from PLL_ON to BUSY_TX.
Figure 7-9. TX Power Ramping Example (O-QPSK 250 kbit/s Mode)
0
2
4
6
8
10
12
14
16
18
Length [µs]
SLP_TR
PLL_ON
State
PA
BUSY_TX
PA_LT
MODULATION
1 1 0 1 1 0 0 1 1
Using an external RF front-end (refer to section 9.4) it may be required to adjust the
startup time of the external PA relative to the internal building blocks to optimize the
overall PSD. This can be achieved using register bits PA_LT (register 0x16,
RF_CTRL_0).
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7.3.6 Register Description
Register 0x16 (RF_CTRL_0):
This register contains control signals to configure the transmit path.
Table 7-10. Register 0x16 (RF_CTRL_0)
Bit
7
6
5
4
Name
PA_LT
PA_LT
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
1
Bit
3
2
1
0
Name
Reserved
Reserved
GC_TX_OFFS
GC_TX_OFFS
Read/Write
R
R
R/W
R/W
Reset Value
0
0
0
1
• Bit 7:6 – PA_LT
These register bits control the lead time of the PA enable signal relative to the TX data
start, see Figure 7-9. This allows to enable the PA 2, 4, 6 or 8 µs before the transmit
signal starts. The PA enable signal can also be output at pin DIG3/DIG4 to provide a
control signal for an external RF front-end, for details refer to section 9.4.
Table 7-11. PA Enable Time Relative to the TX start
Register Bits
Value
PA Enable Lead Time [μs]
0
2
1
4
2
6
3
8
PA_LT
Setting GC_PA is only effective in TRX_OFF, PLL_ON and TX_ARET_ON mode.
• Bit 5:2 – Reserved
• Bit 1:0 – GC_TX_OFFS
These register bits provide an offset between the TX power control word (TX_PWR,
register 0x05, PHY_TX_PWR) and the actual TX power. This 2-bit word is added to the
TX power control word before it is applied to the circuit block which adjusts the TX
power. It can be used to compensate differences of the average TX power depending of
the modulation format.
Table 7-12. TX Power Offset
Register Bits
Value
TX Power Offset [dB]
GC_TX_OFFS
0
-1
1
0
2
+1
3
+2
Register 0x05 (PHY_TX_PWR):
This register controls the transmitter output power.
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Table 7-13. Register 0x05 (PHY_TX_PWR)
Bit
7
6
5
4
Name
PA_BOOST
GC_PA
GC_PA
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
1
0
Bit
3
2
1
0
Name
TX_PWR
TX_PWR
TX_PWR
TX_PWR
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – PA_BOOST
This bit enables the PA boost mode where the TX output power is increased by
approximately 5 dB when PA_BOOST=1. In PA boost mode the PA linearity is
decreased compared to the normal mode when PA_BOOST=0. This leads to higher
spectral side lobes of the TX power spectrum and higher power of the harmonics.
Consequently, the higher TX power settings do not fulfill the regulatory requirements of
the European 868.3 MHz band regarding spurious emissions in adjacent frequency
bands (see ETSI EN 300 220, ERC/REC 70-03, and ERC/DEC/(01)04.
• Bit 6:5 – GC_PA
These register bits control the gain of the PA by changing its bias current. GC_PA
needs to be set in TRX_OFF mode only. It can be used to reduce the supply current in
TX mode when a reduced TX power is selected with the TX_PWR control word. A
reduced PA bias current causes lower RF gain and lowers the 1 dB- compression point
of the PA. Hence, it is advisable to use a reduced bias current of the PA only in
combination with lower values of TX_PWR. A reasonable combination of TX_PWR and
GC_PA is shown in Table 7-15.
Table 7-14. AT86RF212 PA Gain Reduction Relative to the Gain at GC_PA=3
Register Bits
GC_PA
Value
PA Gain [dB]
0
-2.9
1
-1.3
2
-0.9
3
0
• Bit 4 – Reserved
• Bit 3:0 – TX_PWR
These register bits control the transmitter output power. The value of TX_PWR
describes the power reduction relative to the maximum output power. The value
GC_TX=0 provides the maximum output power. The resolution is 1 dB per step. Since
TX_PWR adjusts the gain in the TX path prior to the PA, the PA bias setting is not
optimal for increased values of TX_PWR regarding PA efficiency.
PA power efficiency can be improved when PA bias is reduced (decreased GC_PA
value) along with the TX power setting (increased TX_PWR value). A recommended
combination of TX power control (TX_PWR), PA bias control (GC_PA) and PA boost
mode (PA_BOOST) is listed in Table 7-15. It is a recommended mapping of intended
TX power to the 8-bit word in register 0x05. The value of TX_PWR shall be within the
range of 0 to 12 to guarantee the transmit signal quality.
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The North American mapping table is optimized for lowest supply current. The more
relaxed spectral side lobe requirements of the IEEE 802.15.4 standard are fulfilled.
The EU1 and EU2 mapping tables take into account that linearity is needed to keep the
out-of-band spurious emissions below the ETSI requirements.
The map EU1 takes more supply current than the North American map and uses the
normal (linearized) PA mode to provide medium output power up to -1 dBm for OQPSK
100/200/400 kbit/s mode and +2 dBm for BPSK 20 kbit/s mode.
The map EU2 uses the boost mode to provide higher TX power levels at the expense of
higher supply current. As a result, the maximum TX power is 3 dBm for OQPSK with
100/200/400 kbit/s and 5 dBm for BPSK with 20 kbit/s.
Proprietary High Data Rate Modes (refer to section 7.1.4) are more sensitive to
nonlinearities than the complementary modes with larger spreading. In addition to other
restrictions (e.g. out-of-band spurious emissions) it is recommended to limit the
maximum output power to 0 dBm for O-QPSK with 400 kbit/s and 3 dBm for O-QPSK
with 200 and 1000 kbit/s.
Table 7-15. Recommended mapping of TX power and register 0x05 value
TX Power
[dBm]
Register 0x05 hex Value
North
America
Europe
EU1
EU2
11
0xe0
0xe0
10
0xc1
0xc1
0xc1
9
0xa1
0xa1
0xa1
8
0x81
0x81
0x81
7
0x82
0x82
0x82
6
0x83
0x83
0x83
5
0x60
0x60
0xe7
4
0x61
0x61
0xe8
3
0x41
0x62
0xe9
2
0x42
0x63
1
0x22
0x64
0xab
0
0x23
0x65
0x89
-1
0x02
0x66
-2
0x03
0x46
0x46
-3
0x04
0x26
0x26
-4
0x05
0x05
0x05
-5
0x06
0x06
0x06
-6
0x07
0x07
0x07
-7
0x08
0x08
0x08
-8
0x09
0x09
0x09
-9
0x0a
0x0a
0x0a
-10
0x0b
0x0b
0x0b
-11
0x0c
0x0c
0x0c
Note 1
Note 2
Note 3
0xe0
Note 1
Note 2
Note 3
0xea
0x66
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Note 1: Power settings are not suitable for 868.3 MHz band, as defined in European
Radio Communications Committee Recommendation ERC/REC 70-03 band g1, since
spectral side lobes violate requirements defined in CEPT/ERC/REC 74-01 and decision
ERC/DEC/(01)04. Power settings can be used in some EU countries when channels
are placed in 863-870 MHz band according to the harmonized European standard ETSI
EN 300 220.
Note 2: Power settings can be used in 868.3 MHz band with BPSK 20 kbit/s mode.
Spectral side lobes remain < -40dBm.
Note 3: Power settings can be used in 868.3 MHz band with both OQPSK 100 kbit/s
mode and BPSK 20 kbit/s mode. Spectral side lobes remain < -40 dBm.
This mapping is based on a mode dependent setting of GC_TX_OFFS (register 0x16,
RF_CTRL_0), which is shown in Table 7-16.
Table 7-16. Mode-dependent setting of GC_TX_OFFS
Mode
BPSK
O-QPSK
GC_TX_OFFS
3
2
Figure 7-10. Supply Current depending on TX Power setting
28
26
Supply Current [mA]
24
22
USA
20
EU1
18
EU2
16
14
12
10
-11
-9
-7
-5
-3
-1
1
3
5
7
9
11
TX Power [dBm]
7.4 Frame Buffer
The AT86RF212 contains a 128 byte dual port SRAM. One port is connected to the SPI
interface, the other one to the internal transmitter and receiver modules. For data
communication, both ports are independent and simultaneously accessible.
The Frame Buffer utilizes the SRAM address space 0x00 to 0x7F for RX and TX
operation of the radio transceiver and can keep a single IEEE 802.15.4 RX or a single
TX frame of maximum length at a time.
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Frame Buffer access modes are described in section 4.3.2. Frame Buffer access
conflicts are indicated by an underrun interrupt IRQ_6 (TRX_UR). Note that this
interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame
Buffer (overflow). In this case, the content of the Frame Buffer is undefined.
Frame Buffer access is only possible if the digital voltage regulator is turned on. This is
valid in all device states except in SLEEP state. An access in P_ON state is possible
once pin 17 (CLKM) provides the 1 MHz master clock.
7.4.1 Data Management
Data in Frame Buffer (received data or data to be transmitted) can be changed by:
•
•
•
•
Frame Buffer or SRAM write access over SPI
Receiving a new frame in BUSY_RX or BUSY_RX_AACK state
A change into SLEEP state
A RESET
By default, there is no protection of the Frame Buffer against overwriting. Therefore, if a
frame is received during Frame Buffer read access of a previously received frame,
interrupt IRQ_6 (TRX_UR) is issued and the stored data might be overwritten.
Even so, the old frame data can be read, if the SPI data rate is higher than the effective
over air data rate. For a data rate of 250 kbit/s a minimum SPI clock rate of 1 MHz is
recommended. Finally the microcontroller should check the transferred frame data
integrity by an FCS check.
To protect the Frame Buffer content against being overwritten by newly incoming
frames the radio transceiver state should be changed to PLL_ON state after reception.
This can be achieved by writing the command PLL_ON to register bits TRX_CMD
(register 0x02, TRX_STATE) while or immediately after receiving the frame.
Alternatively, Dynamic Frame Buffer Protection can be used to protect received frames
against overwriting, for details refer to section 9.7.
Both procedures do not protect the Frame Buffer from overwriting by the
microcontroller.
In Extended Operating Mode during TX_ARET operation, see 5.2.4, the radio
transceiver switches to receive state, if an acknowledgement of a previously transmitted
frame was requested. During this period, received frames are evaluated but not stored
in the Frame Buffer. This allows the radio transceiver to wait for an acknowledgement
frame and retry the frame transmission without writing the frame again.
A radio transceiver state change, except a transition to SLEEP state or a reset, does
not affect the Frame Buffer content. If the radio transceiver is taken into SLEEP, the
Frame Buffer is powered off and the stored data get lost.
7.4.2 Frame Content
The AT86RF212 supports an IEEE 802.15.4 compliant frame format as shown in Figure
7-11.
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Figure 7-11. AT86RF212 Frame Structure
0
Frame
Duration
Access
Length [octets]
4
5
Preamble Sequence
SFD
4 octets
1
SHR not accesible
Note:
n+3
PHR
Payload
n+5
FCS
n+6
LQI
n octets (n <= 128)
SFD_VALUE
PHY generated
6
n+7
ED
n+8
RX_STATUS
3 octets
Frame Buffer content /
Frame Write Access(1)
Frame Read Access
1. Writing FCS can
TXR_CTRL_1).
be
omitted,
if
TX_AUTO_CRC_ON=1
(register
0x04,
A frame comprises two sections, the radio transceiver internally generated SHR field
and the user accessible part stored in the Frame Buffer. The SHR contains the
preamble and the SFD field. The variable frame section contains the PHR and the
PSDU including the FCS, see section 6.3.
To access the data follow the procedures described in section 4.3.2.
The frame length information (PHR field) and the PSDU are stored in the Frame Buffer.
During frame reception, the link quality indicator (LQI) value, the energy detection (ED)
value, and the status information (RX_STATUS) of a received frame are additionally
stored, see sections 6.8, 6.5, and 4.3.2, respectively. The radio transceiver appends
these values to the frame data during Frame Buffer read access.
If the SRAM read access is used to read an RX frame, the frame length field (PHR) can
be accessed at address 0. The SHR (except the SFD value used to generate the SHR)
cannot be read by the microcontroller.
For frame transmission, the PHR and the PSDU need to be stored in the Frame Buffer.
The maximum Frame Buffer size supported by the radio transceiver is 128 bytes. If the
TX_AUTO_CRC_ON bit is set in register 0x05 (PHY_TX_PWR), the FCS field of the
PSDU is replaced by the automatically calculated FCS during frame transmission.
There is no need to write the FCS field when using the automatic FCS generation.
To manipulate individual bytes of the Frame Buffer a SRAM write access can be used
instead.
For non IEEE 802.15.4 compliant frames, the minimum frame length supported by the
radio transceiver is one byte (Frame Length Field + 1 byte of data).
7.4.3 Interrupt Handling
Access conflicts may occur when reading and writing data simultaneously at the
independent ports of the Frame Buffer, TX/RX BBP and SPI. These ports have their
own address counter that points to the Frame Buffer’s current address.
Access violations occurs during concurrent Frame Buffer read or write accesses, when
the SPI port’s address counter value becomes greater than or equal to that of TX/RX
BBP port.
While receiving a frame, first the data need to be stored in the Frame Buffer before
reading it. This can be ensured by accessing the Frame Buffer at least 8 symbols
(BPSK) or 2 symbols (O-QPSK) after interrupt IRQ_2 (RX_START). When reading the
frame data continuously, the SPI data rate shall be lower than the current TRX bit rate
to ensure no underrun interrupt occurs. To avoid access conflicts and to simplify the
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Frame Buffer read access, Frame Buffer Empty indication may be used, for details refer
to section 9.6.
During transmission, an access violation occurs on Frame Buffer write access, when
the SPI port’s address counter value becomes less than or equal to that of TX BBP
port.
Both access violations may cause data corruption and are indicated by IRQ_6
(TRX_UR) interrupt when using the Frame Buffer access mode. Note that access
violations are not indicated when using the SRAM access mode.
When writing data to the Frame Buffer during frame transmission, the SPI data rate
shall be higher than the PHY data rate avoiding underrun. The first byte of the PSDU
data must be available in the Frame Buffer before SFD transmission is complete, which
takes 41 symbol periods for BPSK (1 symbol PA ramp up + 40 symbols SHR) and 11
symbol periods for O-QPSK (1 symbol PA ramp up + 10 symbols SHR) from the rising
edge of SLP_TR pin (see Figure 5-2).
Notes
• Interrupt IRQ_6 (TRX_UR) is valid 1 octet after IRQ_2 (RX_START). The occurrence
of the interrupt shall be ignored when reading the first byte of the Frame Buffer
between the first and second octet after the RX_START interrupt.
• If a Frame Buffer read access is not finished until a new frame is received, a
TRX_UR interrupt occurs. Nevertheless, the old frame data can be read if the SPI
data rate is higher than the effective PHY data rate. A minimum SPI clock rate of
1 MHz is recommended in this case. Finally, the microcontroller should check the
integrity of the transferred frame data by calculating the FCS.
7.5 Voltage Regulators (AVREG, DVREG)
The main features of the Voltage Regulator blocks are:
• Bandgap stabilized 1.8 V supply for analog and digital domain
• Low dropout (LDO) voltage regulator
• Configurable for usage of external voltage regulator
7.5.1 Overview
The internal voltage regulators supply a stabilized voltage to the AT86RF212. The
AVREG provides the regulated 1.8 V supply voltage for the analog section and the
DVREG supplies the 1.8 V supply voltage for the digital section.
A simplified schematic of the internal analog voltage regulator is shown in Figure 7-12.
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Figure 7-12. Simplified Schematic of AVREG
EVDD
Bandgap
voltage
reference
1.25V
AVDD
A simplified schematic of the internal digital voltage regulator is shown in Figure 7-13.
Figure 7-13. Simplified Schematic of DVREG
DEVDD
Bandgap
voltage
reference
1.25V
BIAS
DVDD
Low power voltage regulator
Voltage regulator
Digital voltage regulator
The block “Low power voltage regulator” within the “Digital voltage regulator” maintains
the DVDD supply voltage when the voltage regulator is disabled, which is the case
during sleep mode (refer to Figure 7-13). The DVDD voltage drops down to 1.5 V
(typical) if the AT86RF212 is in sleep mode, all register values are stored.
The low power voltage regulator is always enabled. Therefore its bias current
contributes to the leakage current in sleep mode of about 100 nA (typ.).
The voltage regulators (AVREG, DVREG) require bypass capacitors for stable
operation. The value of the bypass capacitors determine the settling time of the voltage
regulators. The bypass capacitors shall be placed as close as possible to the pins and
shall be connected to ground with the shortest possible traces (see Table 3-1).
7.5.2 Configuration
The voltage regulators can be configured by the register 0x10 (VREG_CTRL).
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It is recommended to use the internal regulators, but it is also possible to supply the low
voltage domains by an external voltage supply. For this configuration, the internal
regulators need to be switched off by setting the register bits to the values
AVREG_EXT = 1 and DVREG_EXT = 1. A regulated external supply voltage of 1.8 V
needs to be connected to the pins 13, 14 (DVDD) and pin 29 (AVDD). When turning on
the external supply, ensure a sufficiently long stabilization time before interacting with
the AT86RF212.
7.5.3 Data Interpretation
The status bits AVDD_OK = 1 and DVDD_OK = 1 of register 0x10 (VREG_CTRL)
indicate an enabled and stable internal supply voltage. Reading value 0 indicates a
disabled voltage regulator or the internal supply voltage is not settled to the final value.
Setting AVREG_EXT=1 and DVREG_EXT=1 forces the signals AVDD_OK and
DVDD_OK to 1.
7.5.4 Register Description
Register 0x10 (VREG_CTRL):
This register controls the use of the voltage regulators and indicates the status of these.
Table 7-17. Register 0x10 (VREG_CTRL)
Bit
7
6
5
4
Name
AVREG_EXT
AVDD_OK
Reserved
Reserved
Read/Write
R/W
R
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
DVREG_EXT
DVDD_OK
Reserved
Reserved
Read/Write
R/W
R
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – AVREG_EXT
If set this register bit disables the internal analog voltage regulator to apply an external
regulated 1.8 V supply for the analog building blocks.
Table 7-18. Regulated Voltage Supply Control for Analog Building Blocks
Register Bit
Value
Description
AVREG_EXT
0
Internal voltage regulator enabled, analog section
1
Internal voltage regulator disabled, use external
regulated 1.8 V supply voltage for the analog section
• Bit 6 – AVDD_OK
This register bit indicates if the internal 1.8 V regulated voltage supply AVDD has
settled. The bit is set to logic high, if AVREG_EXT = 1.
Table 7-19. Regulated Voltage Supply Control for Analog Building Blocks
Register Bit
AVDD_OK
Value
Description
0
Analog voltage regulator disabled or supply voltage not
stable
1
Analog supply voltage has settled
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• Bit 5:4 – Reserved
• Bit 3 – DVREG_EXT
If set this register bit disables the internal digital voltage regulator to apply an external
regulated 1.8 V supply for the digital building blocks.
Table 7-20. Regulated Voltage Supply Control for Digital Building Blocks
Register Bit
Value
Description
DVREG_EXT
0
Internal voltage regulator enabled, digital section
1
Internal voltage regulator disabled, use external
regulated 1.8 V supply voltage for the digital section
• Bit 2 – DVDD_OK
This register bit indicates if the internal 1.8 V regulated voltage supply DVDD has
settled. The bit is set to logic high, if DVREG_EXT = 1.
Table 7-21. Regulated Voltage Supply Control for Digital Building Blocks
Register Bit
Value
DVDD_OK
Description
0
Digital voltage regulator disabled or supply voltage not
stable
1
Digital supply voltage has settled
Note
• While the reset value of this bit is 0, any practical access to the register is only
possible when DVREG is active. So this bit is normally always read out as 1.
• Bit 1:0 – Reserved
Register 0x0C (TRX_CTRL_2):
This register controls the TRX behavior.
Table 7-22. Register 0x0C (TRX_CTRL_2)
Bit
7
6
5
4
Name
RX_SAFE
TRX_OFF_AVDD_EN
OQPSK_SCRAM_EN
OQPSK_SUB1_RC_EN
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
BPSK_OQPSK
SUB_MODE
OQPSK_DATA_RATE
OQPSK_DATA_RATE
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
0
• Bit 6 – TRX_OFF_AVDD_EN
If this register bit is set the analog voltage regulator is turned on during TRX_OFF,
enabling faster RX/TX turn on time. The current consumption increases by typical
100uA.
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7.6 Battery Monitor (BATMON)
The main features of the battery monitor are:
• Configurable voltage threshold range: 1.7 V to 3.675 V
• Generation of an interrupt when supply voltage drops below the threshold
• Current state can be monitored in a register bit
7.6.1 Overview
The battery monitor (BATMON) detects and indicates a low supply voltage of the
external supply voltage at pin 28 (EVDD). This is done by comparing the voltage on the
external supply pin 28 (EVDD) with a configurable internal threshold voltage. A
simplified schematic of the BATMON with the most important input and output signals is
shown in Figure 7-14.
Figure 7-14. Simplified Schematic of BATMON
EVDD
BATMON_HR
+
DAC
4
BATMON_VTH
Threshold
Voltage
For input-to-output mapping
see control register
0x11 (BATMON)
BATMON_OK
-
„1“
clear
D
Q
BATMON_IRQ
7.6.2 Configuration
The BATMON can be configured using the register 0x11 (BATMON). Register subfield
BATMON_VTH sets the threshold voltage. It is configurable with a resolution of 75 mV
in the upper voltage range (BATMON_HR = 1) and with a resolution of 50 mV in the
lower voltage range (BATMON_HR = 0), for details refer to register 0x11 (BATMON).
7.6.3 Data Interpretation
The register bit BATMON_OK of register 0x11 (BATMON) represents the current value
of the supply voltage:
• If BATMON_OK = 0, the supply voltage is lower than the threshold voltage
• If BATMON_OK = 1, the supply voltage is higher than the threshold voltage
After setting a new threshold, the value BATMON_OK should be read out to verify the
current supply voltage value.
Note, the battery monitor is inactive during P_ON and SLEEP states, see status register
0x01 (TRX_STATUS).
7.6.4 Interrupt Handling
A supply voltage drop below the configured threshold value is indicated by interrupt
IRQ_7 (BAT_LOW), see section 4.7. Note that the interrupt is issued only if
BATMON_OK changes from 1 to 0.
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No interrupt is generated when:
• The supply voltage is below the default 1.8 V threshold at power up (BATMON_OK
was never 1), or
• A new threshold is set, which is still above the current supply voltage (BATMON_OK
remains 0).
When the battery voltage is close to the programmed threshold voltage, noise or
temporary voltage drops may generate unwanted interrupts. To avoid this:
• Disable the IRQ_7 (BAT_LOW) in register 0x0E (IRQ_MASK) and treat the battery
as empty, or
• Set a lower threshold value.
7.6.5 Register Description
Register 0x11 (BATMON):
This register configures the battery monitor to compare the supply voltage EVDD at pin
28 to the threshold. Additionally, the supply voltage status at pin 28 (EVDD) can be
read from register bit BATMON_OK according to the actual BATMON settings.
Table 7-23. Register 0x11 (BATMON)
Bit
7
6
5
4
Name
Reserved
Reserved
BATMON_OK
BATMON_HR
Read/Write
R
R
R
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
BATMON_VTH
BATMON_VTH
BATMON_VTH
BATMON_VTH
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
• Bit 7:6 – Reserved
• Bit 5 – BATMON_OK
The register bit BATMON_OK indicates the level of the external supply voltage with
respect to the programmed threshold BATMON_VTH.
Table 7-24. Battery Monitor Status
Register Bit
BATMON_OK
Value
Description
0
The battery voltage is below the threshold.
1
The battery voltage is above the threshold.
• Bit 4 – BATMON_HR
The register bit BATMON_HR sets the range and resolution of the battery monitor.
Table 7-25. Battery Monitor Range Selection
Register Bit
BATMON_HR
116
Value
Description
0
Enables the low range, see BATMON_VTH
1
Enables the high range, see BATMON_VTH
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• Bit 3:0 – BATMON_VTH
The threshold values for the battery monitor are set by register bits BATMON_VTH:
Table 7-26. Battery Monitor Threshold Voltages
Value
BATMON_VTH[3:0]
Voltage [V]
BATMON_HR = 1
Voltage [V]
BATMON_HR = 0
0x0
2.550
1.70
0x1
2.625
1.75
0x2
2.700
1.80
0x3
2.775
1.85
0x4
2.850
1.90
0x5
2.925
1.95
0x6
3.000
2.00
0x7
3.075
2.05
0x8
3.150
2.10
0x9
3.225
2.15
0xA
3.300
2.20
0xB
3.375
2.25
0xC
3.450
2.30
0xD
3.525
2.35
0xE
3.600
2.40
0xF
3.675
2.45
7.7 Crystal Oscillator (XOSC) and Clock Output (CLKM)
The main features are:
•
•
•
•
16 MHz amplitude-controlled crystal oscillator
Fast settling time after leaving SLEEP state
Configurable trimming capacitance array
Configurable clock output (CLKM)
7.7.1 Overview
The crystal oscillator generates the reference frequency for the AT86RF212. All other
internally generated frequencies of the radio transceiver are derived from this
frequency. Therefore, the overall system performance is mainly determined by the
accuracy of crystal reference frequency. The external components of the crystal
oscillator should be selected carefully and the related board layout should be done with
caution (see section 3).
Two operating modes are supported. The recommended mode is the integrated
oscillator setup as described in Figure 7-15. Alternatively, a reference frequency can be
fed to the internal circuitry by using an external clock reference as shown in Figure 716. The XOSC operating modes are configurable by register 0x12 (XOSC_CTRL).
7.7.2 Integrated Oscillator Setup
Using the internal oscillator, the oscillation frequency depends on the load capacitance
between the crystal pins XTAL1 and XTAL2. The total load capacitance CL must be
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equal to the specified load capacitance of the crystal itself. It consists of the external
capacitors CX and parasitic capacitances connected to the XTAL nodes.
Figure 7-15 shows all parasitic capacitances, such as PCB stray capacitances and the
pin input capacitance, summarized to CPAR.
Figure 7-15. Simplified XOSC Schematic with External Components
CPAR
CX
CX
CPAR
VDD
XTAL1
EVDD
16MHz
XTAL2
PCB
AT86RF212
CTRIM
CTRIM
XTAL_TRIM[3:0]
XTAL_TRIM[3:0]
EVDD
Additional internal trimming capacitors CTRIM are available. Values in the range from
0 pF to 4.5 pF with a 0.3 pF resolution are selectable using the bits XTAL_TRIM of
register 0x12 (XOSC_CTRL). To calculate the total load capacitance, the following
formula can be used
CL = 0.5 • (CX + CTRIM + CPAR).
The trimming capacitors provide the possibility of reducing frequency deviations caused
by production process variations or by external components tolerances. Note that the
oscillation frequency can only be reduced by increasing the trimming capacitance. The
frequency deviation caused by one step of CTRIM decreases with increasing crystal load
capacitor values.
An amplitude control circuit is included to ensure stable operation under different
operating conditions and for different crystal types. Enabling the crystal oscillator in
P_ON state and after leaving SLEEP state causes a slightly higher current during the
amplitude build-up phase to guarantee a short start-up time. At stable operation, the
current is reduced to the amount necessary for a robust operation. This also keeps the
drive level of the crystal low.
Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling
effects caused by external component variations or by variations of board and circuit
parasitics. On the other hand, a larger crystal load capacitance results in a longer startup time and a higher steady state current consumption.
7.7.3 External Reference Frequency Setup
When using an external reference frequency, the signal must be connected to
pin 26 (XTAL1) as indicated in Figure 7-16 and the register bits XTAL_MODE (register
0x12, XOSC_CTRL) need to be set to the external oscillator mode. The oscillation
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peak-to-peak amplitude shall be 400 mV, but not larger than 500 mV. Note that the
quality of the external reference (i.e. phase noise) determines the system performance.
Figure 7-16. Setup for Using an External Frequency Reference
16 MHz
XTAL1
XTAL2
PCB
AT86RF212
7.7.4 Master Clock Signal Output (CLKM)
The generated reference clock signal can be fed into a microcontroller using
pin 17 (CLKM). The internal 16 MHz raw clock can be divided by an internal prescaler.
Thus, clock frequencies of 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 250 kHz, or the
current SHR symbol rate frequency can be supplied by pin CLKM.
The CLKM frequency and pin driver strength is configurable using register
0x03 (TRX_CTRL_0). There are two modes how a CLKM frequency change gets
effective. If CLKM_SHA_SEL = 0, changing the register bits CLKM_CTRL (register
0x03, TRX_CTRL_0) immediately affects the CLKM clock rate. Otherwise
(CLKM_SHA_SEL = 1) the new clock rate is supplied when leaving the SLEEP state
the next time.
To reduce power consumption and spurious emissions, it is recommended to turn off
the CLKM clock when not in use or to reduce its driver strength to a minimum, refer to
section 2.2.2.
CLKM reset behavior
During reset procedure, see section 5.1.4.5, register bits CLKM_CTRL are shadowed.
Although the clock setting of CLKM remains after reset, a read access to register bits
CLKM_CTRL delivers the reset value 1. For that reason it is recommended to write the
previous configuration, before reset, to register bits CLKM_CTRL, after reset, to align
the radio transceiver behavior and register configuration. Otherwise the CLKM clock
rate is set back to the reset value (1 MHz) after the next SLEEP cycle.
For example, if the CLKM clock rate is configured to 16 MHz the CLKM clock rate
remains at 16 MHz after a reset, however the register bits CLKM_CTRL are set back to
1. Since CLKM_SHA_SEL reset value is 1, the CLKM clock rate changes to 1 MHz
after the next SLEEP cycle if the CLKM_CTRL setting is not updated.
7.7.5 Register Description
Register 0x03 (TRX_CTRL_0):
Table 7-27. Register 0x03 (TRX_CTRL_0)
Bit
7
6
5
4
Name
PAD_IO
PAD_IO
PAD_IO_CLKM
PAD_IO_CLKM
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
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Bit
3
2
1
0
Name
CLKM_SHA_SEL
CLKM_CTRL
CLKM_CTRL
CLKM_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
1
0
0
1
The TRX_CTRL_0 register controls the drive current of the digital outputs and the
CLKM clock rate. It is recommended using the lowest value for the drive current to
reduce the current consumption and the emission of signal harmonics.
• Bit 7:6 – PAD_IO
Refer to section 2.2.2.3.
• Bit 5:6 – PAD_IO_CLKM
These register bits set the output driver strength of pin CLKM. It is recommended
reducing the driver strength to 2 mA (PAD_IO_CLKM = 0) if possible. This reduces
power consumption and spurious emissions.
Table 7-28. CLKM Driver Strength
Register Bits
PAD_IO_CLKM
Value
Description
0
2 mA
1
4 mA
2
6 mA
3
8 mA
• Bit 3 – CLKM_SHA_SEL
The register bit CLKM_SHA_SEL defines whether a new clock rate, defined by
CLKM_CTRL, is set immediately or gets effective after the next SLEEP cycle.
Table 7-29. CLKM Clock Rate Update Scheme
Register Bit
CLKM_SHA_SEL
Value
Description
0
CLKM clock rate change appears immediately
1
CLKM clock rate change appears after SLEEP cycle
• Bit 2:0 – CLKM_CTRL
These register bits set clock rate of pin 17 (CLKM).
Table 7-30. Clock Rate Setting at pin CLKM
120
Register Bits
Value
Description
CLKM_CTRL
0
No clock at pin 17 (CLKM)
1
1 MHz
2
2 MHz
3
4 MHz
4
8 MHz
5
16 MHz
6
250 kHz
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Register Bits
Value
Description
7
Note:
IEEE 802.15.4 Symbol Rate Frequencies
BPSK_OQPSK (1)
SUB_MODE (1)
Frequency
0
0
20 kHz
0
1
40 kHz
1
0
25 kHz
1
1
62.5 kHz
1. Refer to section 7.1.5
Register 0x12 (XOSC_CTRL):
The register XOSC_CTRL configures the crystal oscillator.
Table 7-31. Register 0x12 (XOSC_CTRL)
Bit
7
6
5
4
Name
XTAL_MODE
XTAL_MODE
XTAL_MODE
XTAL_MODE
Read/Write
R/W
R/W
R/W
R/W
Reset Value
1
1
1
1
Bit
3
2
1
0
Name
XTAL_TRIM
XTAL_TRIM
XTAL_TRIM
XTAL_TRIM
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7:4 – XTAL_MODE
These register bits set the operating mode of the crystal oscillator, see Table 7-32.
Table 7-32. Crystal Oscillator Operating Mode
Register Bits
Value
XTAL_MODE
0x4
Internal crystal oscillator disabled, use external
reference frequency
0xF
Internal crystal oscillator enabled
XOSC voltage regulator enabled
Other
Description
Reserved
• Bit 3:0 – XTAL_TRIM
The register bits XTAL_TRIM control the two internal capacitance arrays connected to
pins XTAL1 and XTAL2. A capacitance value in the range from 0 pF to 4.5 pF is
selectable with a resolution of 0.3 pF.
Table 7-33. Crystal Oscillator Trimming Capacitors
Register Bits
XTAL_TRIM
Value
Description
0x0
0.0 pF
0x1
0.3 pF
…
0xF
other
4.5 pF
Reserved
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7.8 Frequency Synthesizer (PLL)
The main PLL features are:
•
•
•
•
Generate RX/TX frequencies for all supported channels
Autonomous calibration loops for stable operation within the operating range
Two PLL interrupts for status indication
Fast PLL settling to support frequency hopping
7.8.1 Overview
The PLL generates the RF frequencies for the AT86RF212. During receive and transmit
operations the frequency synthesizer operates as a local oscillator. The frequency
synthesizer is implemented as a fractional-N PLL with analog compensation of the
fractional phase error. The VCO is running at double of the RF frequency.
Two calibration loops ensure correct PLL functionality within the specified operating
limits.
7.8.2 RF Channel Selection
The PLL is designed to support
• one channel in the European SRD Band from 863 to 870 MHz at 868.3 MHz
according to IEEE 802.15.4 (channel k=0)
• 10 channels in the North American ISM Band from 902 to 928 MHz with a channel
spacing of 2 MHz according to IEEE 802.15.4-2006. The center frequency of these
channels is defined as
Fc = 906 + 2 (k-1) [MHz]
where k is the channel number ranging from 1 to 10.
The channel k is selected by register bits CHANNEL (register 0x08, PHY_CC_CA).
Additionally, the PLL supports all frequencies from 833 – 935 MHz with 1 MHz
frequency spacing, and 2 bands with 100 kHz spacing from 857 to 882.5 MHz, and 903
to 928.5 MHz.
The frequency is selected by registers 0x13 (CC_NUMBER, CC_CTRL_0[7:0]) and
0x14 (CC_BAND, CC_CTRL_1[2:0]).
Table 7-34 shows the settings of the registers CC_CTRL_0 and CC_CTRL_1.
Table 7-34. Frequency Bands and Numbers
122
CC_BAND,
CC_CTRL_1
CC_NUMBER,
CC_CTRL_0
Description
0
Not used
Frequency selected by channel number (PHY_CC_CCA)
2
0 – 255
857 – 882.5 MHz; Fc = 857 + 0.1 * CC_CTRL_0 [MHz]
3
0 – 255
903 – 928.5 MHz; Fc = 903 + 0.1 * CC_CTRL_0 [MHz]
5
0 – 102
833 – 935 MHz; Fc = 833 + CC_CTRL_0 [MHz]
1, 4, 6, 7
0 – 255
Reserved
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The PLL frequency in PLL_ON and receive states is 1 MHz below the PLL frequency in
transmit states.
7.8.3 PLL Settling Time
When the PLL is enabled during state transition from TRX_OFF to PLL_ON the settling
time is typically 50 µs (plus 60 µs settling time of AVREG), including PLL self
calibration, refer to 7.8.4. The locking of the PLL is indicated with the interrupt IRQ_0
(PLL_LOCK).
In PLL_ON state and receive states the PLL settles to the receive frequency.
When starting the transmit procedure the PLL frequency is changed to the transmit
frequency within a period of 16 µs before starting the transmission. After the
transmission the PLL settles back to the receive frequency within a period of 32 µs.
These frequency changes do not generate the interrupt IRQ_0 (PLL_LOCK) or IRQ_1
(PLL_UNLOCK).
7.8.4 Calibration Loops
Due to variation of temperature, supply voltage and center frequency the VCO
characteristics may vary.
To ensure a stable operation, two automated control loops are implemented: center
frequency and delay cell calibration. Both calibration loops are initiated automatically
when the PLL is enabled during state transition from TRX_OFF to PLL_ON or RX_ON.
Additionally, both calibration loops are initiated when the PLL changes to a different
frequency setting.
If the PLL operates for a long time on the same channel or the operating temperature
changes significantly, the calibration loops should be initiated manually. The
recommended calibration interval is 5 minutes or less.
Both calibration loops can be initiated manually by SPI command. To start the
calibration the device should be in state PLL_ON.
The center frequency calibration can be initiated by setting PLL_CF_START = 1
(register 0x1A, PLL_CF). Center frequency calibration generates (if enabled) a
PLL_UNLOCK interrupt. The calibration loop is completed when the PLL_LOCK
interrupt occurs (if enabled). The duration of the center frequency calibration loop
depends on the difference between the current CF value and the final CF value. During
the calibration the CF value will be incremented or decremented. Each step takes 8 µs.
The minimum time is 8 µs, the maximum time is 270 µs. The recommended procedure
to start the center frequency calibration is to read the register 0x1A (PLL_CF), to set the
PLL_CF_START register bit to 1, and to write the value back to the register.
The delay cell calibration can be initiated by setting the bit PLL_DCU_START of
register 0x1B (PLL_DCU) to 1. The delay time of the programmable delay unit is
adjusted to the correct value. The calibration works as successive approximation and is
independent of the values in the register 0x1B (PLL_DCU). The duration of the
calibration is 10 µs.
During both calibration processes no correct receive or transmit operation is possible.
The recommended state for the calibration is therefore PLL_ON, but calibration is not
blocked at receives or transmit states.
Both calibrations can be executed concurrently.
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7.8.5 Interrupt Handling
Two different interrupts indicate the PLL status. IRQ_0 (PLL_LOCK) indicates that the
PLL has locked. IRQ_1 (PLL_UNLOCK) interrupt indicates an unexpected unlock
condition. A PLL_LOCK interrupt clears any preceding PLL_UNLOCK interrupt
automatically and vice versa.
A PLL_LOCK interrupt occurs in the following situations:
• State change from TRX_OFF to PLL_ON / RX_ON
• Frequency setting change in states PLL_ON / RX_ON
• A manually started center frequency calibration has been completed
All other PLL_LOCK interrupt events indicate that the PLL locked again after a prior
unlock happened.
A PLL_UNLOCK interrupt occurs in the following situations:
• A manually initiated center frequency calibration in states PLL_ON / (RX_ON)
• Frequency setting change in states PLL_ON / RX_ON
PLL_LOCK and PLL_UNLOCK affect the behavior of the transceiver:
In the states BUSY_TX and BUSY_TX_ARET, the transmission is stopped and the
transceiver returns into state PLL_ON. During BUSY_RX and BUSY_RX_AACK the
transceiver returns to state RX_ON and RX_AACK_ON, respectively, once the PLL has
locked.
7.8.6 Register Description
Register 0x08 (PHY_CC_CCA):
The register PHY_CC_CCA contains register bits to set the channel center frequency.
A write access to the register bits CHANNEL sets the IEEE 802.15.4 channel number.
A read access shows the current channel number.
Table 7-35. Register 0x08 (PHY_CC_CCA)
Bit
7
6
5
4
Name
CCA_REQUEST
CCA_MODE
CCA_MODE
CHANNEL
Read/Write
W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
CHANNEL
CHANNEL
CHANNEL
CHANNEL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
1
The channel assignment of register bits CHANNEL is according to the IEEE 802.15.4
standard.
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Table 7-36. Channel Assignment according to IEEE 802.15.4
Register Bits
Value
Channel Number k
Frequency [MHz]
CHANNEL
0x00
0
868.3
0x01
1
906
0x02
2
908
0x03
3
910
0x04
4
912
0x05
5
914
0x06
6
916
0x07
7
918
0x08
8
920
0x09
9
922
0x0A
10
924
0x0B…0x1F
Reserved
Register 0x13 (CC_CTRL_0):
This register controls the frequency selection, if the selection by channel number is not
used.
Table 7-37. Register 0x13 (CC_CTRL_0)
Bit
7
6
5
Name
4
2
1
0
0
0
0
CC_NUMBER[7:0]
Read/Write
Reset Value
3
R/W
0
0
0
0
0
Register 0x14 (CC_CTRL_1):
This register selects the frequency band.
Table 7-38. Register 0x14 (CC_CTRL_1)
Bit
7
6
5
4
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
Reserved
CC_BAND[2]
CC_BAND[1]
CC_BAND[0]
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
The functionality of the registers CC_CTRL_0 and CC_CTRL_1 is documented in Table
7-34.
Register 0x1A (PLL_CF):
This register controls the operation of the center frequency calibration loop.
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Table 7-39. Register 0x1A (PLL_CF)
Bit
7
6
5
4
Name
PLL_CF_START
Reserved
Reserved
PLL_CF[4]
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
0
Bit
3
2
1
0
Name
PLL_CF[3]
PLL_CF[2]
PLL_CF[1]
PLL_CF[0]
Read/Write
R/W
R/W
R/W
R/W
Reset Value
1
0
0
0
• Bit 7 – PLL_CF_START
PLL_CF_START = 1 initiates the center frequency calibration. When the calibration
cycle has finished after at most 25 µs the register bit PLL_CF_START is reset to 0.
• Bit 6:5
These bits are reserved and must always be written back using the reset values.
• Bit 4:0 – PLL_CF
Bits 4:0 represent the current CF state of the PLL. In order to assure the shortest
possible calibration time they should not be changed when starting center frequency
tuning.
Register 0x1B (PLL_DCU):
This register controls the operation of the delay cell calibration loop.
Table 7-40. Register 0x1B (PLL_DCU)
Bit
7
6
5
4
Name
PLL_DCU_START
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
1
0
0
Bit
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – PLL_DCU_START
PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle is
completed after 10 µs, and the register bit PLL_DCU_START is set to 0. The register bit
is cleared immediately after finishing the calibration.
• Bit 6:0 – Reserved
7.9 Automatic Filter Tuning (FTN)
7.9.1 Overview
The FTN is incorporated to compensate for temperature, supply voltage variations, and
part-to-part variations of the radio transceiver. A calibration cycle is initiated
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automatically when entering the TRX_OFF state from the SLEEP, RESET or P_ON
states.
Although receiver and transmitter are very robust against these variations, it is
recommended to initiate the FTN manually, if the radio transceiver does not regularly
use the SLEEP state. This applies in particular for the High Data Rate Modes with
higher sensitivity against variations. The recommended calibration interval is about
5 minutes.
7.9.2 Register Description
Register 0x18 (FTN_CTRL):
This register controls the operation of the filter tuning calibration loop.
Table 7-41. Register 0x18 (FTN_CTRL)
Bit
7
6
5
4
Name
FTN_START
Reserved
Reserved
Reserved
Read/Write
S
R/W
R/W
R/W
Reset Value
0
1
0
1
Bit
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
1
0
0
0
• Bit 7 – FTN_START
FTN_START = 1 initiates the filter tuning calibration loop. Ones the calibration cycle has
finished within a maximum time period of 25 µs, the register bit is automatically reset to
0.
• Bit 6:0 – Reserved
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8 Radio Transceiver Usage
This section describes basic procedures to receive and transmit frames using the
AT86RF212.
8.1 Frame Receive Procedure
A frame reception comprises of two actions: The transceiver listens for, receives and
demodulates the frame to the Frame Buffer and signals the reception to the
microcontroller. After or during that process, the microcontroller can read the available
frame data from the Frame Buffer via the SPI interface.
While being in state RX_ON or RX_AACK_ON, the radio transceiver searches for
incoming frames on the selected channel. Assuming the appropriate interrupts are
enabled, a detection of an IEEE 802.15.4-2006 compliant frame is indicated by interrupt
IRQ_2 (RX_START). When the frame reception is completed, interrupt IRQ_3
(TRX_END) is issued.
Different Frame Buffer read access scenarios are recommended for:
• Non-time critical applications
• Time-critical applications
read access starts after IRQ_3 (TRX_END)
read access starts after IRQ_2 (RX_START)
For non time critical operations, it is recommended to wait for interrupt IRQ_3
(TRX_END) before starting a Frame Buffer read access. Figure 8-1 illustrates the frame
receive procedure using IRQ_3 (TRX_END).
Figure 8-1. Transactions between AT86RF212 and Microcontroller during Receive
Read IRQ status, pin 24 (IRQ) deasserted
IRQ issued (IRQ_3)
Read IRQ status, pin 24 (IRQ) deasserted
Microcontroller
AT86RF212
IRQ issued (IRQ_2)
Read frame data (Frame Buffer access)
Critical protocol timing could require starting the Frame Buffer read access after
interrupt IRQ_2 (RX_START). The first byte of the frame data can be read one octet
time period after the IRQ_2 (RX_START) interrupt. The microcontroller must ensure to
read slower than the frame is received. Otherwise, a Frame Buffer underrun occurs,
IRQ_6 (TRX_UR) is issued, and the frame data may be not valid. To avoid this, the
Frame Buffer read access can be controlled by using a Frame Buffer Empty indicator,
refer to section 9.6.
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8.2 Frame Transmit Procedure
A frame transmission comprises of two actions, a Frame Buffer write access and the
transmission of the Frame Buffer content. Both actions can be run in parallel if required
by critical protocol timing.
Figure 8-2 illustrates the frame transmit procedure, when writing and transmitting the
frame consecutively. After a Frame Buffer write access, the frame transmission is
initiated by asserting pin 11 (SLP_TR) or writing command TX_START to register 0x02
(TRX_STATE), while the radio transceiver is in state PLL_ON or TX_ARET_ON. The
completion of the transaction is indicated by interrupt IRQ_3 (TRX_END).
Figure 8-2. Transaction between AT86RF212 and Microcontroller during Transmit
Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)
IRQ_3 (TRX_END) issued
Microcontroller
AT86RF212
Write frame data (Frame Buffer access)
Read IRQ_STATUS register, pin 24 (IRQ) deasserted
Alternatively a frame transmission can be started first, followed by the Frame Buffer
write access (PSDU data); refer to Figure 8-3. This is applicable for time critical
applications.
Initiating a transmission, either by asserting pin 11 (SLP_TR) or command TX_START
to register bits TRX_CMD (register 0x02, TRX_STATE), the radio transceiver starts
transmitting the SHR, which is internally generated.
Front end initialization takes one symbol period for PLL settling and PA ramp up. SHR
transmission takes another 40 symbol periods for BPSK or 10 symbol periods for OQPSK.
The PHR must be available in the Frame Buffer before this time elapses. Furthermore,
the SPI data rate must be higher than the PHY data rate selected by register bits
OQPSK_DATA_RATE (register 0x0C, TRX_CTRL_2) to avoid a Frame Buffer
underrun, indicated by IRQ_6 (TRX_UR), refer to section 7.1.4.
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Figure 8-3. Time Optimized Frame Transmit Procedure
Write frame data (Frame Buffer access)
IRQ_3 (TRX_END) issued
Microcontroller
AT86RF212
Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)
Read IRQ_STATUS register, pin 24 (IRQ) deasserted
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9 Extended Feature Set
9.1 Security Module (AES)
The security module (AES) is characterized by:
•
•
•
•
Hardware accelerated encryption and decryption
Compatible with AES-128 standard (128 bit key and data block size)
ECB (encryption/decryption) mode and CBC (encryption) mode support
Stand-alone operation, independent of other blocks
9.1.1 Overview
The security module is based on an AES-128 core according to FIPS197 standard,
refer to [5]. The security module is independent from other building blocks of the
AT86RF212. Encryption and decryption can be performed in parallel to a frame
transmission or reception.
Controlling the security block is implemented as an SRAM access to address space
0x82 to 0x94. A Fast SRAM access mode allows simultaneously writing new data and
reading data from previously processed data within the same SPI transfer. This access
procedure is used to reduce the turnaround time for ECB mode, see 9.1.5.
In addition, the security module contains another 128-bit register to store the initial key
used for security operations. This initial key is not modified by the security module.
9.1.2 Security Module Preparation
The use of the security module requires a configuration of the security engine before
starting a security operation. The required steps are listed in Table 9-1.
Table 9-1. AES Engine Configuration Steps
Step
Description
Description
Chapter
1
Key Setup
Write encryption or decryption key to SRAM
9.1.3
2
AES mode
Select AES mode: ECB or CBC
Select encryption or decryption
9.1.4.1
9.1.4.2
3
Write Data
Write plaintext or cipher text to SRAM
9.1.5
4
Start operation
Start AES operation
5
Read Data
Read cipher text or plaintext from SRAM
9.1.5
Before starting any security operation a key must be written to the security engine, refer
to 9.1.3. The key set up requires the configuration of the AES engine KEY mode using
register bits AES_MODE (SRAM address 0x83, AES_CON).
The following step selects the AES mode, either electronic code book (ECB) or cipher
block chaining (CBC). These modes are explained in more detail in section 9.1.4.
Further, encryption or decryption must be selected with register bit AES_DIR (SRAM
address 0x83, AES_CON).
As next the 128-bit plain text or cipher text data has to be provided to the AES
hardware engine. The data uses the SRAM address range 0x84 – 0x93.
An encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM
address 0x83, AES_CON or the mirrored version with SRAM address 0x94,
AES_CON_MIRROR).
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The AES module control registers are only accessible using SRAM read and write
accesses on address space 0x82 to 0x94. Configuring the AES mode, providing the
data and starting a decryption or encryption operation can be combined in a single
SRAM access.
Notes
• No additional register access is required to operate the security block.
• Using AES in TRX_OFF state requires an activated clock at pin 17 (CLKM), i.e.
register bits CLKM_CTRL ≠ 0. For further details refer to section 7.7.4.
• Access to the security block is not possible while the radio transceiver is in state
SLEEP.
• All configurations of the security module, the SRAM content and keys are reset
during SLEEP or RESET states.
• A read or write access to register 0x83 (AES_CON) during AES operation terminates
the current processing.
9.1.3 Security Key Setup
The setup of the key is prepared by setting register bits AES_MODE = 0x1 (SRAM
address 0x83, AES_CON). Afterwards the 128 bit key must be written to SRAM
addresses 0x84 through 0x93 (registers AES_KEY). It is recommended to combine the
setting of control register 0x83 (AES_CON) and the 128 bit key transfer using only one
SRAM access starting from address 0x83.
The address space of the 128-bit key and 128-bit data is identical from programming
point of view. However, both use different pages which are selected by register bit
AES_MODE before storing the data.
A read access to registers AES_KEY (0x84 – 0x93) returns the last round key of the
preceding security operation. After an ECB encryption operation, this is the key that is
required for the corresponding ECB decryption operation. However, the initial AES key,
written to the security module in advance of an AES run, see step 1 in Table 9-1, is not
modified during an AES operation. This initial key is used for the next AES run even it
cannot be read from AES_KEY.
Note
• ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The
AT86RF212 provides this functionality as an additional feature.
9.1.4 Security Operation Modes
9.1.4.1 Electronic Code Book (ECB)
ECB is the basic operating mode of the security module. After setting up the initial AES
key, register bits AES_MODE = 0 (SRAM address 0x83, AES_CON) sets up ECB
mode. Register bit AES_DIR (SRAM address 0x83, AES_CON) selects the direction,
either encryption or decryption. The data to be processed has to be written to SRAM
addresses 0x84 through 0x93 (registers AES_STATE).
An example for a programming sequence is shown in Figure 9-1. This example
assumes that a suitable key has been loaded before.
A security operation can be started within one SRAM access by appending the start
command AES_REQUEST = 1 (register 0x94, AES_CON_MIRROR) to the SPI
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sequence. Register AES_CON_MIRROR is a mirrored version of register 0x83
(AES_CON).
Figure 9-1. ECB Programming SPI Sequence – Encryption
byte 0 (cmd.)
byte 1 (address)
byte 2 (AES cmd)
byte 3
0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
SRAM write
0x83
data_0[7:0]
….
byte 18
byte 19 (AES cmd)
data_15[7:0]
1 0 0 0 0 0 0 0
ECB, encryption
AES start
Summarizing, the following steps are required to perform a security operation using
only one SPI access:
1. Configure SPI access
a) SRAM write, refer to section 4.3
b) Start address 0x83
2. Configure AES operation
3. Write 128-bit data block
4. Start AES operation
address 0x83: select ECB mode, direction
addresses 0x84 – 0x93: either plain or cipher text
address 0x94: start AES operation, ECB mode
This sequence is recommended because the security operation is configured and
started within one SPI transaction.
The ECB encryption operation is illustrated in Figure 9-2. Figure 9-3 shows the ECB
decryption mode, which is supported in a similar way.
Figure 9-2. ECB Mode - Encryption
Plaintext
Encryption
Key
Block Cipher
Encryption
Ciphertext
Plaintext
Encryption
Key
Block Cipher
Encryption
Ciphertext
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Figure 9-3. ECB Mode - Decryption
Ciphertext
Decryption
Key
Ciphertext
Block Cipher
Decryption
Decryption
Key
Plaintext
Block Cipher
Decryption
Plaintext
When decrypting, due to the nature of AES algorithm, the initial key to be used is not
the same as the one used for encryption, but rather the last round key instead. This last
round key is the content of the key address space stored after running one full
encryption cycle, and must be saved for decryption. If the decryption key has not been
saved, it has to be recomputed by first running a dummy encryption (of an arbitrary
plaintext) using the original encryption key, then fetching the resulting round key from
the key memory, and writing it back into the key memory as the decryption key.
ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of
these standards do not directly encrypt the payload, but rather a nonce instead, and
protect the payload by applying an XOR operation between the resulting (AES-) cipher
text and the original payload. As the nonce is the same for encryption and decryption
only ECB encryption is required. Decryption is performed by XORing the received
cipher text with its own encryption result respectively, which results in the original
plaintext payload upon success.
9.1.4.2 Cipher Block Chaining (CBC)
In CBC mode, the result of a previous AES operation is XORed with the new incoming
vector, forming the new plaintext to encrypt, see Figure 9-4. This mode is used for the
computation of a cryptographic checksum (message integrity code, MIC).
Figure 9-4. CBC Mode - Encryption
Plaintext
Encryption
Key
134
Initialization Vector (IV)
Block Cipher
Encryption
Encryption
Key
Plaintext
Block Cipher
Encryption
Ciphertext
Ciphertext
ECB
mode
CBC
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After preparing the AES key and defining the AES operation direction using SRAM
register bit AES_DIR, the data has to be provided to the AES engine and the CBC
operation can be started.
The first CBC run has to be configured as ECB to process the initial data (plaintext
XORed with an initialization vector provided by the microcontroller). All succeeding AES
runs are to be configured as CBC by setting register bits AES_MODE = 0x2 (register
0x83, AES_CON). Register bit AES_DIR (register 0x83, AES_CON) must be set to
AES_DIR = 0 to enable AES encryption. The data to be processed has to be
transferred to the SRAM starting with address 0x84 to 0x93 (register AES_STATE).
Setting register bit AES_REQUEST = 1 (register 0x94, AES_CON_MIRROR) as
described in section 9.1.4 starts the first encryption within one SRAM access. This
causes the next 128 bits of plaintext data to be XORed with the previous cipher text
data, see Figure 9-4.
According to IEEE 802.15.4 the input for the very first CBC operation has to be
prepared by a XORing a plaintext with an initialization vector (IV). The value of the
initialization vector is 0. However, for non-compliant usage any other initialization vector
can be used. This operation has to be prepared by the microcontroller.
Note that IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption
only, as it implements a one-way hash function.
9.1.5 Data Transfer – Fast SRAM Access
The ECB and CBC modules including the AES core are clocked with 16 MHz. One AES
operation takes 24 µs to execute, refer to parameter 10.4.15 in section 10.4. This
means that the processing of the data is usually faster than the transfer of the data via
the SPI interface.
5
To reduce the overall processing time, the AT86RF212 provides a Fast SRAM access
for the address space 0x83 to 0x94.
Figure 9-5. Packet Structure – Fast SRAM Access Mode
AES run #n
AES run #0
AES access #1
AES access #n+1
MOSI
cmd add cfg P0 P1
... P14 P15 start
cmd add cfg P0 P1
... P14 P15 start
MISO
stat xx
...
stat xx
... C13 C14 C15
xx
xx
0x83
Address
xx
xx
...
xx
xx
0x94
xx
xx C0
0x83
...
byte 1 (addr.)
byte 2 (cmd)
byte 3
byte 4
MOSI
SRAM write
address 0x83
<AES_CON>
P0[7:0]
P1[7:0]
MISO
PHY_STATUS
XX
XX
XX
C0[0:7]
0x83
0x84
0x85
Note:
cmd add cfg xx
stat xx
xx
0x83
0x94
byte 0 (cmd)
Address
...
AES access #0
xx
xx C0
...
xx
xx start
... C13 C14 C15
...
byte 18
byte 19
...
P15[7:0]
<AES_CON>(1)
...
C14[0:7]
C15[0:7]
0x93
0x94
0x94
1. Byte 19 is the mirrored version of register AES_CON on SRAM address 0x94, see
register description AES_CON_MIRROR for details.
The Fast SRAM access allows writing and reading of data simultaneously during one
SPI access for consecutive AES operations (AES run).
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For each byte P0 transferred to pin 22 (MOSI), the previous content of the respective
AES register C0 is clocked out at pin 20 (MISO) with an offset of one byte. See Figure
9-5 as an example for “AES access #1”.
In the example shown in Figure 9-5 the initial plaintext P0 – P15 is written to the SRAM
within “AES access #0”. The last command on address 0x94 (AES_CON_MIRROR)
starts the AES operation (“AES run #0”). In the next “AES access #1” new plaintext data
P0 – P15 is written to the SRAM for the second AES run, in parallel the cipher text C0 –
C15 from the first AES run is clocked out at pin MISO. To read the cipher text from the
last “AES run #(n)” one dummy “AES access #(n+1)” is needed.
Note that the SRAM write access always overwrites the previous processing result.
The Fast SRAM access automatically applies to all write operations to SRAM
addresses 0x83 to 0x94.
9.1.6 Security Operation Status
The status of the security processing is indicated by register 0x82 (AES_ST). After
24 µs AES processing time register bit AES_RY changes to 1 (register 0x82, AES_ST)
indicating that the security operation has finished, see parameter 10.4.15 in section
10.4.
5
9.1.7 SRAM Register Summary
The following registers are required to control the security module:
Table 9-2. SRAM Security Module Address Space Overview
SRAM-Addr.
Register Name
Description
0x80 – 0x81
Reserved
0x82
AES_ST
AES status
0x83
AES_CON
Security module control, AES mode
Depends on AES_MODE setting:
AES_MODE = 1:
- Contains AES_KEY (key)
AES_MODE = 0 | 2:
- Contains AES_STATE (128 bit data block)
0x84 – 0x93
AES_KEY
AES_STATE
0x94
AES_CON_MIRROR
0x95 – 0xFF
Mirror of register 0x83 (AES_CON)
Reserved
These registers are only accessible using SRAM write and read, for details refer to
section 4.3.3. Note that the SRAM register are reset when entering the SLEEP state.
9.1.8 AES SRAM Configuration Register
Register 0x82 (AES_ST):
This read-only register signals the status of the security module and operation.
Table 9-3. Register 0x82 (AES_ST)
136
Bit
7
6
5
4
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R
R
R
R
Reset Value
0
0
0
0
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Bit
3
2
1
0
Name
Reserved
Reserved
Reserved
AES_RY
Read/Write
R
R
R
R
Reset Value
0
0
0
0
• Bit 7:1 –Reserved
• Bit 0 – AES_RY
Table 9-4. AES Core Operation Status
Register Bit
Value
AES_RY
Description
0
AES operation has not been completed
1
AES operation has been completed
Register 0x83 (AES_CON):
This register controls the operation of the security module. A read or write access
during AES operation terminates the current processing.
Table 9-5. Register 0x83 (AES_CON)
Bit
7
6
5
4
Name
AES_REQUEST
AES_MODE
AES_MODE
AES_MODE
Read/Write
W
R/W
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
AES_DIR
Reserved
Reserved
Reserved
Read/Write
R/W
R
R
R
Reset Value
0
0
0
0
• Bit 7 – AES_REQUEST
A write access with AES_REQUEST = 1 initiates the AES operation.
• Bit 6:4 – AES_MODE
This register bit sets the AES operation mode.
Table 9-6. AES Mode
Register Bits
Value
AES_MODE
Description
0
ECB mode, refer to 9.1.4.1
1
KEY mode, refer to 9.1.3
2
CBC mode, refer to 9.1.4.2
3–7
Reserved
• Bits 3 – AES_DIR
This register bit sets the AES operation direction, either encryption or decryption.
Table 9-7. AES Direction
Register Bit
AES_DIR
Value
0
Description
AES encryption (ECB, CBC)
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Register Bit
Value
Description
1
AES decryption (ECB)
• Bit 1:0 – Reserved
Register 0x84 (AES_CON_MIRROR):
Register 0x84 is a mirrored version of register 0x83 (AES_CON), for details refer to
register 0x83 (AES_CON).
Table 9-8. Register 0x84 (AES_CON_MIRROR)
Bit
7
6
5
4
Name
AES_REQUEST
AES_MODE
AES_MODE
AES_MODE
Read/Write
W
R/W
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
AES_DIR
Reserved
Reserved
Reserved
Read/Write
R/W
R
R
R
Reset Value
0
0
0
0
This register could be used to start a security operation within a single SRAM access by
appending it to the data stream and setting register bit AES_REQUEST = 1.
9.2 Random Number Generator
9.2.1 Overview
The AT86RF212 provides a 2-bit random number generator. This random number can
be used to:
• Generate random seeds for CSMA-CA algorithm
• Generate random values for AES key generation
see section 5.2
see section 9.1
The random number is updated every 1 µs in Basic Operating Mode receive states. The
values are stored in register bits RND_VALUE (register 0x06, PHY_RSSI).
9.2.2 Register Description
Register 0x06 (PHY_RSSI):
Register 0x06 (PHY_RSSI) is a multi purpose register to indicate FCS validity, to
provide random numbers and an RSSI value.
Table 9-9. Register 0x06 (PHY_RSSI)
138
Bit
7
6
5
4
Name
RX_CRC_VALID
RND_VALUE
RND_VALUE
RSSI
Read/Write
R
R
R
R
Reset Value
0
0
0
0
AT86RF212
8168A-AVR-06/08
AT86RF212
Bit
3
2
1
0
Name
RSSI
RSSI
RSSI
RSSI
Read/Write
R
R
R
R
Reset Value
0
0
0
0
• Bit 7 – RX_CRC_VALID
Refer to register description in section 6.3.5.
• Bit 6:5 – RND_VALUE
The 2-bit random value can be retrieved by reading register bits RND_VALUE. Note
that the radio transceiver shall be in Basic Operating Mode receive state. The values
are updated each 1 µs.
• Bit 4:0 – RSSI
Refer to register description in section 6.4.4.
9.3 Antenna Diversity
The AT86RF212 supports a MAC based antenna diversity to improve signal path
robustness between nodes.
9.3.1 Overview
Due to multipath propagation effects between network nodes, the receive signal
strength may vary and affects the link quality, even for small changes of the antenna
location. These fading effects can result in an increased error floor or loss of the
connection between devices.
To improve the reliability of an RF connection between network nodes, Antenna
Diversity can be applied to reduce effects of multipath propagation and fading. Antenna
Diversity uses two antennas to select the most reliable RF signal path. To ensure highly
independent receive signals on both antennas, the antennas should be carefully
separated from each other.
The AT86RF212 supports MAC based antenna diversity, i.e. the microcontroller
controls which antenna will be used for transmission and reception. This is done by
register settings.
Antenna Diversity can be used in Basic and Extended Operating Modes and can also
be combined with other features and operating modes like High Data Rate Modes and
RX/TX Indication.
9.3.2 Application Example
A block diagram for a typical application is shown in Figure 9-6.
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Figure 9-6. Antenna Diversity – Block Diagram
ANT0
1
AT86RF212
DIG3
2 DIG4
B1
3 AVSS
4 RFP
Balun
6 AVSS
...
DIG2
5 RFN
DIG1
RFSwitch
SW1
9
10
ANT1
The use of pins 9 and 10 (DIG 1 and DIG2) for antenna diversity is enabled by
ANT_EXT_SW_EN = 1 (register 0x0D, ANT_DIV). In this case, the internal connection
of the control pins 9 and 10 to digital ground is disabled (refer to section 2.2.2), and
they provide a differential control signal to the antenna switch (SW1).
For transmission and reception, the antenna defined by register bits ANT_CTRL
(register 0x0D, ANT_DIV) is selected.
9.3.3 Register Description
Register 0x0D (ANT_DIV):
The ANT_DIV register controls Antenna Diversity.
Table 9-10. Register 0x0D (ANT_DIV)
Bit
7
6
5
4
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R
R
R
R
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
Reserved
ANT_EXT_SW_EN
ANT_CTRL
ANT_CTRL
Read/Write
R
R/W
R/W
R/W
Reset Value
0
0
0
1
• Bit 7:3 – Reserved
• Bit 2 – ANT_EXT_SW_EN
If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential
control signal for an Antenna Diversity switch. The selection of a specific antenna is
done according to register bits ANT_CTRL.
If RX Frame Time Stamping (refer to section 9.5) is used in combination with Antenna
Diversity, DIG1 is used for Antenna Diversity and DIG2 is used for RX Frame Time
Stamping. AT86RF212 do not provide a differential control signal in this case, see
Figure 3-2.
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AT86RF212
If the register bit is set the control pins DIG1/DIG2 are activated in all radio transceiver
states as long as register bit ANT_EXT_SW_EN is set. If the AT86RF212 is not in a
receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN
to reduce the power consumption or avoid leakage current of an external RF switch,
especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1
and DIG2 are internally connected to digital ground.
Table 9-11. Antenna Diversity RF Switch Enable
Register Bit
ANT_EXT_SW_EN
Value
Description
0
Antenna Diversity RF switch control disabled
1
Antenna Diversity RF switch control enabled
• Bit 1:0 – ANT_CTRL
•
These register bits provide a static control of an Antenna Diversity switch.
Table 9-13. Antenna Diversity Switch Control
Register Bit
Value
Description
ANT_CTRL
0
Reserved
1
Antenna 0
DIG1 = H
DIG2 = L
2
Antenna 1
DIG1 = L
DIG2 = H
3
Reserved
9.4 RX/TX Indicator
The main features are:
• RX/TX Indicator to control an external RF front-end
• Microcontroller independent RF front-end control
• Providing TX timing information
9.4.1 Overview
While IEEE 802.15.4 is targeting low cost and low power applications, solutions
supporting higher transmit output power are occasionally desirable. To simplify the
control of an optional external RF front-end, a differential control pin pair can indicate
that the AT86RF212 is currently in transmit mode.
The control of an external RF front-end is done via digital control pins DIG3/DIG4. The
function of this pin pair is enabled with register bit PA_EXT_EN (register 0x04,
TRX_CTRL_1). While the transmitter is turned off, pin 1 (DIG3) is set to low level and
pin 2 (DIG4) to high level. If the radio transceiver starts to transmit, the two pins change
the polarity. This differential pin pair can be used to control PA, LNA, and RF switches.
If the AT86RF212 is not in a receive or transmit state, it is recommended to disable
register bit PA_EXT_EN (register 0x04, TRX_CTRL_1) to reduce the power
consumption or avoid leakage current of external RF switches and other building
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blocks, especially during SLEEP state. If register bits PA_EXT_EN = 0, output pins
DIG3/DIG4 are internally connected to analog ground.
9.4.2 External RF-Front End Control
When using an external RF front-end including a power amplifier (PA), it may be
required to adjust the setup time of the external PA relative to the internal building
blocks to optimize the overall power spectral density (PSD) mask.
Figure 9-8. TX Power Ramping Control of RF Front-End for 250 kbit/s O-QPSK mode
0
TRX_STATE
2
4
6
8
PLL_ON
10
12
14
16
18
Length [µs]
BUSY_TX
SLP_TR
PA_LT
PA
TX Data
Modulation
DIG3
DIG4
The start-up sequence of the individual building blocks of the internal transmitter is
shown in Figure 9-8, where transmission is actually initiated by the rising edge of
pin 11 (SLP_TR). The radio transceiver state changes from PLL_ON to BUSY_TX and
the PLL settles to the transmit frequency within 1 symbol period. The modulation starts
1 symbol period after the rising edge of SLP_TR. During this time, the internal PA is
initialized.
The control of the external PA is done via the differential pin pair DIG3/DIG4.
DIG3 = H / DIG4 = L indicates that the transmission starts and can be used to enable
the external PA. The timing of pins DIG3/DIG4 can be adjusted relative to the start of
the frame using register bits PA_LT (register 0x16, RF_CTRL_0). For details refer to
section 7.3.5.
9.4.3 Register Description
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating
modes and settings of the radio transceiver.
Table 9-14. Register 0x04 (TRX_CTRL_1)
142
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
SPI_CMD_MODE
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
R/W
R/W
R/W
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AT86RF212
Reset Value
0
0
0
0
• Bit 7 – PA_EXT_EN
This register bit enables pin 1 (DIG3) and pin 2 (DIG4) to indicate the transmit state of
the radio transceiver.
Table 9-15. RF Front-End Control Pins
PA_EXT_EN
0
(1)
1
State
n/a
TX_BUSY
Other
Note:
Pin
Value
DIG3
L
DIG4
L
DIG3
H
DIG4
L
DIG3
L
DIG4
H
Description
External RF front-end control disabled
External RF front-end control enabled
1. It is recommended to set PA_EXT_EN = 1 only in receive or transmit states to
reduce the power consumption or avoid leakage current of external RF switches or
other building blocks, especially during SLEEP state.
• Bit 6 – IRQ_2_EXT_EN
Refer to section 9.5.
• Bit 5 – TX_AUTO_CRC_ON
Refer to section 6.3.
• Bit 4 – RX_BL_CTRL
Refer to section 9.6.
• Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
• Bit 1 – IRQ_MASK_MODE
Refer to section 4.7.
• Bit 0 – IRQ_POLARITY
Refer to section 4.7.
9.5 RX Frame Time Stamping
9.5.1 Overview
To determine the exact timing of an incoming frame, e.g. for beaconing networks, the
reception of this frame can be signaled to the microcontroller via pin 10 (DIG2). The pin
turns from L to H after detection of a valid PHR. When enabled, DIG2 is set to DIG2 = H
at the same time as IRQ_2 (RX_START), even if IRQ_2 is disabled. The pin remains
high for the length of the frame receive procedure, see Figure 9-9.
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Figure 9-9. Timing of RX_START and DIG2 for RX Frame Time Stamping within 250 kbit/s O-QPSK mode
128
TRX_STATE
192
192 + m * 32
4
1
1
m < 128
Preamble
SFD
PHR
PSDU (250 kb/s)
Number of Octets
Frame Content
160
RX_ON
BUSY_RX
Time [µs]
Frame
on Air
0
RX_ON
RX
DIG2 (RX Frame Time Stamp)
IRQ
IRQ_2 (RX_START)
TRX_END
tIRQ
Interrupt latency
Note:
tIRQ
Timing figures refer to section 10.4.
This function is enabled with register bit IRQ_2_EXT_EN (register 0x04,
TRX_CTRL_1). Pin 10 (DIG2) can be connected to a timer capture unit of the
microcontroller.
If this pin is not used for RX Frame Time Stamping it can be configured for Antenna
Diversity, refer to section 9.3. Otherwise, this pin is internally connected to ground.
9.5.2 Register Description
Register 0x04 (TRX_CTRL_1):
Register 0x04 (TRX_CTRL_1) is a multi purpose register to control various operating
modes and settings of the radio transceiver.
Table 9-16. Register 0x04 (TRX_CTRL_1)
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
SPI_CMD_MODE
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – PA_EXT_EN
Refer to section 9.4.
• Bit 6 – IRQ_2_EXT_EN
If this register bit is set, the RX Frame Time Stamping Mode is enabled. An incoming
frame with a valid PHR is signaled via pin 10 (DIG2). The pin remains at high level until
the end of the frame receive procedure, see Figure 9-9.
• Bit 5 – TX_AUTO_CRC_ON
Refer to section 6.3.
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• Bit 4 – RX_BL_CTRL
Refer to section 9.6.
• Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
• Bit 1 – IRQ_MASK_MODE
Refer to section 4.7.
• Bit 0 – IRQ_POLARITY
Refer to section 4.7.
9.6 Frame Buffer Empty Indicator
9.6.1 Overview
For time critical applications, it may be desirable to read the frame data as early as
possible. To accomplish this, the Frame Buffer empty status can be indicated to the
microcontroller through a dedicated pin.
Pin 24 (IRQ) can be configured as Frame Buffer Empty Indicator during the Frame
Buffer read access. This mode is enabled by register bit RX_BL_CTRL (register 0x04,
TRX_CTRL_1).
As shown in Figure 9-10, the pin 24 turns from IRQ into Frame Buffer Empty Indicator
after the Frame Buffer read access command has been transferred on the SPI bus, see
(1) in Figure 9-10. The pin 24 turns back to its regular function IRQ when the Frame
Buffer read procedure has been completed by /SEL = H, see (4).
Figure 9-10. Timing Diagram of Frame Buffer Empty Indicator
/SEL
SCLK
MOSI
MISO
IRQ
Command
XX
PHY_STATUS IRQ_STATUS
Command
PHY_STATUS
XX
PHR[7:0]
XX
XX
PSDU[7:0]
PSDU[7:0]
XX
PSDU[7:0]
XX
Command
LQI[7:0]
XX
PYH_STATUS IRQ_STATUS
Frame Buffer Empty Indicator
IRQ_2 (RX_START)
IRQ_3 (TRX_END)
tTR15
Notes
(1)
(2)
(3)
(4)
The microcontroller has to observe pin 24 during the Frame Buffer read procedure. A
Frame Buffer read access can proceed as long as pin 24 = L, see (2). Pin 24 = H
indicates that the Frame Buffer is currently not ready for another SPI cycle, see (3), and
thus the Frame Buffer read procedure has to wait for valid data accordingly.
The Frame Buffer Empty Indicator pin 24 (IRQ) becomes effective tTR15 = 450 ns after
the rising edge of last SCLK clock of the Frame Buffer read command byte.
After finishing the Frame Buffer read access by releasing /SEL = H, see (4), pending
interrupts are immediately indicated by pin IRQ.
If during the Frame Buffer read access a receive error occurs (e.g. a PLL unlock), the
Frame Buffer Empty Indicator locks on 'empty' (pin 24 = H) too. To prevent possible
deadlocks, the microcontroller should impose a timeout counter that checks whether the
Frame Buffer Empty Indicator remains logic high for more than 2 octet periods. A new
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8168A-AVR-06/08
byte must have been arrived at the frame buffer during that period. If not, the Frame
Buffer read access should be aborted.
9.6.2 Register Description
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating
modes and settings of the radio transceiver.
Table 9-17. Register 0x04 (TRX_CTRL_1)
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
SPI_CMD_MODE
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – PA_EXT_EN
Refer to section 9.4.
• Bit 6 – IRQ_2_EXT_EN
Refer to section 9.5.
• Bit 5 – TX_AUTO_CRC_ON
Refer to section 6.3.
• Bit 4 – RX_BL_CTRL
If this register bit is set, the Frame Buffer Empty Indicator is enabled. After sending a
Frame Buffer read command, refer to section 4.3, pin 24 (IRQ) indicates that an access
to the Frame Buffer is not possible since PSDU data are not available yet. Pin 24 (IRQ)
does not indicate any interrupt during this time.
Table 9-18. Frame Buffer Empty Indicator
Register Bit
Value
RX_BL_CTRL
Description
0
Frame Buffer Empty Indicator disabled
1
Frame Buffer Empty Indicator enabled
• Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
• Bit 1 – IRQ_MASK_MODE
Refer to section 4.7.
• Bit 0 – IRQ_POLARITY
Refer to section 4.7.
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9.7 Dynamic Frame Buffer Protection
9.7.1 Overview
The AT86RF212 continues the reception of incoming frames as long as it is in any
receive state. When a frame is successfully received and stored in the Frame Buffer,
the following frame overwrites the Frame Buffer content again.
To relax the timing requirements of a Frame Buffer read access, Dynamic Frame Buffer
Protection prevents that a new incoming frame overwrites the Frame Buffer as long as
the Frame Buffer read access has not been completed by /SEL = H, refer to section 4.3.
A received frame is automatically protected against overwriting:
• in Basic Operating Mode, if its FCS is valid
• in Extended Operating Mode, if an IRQ_3 (TRX_END) is generated
The Dynamic Frame Buffer Protection is enabled, if register bit RX_SAFE_MODE
(register 0x0C, TRX_CTRL_2) is set and the transceiver state is RX_ON or
RX_AACK_ON.
Note that Dynamic Frame Buffer Protection only prevents write accesses from the air
interface – not from the SPI interface. A Frame Buffer or SRAM write access may still
modify the Frame Buffer content.
9.7.2 Register Description
Register 0x0C (TRX_CTRL_2):
The TRX_CTRL_2 register is a multi purpose register to control various settings of the
radio transceiver.
Table 9-19. Register 0x0C (TRX_CTRL_2)
Bit
7
6
5
4
Name
RX_SAFE_MODE
TRX_OFF_AVDD_EN
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
1
0
Bit
3
2
1
0
Name
BPSK_OQPSK
SUB_MODE
OQPSK_DATA_RATE
OQPSK_DATA_RATE
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7 – RX_SAFE_MODE
If this bit is set, Dynamic Frame Buffer Protection is enabled.
Table 9-20. Dynamic Frame Buffer Protection Mode
Register Bit
Value
(1)
RX_SAFE_MODE
Note:
Description
0
Disable Dynamic Frame Buffer protection
1
Enable Dynamic Frame Buffer protection
1. Dynamic Frame Buffer Protection is deactivated with the rising edge of pin 23
(/SEL) of a Frame Buffer read access, see section 4.3.2, or radio transceiver
state change from RX_ON or RX_AACK_ON to another state.
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• Bit 6 – TRX_OFF_AVDD_EN
Refer to section 5.1.4.3.
• Bit 5:4 – Reserved
• Bit 3 – BPSK_OQPSK
Refer to section 7.1.5.
• Bit 2 – SUB_MODE
Refer to section 7.1.5.
• Bit 1:0 – OQPSK_DATA_RATE
Refer to section 7.1.5.
9.8 Configurable Start-Of-Frame Delimiter (SFD)
9.8.1 Overview
The SFD is a field indicating the end of the SHR and the start of the packet data. The
length of the SFD is 1 octet (8 symbols for BPSK and 2 symbols for O-QPSK). This
octet is used for byte synchronization only and is not included in the Frame Buffer.
The value of the SFD could be changed if it is needed to operate non IEEE 802.15.4
compliant networks. An IEEE 802.15.4 compliant network node does not synchronize to
frames with a different SFD value.
Due to the way the SHR is formed, it is not recommended to set the low-order 4 bits to
0.
9.8.2 Register Description
Register 0x0B (SFD_VALUE):
This register contains the one octet start-of-frame delimiter (SFD) to synchronize to a
received frame.
Table 9-21. Register 0x0B (SFD_VALUE)
Bit
7
6
5
4
Name
2
1
0
1
1
1
SFD_VALUE[7:0]
Read/Write
Reset Value
3
R/W
1
0
1
0
0
• Bit 7:0 – SFD_VALUE
For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7, as specified by [1].
This is the default value of the register.
To establish non IEEE 802.15.4 compliant networks, the SFD value can be changed to
any other value. If enabled, IRQ_2 (RX_START) is issued only if the received SFD
matches SFD_VALUE and a valid PHR is received.
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10 Electrical Characteristics
10.1 Absolute Maximum Ratings
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions beyond those indicated in the
operational sections of this specification are not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
No.
Symbol
Parameter
10.1.1
TSTOR
Storage temperature
10.1.2
TLEAD
Lead temperature
T = 10s
Soldering profile compliant with
IPC/JEDEC J-STD-020B
10.1.3
VESD
ESD robustness
Compliant to [3]
Compliant to [4]
10.1.4
PRF
Input RF level
10.1.5
VDIG
Voltage on all pins
except pins 4, 5, 13, 14, 29
Voltage on pins 4, 5, 13, 14, 29
10.1.6
VANA
Condition
Min.
Typ.
-50
Max.
Units
150
°C
260
°C
4
750
kV
V
10
dBm
VCC+0.3
≤ 4.0
V
-0.3
-0.3
2
V
Max.
Units
10.2 Operating Range
No.
Symbol
Parameter
Condition
Min.
Typ.
10.2.1
TOP
Operating temperature range
85
°C
10.2.2
VCC
Supply voltage
Voltage on pins 15, 28(2)
1.8
3.0
3.6
V
10.2.3
VDD1.8
Supply voltage
Voltage on pins 13, 14, 29
External voltage supply (1)(2)
1.7
1.8
1.9
V
Note:
-40
1. Register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage
regulators and supply blocks by an external 1.8 V supply, refer to section 7.5.
2. Even if an implementation uses the external 1.8 V voltage supply VDD1.8 it is
required to connect VCC.
10.3 Digital Pin Specifications
Test Condition: TOP = 25°C
No.
10.3.1
10.3.2
Symbol
VIH
VIL
Parameter
High level input voltage
Low level input voltage
Condition
(1)
Min.
Typ.
Max.
VCC-0.4
(1)
V
0.4
(1)
10.3.3
VOH
High level output voltage
10.3.4
VOL
Low level output voltage (1)
For all output driver strength
defined in TRX_CTRL_0
For all output driver strength
defined in TRX_CTRL_0
Units
VCC-0.4
V
V
0.4
V
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Note:
1. The capacitive load should not be larger than 50 pF for all I/Os when using the
default driver strength settings, refer to section 2.2.2.1. Generally, large load
capacitances increase the overall current consumption.
10.4 Digital Interface Timing Characteristics
Test Conditions: TOP = 25°C, Vcc = 3.0 V, CL = 50 pF
No.
Symbol
Parameter
Condition
10.4.1
fsync
SCLK frequency
10.4.2
fasync
SCLK frequency
10.4.3
10.4.4
10.4.5
t1
t2
t3
Min.
Typ.
Max.
Units
Synchronous operation
8
MHz
Asynchronous operation
7.5
/SEL falling edge to MISO active
SCLK falling edge to MISO out
MHz
(7)
180
Data hold time
MOSI setup time
25
ns
(7)
ns
(7)
ns
10
(7)
10.4.6
t4
MOSI hold time
10
ns
10.4.7
t5
LSB last byte to MSB next byte
250(8)
ns
10.4.8
t6
/SEL rising edge to MISO tri state
10.4.9
t7
SLP_TR pulse width
10(8)
TX start trigger
ns
(1)
62.5
Note
ns
(8)
ns
ns
10.4.10
t8
SEL rising to falling edge
SPI read/write, standard SRAM
and frame access modes;
idle time between consecutive
SPI accesses
250
10.4.11
t8
SEL rising to falling edge
Fast SRAM read/write access
mode, refer to section 9.1.5;
idle time between consecutive
SPI accesses
500(8)
10.4.12
t9
SCLK rising edge LSB to /SEL
rising edge
10.4.13
t10
Reset pulse width
≥ 10 clock cycles at 16 MHz
625
ns
10.4.14
t11
SPI access latency after reset
≥ 10 clock cycles at 16 MHz
625
ns
10.4.15
t12
AES core cycle time
250 (8)
24
(2)
ns
µs
10.4.16
fCLKM
Controller clock frequency at
pin 17 (CLKM)
Programmable via
register 0x03 (TRX_CTRL_0)
0
1(2)
2(2)
4(2)
8(2)
16(2)
1/4(2)
1/50(3)
1/25(4)
1/40(5)
1/16(6)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
10.4.17
tIRQ
IRQ_2, IRQ_3, IRQ_4 latency
Relative to the event to be
indicated
9(9)
µs
150
AT86RF212
8168A-AVR-06/08
AT86RF212
Notes:
1. Maximum pulse width less than (TX frame length + 16 µs)
2. All modes
3. Only in BPSK mode with fPSDU = 20 kbit/s
4. Only in BPSK mode with fPSDU = 40 kbit/s
5. Only in O-QPSK mode with fPSDU = 100/200/400 kbit/s
6. Only in O-QPSK mode with fPSDU = 250/500/1000 kbit/s
7. see Figure 4-3
8. see Figure 4-2
9. see Figure 5-2
10.5 General Transceiver Specifications
Test Conditions: TOP = 25°C, Vcc = 3.0 V
No.
Symbol
Parameter
Condition
Min.
10.5.1
fRF
Frequency range
1.0 MHz spacing
0.1 MHz spacing
0.1 MHz spacing
857
857
903
10.5.2
fCHIP
Chip rate
BPSK as specified in [1]
BPSK as specified in [1]
O-QPSK as specified in [1]
O-QPSK as specified in [1]
300
600
400
1000
kchip/s
kchip/s
kchip/s
kchip/s
10.5.3
fHDR
Header bit rate (SHR, PHR)
BPSK as specified in [1]
BPSK as specified in [1]
O-QPSK as specified in [1]
O-QPSK as specified in [1]
20
40
100
250
kbit/s
kbit/s
kbit/s
kbit/s
10.5.4
fPSDU
PSDU bit rate
BPSK as specified in [1]
BPSK as specified in [1]
O-QPSK as specified in [1]
O-QPSK as specified in [1]
O-QPSK
O-QPSK
O-QPSK
O-QPSK
20
40
100
250
200
400
500
1000
kbit/s
kbit/s
kbit/s
kbit/s
kbit/s
kbit/s
kbit/s
kbit/s
10.5.5
fCLK
Crystal oscillator frequency
Reference oscillator
16
MHz
10.5.6
tXTAL
Reference oscillator settling time
Leaving SLEEP state to clock
available at pin 17 (CLKM)
0.3
10.5.7
Reference oscillator accuracy
fPSDU = 20/40/100/250 kbit/s
fPSDU = 200/400/500/1000 kbit/s
10.5.8
Battery monitor threshold
deviation
Note:
-60
-40
Typ.
(1)
-0.1
0.0
Max.
Units
928
882.5
928.5
MHz
MHz
MHz
1
ms
+60 (1)
+40
ppm
ppm
0.1
V
1. A reference frequency accuracy of ±40 ppm is required by [1]
151
8168A-AVR-06/08
10.6 Transmitter Characteristics
Test Conditions: TOP = 25°C, Vcc = 3.0 V
No.
Symbol
Parameter
Condition
10.6.1
PTX
Nominal output power
Min.
Typ.
Max.
Units
Boost mode (1), BPSK
Boost mode (1), O-QPSK
5
8
10
dBm
dBm
dBm
10.6.2
PRANGE
Output power range
32 steps
32
dB
10.6.3
P1dB
1 dB compression point
Normal mode
Boost mode
5
8
dBm
dBm
10.6.4
EVM
Error vector magnitude
O-QPSK in European band
according to [1]
otherwise
25
% rms
6
% rms
-41
-29
-33
-29
dBm
dBm
dBm
dBm
-38
dBm
-60
-47
dBm
dBm
10.6.5
PHARM
BPSK modulation
PTX = 0 dBm
PTX = 5 dBm
PTX = 0 dBm
PTX = 5 dBm
Harmonics
2nd harmonic
3rd harmonic
10.6.6
PSD
Power spectrum density mask
European band, measured at first
side lobe using 100 kHz
bandwidth (integrated power from
400 to 500 kHz offset from
carrier), PTX = 0 dBm
10.6.7
PSPUR
Spurious emissions
30 – 1000 MHz
1 – 12.75 GHz
Except harmonics
Note:
1. Increased harmonics and spurious in boost mode
10.7 Receiver Characteristics
Test Conditions: TOP = 25°C, Vcc = 3.0 V
No.
Symbol
Parameter
Condition
10.7.1
PSENS
Receiver sensitivity
AWGN channel, PER ≤ 1%
20 kbit/s (1)
40 kbit/s (1)
100 kbit/s (1)
250 kbit/s (1)
PSDU length of 20 octets
PSDU length of 20 octets
PSDU length of 20 octets
PSDU length of 20 octets
-110
-108
-101
-100
dBm
dBm
dBm
dBm
200 kbit/s
400 kbit/s
500 kbit/s
1000 kbit/s
PSDU length of 127 octets
PSDU length of 127 octets
PSDU length of 127 octets
PSDU length of 127 octets
-97
-90
-97
-92
dBm
dBm
dBm
dBm
5
dB
-5
dBm
10.7.2
NF
Noise figure
10.7.3
PRXMAX
Maximum RX input level
152
PER ≤ 1%, PSDU length of 20
octets
Min.
Typ.
Max.
Units
AT86RF212
8168A-AVR-06/08
AT86RF212
No.
Symbol
10.7.4
Parameter
Condition
Adjacent and alternate adjacent
channel rejection,
-1 MHz
32
dB
+1 MHz
19
dB
-2 MHz
37
dB
+2 MHz
38
dB
-2 MHz
36
dB
+2 MHz
35
dB
-4 MHz
52
dB
+4 MHz
53
dB
-1 MHz
25
dB
+1 MHz
16
dB
-2 MHz
34
dB
+2 MHz
35
dB
-2 MHz
27
dB
+2 MHz
27
dB
-4 MHz
49
dB
+4 MHz
49
dB
BPSK with 20 kbit/s
PRX = -89 dBm, PER ≤ 1%
10.7.5
Adjacent and alternate adjacent
channel rejection,
BPSK with 40 kbit/s
PRX = -89 dBm, PER ≤ 1%
10.7.6
Adjacent and alternate adjacent
channel rejection,
O-QPSK with 100 kbit/s
PRX = -82 dBm, PER ≤ 1%
10.7.7
Adjacent and alternate adjacent
channel rejection,
O-QPSK with 250 kbit/s
PRX = -82 dBm, PER ≤ 1%
10.7.8
10.7.9
10.7.10
Min.
LO leakage
IIP3
IIP2
10.7.11
Typ.
Max.
Units
-67
dBm
rd
-12
dBm
nd
20
dBm
3 -order intercept point
2 -order intercept point
RSSI range
-94
Note:
-12
dBm
Max.
Units
1. IEEE 802.15.4-2006 compliant
10.8 Current Consumption Specifications
Test Conditions: TOP = 25°C, Vcc = 3.0 V, CLKM = OFF
No.
Symbol
Parameter
10.8.1
ITX_ACTIVE Supply current transmit mode
10.8.2
IRX_ON
10.8.3
10.8.4
Condition
Min.
Typ.
15
19
26
mA
mA
mA
Supply current receive (listen)
mode
9
mA
ITRX_OFF
Supply current idle mode
0.4
mA
ISLEEP
Supply current sleep mode
0.1
μA
PTX = 0 dBm
PTX = 5 dBm
PTX = 10 dBm (boost mode)
10.9 Crystal Parameter Requirements
No.
Symbol
Parameter
10.9.1
fXTAL
Crystal frequency
10.9.2
CL
Load capacitance
10.9.3
CSTATIC
Static capacitance
Condition
Min.
Typ.
Max.
16
8
Units
MHz
14
pF
7
pF
153
8168A-AVR-06/08
No.
Symbol
Parameter
10.9.4
R1
Series resistance
154
Condition
Min.
Typ.
Max.
Units
100
Ω
AT86RF212
8168A-AVR-06/08
AT86RF212
11 Typical Characteristics
11.1 Active Supply Current
The following charts showing each a typical behavior of the AT86RF212. These figures
are not tested during manufacturing. All power consumption measurements are
performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement
setup used for the measurements is shown in Figure 3-1.
Power consumption for the microcontroller required to program the radio transceiver is
not included in the measurement results.
The power consumption in SLEEP state mode is independent from CLKM master clock
rate selection.
The current consumption is a function of several factors such as: operating voltage,
operating frequency, loading of I/O pins, switching rate of I/O pins, and ambient
temperature. The dominating factors are operating voltage and ambient temperature.
If possible the measurement results are not affected by current drawn from I/O pins.
Register, SRAM or Frame Buffer read or write accesses are not performed during
current consumption measurements.
11.1.1 TRX_OFF State
Figure 11-1. Current Consumption in TRX_OFF State; CLKM off, TOP = 25°C
Current Consumption (mA)
0,50
0,40
0,30
0,20
0,10
0,00
1,6
1,8
2
2,2
2,4
2,6
2,8
3
3,2
3,4
3,6
3,8
EVDD (V)
155
8168A-AVR-06/08
11.1.2 PLL_ON State
Figure 11-2. Current Consumption in PLL_ON State; O-QPSK 250 kbit/s Mode,
Channel 5, CLKM off, TOP = 25°C
Current Consumption (mA)
6,0
5,5
5,0
4,5
4,0
3,5
3,0
1,6
1,8
2
2,2
2,4
2,6
2,8
3
3,2
3,4
3,6
3,8
EVDD (V)
11.1.3 RX_ON State
Figure 11-3. Current Consumption in RX_ON State; O-QPSK 250 kbit/s Mode, Channel
5, CLKM off, TOP = 25°C
Current Consumption (mA)
11,0
10,5
10,0
9,5
9,0
8,5
8,0
1,6
1,8
2
2,2
2,4
2,6
2,8
3
3,2
3,4
3,6
3,8
EVDD (V)
156
AT86RF212
8168A-AVR-06/08
AT86RF212
11.1.4 TX_BUSY State
Figure 11-4. Current Consumption in TX_BUSY State; +5 dBm TX Power, O-QPSK
250 kbit/s Mode, Channel 5, CLKM off, TOP = 25°C
Current Consumption (mA)
19,0
18,5
18,0
17,5
17,0
16,5
16,0
15,5
15,0
1,6
1,8
2
2,2
2,4
2,6
2,8
3
3,2
3,4
3,6
3,8
EVDD (V)
Figure 11-5. Current Consumption in TX_BUSY State; +10 dBm TX Power, O-QPSK
250 kbit/s Mode, Channel 5, CLKM off, TOP = 25°C
Current Consumption (mA)
27,0
26,0
25,0
24,0
23,0
22,0
21,0
20,0
1,6
1,8
2
2,2
2,4
2,6
2,8
3
3,2
3,4
3,6
3,8
EVDD (V)
157
8168A-AVR-06/08
12 Register Reference
The AT86RF212 provides a register space of 64 8-bit registers, used to configure,
control, and monitor the radio transceiver.
Note:
All registers not mentioned within the following table are reserved for internal
use and must not be overwritten. When writing to a register, any reserved bits
shall be overwritten only with their reset value.
Table 12-1. Register Summary
Addr.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x00
-
-
-
-
-
-
-
-
-
0x01
TRX_STATUS
CCA_DONE
CCA_STATUS
-
TRX_STATUS[4]
TRX_STATUS[3]
TRX_STATUS[2]
TRX_STATUS[1]
TRX_STATUS[0]
38,58,86
0x02
TRX_STATE
TRX_CMD[4]
TRX_CMD[3]
TRX_CMD[2]
TRX_CMD[1]
TRX_CMD[0]
39,59
0x03
TRX_CTRL_0
PAD_IO[1]
PAD_IO[0]
PAD_IO_CLKM[1]
PAD_IO_CLKM[0]
CLKM_SHA_SEL
CLKM_CTRL[2]
CLKM_CTRL[1]
CLKM_CTRL[0]
8119
0x04
TRX_CTRL_1
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
SPI_CMD_MODE[1]
SPI_CMD_MODE[0]
IRQ_MASK_MODE
IRQ_POLARITY
20,26,60,
TRAC_STATUS[2] TRAC_STATUS[1] TRAC_STATUS[0]
78,142,
144,146
0x05
PHY_TX_PWR
PA_BOOST
GC_PA[1]
GC_PA[0]
TX_PWR[4]
TX_PWR[3]
TX_PWR[2]
TX_PWR[1]
TX_PWR[0]
106
0x06
PHY_RSSI
RX_CRC_VALID
RND_VALUE[1]
RND_VALUE[0]
RSSI[4]
RSSI[3]
RSSI[2]
RSSI[1]
RSSI[0]
78,80,
0x07
PHY_ED_LEVEL
ED_LEVEL[7]
ED_LEVEL[6]
ED_LEVEL[5]
ED_LEVEL[4]
ED_LEVEL[3]
ED_LEVEL[2]
ED_LEVEL[1]
ED_LEVEL[0]
83
0x08
PHY_CC_CCA
CCA_REQUEST
CCA_MODE[1]
CCA_MODE[0]
CHANNEL[4]
CHANNEL[3]
CHANNEL[2]
CHANNEL[1]
CHANNEL[0]
87,89,
0x09
CCA_THRES
-
-
-
-
CCA_ED_THRES[3]
CCA_ED_THRES[2]
CCA_ED_THRES[1]
CCA_ED_THRES[0]
88,90
0x0A
-
-
-
-
-
-
-
-
-
138
124
0x0B
SFD_VALUE
SFD_VALUE[7]
SFD_VALUE[6]
SFD_VALUE[5]
SFD_VALUE[4]
SFD_VALUE[3]
SFD_VALUE[2]
SFD_VALUE[1]
0x0C
TRX_CTRL_2
RX_SAFE_MODE
TRX_OFF_AVDD_EN
-
-
BPSK_OQPSK
SUB_MODE
OQPSK_DATA_RATE[1]
0x0D
ANT_DIV
ANT_SEL
-
-
-
-
ANT_EXT_SW_EN
ANT_CTRL[1]
0x0E
IRQ_MASK
MASK_BAT_LOW
MASK_TRX_UR
MASK_AMI
0x0F
IRQ_STATUS
BAT_LOW
TRX_UR
AMI
0x10
VREG_CTRL
AVREG_EXT
AVDD_OK
-
-
DVREG_EXT
DVDD_OK
0x11
BATMON
-
-
BATMON_OK
BATMON_HR
BATMON_VTH[3]
BATMON_VTH[2]
0x12
XOSC_CTRL
XTAL_MODE[3]
XTAL_MODE[2]
XTAL_MODE[1]
XTAL_MODE[0]
XTAL_TRIM[3]
XTAL_TRIM[2]
0x13
CC_CTRL_0
CC_NUMBER[7]
CC_NUMBER[6]
CC_NUMBER[5]
CC_NUMBER[4]
CC_NUMBER[3]
0x14
CC_CTRL_1
-
-
-
-
-
0x15
RX_SYN
RX_PDT_DIS
-
-
-
-
-
SFD_VALUE[0]
148
OQPSK_DATA_RATE[0] 95,114,
147
0x16
RF_CTRL_0
PA_LT[1]
PA_LT[0]
0x17
XAH_CTRL_1
CSMA_LBT_MODE
-
0x18
FTN_CTRL
FTN_START
-
-
0x19
RF_CTRL_1
RF_MC[3]
RF_MC[2]
RF_MC[1]
ANT_CTRL[0]
140
MASK_CCA_ED_READY MASK_TRX_END MASK_RX_START MASK_PLL_UNLOCK MASK_PLL_LOCK
25
CCA_ED_READY
PLL_LOCK
26
-
-
113
BATMON_VTH[1]
BATMON_VTH[0]
116
XTAL_TRIM[1]
XTAL_TRIM[0]
121
CC_NUMBER[2]
CC_NUMBER[1]
CC_NUMBER[0]
125
CC_BAND[2]
CC_ BAND[1]
CC_ BAND[0]
125
TRX_END
RX_START
PLL_UNLOCK
RX_PDT_LEVEL[3] RX_PDT_LEVEL[2] RX_PDT_LEVEL[1] RX_PDT_LEVEL[0]
99
-
-
GC_TX_OFFS[1]
GC_TX_OFFS[0]
105
-
AACK_ACK_TIME
AACK_PROM_MODE
-
61,72,90
-
-
-
-
-
127
RF_MC[0]
-
-
-
-
99
AACK_FLTR_RES_FT AACK_UPLD_RES_FT
0x1A
PLL_CF
PLL_CF_START
-
-
-
-
-
-
-
126
0x1B
PLL_DCU
PLL_DCU_START
-
-
-
-
-
-
-
126
0x1C
PART_NUM
PART_NUM[7]
PART_NUM[6]
PART_NUM[5]
PART_NUM[4]
PART_NUM[3]
PART_NUM[2]
PART_NUM[1]
PART_NUM[0]
21
0x1D
VERSION_NUM VERSION_NUM[7] VERSION_NUM[6] VERSION_NUM[5] VERSION_NUM[4] VERSION_NUM[3] VERSION_NUM[2] VERSION_NUM[1] VERSION_NUM[0]
21
0x1E
MAN_ID_0
MAN_ID_0[7]
MAN_ID_0[6]
MAN_ID_0[5]
MAN_ID_0[4]
MAN_ID_0[3]
MAN_ID_0[2]
MAN_ID_0[1]
MAN_ID_0[0]
21
0x1F
MAN_ID_1
MAN_ID_1[7]
MAN_ID_1[6]
MAN_ID_1[5]
MAN_ID_1[4]
MAN_ID_1[3]
MAN_ID_1[2]
MAN_ID_1[1]
MAN_ID_1[0]
22
0x20
SHORT_ADDR_0
SHORT_ADDR_0[7]
SHORT_ADDR_0[6]
SHORT_ADDR_0[5]
SHORT_ADDR_0[4]
SHORT_ADDR_0[3]
SHORT_ADDR_0[2]
SHORT_ADDR_0[1]
SHORT_ADDR_0[0]
73
0x21
SHORT_ADDR_1
SHORT_ADDR_1[7]
SHORT_ADDR_1[6]
SHORT_ADDR_1[5]
SHORT_ADDR_1[4]
SHORT_ADDR_1[3]
SHORT_ADDR_1[2]
SHORT_ADDR_1[1]
SHORT_ADDR_1[0]
73
0x22
PAN_ID_0
PAN_ID_0[7]
PAN_ID_0[6]
PAN_ID_0[5]
PAN_ID_0[4]
PAN_ID_0[3]
PAN_ID_0[2]
PAN_ID_0[1]
PAN_ID_0[0]
73
0x23
PAN_ID_1
PAN_ID_1[7]
PAN_ID_1[6]
PAN_ID_1[5]
PAN_ID_1[4]
PAN_ID_1[3]
PAN_ID_1[2]
PAN_ID_1[1]
PAN_ID_1[0]
73
158
AT86RF212
8168A-AVR-06/08
AT86RF212
Addr.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x24
IEEE_ADDR_0
IEEE_ADDR_0[7]
IEEE_ADDR_0[6]
IEEE_ADDR_0[5]
IEEE_ADDR_0[4]
IEEE_ADDR_0[3]
IEEE_ADDR_0[2]
IEEE_ADDR_0[1]
IEEE_ADDR_0[0]
74
0x25
IEEE_ADDR_1
IEEE_ADDR_1[7]
IEEE_ADDR_1[6]
IEEE_ADDR_1[5]
IEEE_ADDR_1[4]
IEEE_ADDR_1[3]
IEEE_ADDR_1[2]
IEEE_ADDR_1[1]
IEEE_ADDR_1[0]
74
0x26
IEEE_ADDR_2
IEEE_ADDR_2[7]
IEEE_ADDR_2[6]
IEEE_ADDR_2[5]
IEEE_ADDR_2[4]
IEEE_ADDR_2[3]
IEEE_ADDR_2[2]
IEEE_ADDR_2[1]
IEEE_ADDR_2[0]
74
0x27
IEEE_ADDR_3
IEEE_ADDR_3[7]
IEEE_ADDR_3[6]
IEEE_ADDR_3[5]
IEEE_ADDR_3[4]
IEEE_ADDR_3[3]
IEEE_ADDR_3[2]
IEEE_ADDR_3[1]
IEEE_ADDR_3[0]
74
0x28
IEEE_ADDR_4
IEEE_ADDR_4[7]
IEEE_ADDR_4[6]
IEEE_ADDR_4[5]
IEEE_ADDR_4[4]
IEEE_ADDR_4[3]
IEEE_ADDR_4[2]
IEEE_ADDR_4[1]
IEEE_ADDR_4[0]
75
0x29
IEEE_ADDR_5
IEEE_ADDR_5[7]
IEEE_ADDR_5[6]
IEEE_ADDR_5[5]
IEEE_ADDR_5[4]
IEEE_ADDR_5[3]
IEEE_ADDR_5[2]
IEEE_ADDR_5[1]
IEEE_ADDR_5[0]
75
0x2A
IEEE_ADDR_6
IEEE_ADDR_6[7]
IEEE_ADDR_6[6]
IEEE_ADDR_6[5]
IEEE_ADDR_6[4]
IEEE_ADDR_6[3]
IEEE_ADDR_6[2]
IEEE_ADDR_6[1]
IEEE_ADDR_6[0]
75
0x2B
IEEE_ADDR_7
IEEE_ADDR_7[7]
IEEE_ADDR_7[6]
IEEE_ADDR_7[5]
IEEE_ADDR_7[4]
IEEE_ADDR_7[3]
IEEE_ADDR_7[2]
IEEE_ADDR_7[1]
IEEE_ADDR_7[0]
75
0x2C
XAH_CTRL_0 MAX_FRAME_RETRIES[3] MAX_FRAME_RETRIES[2] MAX_FRAME_RETRIES[1] MAX_FRAME_RETRIES[0] MAX_CSMA_RETRIES[2] MAX_CSMA_RETRIES[1] MAX_CSMA_RETRIES[0] SLOTTED_OPERATION
0x2D
CSMA_SEED_0 CSMA_SEED_0[7] CSMA_SEED_0[6] CSMA_SEED_0[5] CSMA_SEED_0[4] CSMA_SEED_0[3] CSMA_SEED_0[2] CSMA_SEED_0[1] CSMA_SEED_0[0]
0x2E
CSMA_SEED_1 AACK_FVN_MODE[1]
AACK_FVN_MODE[0]
AACK_SET_PD
AACK_DIS_ACK
AACK_I_AM_COORD CSMA_SEED_1[2] CSMA_SEED_1[1] CSMA_SEED_1[0]
0x2F
CSMA_BE
MAX_BE[3]
MAX_BE[2]
MAX_BE[1]
MAX_BE[0]
MIN_BE[3]
MIN_BE[2]
MIN_BE[1]
MIN_BE[0]
….
-
-
-
-
-
-
-
-
-
63
63
64,75
65
The reset values of the AT86RF212 registers in state P_ON(1, 2, 3) are shown in Table
12-2.
Note:
All reset values in Table 12-2 are only valid after a power on reset. After a reset
procedure (/RST = L) as described in section 5.1.4.5, the reset values of
selected registers (e.g. registers 0x01, 0x10, 0x11, 0x30) can differ from that in
Table 12-2.
Table 12-2. Register Summary – Reset Values
Address
Reset Value
Address
Reset Value
Address
Reset Value
Address
(1)
Reset Value
0x20
0xFF
0x30
0x00(3)
0x00
0x00
0x10
0x00
0x01
0x00
0x11
0x02(2)
0x21
0xFF
0x31
0x00
0x02
0x00
0x12
0xF0
0x22
0xFF
0x32
0x00
0x03
0x19
0x13
0x00
0x23
0xFF
0x33
0x00
0x04
0x20
0x14
0x00
0x24
0x00
0x34
0x3F
0x05
0x60
0x15
0x00
0x25
0x00
0x35
0x00
0x06
0x00
0x16
0x31
0x26
0x00
0x36
0x00
0x07
0xFF
0x17
0x00
0x27
0x00
0x37
0x00
0x08
0x25
0x18
0x58
0x28
0x00
0x38
0x00
0x09
0x77
0x19
0x00
0x29
0x00
0x39
0x40
0x0A
0x17
0x1A
0x48
0x2A
0x00
0x3A
0x00
0x0B
0xA7
0x1B
0x40
0x2B
0x00
0x3B
0x00
0x0C
0x24
0x1C
0x06
0x2C
0x38
0x3C
0x00
0x0D
0x01
0x1D
0x01
0x2D
0xEA
0x3D
0x00
0x0E
0x00
0x1E
0x1F
0x2E
0x42
0x3E
0x00
0x0F
0x00
0x1F
0x00
0x2F
0x53
0x3F
0x00
Notes:
1. While the reset value of register 0x10 is 0x00, any practical access to the register
is only possible when DVREG is active. So this register is always read out as
0x04. For details refer to section 7.5.
2. While the reset value of register 0x11 is 0x02, any practical access to the register
is only possible when BATMON is activated. So this register is always read out as
0x22 in P_ON state. For details refer to section 7.6.
3. While the reset value of register 0x30 is 0x00, any practical access to the register
159
8168A-AVR-06/08
is only possible when the radio transceiver is accessible. So the register is
usually read out as:
a) 0x11 after a reset in P_ON state
b) 0x07 after a reset in any other state
160
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8168A-AVR-06/08
AT86RF212
13 Abbreviations
ACK
ADC
AES
AGC
AVREG
AWGN
BATMON
BBP
BPF
BPSK
CBC
CCA
CF
CRC
CS
CSMA-CA
CW
DAC
DVREG
ECB
ED
ESD
FCF
FCS
FIFO
FTN
IC
IF
I/O
IRQ
ISM
LBT
LDO
LNA
LO
LPF
LQI
LSB
MAC
MHR
MIC
MISO
MOSI
MSB
MSDU
O-QPSK
PA
PAN
PER
PHR
PHY
PLL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Acknowledgement
Analog-to-Digital Converter
Advanced Encryption Standard
Automatic Gain Control
Analog Voltage Regulator
Additive White Gaussian Noise
Battery Monitor
Base-Band Processor
Band-Pass Filter
Binary Phase Shift Keying
Cipher Block Chaining
Clear Channel Assessment
Center Frequency
Cyclic Redundancy Check
Carrier Sense
Carrier Sense Multiple Access – Collision Avoidance
Continuous Wave
Digital-to-Analog Converter
Digital Voltage Regulator
Electronic Code Book
Energy Detect
Electro Static Discharge
Frame Control Field
Frame Check Sequence
First In First Out
Filter Tuning
Integrated Circuit
Intermediate Frequency
Input/Output
Interrupt Request
Industrial Scientific Medical
Listen Before Talk
Low Dropout
Low-Noise Amplifier
Local Oscillator
Low-Pass Filter
Link Quality Indication
Least Significant Bit
Medium Access Control
MAC Header
Message Integrity Code
Master Input Slave Output
Master Output Slave Input
Most Significant Bit
MAC Service Data Unit
Offset Quadrature Phase Shift Keying
Power Amplifier
Personal Area Network
Packet Error Rate
PHY Header
Physical Layer
Phase-Looked Loop
161
8168A-AVR-06/08
PPDU
PPF
PRBS
PSD
PSDU
QFN
RC
RF
RSSI
RX
SFD
SHR
SPI
SRAM
SRD
TRX
TX
VCO
XOSC
XTAL
162
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PHY Protocol Data Unit
Poly-Phase Filter
Pseudo Random Binary Sequence
Power Spectrum Density
PHY Service Data Unit
Quad Flat No-Lead Package
Raised Cosine
Radio Frequency
Received Signal Strength Indicator
Receiver
Start-Of-Frame Delimiter
Synchronization Header
Serial Peripheral Interface
Static Random Access Memory
Short Range Device
Transceiver
Transmitter
Voltage Controlled Oscillator
Crystal Oscillator
Crystal
AT86RF212
8168A-AVR-06/08
AT86RF212
14 Ordering Information
Ordering Code
Package
Voltage Range
AT86RF212-ZU
QN
1.8V – 3.6V
Temperature Range
Industrial (-40° C to +85° C) Lead-free/Halogen-free
Package Type
Description
QN
32QN2, 32-lead 5.0x5.0 mm Body, 0.50 mm Pitch, Quad Flat No-lead Package (QFN) Sawn
Note:
T&R quantity 4,000.
Please contact your local Atmel sales office for more detailed ordering information and
minimum quantities.
15 Soldering Information
Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C.
16 Package Thermal Properties
Thermal Resistance
Velocity [m/s]
Theta ja [K/W]
0
40.9
1
35.7
2.5
32.0
163
8168A-AVR-06/08
17 Package Drawing – 32QN2
164
AT86RF212
8168A-AVR-06/08
AT86RF212
Appendix A – Continuous Transmission Test Mode
A.1 – Overview
The AT86RF212 offers a Continuous Transmission Test Mode to support application /
production tests as well as certification tests. Using this test mode, the radio transceiver
transmits continuously a previously transferred frame (PRBS mode) or a continuous
wave signal (CW mode).
In CW mode four different signal frequencies per channel can be transmitted:
•
•
•
•
f1 = fCH + 0.25 MHz
f2 = fCH - 0.25 MHz
f3 = fCH + 0.1 MHz
f4 = fCH - 0.1 MHz
using O-QPSK 1000 kbit/s mode
using O-QPSK 1000 kbit/s mode
using O-QPSK 400 kbit/s mode
using O-QPSK 400 kbit/s mode
fCH is the channel center frequency, refer to section 7.8.2.
Note, in CW mode it is not possible to transmit an RF signal directly on the channel
center frequency.
PSDU data in the Frame Buffer must contain at least a valid PHR (see section 6.1). It is
recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data
for the PRBS mode. After transmission of two symbols PSDU data and is repeated
continuously.
A.2 – Configuration
Before enabling Continuous Transmission Test Mode all register configurations shall be
done as follows:
• TX channel setting (optional)
• TX output power setting (optional)
• Mode selection (PRBS / CW)
Register write accesses to register 0x36 and 0x1C enable the Continuous Transmission
Test Mode.
The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the
TX_START command to register 0x02.
Even for CW signal transmission it is required to write valid PSDU data to the Frame
Buffer. For PRBS mode it is recommended to write a frame of maximum length.
The detailed programming sequence is shown in Table A-1. The column R/W informs
about writing (W) or reading (R) a register or the Frame Buffer.
165
8168A-AVR-06/08
Table A-1. Continuous Transmission Programming Sequence
Step
Action
Register
R/W
Value
Description
1
RESET
2
Register Access
0x0E
W
0x01
Set IRQ mask register, enable IRQ_0
(PLL_LOCK)
3
Register Access
0x04
W
0x00
Disable TX_AUTO_CRC_ON
4
Register Access
0x02
W
0x03
Set radio transceiver state TRX_OFF
5
Register Access
W
Set channel, refer to section 7.8.2.
6
Register Access
W
Set TX output power, refer to section
7.3.4
7
Register Access
0x01
R
0x08
Verify TRX_OFF state
8
Register Access
0x36
W
0x0F
Enable Continuous Transmission Test
Mode – step # 1
9
Register Access
0x0C
W
Reset AT86RF212
CW mode: Enable High Data Rate
Mode without scrambler, 400 kbit/s or
1000 kbit/s (register values 0x0A or
0X0E, respectively)
PRBS mode: Select modulation
scheme, refer to section 7.1.5
Write PSDU data (even for CW mode),
refer to Table A-2. Frame Buffer content
varies for different modulation schemes.
10
Frame Buffer
Write Access
11
Register Access
0x1C
W
0x54
Enable Continuous Transmission Test
Mode – step # 2
12
Register Access
0x1C
W
0x46
Enable Continuous Transmission Test
Mode – step # 3
13
Register Access
0x02
W
0x09
Enable PLL_ON state
14
Interrupt event
0x0F
R
0x01
Wait for IRQ_0 (PLL_LOCK)
15
Register Access
0x02
W
0x02
Initiate Transmission,
enter BUSY_TX state
16
Measurement
17
Register Access
18
RESET
W
Perform measurement
0x1C
W
0x00
Disable Continuous Transmission Test
Mode
Reset AT86RF212
The content of the Frame Buffer has to be defined for Continuous Transmission PRBS
mode or CW mode. To measure the power spectral density (PSD) mask of the
transmitter it is recommended to use a random sequence of maximum length for the
PSDU data.
To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame
Buffer, for details refer to Table A-2.
166
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8168A-AVR-06/08
AT86RF212
Table A-2. Frame Buffer Content for various Continuous Transmission Modulation
Schemes
Step
Action
Frame Content
Comment
11
Frame Buffer
Access
Random Sequence
modulated RF signal
0x00 (each byte)
fCH – 0.1 MHz, CW signal
fCH – 0.25 MHz, CW signal
0xFF (each byte)
fCH + 0.1 MHz, CW signal
fCH + 0.25 MHz, CW signal
A.3 – Register Description
Register 0x36 (TST_CTRL_DIGI):
Register TST_CTRL_DIGI enables the continuous transmission test mode.
Table 0-3. Register 0x36 (TST_CTRL_DIGI)
Bit
7
6
5
4
Name
Reserved
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
Bit
3
2
1
0
Name
TST_CTRL_DIG
TST_CTRL_DIG
TST_CTRL_DIG
TST_CTRL_DIG
Read/Write
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
• Bit 7:4 – Reserved
• Bit 3:0 – TX_CTRL_DIG
These register bits enable continuous transmission:
Table 0-4. Continuous Transmission
Register Bits
TST_CTRL_DIG
Value
Description
0x0
Continuous Transmission disabled
0xF
Continuous Transmission enabled
0x1 – 0xE
Reserved
167
8168A-AVR-06/08
Appendix B – Errata
AT86RF212 Rev. A
No known errata.
168
AT86RF212
8168A-AVR-06/08
AT86RF212
References
[1]
IEEE Standard 802.15.4TM-2006: Wireless Medium Access Control (MAC) and
Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area
Networks (WPANs)
[2]
IEEE Standard 802.15.4TM-2003: Wireless Medium Access Control (MAC) and
Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area
Networks (WPANs)
[3]
ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for
electrostatic discharge sensitivity testing – Human Body Model (HBM).
[4]
ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic
discharge sensitivity testing – Charged Device Model (CDM).
[5]
NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal
Information Processing Standards Publication 197, US Department of
Commerce/NIST, November 26, 2001
169
8168A-AVR-06/08
Table of Contents
Disclaimer...............................................................................................2
1 Overview ..............................................................................................2
1.1 General Circuit Description .................................................................................... 2
2 Pin Configuration................................................................................4
2.1 Pin-out Diagram...................................................................................................... 4
2.2 Pin Description ....................................................................................................... 4
3 Application Circuits ..........................................................................10
3.1 Basic Application Schematic ................................................................................ 10
3.2 Extended Feature Set Application Schematic...................................................... 11
4 Microcontroller Interface ..................................................................13
4.1 Overview............................................................................................................... 13
4.2 SPI Timing Description......................................................................................... 14
4.3 SPI Protocol.......................................................................................................... 15
4.4 PHY Status Information........................................................................................ 19
4.5 Radio Transceiver Identification ........................................................................... 20
4.6 Sleep/Wake-up and Transmit Signal (SLP_TR)................................................... 22
4.7 Interrupt Logic....................................................................................................... 24
5 Operating Modes...............................................................................28
5.1 Basic Operating Mode.......................................................................................... 28
5.2 Extended Operating Mode ................................................................................... 40
6 Functional Description .....................................................................66
6.1 Introduction – IEEE 802.15.4-2006 Frame Format .............................................. 66
6.2 Frame Filter .......................................................................................................... 70
6.3 Frame Check Sequence (FCS) ............................................................................ 76
6.4 Received Signal Strength Indicator (RSSI) .......................................................... 79
6.5 Energy Detection (ED) ......................................................................................... 81
6.6 Clear Channel Assessment (CCA)....................................................................... 84
6.7 Listen Before Talk (LBT) ...................................................................................... 88
6.8 Link Quality Indication (LQI) ................................................................................. 91
7 Module Description...........................................................................92
7.1 Physical Layer Modes .......................................................................................... 92
7.2 Receiver (RX) ....................................................................................................... 97
7.3 Transmitter (TX) ................................................................................................. 100
7.4 Frame Buffer....................................................................................................... 108
7.5 Voltage Regulators (AVREG, DVREG).............................................................. 111
170
AT86RF212
8168A-AVR-06/08
AT86RF212
7.6 Battery Monitor (BATMON) ................................................................................ 115
7.7 Crystal Oscillator (XOSC) and Clock Output (CLKM) ........................................ 117
7.8 Frequency Synthesizer (PLL)............................................................................. 122
7.9 Automatic Filter Tuning (FTN) ............................................................................ 126
8 Radio Transceiver Usage ...............................................................128
8.1 Frame Receive Procedure ................................................................................. 128
8.2 Frame Transmit Procedure ................................................................................ 129
9 Extended Feature Set .....................................................................131
9.1 Security Module (AES) ....................................................................................... 131
9.2 Random Number Generator............................................................................... 138
9.3 Antenna Diversity ............................................................................................... 139
9.4 RX/TX Indicator .................................................................................................. 141
9.5 RX Frame Time Stamping.................................................................................. 143
9.6 Frame Buffer Empty Indicator ............................................................................ 145
9.7 Dynamic Frame Buffer Protection ...................................................................... 147
9.8 Configurable Start-Of-Frame Delimiter (SFD).................................................... 148
10 Electrical Characteristics .............................................................149
10.1 Absolute Maximum Ratings.............................................................................. 149
10.2 Operating Range .............................................................................................. 149
10.3 Digital Pin Specifications .................................................................................. 149
10.4 Digital Interface Timing Characteristics............................................................ 150
10.5 General Transceiver Specifications ................................................................. 151
10.6 Transmitter Characteristics .............................................................................. 152
10.7 Receiver Characteristics .................................................................................. 152
10.8 Current Consumption Specifications................................................................ 153
10.9 Crystal Parameter Requirements ..................................................................... 153
11 Typical Characteristics.................................................................155
11.1 Active Supply Current....................................................................................... 155
12 Register Reference .......................................................................158
13 Abbreviations ................................................................................161
14 Ordering Information ....................................................................163
15 Soldering Information...................................................................163
16 Package Thermal Properties........................................................163
17 Package Drawing – 32QN2 ...........................................................164
Appendix A – Continuous Transmission Test Mode ...................... 165
A.1 – Overview ......................................................................................................... 165
171
8168A-AVR-06/08
A.2 – Configuration................................................................................................... 165
A.3 – Register Description........................................................................................ 167
Appendix B – Errata...........................................................................168
AT86RF212 Rev. A .................................................................................................. 168
References..........................................................................................169
Table of Contents...............................................................................170
172
AT86RF212
8168A-AVR-06/08
Disclaimer
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8168A-AVR-06/08