1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 K K PLL bringup: 1. VCTCXO starts up 2. FX3 brings up transceiver, sets CLKOUT to FPGA 3. FX3 programs FPGA 4. FPGA writes to PLL, initializes PLL 5. PLL locks to external ref if avail. 6. If no ref, PLL tristated via SPI J J 3.3V_CLK:1 3.3V_CLK:1 3.3V_CLK:1 R128 D100 10K C111 2 3 0.1uF 0.1uF 3.3V_CLK:1 0.1uF 2345 15dBm max. (3.5V into 50 ohms) C107 142−0701−871 6 7 16 17 18 1 SMA External Reference 3.3V_CLK:1 C106 C104 1 R126 10K ADF4001 11 0.1uF 3.3V_CLK:1 5 R110 49.9 3 DG4157DL U103 B0 A H 1 B1 2 GND S 6 CPGND 8 ref_sel Rset 3.3V:1 GPSDO G L100 MI1206K601R−10 C101 0.1uF C102 22uF X5R 6.3V 8 3.3V_In M9107 1 GND GPS antenna Enter_ISP Serial_In SCLK pll_sclk_filt SDA 13 pll_mosi_filt SLE 14 pll_ce_filt Assume 400Hz/Volt 4kHz loop bandwidth 10MHz compare frequency 5mA CP current reduce C139 by the load cap of trace + tune Eff. Kv is adjusted based on the resistor div formed by R124 and the impedance of Cat DAC when disabled (if R118 installed) C137 180pF vcxo_tune H C138 2.2nF G 3.3V_CLK:1 U100 10MHz_Out 2 Lock_OK 3 PPS_Out 4 5V_Out 6 L107 MI1206K601R−10 100 gps_lock R127 150 PPS_IN_INT 4 C105 10uF X5R 6.3V NMEA_Out 12 gps_txd_nmea Serial_Out 15 gps_txd C109 0.1uF 2 VCTCXO OUT 3 ENB/TUNE 1 Vcc GND X100 pll_lock R101 2.2K pll_lock_filt pll_sclk R105 1K pll_sclk_filt pll_mosi R107 1K pll_mosi_filt pll_ce R112 1K pll_ce_filt F vcxo_tune C119 C108 47uF 6.3V X5R E C115 C120 C121 C122 470pF 470pF 470pF 470pF 470pF R122 510K 2 E Antenna GND gps_rxd 14 auxdac1 R121 1M pll_lock_filt LAYOUT: R110 and C150 Should be close to U101 11 13 2345 142−0701−871 R125 47.0K 1% C139 82pF 12 R106 GND 10 GND 4.7K 1 7 F PPS_In 9 5 DNP CONFIGURE PLL_LOCK AS OPEN DRAIN! R100 J101 R118 MUXOUT 3 2 10 9 21 R111 4.7K 100K I 1 15 REFIN 19 SN74LVC1G3157 works too R124 20 RFIN_B 100pF C150 0.1uF 4 CP C151 5 RFIN_A 0.1uF 4 xo_to_pll C112 Vcc CE R120 1M U101 AVDD AVDD DVDD DVDD VP I C100 0.1uF AGND AGND DGND DGND PAD J100 3.3V_CLK:1 R123 510K S100 1 C118 JLEAD_SW 0.01uF 3.3V_CLK:1 3.3V:1 D U104 CDLVC1103PWR U106 C117 SN74LVC1G04 R113 4 1 CLKIN 2 1G 0.1uF 2 net=3.3V_CLK:5 net=GND:3 Self−biasing clock squarer Vcc LED100 C GPSDO lock LED 1 U102 SN74AUP1T57 3.3V_CLK:1 Y0 3 Y1/NC 8 Y2/NC 5 Y3/NC 7 GND Place at U106 xo_out To transceiver R119 C 5 B 6 2345 Y R104 2K C103 1000pF 3.3V_CLK:1 PPS_IN_EXT C110 10uF X5R 6.3V C Vcc R102 49.9 5V max. A 1 FIN1001 4 3 codec_main_clk_p codec_main_clk_n net=3.3V_CLK:1 net=GND:2 C113 Buffer to FPGA Place near U104 3.3V_CLK:1 0.1uF B GND R109 10K B R103 1K 4 xo_to_pll To PLL RF in C114 Place at U105 0.1uF 2 1 5 J104 External PPS input 142−0701−871 gps_lock 47 U105 Q100 3 47 4 2 R108 150 6 D C116 B200 Clock 0.1uF A A TITLE FILE: clock.sch 1 PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OF 8 15 REVISION: 2 DRAWN BY: nick, matt 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Q Q AD9361−PWR 1.3V_CAT:1 AD9361−DATA A11 U2 1.3V:1 P1_D8/RX_D4_N codec_d19 J9 P1_D7/RX_D3_P codec_d18 K8 P1_D6/RX_D3_N codec_d17 J10 P1_D5/RX_D2_P codec_d16 K9 P1_D4/RX_D2_N codec_d15 J11 P1_D3/RX_D1_P L301 E7 P0_D11/TX_D5_P codec_d10 F8 P0_D10/TX_D5_N codec_d9 D7 P0_D9/TX_D4_P codec_d8 E8 P0_D8/TX_D4_N codec_d7 D8 P0_D7/TX_D3_P codec_d6 E9 MI1206K601R−10 C310 1000pF C331 1uF VDDA1P3_TX_LO VSSD F9 B10 VDDA1P3_TX_VCO_LDO VSSD F11 cat_mosi J4 SPI_MOSI CTRL_IN0 C5 codec_ctrl_in0 B11 TX_VCO_LDO_OUT VSSD G12 cat_miso L6 SPI_MISO CTRL_IN1 C6 codec_ctrl_in1 D2 VDDA1P3_RX_RF VSSD H7 cat_sclk J5 SPI_CLK CTRL_IN3 D5 codec_ctrl_in3 D3 VDDA1P3_RX_TX VSSD H10 cat_ce K6 SPI_CE CTRL_IN2 D6 codec_ctrl_in2 E2 VDDA1P3_RX_LO VSSD K12 codec_txrx H4 TX/RX CTRL_OUT0 D4 codec_ctrl_out0 E3 VDDA1P3_TX_LO_BUFFER VSSA A6 codec_sync H5 SYNC_IN CTRL_OUT1 E4 codec_ctrl_out1 F2 VDDA1P3_RX_VCO_LDO VSSA B1 codec_reset K5 RESETB CTRL_OUT2 E5 codec_ctrl_out2 C314 R301 1000pF 1 VDDD1P3_DIG VSSA B2 codec_en_agc G5 EN_AGC RX_VCO_LDO_OUT VSSA B12 codec_enable G3 VDDA1P1_RX_VCO VSSA C2 VDD_INTERFACE VSSA J3 VDDA1P3_RX_SYNTH K3 K4 1.3V_SYNTH:1 C315 1uF D9 P0_D5/TX_D2_P codec_d4 E10 P0_D4/TX_D2_N codec_d3 D10 P0_D3/TX_D1_P codec_d2 E11 P0_D2/TX_D1_N codec_d1 D11 P0_D1/TX_D0_P codec_d0 E12 P0_D0/TX_D0_N G7 K CTRL_OUT3 E6 codec_ctrl_out3 CTRL_OUT4 F6 codec_ctrl_out4 C4 TEST/ENABLE CTRL_OUT5 F5 codec_ctrl_out5 C7 CTRL_OUT6 F4 codec_ctrl_out6 VSSA C8 CTRL_OUT7 G4 codec_ctrl_out7 VDDA1P3_TX_SYNTH VSSA C9 VDDA1P3_BB VSSA C10 VSSA C11 VSSA C12 VSSA F3 VSSA H2 VSSA H3 VSSA J2 VSSA K2 VSSA L2 VSSA L3 VSSA L7 VSSA L8 VSSA L9 VSSA L10 VSSA L11 VSSA L12 VSSA M6 RX_FRAME_N G8 RX_FRAME_P tx_frame_p G9 TX_FRAME_P codec_data_clk_p H9 TX_FRAME_N G11 DATA_CLK_P H11 DATA_CLK_N P ENABLE FB_CLK_N rx_frame_p U2 G6 codec_fb_clk_p F10 FB_CLK_P G10 AD9361−CTRL G2 H12 P0_D6/TX_D3_N codec_d5 L F7 B9 10uF X5R 4V C330 codec_d11 M D12 VSSD F12 1.8V_CAT:1 codec_d12 K11 P1_D0/RX_D0_N N VSSD VDDA_GPO P1_D1/RX_D0_P 10uF X5R 4V C329 J12 C312 R300 1000pF 1 C313 1uF codec_d14 K10 P1_D2/RX_D1_N codec_d13 0.1uF C311 K7 VDDA1P1_TX_VCO B8 1.3V_CAT:1 0.1uF C309 codec_d20 L300 MI1206K601R−10 0.1uF C308 P1_D9/RX_D4_P 0.1uF C307 J8 0.1uF C306 codec_d21 0.1uF C305 P1_D10/RX_D5_N 0.1uF C304 J7 0.1uF C303 codec_d22 0.1uF C302 P1_D11/RX_D5_P 0.1uF C301 O H8 10uF X5R 4V C300 P codec_d23 U2 AD9361−MISC O N 3.3V:1 C328 0.1uF U2 M B7 GPO_0 L5 AUXADC U304 FIN1002 B6 GPO_1 CLOCK_OUT J6 B5 GPO_2 RBIAS L4 B4 GPO_3 XTALP M11 TP302 auxdac1 B3 AUXDAC1 XTALN M12 TP303 auxdac2 C3 AUXDAC2 3 4 R302 14.3K 1% R307 5 R304 1K cat_clkout_fpga 27 net=3.3V:1 net=GND:2 C327 0.1uF X3 L FA−128 40.0000MF20X−K0 Place C326 on XTALN trace from X3. DNP if using X3 DNP X3 if using external 40MHz osc. C326 1.3V P−P AC coupled XTALN input impedance is 10k || 10pf 0.1uF K xo_out R306 50 J J I I H H C319 C320 C321 C322 C323 C324 C325 0.47uF 0.1uF 0.1uF 0.1uF 0.1uF codec_ctrl_out5 0.47uF D U1 J1 codec_d8 cat_clkout_fpga codec_sync J3 codec_main_clk_n L4 M3 0.47uF IO_L41N_GCLK26_M3DQ5_3 IO_L41P_GCLK27_M3DQ4_3 IO_L42N_GCLK24_M3LDM_3 K4 4.7uF 6.3V X5R C318 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 codec_d5 codec_main_clk_p C316 IO_L1N_VREF_3 xc6slxXXfgg484−IO3 IO_L1P_3 IO_L2N_3 IO_L2P_3 IO_L7N_3 F E K5 4.7uF 6.3V X5R C317 Y1 Y2 W1 P7 W3 IO_L43P_GCLK23_M3RASN_3 codec_data_clk_p 100uF X5R 4V cat_ce codec_reset codec_d18 codec_d20 cat_sclk IO_L7P_3 J4 K3 B P8 IO_L44P_GCLK21_M3A5_3 C IO_L44N_GCLK20_M3A6_3 codec_main_clk is the main FPGA clock (for timestamps, serial timing, etc.) codec_data_clock is the RX data clock (received from transceiver) codec_fb_clk is the TX data clock (sent to transceiver, just the data_clock turned back around) GCLK24/25 and GCLK26/27 are both on the LT clock bus. GCLK22 shares a BUFGMUX with GCLK30, which is unused. 1.8V:1 IO_L8N_3 IO_L9N_3 IO_L10N_3 IO_L9P_3 IO_L10P_3 IO_L11N_3 IO_L23N_3 IO_L11P_3 IO_L23P_3 IO_L24N_3 D G P5 T3 T4 V3 U4 N7 N6 M8 M7 IO_L24P_3 IO_L25P_3 IO_L25N_3 IO_L26N_3 IO_L31N_VREF_3 IO_L31P_3 IO_L32N_M3DQ15_3 IO_L32P_M3DQ14_3 IO_L33N_M3DQ13_3 IO_L33P_M3DQ12_3 IO_L34N_M3UDQSN_3 IO_L35N_M3DQ11_3 IO_L34P_M3UDQS_3 IO_L35P_M3DQ10_3 codec_en_agc P6 IO_L8P_3 tx_frame_p cat_mosi codec_d16 rx_frame_p codec_txrx P4 R4 L6 N4 M6 M4 M5 V1 V2 U1 T1 U3 T2 R1 R3 IO_L36P_M3DQ8_3 IO_L37N_M3DQ1_3 IO_L38N_M3DQ3_3 IO_L37P_M3DQ0_3 IO_L38P_M3DQ2_3 IO_L39N_M3LDQSN_3 IO_L39P_M3LDQS_3 IO_L40N_M3DQ7_3 IO_L45N_M3ODT_3 IO_L40P_M3DQ6_3 IO_L45P_M3A3_3 codec_fb_clk_p P3 IO_L26P_3 codec_d11 cat_miso codec_d14 codec_d19 codec_d21 codec_d17 codec_d12 codec_d13 codec_d23 P2 N1 N3 M1 M2 L1 L3 K1 K2 J6 K6 IO_L46P_M3CLK_3 IO_L47N_M3A1_3 codec_ctrl_out4 P1 IO_L36N_M3DQ9_3 codec_d22 codec_d15 codec_d10 codec_d0 codec_d4 codec_d6 codec_d1 codec_d2 codec_enable H4 H1 IO_L48N_M3BA1_3 IO_L48P_M3BA0_3 IO_L49N_M3A2_3 codec_ctrl_out2 H3 IO_L46N_M3CLKN_3 codec_d7 G1 G3 IO_L49P_M3A7_3 codec_ctrl_out7 H2 IO_L47P_M3A0_3 codec_d9 codec_d3 H5 H6 codec_ctrl_in3 F1 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 codec_ctrl_in1 F2 IO_L50P_M3WE_3 G4 codec_ctrl_out3 F3 IO_L51N_M3A4_3 codec_ctrl_in2 E1 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 codec_ctrl_in0 E3 IO_L52P_M3A8_3 D2 IO_L54P_M3RESET_3 codec_ctrl_out0 D1 IO_L53N_M3A12_3 C3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L57N_VREF_3 IO_L57P_3 IO_L58N_3 IO_L58P_3 IO_L59P_3 IO_L59N_3 codec_ctrl_out1 C1 IO_L54N_M3A11_3 F5 G6 K8 K7 E4 D5 J7 H8 IO_L60P_3 VCCO_3 B2 VCCO_3 N5 IO_L80P_3 U5 IO_L80N_3 VCCO_3 F7 VCCO_3 C2 IO_L81N_3 W2 C4 VCCO_3 G7 VCCO_3 J5 IO_L82N_3 VCCO_3 IO_L81P_3 L2 R2 D3 VCCO_3 IO_L82P_3 VCCO_3 L7 E6 VCCO_3 F6 IO_L83N_VREF_3 E VCCO_3 F4 E5 IO_L83P_3 F G2 B3 A2 1.8V:1 codec_ctrl_out6 B1 IO_L60N_3 XC6SLX75−3FGG484C G C B B200 AD9361−FPGA Interface A A TITLE FILE: fpga_codec.sch 2 PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 OF 8 20 REVISION: 2 DRAWN BY: nick, matt 21 22 B6 IO_L4P_0 debug_06 A7 IO_L37P_GCLK13_0 B12 IO_L5N_0 B8 IO_L6P_0 debug_04 C8 IO_L7N_0 debug_01 D9 IO_L7P_0 A9 IO_L8N_VREF_0 rx_bandsel_a C9 IO_L8P_0 debug_05 D8 IO_L32N_0 debug_07 D7 IO_L32P_0 debug_22 C10 IO_L33N_0 debug_00 D10 IO_L33P_0 rx_bandsel_b A13 IO_L38N_VREF_0 tx_bandsel_a C13 IO_L38P_0 debug_21 D12 IO_L43N_0 debug_30 E12 IO_L43P_0 debug_27 D13 IO_L45N_0 debug_28 F13 IO_L45P_0 debug_29 G13 IO_L46N_0 debug_31 H13 IO_L46P_0 debug_23 F15 IO_L47N_0 debug_24 E14 IO_L47P_0 debug_26 H14 IO_L48N_0 debug_25 F14 IO_L48P_0 debug_20 C14 IO_L49N_0 debug_16 A14 16 12 9 9 SFDX1_TX D14 IO_L49P_0 gps_txd nick, matt 2 SRX2_RX 13 debug_03 U1 15 debug_09 14 SRX2_TX A12 debug_clk0 DRAWN BY: IO_L36P_GCLK15_0 IO_L37N_GCLK12_0 REVISION: U1 IO_L3P_0 IO_L4N_0 8 A6 OF debug_08 11 A2[0] debug_clk1 D11 3 debug_11 D6 IO_L5P_0 37 A2[1] debug_17 35 A2[2] 33 debug_18 A2[3] debug_19 31 A2[4] debug_20 29 A2[5] debug_21 27 A2[6] debug_22 25 A2[7] A3[0] 23 debug_23 debug_24 21 A3[1] debug_25 19 A3[2] A3[3] 17 debug_26 debug_27 15 A3[4] 13 debug_29 SFDX2_RX C12 IO_L6N_0 10 debug_28 11 A3[6] A3[7] GND A3[5] GND 9 C11 IO_L36N_GCLK14_0 10 A0[0] GND debug_30 IO_L35P_GCLK17_0 IO_L3N_0 A8 38 36 A0[1] 34 A0[2] 32 A0[3] A0[4] 30 28 A0[5] 26 A0[6] 24 A0[7] A1[0] 22 20 A1[1] 18 A1[2] A1[3] 16 14 12 A1[4] A1[5] 10 A1[6] A1[7] GND debug_31 IO_L2P_0 fpga_debug.sch C6 PAGE C5 debug_10 FILE: debug_14 PPS_IN_INT TITLE debug_00 debug_01 debug_02 debug_03 debug_04 debug_05 debug_06 debug_07 debug_08 debug_09 debug_10 debug_11 debug_12 debug_13 debug_15 8 debug_14 debug_clk1 6 CLK1 SFDX2_TX 39 GND CLK0 A11 40 NC 7 PPS_IN_EXT IO_L35N_GCLK16_0 C7 1 5 IO_L34P_GCLK19_0 IO_L2N_0 41 NC debug_clk0 IO_L1P_HSWAPEN_0 B10 42 J502 A5 2 MICTOR43−LA A10 43 debug connector IO_L34N_GCLK18_0 IO_L1N_VREF_0 B200 debug and misc 17 A B C D E F G H I J K 17 16 debug_12 debug_02 NC 13 debug_15 A3 auth_reset NC 12 A4 3 11 debug_13 4 14 15 xc6slxXXfgg484−IO0 IO_L50N_0 0.47uF C506 A15 IO_L51N_0 C15 IO_L51P_0 C16 IO_L62N_VREF_0 gps_rxd 0.47uF C504 8 gps_txd_nmea SRX1_TX 8 gps_lock B14 IO_L50P_0 0.47uF C503 SRX1_RX D15 IO_L62P_0 4.7uF 6.3V X5R C502 SFDX1_RX A16 IO_L63N_SCP6_0 debug_19 C17 IO_L64P_SCP5_0 debug_16 A18 IO_L65N_SCP2_0 debug_17 B18 IO_L65P_SCP3_0 tx_bandsel_b D17 IO_L66N_SCP0_0 rx_bandsel_c E16 IO_L66P_SCP1_0 F8 gpio_L14p E8 NC/IO_L14P_0 gpio_L15n F9 NC/IO_L15N_0 gpio_L15p G8 NC/IO_L15P_0 gpio_L16n H10 NC/IO_L16N_0 gpio_L16p G9 NC/IO_L16P_0 gpio_L17n F10 NC/IO_L17N_0 gpio_L17p E10 NC/IO_L17P_0 14 7 5 4 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 B19 B11 B15 B7 B4 VCCO_0 VCCO_0 E17 3 3.3V:1 E13 VCCO_0 NC/IO_L44P_0 VCCO_0 NC/IO_L44N_0 2 INIT/NC F12 H12 GND NC/NC GND 11 NC/IO_L18P_0 A B C D E F G H I J K 1 13 12 10 Din/TDI GND 9 8 Done/TDO GND 7 6 CCLK/TCK GND 5 4 PROG/TMS GND 3 Vref/Vref GND 1 NC/IO_L18N_0 G11 1 J503 XIL−PLAT−CABLE 2 3.3V:1 3 2 NC/IO_L14N_0 E9 XC6SLX75−3FGG484C 10 9 gpio_L17p 8 7 gpio_L17n gpio_L16p gpio_L16n gpio_L15p 6 4 5 3 gpio_L15n gpio_L14p 2 1 gpio_L14n J504 TMS TDO 10K TDI R526 TCK 3.3V:1 4 10K 6 gpio_L14n H11 R528 IO_L64N_SCP4_0 VCCO_0 10K A17 G10 R530 debug_18 G14 R503 DNP R502 DNP 3.3V:1 VFS XC6SLX75−3FGG484C VFS P16 VBATT R17 TMS C18 TDO A19 TDI E18 G15 SUSPEND TCK SUSPEND 5 R501 DNP R500 DNP 3.3V:1 N15 RFUSE P15 RFUSE xc6slxXXfgg484−MISC 7 C500 6 100uF X5R 4V 3.3V:1 4.7uF 6.3V X5R C501 AUX_PWR_ON B16 IO_L63P_SCP7_0 K J K GND E7 GND GND N13 N11 GND GND N17 AB22 GND GND M10 M12 GND GND M14 E11 GND GND E15 V10 GND GND V14 AA5 GND GND D4 N21 GND GND J2 W7 GND GND L18 L11 GND GND L13 D18 GND GND A22 V4 GND GND K12 K10 GND GND K14 B5 GND GND B9 2 GND E2 xc6slxXXfgg484−VCCAUX W16 G12 W19 3 3 VCCAUX GND VCCAUX GND VCCAUX R5 J9 VCCAUX L5 GND R6 GND GND VCCAUX GND L9 U11 AB1 VCCAUX G18 VCCAUX GND H15 GND V6 U21 VCCAUX GND VCCAUX GND E21 VCCAUX P12 P14 VCCAUX J21 GND R12 GND GND VCCAUX GND 2 G5 P10 H9 XC6SLX75−3FGG484C U1 1 3.3V:1 J I H G F E D C B A 1 xc6slxXXfgg484−GND 4 4 U1 VCCAUX VCCAUX L8 F11 M15 D16 K15 R10 N8 5 3.3V:1 5 6 6 GND U2 GND GND H7 B17 GND GND B13 J15 GND GND J13 J11 GND GND N9 N2 GND GND AA13 AA17 GND GND A1 AA9 GND 7 GND 7 U7 R18 1.2V_FPGA:1 M9 P13 N12 N14 M13 L14 L12 K13 R14 J12 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT 9 VCCINT VCCINT 8 VCCINT VCCINT xc6slxXXfgg484−VCCINT VCCINT 9 VCCINT XC6SLX75−3FGG484C XC6SLX75−3FGG484C 8 10 10 0.47uF C220 0.47uF C205 0.47uF C222 0.1uF C206 0.1uF C224 0.1uF C207 0.1uF C226 0.1uF C208 0.1uF C228 0.1uF C209 OF 0.1uF C230 0.1uF C211 8 0.1uF C231 0.1uF C213 0.1uF C232 0.1uF C215 0.1uF C233 0.1uF C217 0.1uF C219 0.1uF C221 0.1uF C223 0.1uF C225 0.1uF C227 0.1uF C229 TITLE FILE: 14 4 fpga_power.sch PAGE REVISION: nick, matt 2 16 DRAWN BY: B200 FPGA Power 15 16 C204 15 0.47uF 14 C218 13 0.47uF 12 C203 11 0.47uF 1.2V_FPGA:1 C216 P11 0.47uF U1 4.7uF 6.3V X5R C202 3.3V:1 4.7uF 6.3V X5R C214 13 4.7uF 6.3V X5R C201 K9 C200 4.7uF 6.3V X5R C212 N10 100uF X5R 4V 1.2V_FPGA:1 12 C210 M11 J8 L10 P9 K11 J14 J10 11 100uF X5R 4V 17 17 I H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 L L 3.3V:1 U700 24Cxx pins swapped for routing 7 6 5 14 T700 T701 R721 100K U3 CYUSB3014−BANK5 D9 FX3_SDA D10 TDO TRST# 13 33_SDA 4 R720 10K U3 CYUSB3014−USB D11 U3TXVDDQ SSRX+ A4 A2 U3RXVDDQ SSRX− A3 SSTX+ A5 SSTX− A6 D+ A9 D− A10 auth_reset 1 SDA VCC 2 C400 1.8V_FX3:1 VIO5 TCK GND i 10 5 6 7 8 o U702 OTG_ID C9 VBATT E10 VBUS E11 U703 GND 3 I usb_vbus R714 5.11K H 3.3V:1 1.2V_FX3:1 R700 2.2K footprint=TBD value=GSB3211XXXWEU R713 10K 0.1uF 1.8V_FX3:1 J BLM18AG102SN1D C717 0.1uF SSRX+ SSRX− SSTX+ SSTX− D+ D− Vbus GND GND SHLD VUSB:1 L700 Opt. secure auth. H 9 8 6 5 3 2 1 4 7 10 C703 0.1uF U400 ATSHA204−TSU−T 3.3V:1 33_SDA 9 4 3 2 1 C702 0.1uF T703 TMS K J701 B5 C11 F6 SDA RES R5H30211 33_SCL TDI B11 E8 12 I2C_SDA C10 I CLK I2C_SCL O[60]/Charger_detect_out E7 P4 3 1.2V_FX3:1 SCL esd clamp U701 RCLAMP0524J A1 J FX3_SCL 2 U704 U3VSSQ 24LC256 1.8V_FX3:8 GND:4 P3 VCC 5 Opt. secure auth. VSS FX3 boot ROM A0 A1 n/c A2 SCL SDA 11 K 1 2 3 R702 2.2K R701 2.2K A7 R703 2.2K U3 CYUSB3014−PWR AVDD AVSS B7 Q701 33_SCL Q700 33_SDA F SPI is unusable in 32−bit GPIF mode. fx3_mosi D5 usb_vbus C4 B2 GPIO[54]/SPI_SSN/UART_CTS/I2S_CLK B4 GPIO[55]/SPI_MISO/UART_TX/I2S_SD E6 GPIO[56]/SPI_MOSI/UART_RX/I2S_WS C5 GPIO[57]/I2S_MCLK R709 10K 1.8V_FX3:1 B1 D 1.8V_FX3:1 C700 XTALIN C6 XTALOUT C7 FSLC[2] CLKIN D7 RESET# CLKIN_32 D6 FSLC[0] FSLC[1] NC VDD VSS B9 E9 VDD VSS K4 F11 VDD VSS L3 H1 VDD VSS K3 VDD VSS L2 J11 VDD VSS A8 L5 VDD VSS D8 VSS E2 VSS G1 VSS G11 VSS L1 VSS L6 VSS L11 12pF X700 19.2MHz C701 12pF T702 A11 G 1.8V_FX3:1 L7 R_USB2 fx3_miso C2 GPIO[53]/SPI_SCK/UART_RTS CVDDQ fx3_ce C1 CYUSB3014−CLK U3 B8 B6 D4 VIO4 E fx3_sclk U3 VSS C8 CYUSB3014−BANK4 VDD C3 R_USB3 FX3_SDA B10 B3 FX3_SCL G 1.2V_FX3:1 22uF X5R 6.3V C704C705C706C707C708C709C710C711C712C713C714C715 22uF X5R 6.3V C721 0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF C722 F E D R711 200 1.8V_FX3:1 R712 6.04K 2 C716 S700 1 0.1uF JLEAD_SW C C B B B200 FX3 interface A A TITLE FILE: fx3.sch 5 PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OF 8 15 REVISION: 2 DRAWN BY: nick, matt 16 17 IO_L41P_2 A21 IO_L20N_1 IO_L21N_1 AA6 IO_L49P_D3_2 AB4 LED_TXRX1_RX H17 IO_L28N_VREF_1 GPIF_D07 IO_L57P_2 H16 IO_L28P_1 GPIF_D06 AB3 IO_L58N_2 D20 IO_L29N_A22_M1A14_1 GPIF_D05 Y3 IO_L58P_2 D19 IO_L29P_A23_M1A13_1 IO_L30N_A20_M1A11_1 IO_L62N_D6_2 F19 IO_L62P_D5_2 F18 IO_L30P_A21_M1RESET_1 GPIF_D09 AB2 IO_L64N_D9_2 LED_TXRX2_TX D22 IO_L31N_A18_M1A12_1 GPIF_CTL5 AA2 LED_TXRX2_RX D21 IO_L31P_A19_M1CKE_1 LED_RX1 C22 IO_L32N_A16_M1A9_1 LED_TXRX1_TX C20 IO_L32P_A17_M1A8_1 IO_L65P_INIT_B_2 Y18 NC/IO_L6N_2 F20 IO_L33N_A14_M1A4_1 NC/IO_L6P_2 G19 IO_L33P_A15_M1A10_1 T15 NC/IO_L7N_2 H18 IO_L34N_A12_M1BA2_1 T16 NC/IO_L7P_2 H19 IO_L34P_A13_M1WE_1 U16 NC/IO_L8N_2 E22 IO_L35N_A10_M1A2_1 U17 NC/IO_L8P_2 E20 IO_L35P_A11_M1A7_1 V18 NC/IO_L9N_2 K17 IO_L36N_A8_M1BA1_1 V19 NC/IO_L9P_2 J17 IO_L36P_A9_M1BA0_1 R15 NC/IO_L10N_2 F22 IO_L37N_A6_M1A1_1 IO_L37P_A7_M1A0_1 GPIF_D31 NC/IO_L10P_2 F21 NC/IO_L11N_2 J19 IO_L38N_A4_M1CLKN_1 H20 IO_L38P_A5_M1CLK_1 GPIF_D30 G22 IO_L39N_M1ODT_1 fx3_miso G20 IO_L39P_M1A3_1 GPIF_D25 K22 IO_L44N_A2_M1DQ7_1 K21 IO_L44P_A3_M1DQ6_1 GPIF_D26 L22 IO_L45N_A0_M1LDQSN_1 GPIF_D27 L20 IO_L45P_A1_M1LDQS_1 GPIF_CTL6 M22 IO_L46N_FOE_B_M1DQ3_1 GPIF_CTL11 M21 IO_L46P_FCS_B_M1DQ2_1 GPIF_CTL1 N22 IO_L47N_LDC_M1DQ1_1 GPIF_D17 N20 IO_L47P_FWE_B_M1DQ0_1 GPIF_CTL0 P22 IO_L48N_M1DQ9_1 NC/IO_L18N_2 V13 NC/IO_L18P_2 Y14 NC/IO_L20N_2 W14 NC/IO_L20P_2 R13 NC/IO_L23N_2 T14 NC/IO_L23P_2 T11 NC/IO_L40N_2 fx3_ce NC/IO_L40P_2 Y10 NC/IO_L44N_2 W10 NC/IO_L44P_2 V7 NC/IO_L46N_2 W8 NC/IO_L46P_2 Y8 NC/IO_L47N_2 W9 NC/IO_L47P_2 V9 NC/IO_L50N_2 U9 NC/IO_L50P_2 R8 NC/IO_L59N_2 R9 NC/IO_L59P_2 R7 NC/IO_L60N_2 T7 NC/IO_L60P_2 V5 NC/IO_L63N_2 IO_L48P_HDC_M1DQ8_1 GPIF_D13 R22 IO_L49N_M1DQ11_1 GPIF_CTL9 R20 IO_L49P_M1DQ10_1 GPIF_D11 T22 IO_L50N_M1UDQSN_1 GPIF_D18 T21 IO_L50P_M1UDQS_1 GPIF_D12 U22 IO_L51N_M1DQ13_1 FX3_EXTINT U20 IO_L51P_M1DQ12_1 V22 IO_L52N_M1DQ15_1 Y16 NC/NC/IO_L17P_2 GPIF_D10 V21 IO_L52P_M1DQ14_1 GPIF_D24 N19 IO_L53N_VREF_1 GPIF_CTL8 M19 IO_L53P_1 LED_RX2 L15 IO_L58N_1 M16 IO_L58P_1 P20 IO_L59N_1 P19 IO_L59P_1 IO_L60N_1 23 nick, matt DRAWN BY: 22 21 6 NC/NC/IO_L17N_2 U12 NC/NC/IO_L22N_2 T12 NC/NC/IO_L22P_2 U8 NC/NC/IO_L51N_2 W22 T8 NC/NC/IO_L51P_2 W20 IO_L60P_1 U10 NC/NC/IO_L52N_2 GPIF_D19 K18 IO_L61N_1 T10 NC/NC/IO_L52P_2 L17 IO_L61P_1 Y6 NC/NC/IO_L53N_2 GPIF_D08 V20 IO_L70N_1 5 GPIF_CTL4 4 VCCO_2 T9 VCCO_2 VCCO_2 AA3 AA19 AA15 V8 AA11 W5 T13 AA7 V16 V12 VCCO_2 IO_L72N_1 VCCO_2 IO_L71P_1 N16 VCCO_2 M17 NC/NC/IO_L54P_2 VCCO_2 IO_L71N_1 VCCO_2 IO_L70P_1 M18 VCCO_2 U19 NC/NC/IO_L54N_2 VCCO_2 NC/NC/IO_L53P_2 VCCO_2 W6 AB5 1.8V:1 tx_enable2 P17 IO_L72P_1 R19 IO_L73N_1 IO_L73P_1 T20 IO_L74N_DOUT_BUSY_1 T19 IO_L74P_AWAKE_1 VCCO_1 R21 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 L21 L16 C21 U18 N18 1 A B C D E F G H I J K L M N O P Q 1 2 1.8V:1 G21 XC6SLX75−3FGG484C VCCO_1 3 P18 VCCO_1 FX3_EXTINT L8 1.8V_FX3:1 FX3_PMODE2 L4 PMODE[2] CTL[15]/INT# FX3_PMODE1 H4 GPIF_D15 DQ[14] NC/IO_L63P_2 W15 DQ[15] J8 G8 GPIF_D14 P21 7 R11 10 NC/IO_L11P_2 8 V17 W13 11 R16 W17 XC6SLX75−3FGG484C PMODEs usable as GPIO after boot FX3_PMODE0 G4 PMODE[1] PMODE[0] GPIF_CTL12 H5 CTL[12]/A0 DQ[13] K9 GPIF_D13 13 T6 12 IO_L65N_CSO_B_2 W18 1.8V_FX3:1 DQ[27] DQ[26] G3 IO_L64P_D8_2 T5 14 Y4 W4 F3 GPIF_D27 GPIF_CTL11 J5 GPIF_D26 FPGA_CFG_DONE K5 CTL[11]/A1 CTL[10]/GPIO DQ[12] DQ[11] L10 K10 GPIF_D12 GPIF_D11 IO_L21P_1 IO_L57N_2 AA4 R415 10K DQ[25] DQ[24] F4 G2 GPIF_D25 GPIF_CTL9 H6 GPIF_D24 GPIF_CTL8 G5 CTL[9]/GPIO CTL[8]/GPIO DQ[9] GPIF_D10 DQ[10] J9 K11 GPIF_D09 K16 9 IO_L20P_1 J16 GPIF_D03 IFCLK is the FX3−FPGA data clock. the FX3 can be configured to supply or accept a clock on this pin. A20 R411 4.7K 1.8V:1 GPIO[52]/I2S_WS 8 GPIF_D21 IO_L48N_RDWR_B_VREF_2 IO_L48P_D7_2 SHDN_SW DQ[22] DQ[23] H3 H2 GPIF_CTL7 GPIF_D23 GPIF_CTL6 H8 CTL[6]/GPIO GPIF_D08 DQ[8] H9 J10 GPIF_D07 DQ[7] CTL[7]/PKTEND# K6 GPIF_D22 DQ[21] J1 GPIF_D21 GPIF_CTL5 G6 CTL[5]/FLAGB DQ[6] H10 GPIF_D06 OF J20 D3 AUX_PWR_ON_lv D2 GPIO[51]/I2S_SD FPGA_CFG_INIT_B D1 GPIO[50]/I2S_CLK DQ[31]/UART_RX E4 GPIF_D31 DQ[19] DQ[20] J3 J2 GPIF_CTL4 GPIF_D20 GPIF_CTL3 G7 CTL[3]/SLRD# F8 GPIF_D05 DQ[5] G9 GPIF_D04 DQ[4] CTL[4]/FLAGA H7 GPIF_D19 DQ[18] DQ[17] J4 K1 GPIF_D18 GPIF_CTL2 J7 GPIF_D17 GPIF_CTL1 K7 CTL[2]/SLOE# CTL[1]/SLWR# DQ[2] DQ[3] F7 G10 GPIF_D03 PAGE 6 IO_L43P_GCLK5_M1DQ4_1 2 GPIF_D02 2 20 IO_L19P_1 Y5 REVISION: 17 B21 16 GPIF_D28 IO_L45P_2 IO_L49N_D4_2 1.8V_FX3:1 FX3_PMODE2 FX3_PMODE1 FX3_PMODE0 boot mode select E5 GPIF_D30 GPIF_D29 E1 DQ[30]/UART_TX DQ[29]/UART_CTS DQ[28]/UART_RTS CYUSB3014−BANK3 F2 FPGA_CFG_PROG_B TITLE GPIF_CTL12 J22 Y7 GPIO[45] DQ[16] K2 GPIF_D16 GPIF_CTL0 K8 CTL[0]/SLCS# DQ[1] VIO1 VIO1 F9 L9 H11 GPIF_D01 1.8V:1 1.8V:1 R414 DNP FPGA_CFG_M1 M20 AB6 C401 U3 CYUSB3014−BANK2 GPIF_D23 GPIF_D04 C402 IFCLK L19 0.1uF J6 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43N_GCLK4_M1DQ5_1 0.1uF PCLK/CLK IO_L10N_1 IO_L42P_GCLK7_M1UDM_1 8 VIO2 DQ[0] IFCLK F17 IO_L19N_1 U6 F1 CYUSB3014−BANK1 U3 H21 IO_L10P_1 FPGA_CFG_INIT_B C403 F10 IO_L41P_GCLK9_IRDY1_M1RASN_1 F16 0.1uF GPIF_D00 IO_L9P_1 VCCO_1 87224−3 Debug serial (3.3V) 3 2 FPGA_RXD0 FPGA_TXD0 13 F5 VIO3 GPIF_D28 E3 U3 C422 R402 DNP 12 GPIF_D20 G16 B22 tx_enable1 11 H22 IO_L43P_2 0.1uF 1.8V_FX3:1 R403 10K 10 IO_L41N_GCLK8_M1CASN_1 AB7 R405 DNP 9 IO_L9N_1 IO_L45N_2 15 1 J400 IO_L43N_2 14 R404 DNP 7 GPIF_D29 G17 FPGA_TXD0 R406 DNP 6 GPIF_D22 K20 Y9 R407 DNP 5 K19 IO_L40P_GCLK11_M1A5_1 AB8 AA8 16 IO_L42P_2 IO_L40N_GCLK10_M1A6_1 IO_L1P_A25_1 15 AB9 IO_L42N_2 IO_L1N_A24_VREF_1 C19 E19 17 V11 4 A 24 AA10 xc6slxXXfgg484−IO1 B20 W21 18 pll_lock IO_L41N_VREF_2 W11 FPGA_RXD0 IO_L21P_2 AB10 19 IO_L21N_2 18 IO_L19P_2 AB15 U1 IO_L19N_2 AA16 R413 DNP IO_L16P_2 AB16 FPGA_CFG_M0 AA14 Y15 pll_ce R412 2.2K IO_L16N_VREF_2 M0=0, M1=1: Slave SelectMAP M0=1, M1=1: Slave serial ref_sel IO_L15P_2 AB14 R410 2.2K IO_L15N_2 Y17 1.8V:1 R417 in case ADF4002 misconfigured for PP output on LOCK FPGA_CFG_CLK not used in slave serial mode FPGA_CFG_CS not used in slave serial mode 20 19 IO_L14P_D11_2 AB17 C404 IO_L14N_D12_2 AA18 100uF X5R 4V AB18 GPIF_CTL2 4.7uF 6.3V X5R C405 GPIF_CTL3 C415 IO_L13N_D10_2 IO_L13P_M1_2 FPGA_CFG_PROG_B 4.7uF 6.3V X5R C416 V15 U15 AA1 VCCO_1 21 4.7uF 6.3V X5R C406 FPGA_CFG_M1 PROGRAM_B_2 B200 FX3 GPIF interface IO_L12P_D1_MISO2_2 gpif.sch IO_L12N_D2_MISO3_2 U14 FILE: U13 GPIF_D01 pll_mosi J18 sampled on rising edge fx3_sclk R408 330 GPIF_D02 R409 4.7K Y11 R418 2.2K 3 B C D E F G H I J K L M N O P Q 24 R400 100 R401 100 AB11 IO_L32P_GCLK29_2 100uF X5R 4V 22 IO_L32N_GCLK28_2 IO_L5P_2 C407 IO_L5N_2 Y19 4.7uF 6.3V X5R C417 AB19 GPIF_CTL7 1.8V:1 C408 GPIF_D14 0.47uF AA12 C418 IO_L31P_GCLK31_D14_2 0.47uF IO_L4P_2 C409 GPIF_D15 T18 0.47uF AB12 0.47uF GPIF_D16 IO_L31N_GCLK30_D15_2 C419 0.47uF C410 Y13 IO_L4N_VREF_2 GPIF_D00 IO_L30P_GCLK1_D13_2 C420 1.8V:1 U1 AB13 T17 fx3_mosi 0.47uF IO_L3P_D0_DIN_MISO_MISO1_2 W12 0.47uF AA20 IO_L29P_GCLK3_2 IO_L30N_GCLK0_USERCCLK_2 C411 IO_L3N_MOSI_CSI_B_MISO0_2 FPGA_CFG_DONE pll_sclk 0.47uF C421 IO_L2P_CMPCLK_2 AB20 Y12 C412 AA21 Y22 IO_L29N_GCLK2_2 0.1uF IO_L2N_CMPMOSI_2 Y20 DONE_2 C413 AB21 CMPCS_B_2 0.1uF IO_L1P_CCLK_2 C414 Y21 0.1uF FPGA_CFG_M0 AA22 IO_L1N_M0_CMPMISO_2 0.1uF 23 1.8V:1 xc6slxXXfgg484−IO2 1 2 3 4 5 6 7 8 9 10 11 U802 L BD3150L50100A00 UNBAL 10pF C880 10pF C881 Receive 1:2 13 14 15 16 17 C882 10pF C883 UNBAL BAL GND AD9361−RX U801 SKY13317−373LF L BD3150L50100A00 10pF BAL 3000−6000 BIAS BAL GND 12 U808 BAL GND U2 BIAS 1:2 GND U810 SKY13317−373LF M1 RX1A_P RX2A_P A2 M2 RX1A_N RX2A_N A1 RX1B_P RX2B_P E1 1 F1 3 S K K 470pF 470pF C806 470pF 1 K1 RX1C_P RX2C_P C1 1 3 L1 RX1C_N RX2C_N D1 3 S M4 VSSA VSSA A4 M3 NC NC A3 G1 RX_EXT_LO_IN H6 VSSA 1:1 C818 100pF 5 T803 P 4 RF2 V1 R831 1K RF3 V2 R832 1K rx_bandsel_c GND V3 R833 1K rx_bandsel_a C821 470pF R802 150 C847 DNP 1 3 2 2 4 1 TXRX1 3 RFC C814 470pF 5 OUT2 1 J800 5432 SFDX1_TX 1K R825 6 SRX1_TX R826 4 1K TXRX1 TXRX2 OUT1 VCTL1 VCTL2 J801 142−0701−871 C826 470pF 1 5 OUT1 1 OUT2 3 R834 R836 R810 150 TXRX2 2345 142−0701−871 PAD 7 PAD VCTL1 6 GND 2 2 GND VCTL2 4 C832 220pF 1K TX2 LED802 SRX2_TX C834 1K SFDX2_TX 470pF C859 470pF C869 470pF C860 470pF C871 Q804 LED_TXRX1_RX RX1 U807SKY13335−381LF 3 RX2 142−0701−871 J803 R805 10K 7 PAD VCTL1 6 R829 1K SFDX1_RX 2 GND VCTL2 4 R830 1K SRX1_RX C848 DNP F 470pF 470pF C829 470pF SRX2_RXR835 1 2345 142−0701−871 C854 DNP C851 DNP C861 SFDX2_RXR837 SFDX1 0 1 Result RX only on TXRX1 ant Full duplex operation C890 1000pF C862 C807 C808 0.01uF 1000pF L800 100nH 1.3V_TX:1 C825 1000pF TX1 D 3 L804 100nH U809 1.3V_TX:1 BD3150L50100A00 C811 1 5 OUT1 1 OUT2 3 C816 22pF RFC 220pF UNBAL BIAS 4 7 PAD VCTL1 6 2 GND VCTL2 4 1K 3.3V:1 L802 2.2uH C817 10pF C864 R828 470pF tx_bandsel_b 1K 6 VCTL1 1K 4 C868 E C B B L807 15nH M7 5 C828 220pF C884 L808 100nH R820 680 470pF C870 4 P 1 1:1 M9 AD9361−TX L810 15nH U2 7 GND 2 RX2 R813 10K R816 10K S 3 M10 TX1A_P TX2A_P TX1A_N TX1B_P R809 680 C845 C846 1000pF 0.01uF L809 R821 100nH 680 TX1B_N TX2A_N A7 TX2B_P A10 TX2B_N A9 TX_MON2 A5 TX_MON1 1:2 GND 5 C839 P 4 220pF 1 1:1 C843 22pF UNBAL BAL BIAS C841 C842 220pF 10pF 10uF X5R 4V C885 TX_EXT_LO_IN 3.3V:1 tx_enable1 Q807 ZXTC2062E6 1.3V_TX:1 tx_enable2 C837 4.7uF 6.3V X5R TX amp power C E B B L815 15nH C840 4.7uF 6.3V X5R 10K 1 OUT1 3 OUT2 RFC C844 5 1 220pF TX2 SOT89 D 3 6 VCTL1 PAD 7 4 VCTL2 GND 2 4 R838 1K tx_bandsel_b R839 1K tx_bandsel_a 2 C L816 2.2uH B C857 4.7uF 6.3V X5R R818 2.2uH E GND 10uF X5R 4V A12 U817 PGA−102+ U816 SKY13335−381LF L811 15nH 3 S L814 100nH 10uF X5R 4V T805 M5 R817 10K C891 1000pF A8 T804 10K E PAD C833 470pF 3.3V_TXAMP2:1 C835 1000pF R807 R806 5 C856 DNP L812 3.3V_TXAMP1:1 RFC U815 BD3150L50100A00 1.3V_TX:1 Transmit 1.3V:1 4.7uF 6.3V X5R C VCTL2 BAL Q803 ZXTC2062E6 C813 L805 R815 100nH 680 M8 C863 1K C B OUT2 BAL GND C827 220pF 470pF tx_bandsel_a R827 L806 15nH BAL 1:2 GND 2 3 470pF 1.3V_TX:1 R814 680 U806SKY13335−381LF SOT89 OUT1 C836 10uF X5R 4V L801 15nH 1 C822 U804 PGA−102+ G LED_RX2 F 3.3V_TXAMP1:1 R808 680 Q806 LED_TXRX2_TX J802 5432 Q805 SKY13335−381LFU814 C873 OUT2 RFC 1 470pF R804 10K 5 C819 470pF C872 R803 10K C812 470pF 1 TX2 mode LED H RX2 active LED LED_TXRX2_RX 470pF RX1 OUT1 LED803 470pF Q802 LED_RX1 R812 150 RFC 7 LED_TXRX1_TX R811 150 4 Q801 470pF 1 C855 DNP SKY13335−381LF U811 2 Q800 C809 C810 220pF C852 DNP I 3.3V:1 3 LED801 TX1 mode LED U813 J 1 LED800 C849 DNP U805 SKY13335−381LF RX2 2 R801 150 G E rx_bandsel_b 3.3V:1 TX1 RX1 active LED RX2B_N C820 470pF 3.3V:1 R800 150 H RX1B_N C824 10pF C831 470pF 1 3.3V:1 100pF C801 J1 100pF 5 T802 P 4 C867 GND 3 1:1 470pF V3 H1 C866 1K C805 100pF 1 RFC C865 rx_bandsel_b R824 5 T800 1600−4000 S 4 P 1:1 5 70−2200 T801 S 4 P 1:1 RF1 470pF RF3 C823 470pF RF2 V2 C804 10pF C802 470pF C858 V1 1K C838 1K J I RF1 rx_bandsel_a R822 rx_bandsel_c R823 C830 U800 RFC 470pF C800 470pF RX1 3.3V_TXAMP2:1 E C B200 RF Interface R819 A A TITLE 1K FILE: 1K rf.sch 8 PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OF 8 15 REVISION: 2 DRAWN BY: nick, matt 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Q Q VSYS:1 VSYS:1 C622 0.1uF 0.1uF C676 100uF F100 SF−1206F400−2 1 L601 C679 DNP 26 SHDN1 1 R625 DNP 3 C601 100uF SHDN2 15 BST1 BST2 8 28 SW1 SW2 13 IND1 IND2 11 SHDN_SW C681 DNP C680 560pF L605 6.8uH 27 14 SHDN_SW 26 SHDN1 C629 0.47uF 1 R632 DNP R626 3.7 L603 15uH D601 CDBQR70 C617 0.47uF D606 Vin1 Vin2 27 14 SHDN1 30 C602 0.1uF 2 C600 0.1uF 10uF X5R 16V P U604 LT3692 CDBQR70 D602 1 FBMH3225HM601NT 2 C635 3.7V:1 D604 U600 LT3692 R600 C605 0.47uF 0.1uF 3.7V:1 Vin1 Vin2 J601 O CDBQR70 C650 0.1uF 10uF X5R 16V DNP D600 T600 C648 2 C613 10uF X5R 16V R602 4.87K C628 2 C604 1 P External power supply 5−12VDC C678 100uF 1 C603 10uF X5R 16V D605 6.8uH CDBQR70 SHDN2 BST1 15 BST2 8 SHDN_SW C637 0.47uF C682 DNP O 28 SW1 SW2 13 30 IND1 IND2 11 R633 DNP L607 4.7uH L608 D607 D603 1.2V_FPGA:1 1.2V_FX3:1 10uF X5R 6.3V 24 100uF FX3 1.2V 500kHz 0.1uF 2 1M U609 1 VIN GATE 5 STAT 4 R614 1.74M 3.3V:1 C608 stat Q602 BSS84 LTC4412 CTL SENSE 6 GND 0.01uF C614 R605 10K 33pF R606 33K AUX_PWR_ON 5 CMPI1 CMPI2 6 CMPO1 CMPO2 7 ILIM1 23 VC1 22 RT/SYNC 19 DIV R607 1000pF L 3 C612 FB2 SS2 16 ILIM2 17 SS1 R610 0 VC2 18 CLKOUT 21 Tj 20 C627 0.1uF C619 C623 100pF C630 C677 47uF X5R 6.3V 47uF X5R 6.3V R611 3 I 1 R635 Q605 BT3904 4 3 or LED600 bl 1 2 FB1 6.65K 1% 3 2 3.7V 500kHz FPGA 1.2V 500kHz CLK_SW C634 CLK_SW C626 1000pF C624 C632 C625 R617 56K 33pF R615 20K C636 R620 125K C631 0.01uF R621 16K 0.1uF 47uF X5R 6.3V CMPI1 CMPI2 6 4.53K 1% CMPO1 CMPO2 7 24 ILIM1 23 VC1 22 RT/SYNC 19 DIV SS2 16 ILIM2 17 VC2 18 CLKOUT 21 Tj C640 100pF R624 SS1 R623 0 27pF C638 5 25 2700pF R622 5.62K 1% FB2 M 1.8V 500kHz C642 20 1000pF C639 C641 0.01uF R628 56K 33pF R627 33K C643 L 0.01uF K Vout 3.7 1.8 1.2 1.2 RT: 2.5MHz @ 950mV, 110kHz @ 0V, 12uA bias 1.5MHz @ 44.2K 1.0MHz @ 28.0K 500kHz @ 13.0K 110kHz @ 0 Rdiv: 0 62k 100k 150k Power Imin 0.2 0.6 0.25 0.1 Imax 0.7 1.5 3.5 0.4 (FPGA) (FX3) J Ch1 freq divider: 1 2 4 8 ILIM: 4.8A @ 1.5V, 2A @ 0V, 12uA bias Q603 FDV301N 3 4 2.05K 1% 0.806V Vfb Q604 FDV301N 2 100k R619 3.24K 1% Increase R621 to 27K dependent on transient response (watch VC1). R634 10K AUX_PWR_ON 100pF R618 AUX_PWR_ON_lv R608 220 J C633 0.1uF 47uF X5R 6.3V R612 10K VSYS:1 C649 C654 0.1uF LT3692EUH#PBF 2 K 9 N 0.01uF 13K Vout2 GND C674 R601 2 25 Vout1 33 C672 0.1uF C675 32 9 R609 7.68K 1% FB1 3 Watch this supply for discontinuous operation. (<100mA) 1 C671 0.1uF 4 6.65K 1% FBMH3225HM601NT C673 R604 3.24K 1% 100pF R603 Q600 Si4963BDY USB power input L611 M C610 Vout2 33 VUSB:1 C606 0.1uF C607 47uF X5R 6.3V Vout1 GND Q600 Si4963BDY VSYS:1 1.8V:1 3.7V:1 32 N 3 CMPI thresholds 720mV w/60mV hyster. 1 1 I stat 2 2 R636 49.9 1.8V:1 MI1206K601R−10 3.3V:1 U602 LT1963 ADP150 1.8V_CAT:1 U606 L602 L600 1 Vin Vout 3 MI1206K601R−10 MI1206K601R−10 3.3V digital/TX amp supply G C658 C609 GND GND 2 47uF X5R 6.3V C611 0.1uF C621 47uF X5R 6.3V C615 C618 0.1uF 220pF Vin Vout 5 3 EN NC 4 C659 0.1uF 47uF X5R 6.3V 4 1 C651 0.1uF 2 C652 C653 0.1uF 1 Vin PG 5 2 Vin Vout 14 3 Vin Vout 13 15 Vin Vout 12 16 Vin Vout 11 Vout 10 47uF X5R 6.3V GND C660 220pF C661 0.1uF H T601 L606 3.7V:1 U603 ADP1755ACPZ−R7 ADP174X H C662 47uF X5R 6.3V 1.3V:1 3.7V:1 R613 6.81K C655 C657 0.1uF 47uF X5R 6.3V 1.3V transceiver supply 1 2 G 4 EN Sense/Adj SS NC GND 7 8 1.8V:1 9 1 GND_PAD 6 1.3V:1 1 0.01uF L610 FX3 1.8V supply For clocks, I/O U608 LT1963 1 Vin Vout 3 1.2V_FPGA:1 1 E GND GND 2 10uF X5R 6.3V C670 10uF X5R 6.3V 4 1.8V:1 1 C663 C664 0.1uF 10uF X5R 6.3V 3.3V_CLK:1 D L604 1 Vin C665 0.1uF Vout 5 NC 4 Vin PG 3.3V oscillator/clock supply 3 EN Vin Vout 14 3 Vin Vout 13 15 Vin Vout 12 16 Vin Vout 11 Vout 10 2 10uF X5R 6.3V 4 C620 10uF X5R 6.3V GND C616 E 5 2 MI1206K601R−10 EN Sense/Adj SS NC GND 7 C 8 J605 87224−2 2 T602 L609 ADP151AUJZ−3.3−R7 ADP150 U601 U607 ADP1755ACPZ−R7 ADP174X MI1206K601R−10 3.7V:1 F J604 87224−2 2 1.8V_FX3:1 MI1206K601R−10 C669 J609 87224−2 2 R616 4.22K 17 C656 F VSYS:1 J603 87224−2 1.2V_FX3:1 1.3V_SYNTH:1 1 J606 87224−2 2 R630 6.81K C667 1.3V transceiver synth supply C668 10uF X5R 6.3V 0.1uF D 9 GND_PAD 6 R631 4.22K 17 C C666 0.01uF B B B200 Power A A TITLE FILE: power.sch 7 PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 OF 8 22 REVISION: 2 DRAWN BY: nick, matt 23 24