CY62177DV30 MoBL® 32-Mbit (2 M × 16) Static RAM 32-Mbit (2 M × 16) Static RAM Features automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). ■ Very high speed: 55 ns ■ Wide voltage range: 2.20 V–3.60 V ■ Ultra-low active power ❐ Typical active current: 2 mA at f = 1 MHz ❐ Typical active current: 15 mA at f = fmax ■ Ultra low standby power ■ Easy memory expansion with CE1, CE2 and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Packages offered in a 48-ball fine ball grid array (FBGA) Functional Description The CY62177DV30 is a high-performance CMOS static RAM organized as 2M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones.The device also has an Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes. For a complete list of related documentation, click here. Logic Block Diagram 2048K × 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA-IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 BHE WE OE CE2 CE1 BLE Power-down Circuit Cypress Semiconductor Corporation Document Number: 38-05633 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 14, 2015 CY62177DV30 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05633 Rev. *I Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY62177DV30 MoBL® Pin Configuration Figure 1. 48-ball FBGApinout (Top View) [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A20 H Product Portfolio Power Dissipation VCC Range (V) Product CY62177DV30LL Speed (ns) Min Typ[2] Max 2.2 3.0 3.6 55 Operating ICC(mA) f = 1 MHz Standby ISB2(A) f = fmax Typ[2] Max Typ[2] Max Typ[2] Max 2 4 15 30 5 50 Notes 1. DNU pins have to be left floating or tied to Vss to ensure proper application. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. Document Number: 38-05633 Rev. *I Page 3 of 17 CY62177DV30 MoBL® Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied ......................................... –55 °C to + 125 °C Static discharge voltage (per MIL-STD-883, method 3015) .......................... >2001 V Latch-up current ..................................................... >200 mA Operating Range Supply voltage to ground potential ..... –0.3 V to VCC + 0.3 V DC voltage applied to outputs in High Z state [3, 4] ............................. –0.3 V to VCC + 0.3 V Device CY62177DV30LL Range Ambient Temperature VCC[5] Industrial –40 °C to +85 °C 2.20 V to 3.60 V DC input voltage[3, 4] ........................... –0.3 V to VCC + 0.3 V Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH voltage VOL Output LOW voltage VIH Input HIGH voltage Test Conditions Min Typ[6] Max Unit IOH = –0.1 mA VCC = 2.20 V 2.0 – – V IOH = –1.0 mA VCC = 2.70 V 2.4 – – V IOL = 0.1 mA VCC = 2.20 V – – 0.4 V IOL = 2.1 mA VCC = 2.70 V – – 0.4 V VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V V VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 V V VCC = 2.2 V to 2.7 V –0.3 – 0.6 V VCC = 2.7 V to 3.6 V VIL Input LOW voltage –0.3 – 0.8 V IIX Input leakage current GND VI VCC –1 – +1 A IOZ Output leakage current GND VO VCC, output disabled –1 – +1 A ICC VCC operating supply current f = fMAX = 1/tRC – 15 30 mA 2 4 mA f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels ISB1 Automatic CE power-down current – CMOS inputs CE1 VCC0.2 V, CE2 < 0.2 V, VIN VCC – 0.2 V, VIN 0.2 V), f = fMAX (address and data only), f = 0 (OE, WE, BHE and BLE), VCC = 3.60 V – 5 100 A ISB2 Automatic CE power-down current – CMOS inputs CE1 VCC 0.2 V, CE2 < 0.2 V, VIN VCC – 0.2 V or VIN 0.2 V, f = 0, VCC = 3.60 V – 5 50 A Notes 3. VIL(min.) = –2.0 V for pulse durations less than 20 ns. 4. VIH(Max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation requires linear VCC ramp from 0 to VCC(min) 500 s. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. Document Number: 38-05633 Rev. *I Page 4 of 17 CY62177DV30 MoBL® Capacitance Parameter [7] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max. Unit 12 pF 12 pF Thermal Resistance Parameter [7] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions BGA Unit Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 55 C/W 16 C/W AC Test Loads and Waveforms R1 VCC OUTPUT 50 pF Figure 2. AC Test Loads and Waveforms ALL INPUT PULSES VCC 90% 90% 10% 10% GND Fall time = 1 V/ns R2 Rise time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 2.5 V (2.2 V to 2.7 V) 3.0 V (2.7 V to 3.6 V) Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Note 7. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05633 Rev. *I Page 5 of 17 CY62177DV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ[9] Max Unit 1.5 – – V – – 25 A VDR VCC for data retention ICCDR Data retention current tCDR[8] Chip deselect to data retention time 0 – – ns tR[10] Operation recovery time 55 – – ns VCC= 1.5 V CE1 VCC 0.2 V, CE2 < 0.2 V, VIN VCC – 0.2 V or VIN 0.2 V Data Retention Waveform Figure 3. Data Retention Waveform [11, 12] VCC VCC, min. tCDR DATA RETENTION MODE VDR 1.5 V VCC, min. tR CE or BHE.BLE Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C 10. Full device operation requires linear VCC ramp from VDR to VCC(min.) 100 s or stable at VCC(min.) 100 s. Document Number: 38-05633 Rev. *I Page 6 of 17 CY62177DV30 MoBL® Switching Characteristics Over the Operating Range Parameter [12, 13] Description Min Max Unit Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 55 ns tDOE OE LOW to data valid – 25 ns tLZOE OE LOW to LOW Z[14] 5 – ns – 20 ns 10 – ns tHZOE tLZCE [14, 15] OE HIGH to High Z CE LOW to Low Z[14] Z[14, 15] tHZCE CE HIGH to High – 20 ns tPU CE LOW to power-up 0 – ns tPD CE HIGH to power-down – 55 ns tDBE BLE/BHE LOW to data valid – 55 ns Z[14] 10 – ns – 20 ns tLZBE BLE/BHE LOW to Low tHZBE BLE/BHE HIGH to HIGH Z[14, 15] Write Cycle [16, 17] tWC Write cycle time 55 – ns tSCE CE LOW to write end 40 – ns tAW Address set-up to write end 40 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE pulse width 40 – ns tBW BLE/BHE LOW to write end 40 – ns tSD Data set-up to write end 25 – ns tHD Data hold from write end 0 – ns [14, 15] tHZWE WE LOW to High Z – 20 ns tLZWE WE HIGH to Low Z[14] 10 – ns Notes 11. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 12. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 16. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 17. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 38-05633 Rev. *I Page 7 of 17 CY62177DV30 MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [18, 19, 20] tRC ADDRESS tOHA DATA I/O tAA VALID DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [18, 20, 21, 22] ADDRESS tRC CE tPD tHZCE tACE BHE/BLE tLZBE tDBE tHZBE OE tDOE DATA I/O tLZOE HIGH IMPEDANCE tHZOE HIGH IMPEDANCE VALID DATA OUT tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 18. All Read/Write switching waveforms are shown for 16-bit data transactions only. 19. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 20. WE is HIGH for read cycle. 21. Address valid prior to or coincident with CE, BHE, BLE transition LOW. 22. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 38-05633 Rev. *I Page 8 of 17 CY62177DV30 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (WE Controlled) [23, 24, 25, 26, 27, 28] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA IN See Note 26 tHZOE Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24, 25, 26, 27, 28] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA IN See Note 26 tHZOE Notes 23. All Read/Write switching waveforms are shown for 16-bit data transactions only. 24. Data I/O is high impedance if OE = VIH. 25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 26. During this period, the I/Os are in output state and input signals should not be applied. 27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 28. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document Number: 38-05633 Rev. *I Page 9 of 17 CY62177DV30 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [29, 30, 31, 32] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tHD tSD DATA I/O See Note 33 VALID DATA tLZWE tHZWE Figure 9. Write Cycle No. 4 (BHE/BLE Controlled) [29, 30, 31] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O See Note 33 tHD VALID DATA Notes 29. All Read/Write switching waveforms are shown for 16-bit data transactions only. 30. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 31. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 32. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. 33. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 38-05633 Rev. *I Page 10 of 17 CY62177DV30 MoBL® Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X X X X L H H L H L Mode Power High Z Deselect/power-down Standby (ISB) X High Z Deselect/power-down Standby (ISB) H H High Z Deselect/power-down Standby (ISB) L L L Data out (I/O0–I/O15) Read Active (ICC) H L H L Data out (I/O0–I/O7); High Z (I/O8–I/O15) Read Active (ICC) H H L L H High Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) L H H H L H High Z Output disabled Active (ICC) L H H H H L High Z Output disabled Active (ICC) L H H H L L High Z Output disabled Active (ICC) L H L X L L Data in (I/O0–I/O15) Write Active (ICC) L H L X H L Data in (I/O0–I/O7); High Z (I/O8–I/O15) Write Active (ICC) L H L X L H High Z (I/O0–I/O7); Data in (I/O8–I/O15) Write Active (ICC) Document Number: 38-05633 Rev. *I Inputs/Outputs Page 11 of 17 CY62177DV30 MoBL® Ordering Information Speed (ns) 55 Package Diagram Ordering Code CY62177DV30LL-55BAXI Package Type 51-85191 48-ball FBGA (8 mm × 9.5 mm × 1.2 mm) (Pb-free) Operating Range Industrial Ordering Code Definitions CY 621 7 7D V30 LL 55 BAX I Temperature Grade I = Industrial Package Type = BAX :48-ball FBGA (Pb-free) Speed Grade = 55ns Low Power Voltage Range (3 V Typical) Bus Width = X16 D = 130nm Technology Density = 32 Mbit MoBL SRAM Family Company ID: CY = Cypress Document Number: 38-05633 Rev. *I Page 12 of 17 CY62177DV30 MoBL® Package Diagram Figure 10. 48 ball FBGA (8 × 9.5 × 1.2 mm) Package Outline, 51-85191 51-85191 *C Document Number: 38-05633 Rev. *I Page 13 of 17 CY62177DV30 MoBL® Acronyms Acronym Document Conventions Description Units of Measure CMOS complementary metal oxide semiconductor FBGA fine ball grid array °C degrees Celsius I/O input/output MHz megahertz SRAM static random access memory A microampere mA milliampere ns nanosecond pF picofarad V volt ohm W watt Document Number: 38-05633 Rev. *I Symbol Unit of Measure Page 14 of 17 CY62177DV30 MoBL® Document History Page Document Title: CY62177DV30 MoBL®, 32-Mbit (2 M × 16) Static RAM Document #: 38-05633 Revision ECN Orig. of Change Submission Date ** 251075 AJU See ECN New data sheet *A 330363 AJU See ECN Updated Document Title (Replaced CYM62177DV30 with CY62177DV30). Added second chip enable (CE2) related information in all instances across the document. Updated Switching Characteristics: Added Note 12 and referred the same note in “Parameter” column. *B 400960 NXR See ECN Changed address of Cypress Semiconductor Corporation on Page 1 from “3901 North First Street” to “198 Champion Court”. Updated Electrical Characteristics: Changed maximum value of ISB1 parameter from 60 and 40 A to 100 A corresponding to L and LL versions for both the 55 and the 70 ns speed bins respectively. *C 469187 NXR See ECN Changed status from Preliminary to Final. Updated Electrical Characteristics: Changed maximum value of ISB2 parameter from 40 A to 50 A corresponding to LL version for both 45 ns and 55 ns speed bins. Updated Data Retention Characteristics: Changed maximum value of ICCDR parameter from 20 A to 25 A for LL version. Updated Ordering Information. *D 2896036 AJU 03/19/10 Updated Ordering Information (Removed inactive parts). Updated Package Diagram. Updated to new template. *E 3153110 RAME 01/25/2011 *F 3329873 RAME 07/27/11 *G 3685455 MEMJ 07/20/2012 Updated Switching Waveforms: Added Note 18 and referred the same note in all waveforms. Updated text in Switching Waveforms diagrams. Updated Package Diagram. *H 4576526 MEMJ 11/21/2014 Document Number: 38-05633 Rev. *I Description of Change Removed CY62177DV30L related information in all instances across the document. Removed 70 ns speed bin related information in all instances across the document. Added Ordering Code Definitions Updated to new template. Updated Functional Description: Removed Note “For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com website.” and its reference. Updated Capacitance: Removed Note “This applies for all packages.” and its reference in “Parameter” column (because of single package availability). Added Acronyms and Units of Measure. Updated template and styles according to current Cypress standards. Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Switching Characteristics: Added Note 17 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 32 and referred the same note in Figure 8. Updated Package Diagram: spec 51-85191 – Changed revision from *B to *C. Page 15 of 17 CY62177DV30 MoBL® Document History Page (continued) Document Title: CY62177DV30 MoBL®, 32-Mbit (2 M × 16) Static RAM Document #: 38-05633 Revision ECN Orig. of Change *I 4919314 VINI Document Number: 38-05633 Rev. *I Submission Date Description of Change 09/14/2015 Updated Switching Waveforms: Updated caption of Figure 9 (Removed “OE LOW”). Updated to new template. Completing Sunset Review. Page 16 of 17 CY62177DV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2015. T6he information contained herein is subject to change without notice. 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Document Number: 38-05633 Rev. *I Revised September 14, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 17