CY7C1010DV33 2-Mbit (256 K × 8) Static RAM 2-Mbit (256 K × 8) Static RAM Features Functional Description ■ Pin and function compatible with CY7C1010CV33 The CY7C1010DV33 is a high performance CMOS Static RAM organized as 256 K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1010DV33 is available in 36-pin SOJ and 44-pin TSOP II packages with center power and ground (revolutionary) pinout. For a complete list of related documentation, click here. Logic Block Diagram IO0 INPUT BUFFER IO1 256K x 8 ARRAY IO3 IO4 IO5 IO6 CE • IO7 POWER DOWN A17 A15 A16 A11 OE A12 A13 A14 COLUMN DECODER WE Cypress Semiconductor Corporation Document Number: 001-00062 Rev. *F IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 19, 2014 CY7C1010DV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 AC Switching Characteristics ......................................... 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 10 Document Number: 001-00062 Rev. *F Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1010DV33 Selection Guide -10 Unit Maximum Access Time Description 10 ns Maximum Operating Current 90 mA Maximum CMOS Standby Current 10 mA Pin Configuration Figure 1. 36-pin SOJ pinout [1] A4 A3 A2 A1 A0 CE IO0 IO1 VCC GND IO2 IO3 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A5 A6 A7 A8 OE IO7 IO6 GND VCC IO5 IO4 A9 A10 A11 A12 NC NC Figure 2. 44-pin TSOP II pinout [1] NC NC A4 A3 A2 A1 A0 CE IO0 IO1 VCC VSS IO2 IO3 WE A17 A16 A15 A14 A13 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE IO7 IO6 VSS VCC IO5 IO4 A9 A10 A11 A12 NC NC NC NC Note 1. NC pins are not connected on the die. Document Number: 001-00062 Rev. *F Page 3 of 16 CY7C1010DV33 DC Input Voltage [2] ............................ –0.3 V to VCC + 0.3 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage (MIL-STD-883, Method 3015) ................................ > 2001 V Storage Temperature ............................... –65 C to +150 C Latch Up Current ................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 C to +125 C Operating Range Supply Voltage on VCC Relative to GND [2] ...............................–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State [2] ................................ –0.3 V to VCC + 0.3 V Range Ambient Temperature VCC Industrial –40C to +85C 3.3V 0.3V Electrical Characteristics Over the Operating Range Parameter Description -10 Test Conditions VOH Output HIGH Voltage VCC = Min; IOH = –4.0 mA VOL Output LOW Voltage VCC = Min; IOL = 8.0 mA VIH Input HIGH Voltage Voltage[2] Min Max Unit 2.4 – V – 0.4 V 2.0 VCC + 0.3 V VIL Input LOW –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC 100 MHz – 90 mA 83 MHz – 80 66 MHz – 70 40 MHz – 60 ISB1 Automatic CE Power-down Current – TTL Inputs Max VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX – 20 mA ISB2 Automatic CE Power-down Current – CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 10 mA Note 2. VIL (min.) = –2.0V and VIH (max.) = VCC + 2.0V for pulse durations of less than 20 ns. Document Number: 001-00062 Rev. *F Page 4 of 16 CY7C1010DV33 Capacitance Parameter [3] Description CIN Input capacitance COUT I/O capacitance Test Conditions 36-pin SOJ TA = 25 C, f = 1 MHz, VCC = 3.3 V 44-pin TSOP II Unit 8 8 pF 8 8 pF Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 36-pin SOJ Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 44-pin TSOP II Unit 59.17 50.66 C/W 32.63 17.77 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [4] Z = 50 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT ALL INPUT PULSES 3.0 V OUTPUT 30 pF* GND 1.5 V (a) High-Z characteristics: 90% 90% 10% 10% Rise Time: 1 V/ns (b) Fall Time: 1 V/ns R 317 3.3 V OUTPUT 5 pF (c) R2 351 Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for all speeds using the test load shown in Figure 3 (c). Document Number: 001-00062 Rev. *F Page 5 of 16 CY7C1010DV33 Data Retention Characteristics Over the Operating Range Parameter [5] Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [6] Chip Deselect to Data Retention Time tR [7] VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Operation Recovery Time Min Max Unit 2 – V – 10 mA 0 – ns tRC – ns Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE VCC 3.0V VDR > 2V tCDR 3.0V tR CE Notes 5. No inputs may exceed VCC + 0.3 V. 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. Document Number: 001-00062 Rev. *F Page 6 of 16 CY7C1010DV33 AC Switching Characteristics Over the Operating Range Parameter [8] Description -10 Min Max Unit Read Cycle tpower[9] VCC(typical) to the first access 100 – s tRC Read Cycle Time 10 – ns tAA Address to Data Valid – 10 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 10 ns tDOE OE LOW to Data Valid – 5 ns [10] 0 – ns – 5 ns 3 – ns – 5 ns tLZOE OE LOW to Low Z Z[10, 11] tHZOE OE HIGH to High tLZCE CE LOW to Low Z[10] Z[10, 11] tHZCE CE HIGH to High tPU CE LOW to Power-up 0 – ns tPD CE HIGH to Power-down – 10 ns Write Cycle[12, 13] tWC Write Cycle Time 10 – ns tSCE CE LOW to Write End 7 – ns tAW Address Set-up to Write End 7 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-up to Write Start 0 – ns tPWE WE Pulse Width 7 – ns tSD Data Set-up to Write End 5 – ns tHD Data Hold from Write End 0 – ns [10] 3 – ns [10, 11] – 5 ns tLZWE tHZWE WE HIGH to Low Z WE LOW to High Z Notes 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 9. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 5. Transition is measured when the outputs enter a high impedance state. 12. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 13. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-00062 Rev. *F Page 7 of 16 CY7C1010DV33 Switching Waveforms Figure 5. Read Cycle No. 1 [14, 15] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 14. The device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid before or similar to CE transition LOW. Document Number: 001-00062 Rev. *F Page 8 of 16 CY7C1010DV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [17, 18] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 19 tHZOE Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 19 tHD DATA VALID tHZWE tLZWE Notes 17. Data IO is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 19. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 001-00062 Rev. *F Page 9 of 16 CY7C1010DV33 Truth Table CE H OE X WE X I/O0–I/O7 I/O8–I/O15 Mode High Z High Z Power Down Power Standby (ISB) L L H Data Out Data Out Read All Bits Active (ICC) L X L Data In Data In Write All Bits Active (ICC) L H H High Z High Z Selected, Outputs Disabled Active (ICC) Document Number: 001-00062 Rev. *F Page 10 of 16 CY7C1010DV33 Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C1010DV33-10VXI 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) CY7C1010DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 01 0 D V33 - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = V or ZS V = 36-pin (400-Mil) Molded SOJ ZS = 44-pin TSOP II Speed: 10 ns V33 = Voltage range (3 V to 3.6 V) Process Technology: D = C9, 90 nm Technology Data Width: 0 = 8-bits Density: 01 = 2-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-00062 Rev. *F Page 11 of 16 CY7C1010DV33 Package Diagrams Figure 9. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090 51-85090 *F Document Number: 001-00062 Rev. *F Page 12 of 16 CY7C1010DV33 Package Diagrams (continued) Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 001-00062 Rev. *F Page 13 of 16 CY7C1010DV33 Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable A microampere SOJ Small Outline J-lead s microsecond SRAM Static Random Access Memory mA milliampere TSOP Thin Small Outline Package mm millimeter TTL Transistor-Transistor Logic mW milliwatt WE Write Enable ns nanosecond ohm % percent pF picofarad V volt W watt Document Number: 001-00062 Rev. *F Symbol Unit of Measure Page 14 of 16 CY7C1010DV33 Document History Page Document Title: CY7C1010DV33, 2-Mbit (256 K × 8) Static RAM Document Number: 001-00062 Rev. ECN No. Submission Date Orig. of Change ** 342195 See ECN PCI New data sheet. *A 459073 See ECN NXR Converted Preliminary to Final. Removed Commercial Operating Range from product offering. Removed -8 ns and -12 speed bin Removed the Pin definitions table. Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Changed ICC max from 65 mA to 90 mA Changed the description of IIX from “Input Load Current” to “Input Leakage Current” Updated the Thermal Resistance table. Updated footnote #7 on High-Z parameter measurement Added footnote #12 Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table. *B 2602853 11/07/08 VKN / PYRS Added 36-pin SOJ package and its related information *C 3059211 10/14/2010 PRAS Added Ordering Code Definitions. Updated Package Diagrams. *D 3272897 06/07/2011 AJU *E 4207615 12/02/2013 MEMJ Updated Package Diagrams: spec 51-85090 – Changed revision from *E to *F. spec 51-85087 – Changed revision from *C to *E. Updated in new template. Completing Sunset Review. *F 4574311 11/19/2014 MEMJ Added related documentation hyperlink in page 1. Document Number: 001-00062 Rev. *F Description of Change Updated Functional Description (Removed “Refer to the Cypress application note AN1064, SRAM System Guidelines for best practice recommendations.”). Added Acronyms and Units of Measure. Updated in new template. Page 15 of 16 CY7C1010DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-00062 Rev. *F Revised November 19, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16