CY62157EV18 MoBL® 8-Mbit (512 K × 16) Static RAM 8-bit (512K x 16) Static RAM Features consumption when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: ■ Very high speed: 55 ns ■ Wide voltage range: 1.65 V–2.25 V ■ Pin compatible with CY62157DV18 and CY62157DV20 ■ Ultra low standby power ❐ Typical Standby current: 2 A ❐ Maximum Standby current: 8 A ■ Ultra low active power ❐ Typical active current: 1.8 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2 and OE features ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Available in Pb-free 48-ball very fine-pitch ball grid array (VFBGA) package Functional Description The CY62157EV18 is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power ■ Deselected (CE1 HIGH or CE2 LOW) ■ Outputs are disabled (OE HIGH) ■ Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or ■ Write operation is active (CE1 LOW, CE2 HIGH and WE LOW). Write to the device by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Read from the device by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 13 for a complete description of read and write modes. For a complete list of related documentation, click here. Product Portfolio Power Dissipation VCC Range (V) Product CY62157EV18 Speed (ns) Min Typ [1] Max 1.65 1.8 2.25 55 Operating ICC, (mA) Standby, ISB2 (A) f = fmax f = 1MHz Typ [1] Max Typ [1] Max Typ [1] Max 1.8 3 18 25 2 8 Note 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Cypress Semiconductor Corporation Document Number: 38-05490 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 21, 2014 CY62157EV18 MoBL® Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 512K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A17 A18 A15 A16 A14 A11 A12 A13 BHE WE CE2 OE BLE CE1 POWER DOWN CIRCUIT Document Number: 38-05490 Rev. *K BHE CE2 BLE CE1 Page 2 of 19 CY62157EV18 MoBL® Contents Pin Configuration ............................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Characteristics ................................................ 8 Switching Waveforms ...................................................... 9 Truth Table ...................................................................... 13 Ordering Information ...................................................... 14 Ordering Code Definitions ......................................... 14 Document Number: 38-05490 Rev. *K Package Diagrams .......................................................... 15 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History ........................................................... 17 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 3 of 19 CY62157EV18 MoBL® Pin Configuration Figure 1. 48-ball VFBGA pinout (Top View) [2] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O12 I/O3 I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Note 2. NC pins are not connected on the die. Document Number: 38-05490 Rev. *K Page 4 of 19 CY62157EV18 MoBL® Maximum Ratings DC input voltage [3, 4] ....... –0.2 V to 2.45 V (VCCmax + 0.2 V) Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Output current into outputs (LOW) ............................. 20 mA Ambient temperature with power applied ......................................... –55 °C to + 125 °C Latch-up current .................................................... > 200 mA Supply voltage to ground potential ........................... –0.2 V to 2.45 V (VCCmax + 0.2 V) Operating Range DC voltage applied to outputs in High-Z state [3, 4] .......... –0.2 V to 2.45 V (VCCmax + 0.2 V) Static discharge voltage (in accordance with MIL-STD-883, Method 3015) ................................. > 2001 V Device Range Ambient Temperature VCC [5] CY62157EV18LL Industrial –40 °C to +85 °C 1.65 V to 2.25 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 55 ns Min Typ [6] Max Unit VOH Output HIGH voltage IOH = –0.1 mA VCC = 1.65 V 1.4 – – V VOL Output LOW voltage IOL = 0.1 mA VCC = 1.65 V – – 0.2 V VIH Input HIGH voltage VCC = 1.65 V to 2.25 V 1.4 – VCC + 0.2 V V VIL Input LOW voltage VCC = 1.65 V to 2.25 V –0.2 – 0.4 V IIX Input leakage current GND < VI < VCC –1 – +1 A IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 A ICC VCC operating supply current f = fmax = 1/tRC – 18 25 mA – 1.8 3 mA f = 1 MHz VCC = VCC(max), IOUT = 0 mA CMOS levels ISB1[7] Automatic CE power down current – CMOS inputs CE1 > VCC0.2 V or CE2 < 0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V), f = fmax (address and data only), f = 0 (OE, WE, BHE and BLE), VCC = VCC(max). – 2 8 A ISB2 [7] Automatic CE power down current – CMOS Inputs CE1 > VCC – 0.2 V or CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max). – 2 8 A Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.5 V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating. Document Number: 38-05490 Rev. *K Page 5 of 19 CY62157EV18 MoBL® Capacitance Parameter [8] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 10 pF 10 pF Test Conditions BGA Unit Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 72 C/W 8.86 C/W TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Parameter [8] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms VCC OUTPUT R1 3V 30 pF INCLUDING JIG AND SCOPE 10% GND Rise Time = 1 V/ns R2 ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters Value Unit R1 13500 R2 10800 RTH 6000 VTH 0.80 V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05490 Rev. *K Page 6 of 19 CY62157EV18 MoBL® Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ [9] Max Unit 1.0 – – V – 1 3 A VDR VCC for data retention ICCDR[10] Data retention current tCDR [11] Chip deselect to data retention time 0 – – ns tR [12] Operation recovery time 55 – – ns VCC= VDR, CE1 > VCC – 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Data Retention Waveform Figure 3. Data Retention Waveform [13] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.0V VCC(min) tR CE1 or BHE.BLE or CE2 Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. Document Number: 38-05490 Rev. *K Page 7 of 19 CY62157EV18 MoBL® Switching Characteristics Over the Operating Range Parameter [14, 15] Description 55 ns Min Max Unit Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE1 LOW and CE2 HIGH to data valid – 55 ns tDOE OE LOW to data valid – 25 ns tLZOE OE LOW to Low-Z [16] 5 – ns [16, 17] tHZOE OE HIGH to High-Z tLZCE CE1 LOW and CE2 HIGH to Low-Z [16] tHZCE CE1 HIGH and CE2 LOW to High-Z [16, 17] – 18 ns 10 – ns – 18 ns ns tPU CE1 LOW and CE2 HIGH to power up 0 – tPD CE1 HIGH and CE2 LOW to power down – 55 ns BLE/BHE LOW to data valid – 55 ns 10 – ns – 18 ns tDBE tLZBE [18] tHZBE Write Cycle BLE/BHE LOW to Low-Z [16] BLE/BHE HIGH to High-Z [16, 17] [19, 20] tWC Write cycle time 45 – ns tSCE CE1 LOW and CE2 HIGH to write end 35 – ns ns tAW Address setup to write end 35 – tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns ns tPWE WE pulse width 35 – tBW BLE/BHE LOW to write end 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 18 ns 10 – ns tHZWE tLZWE WE LOW to High-Z [16, 17] WE HIGH to Low-Z [16] Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 6. 15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in production. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state. 18. If both byte enables are toggled together, this value is 10 ns. 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 20. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05490 Rev. *K Page 8 of 19 CY62157EV18 MoBL® Switching Waveforms Figure 4. Read Cycle 1 (Address Transition Controlled) [21, 22] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle 2 (OE Controlled) [22, 23] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 21. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 22. WE is HIGH for read cycle. 23. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document Number: 38-05490 Rev. *K Page 9 of 19 CY62157EV18 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle 1 (WE Controlled) [24, 25, 26] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA I/O NOTE 27 VALID DATA tHZOE Notes 24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 25. Data I/O is high impedance if OE = VIH. 26. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 27. During this period, the I/Os are in output state and input signals must not be applied. Document Number: 38-05490 Rev. *K Page 10 of 19 CY62157EV18 MoBL® Switching Waveforms (continued) Figure 7. Write Cycle 2 (CE1 or CE2 Controlled) [28, 29, 30] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O NOTE 31 tHD VALID DATA tHZOE Notes 28. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 29. Data I/O is high impedance if OE = VIH. 30. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 31. During this period, the I/Os are in output state and input signals must not be applied. Document Number: 38-05490 Rev. *K Page 11 of 19 CY62157EV18 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle 3 (WE Controlled, OE LOW) [32, 33] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATA I/O NOTE 34 tHD VALID DATA tLZWE tHZWE Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW) [32] WC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 34 tHD VALID DATA Notes 32. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 33. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 34. During this period, the I/Os are in output state and input signals must not be applied. Document Number: 38-05490 Rev. *K Page 12 of 19 CY62157EV18 MoBL® Truth Table CE1 CE2 WE OE BHE BLE H X[35] X X X[35] X[35] X[35] L X X X[35] X[35] X[35] X X L H H L H L Inputs/Outputs Mode Power High-Z Deselect/Power down Standby (ISB) X[35] High-Z Deselect/Power down Standby (ISB) H H High-Z Deselect/Power down Standby (ISB) L L L Data out (I/O0–I/O15) Read Active (ICC) H L H L Data out (I/O0–I/O7); High-Z (I/O8–I/O15) Read Active (ICC) H H L L H High-Z (I/O0–I/O7); Data out (I/O8–I/O15) Read Active (ICC) L H H H L H High-Z Output disabled Active (ICC) L H H H H L High-Z Output disabled Active (ICC) L H H H L L High-Z Output disabled Active (ICC) L H L X L L Data in (I/O0–I/O15) Write Active (ICC) L H L X H L Data in (I/O0–I/O7); High-Z (I/O8–I/O15) Write Active (ICC) L H L X L H High-Z (I/O0–I/O7); Data in (I/O8–I/O15) Write Active (ICC) Note 35. The ‘X’ (Don’t care) state for the Chip enables and Byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document Number: 38-05490 Rev. *K Page 13 of 19 CY62157EV18 MoBL® Ordering Information Speed (ns) Ordering Code 55 CY62157EV18LL-55BVXI Package Diagram Package Type 51-85150 48-ball VFBGA (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 5 7 E V18 LL - 55 BV X I Temperature Range: I = Industrial Pb-free Package Type: BV = 48-ball VFBGA Speed Grade: 55 ns Low Power Voltage Range: V18 = 1.8 V typical Process Technology: E = 90 nm Technology Datawidth: 7 = × 16 Density: 5 = 8-Mbit Family Code: 621 = MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05490 Rev. *K Page 14 of 19 CY62157EV18 MoBL® Package Diagrams Figure 10. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 38-05490 Rev. *K Page 15 of 19 CY62157EV18 MoBL® Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degrees Celsius CE Chip Enable A microampere CMOS Complementary Metal Oxide Semiconductor mA milliampere I/O Input/Output MHz megahertz OE Output Enable ns nanosecond SRAM Static Random Access Memory ohm VFBGA Very Fine-Pitch Ball Grid Array pF picofarad WE Write Enable V volt W watt Document Number: 38-05490 Rev. *K Symbol Unit of Measure Page 16 of 19 CY62157EV18 MoBL® Document History Document Title: CY62157EV18 MoBL®, 8-Mbit (512 K × 16) Static RAM Document Number: 38-05490 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 202862 See ECN AJU New data sheet *A 291272 See ECN SYT Converted from Advance Information to Preliminary Changed VCC Max from 2.20 to 2.25 V Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed ICCDR from 4 to 4.5 A Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bins Changed tDOE from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns Speed Bins respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Changed tSCE, tAW, and tBW from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns Speed Bins respectively Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Added Pb-Free Package Information *B 444306 See ECN NXR Converted from Preliminary to Final Removed 35 ns speed bin and “L” bin Changed ball E3 from DNU to NC Removed redundant footnote on DNU Modified Maximum Ratings spec for Supply Voltage and DC Input Voltage from 2.4V to 2.45V Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA to 25 mA for test condition f = fax = 1/tRC Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz Changed the ISB1 and ISB2 Max value from 4.5 A to 8 A and Typ value from 0.9 A to 2 A respectively Updated Thermal Resistance table Changed Test Load Capacitance from 50 pF to 30 pF Added Typ value for ICCDR Changed the ICCDR Max value from 4.5 A to 3 A Corrected tR in Data Retention Characteristics from 100 s to tRC ns Changed tLZOE from 3 to 5, changed tLZCE from 6 to 10, changed tHZCE from 22 to 18, changed tLZBE from 6 to 5, changed tPWE from 30 to 35, changed tSD from 22 to 25, and changed tLZWE from 6 to 10 Added footnote #13 Updated the ordering Information and replaced the Package Name column with Package Diagram *C 571786 See ECN VKN Replaced 45ns speed bin with 55ns *D 908120 See ECN VKN Added footnote #7 related to ISB2 Added footnote #12 related AC timing parameters *E 2934396 06/03/10 VKN Added footnote #23 related to chip enable Updated package diagram and template Document Number: 38-05490 Rev. *K Page 17 of 19 CY62157EV18 MoBL® Document History (continued) Document Title: CY62157EV18 MoBL®, 8-Mbit (512 K × 16) Static RAM Document Number: 38-05490 Rev. ECN No. Issue Date Orig. of Change *F 3110053 12/14/2010 PRAS Changed Table Footnotes to Footnotes. Added Ordering Code Definitions. *G 3243545 04/28/2011 RAME Updated as per template. Added Acronyms and Units of Measure table. *H 3295175 06/29/2011 RAME Added ISB1 and ICCDR to footnotes 7 and 11. Modified footnote 29 and referenced in Truth Table. *I 4102022 08/22/2013 VINI Updated Switching Characteristics: Updated Note 15. Updated Package Diagrams: spec 51-85150 – Updated to the latest revision *H. Updated in new template. *J 4384935 05/20/2014 MEMJ Updated Switching Characteristics: Added Note 20 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 33 and referred the same note in Figure 8. Completing Sunset Review. *K 4576526 11/21/2014 MEMJ Added related documentation hyperlink in page 1. Document Number: 38-05490 Rev. *K Description of Change Page 18 of 19 CY62157EV18 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05490 Rev. *K Revised November 21, 2014 Page 19 of 19 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.