CY7C1034DV33 6-Mbit (256K X 24) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 175 mA at f = 100 MHz ■ Low CMOS standby power ❐ ISB2 = 25 mA The CY7C1034DV33 is a high performance CMOS static RAM organized as 256K words by 24 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. To write to the device, enable the chip (CE1 LOW, CE2 HIGH, and CE3 LOW) while forcing the Write Enable (WE) input LOW. To read from the device, enable the chip by taking CE1 LOW, CE2 HIGH, and CE3 LOW, while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. See the Truth Table on page 7 for a complete description of Read and Write modes. ■ Operating voltages of 3.3 ± 0.3 V ■ 2.0 V data retention ■ Automatic power-down when deselected ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ Easy memory expansion with CE1, CE2, and CE3 features ■ Available in Pb-free standard 119-Ball PBGA The 24 IO pins (IO0 to IO23) are placed in a high impedance state when the device is deselected (CE1 HIGH, CE2 LOW, or CE3 HIGH) or when the output enable (OE) is HIGH during a write operation. (CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW). For a complete list of related documentation, click here. Logic Block Diagram 256K x 24 ARRAY IO0 – IO23 SENSE AMPS A(9:0) ROW DECODER INPUT BUFFER COLUMN DECODER CONTROL LOGIC CE1, CE2, CE3 WE OE A(17:10) Cypress Semiconductor Corporation Document Number: 001-08351 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 28, 2014 CY7C1034DV33 Selection Guide Description –10 Unit Maximum access time 10 ns Maximum operating current 175 mA Maximum CMOS standby current 25 mA Pin Configuration Figure 1. 119-Ball PBGA Top View [1] 1 2 3 4 5 6 7 A NC A B NC A A A A A NC A CE1 A A NC C IO12 NC CE2 A CE3 NC IO0 D IO13 E IO14 VDD VSS VSS VSS VDD IO1 VSS VDD VSS VDD VSS IO2 F IO15 VDD VSS VSS VSS VDD IO3 G H IO16 VSS VDD VSS VDD VSS IO4 IO17 VDD VSS VSS VSS VDD IO5 J NC VSS VDD VSS VDD VSS NC K IO18 VDD VSS VSS VSS VDD IO6 L IO19 VSS VDD VSS VDD VSS IO7 M IO20 VDD VSS VSS VSS VDD IO8 N IO21 VSS VDD VSS VDD VSS IO9 P IO22 VDD VSS VSS VSS VDD IO10 R IO23 NC NC NC NC NC IO11 T NC A A WE A A NC U NC A A OE A A NC Note 1. NC pins are not connected on the die. Document Number: 001-08351 Rev. *G Page 2 of 12 CY7C1034DV33 DC Input Voltage [2] ............................. –0.5 V to VCC + 0.5 V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage............ ...............................>2001 V Storage Temperature ............................... –65 C to +150 C (MIL-STD-883, Method 3015) Ambient Temperature with Power Applied .......................................... –55 C to +125 C Latch up Current...................................................... >200 mA Operating Range Supply Voltage on VCC Relative to GND [2] ..–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State [2] ................................. –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Industrial –40 C to +85 C 3.3 V 0.3 V DC Electrical Characteristics Over the operating range Parameter Description Test Conditions [3] VOH Output HIGH voltage Min VCC, IOH = –4.0 mA VOL Output LOW voltage Min VCC, IOL = 8.0 mA –10 Min Unit Max 2.4 V 0.4 V VIH Input HIGH voltage 2.0 VCC + 0.3 V VIL [2] Input LOW voltage –0.3 0.8 V IIX Input leakage current GND < VIN < VCC –1 +1 A IOZ Output leakage current GND < VOUT < VCC, output disabled –1 +1 A ICC VCC operating supply current Max VCC, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels 175 mA ISB1 Automatic CE power-down current — TTL inputs Max VCC, CE1, CE3 > VIH, CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX 30 mA ISB2 Automatic CE power-down current — CMOS inputs Max VCC, CE1, CE3 > VCC – 0.3 V, CE2 < 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 25 mA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input capacitance COUT IO capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 10 pF 119-Ball PBGA Unit 20.31 C/W 8.35 C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board Notes 2. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 3. CE refers to a combination of CE1, CE2, and CE3. CE is active LOW when CE1 is LOW, CE2 is HIGH, and CE3 is LOW. CE is HIGH when CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 001-08351 Rev. *G Page 3 of 12 CY7C1034DV33 AC Test Loads and Waveform [4] 50 OUTPUT Z0 = 50 R1 317 3.3V VTH = 1.5 V OUTPUT 30 pF* R2 351 5 pF* *Including jig and scope (a) (b) *Capacitive Load consists of all components of the test environment All input pulses 3.0V 90% 10% GND 90% 10% Fall Time:> 1V/ns Rise Time > 1V/ns (c) AC Switching Characteristics Over the operating range [5] Parameter Description –10 Min Max Unit Read Cycle tpower [6] VCC(Typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns – 10 ns – 5 ns 1 – ns – 5 ns tACE CE active LOW to data tDOE OE LOW to data valid Z [7] tLZOE OE LOW to low tHZOE OE HIGH to high Z [7] tLZCE tHZCE valid [3] CE active LOW to low Z [3, 7] 3 – ns Z [3, 7] – 5 ns power-up [3, 8] 0 – ns – 10 ns CE deselect HIGH to high tPU CE active LOW to tPD CE deselect HIGH to power-down [3, 8] Notes 4. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of the AC Test Loads and Waveform [4], unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveform [4]. Transition is measured 200 mV from steady state voltage. 8. These parameters are guaranteed by design and are not tested. Document Number: 001-08351 Rev. *G Page 4 of 12 CY7C1034DV33 AC Switching Characteristics (continued) Over the operating range [5] Parameter –10 Description Unit Min Max 10 – ns 7 – ns Write Cycle [9, 10, 13] tWC Write cycle time tSCE CE active LOW to write end [3] tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data setup to write end 5.5 – ns tHD Data hold from write end 0 – ns WE HIGH to low Z [7] 3 – ns WE LOW to high Z [7] – 5 ns tLZWE tHZWE Data Retention Characteristics Over the operating range Parameter VDR Conditions [3] Description VCC for data retention current[9] ICCDR Data retention tCDR [11] Chip deselect to data retention time tR [12] Operation recovery time VCC = 2 V, CE1, CE3 > VCC – 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min Typ Max Unit 2 – – V – – 25 mA 0 – – ns tRC – – ns Figure 2. Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE Notes 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW. Chip enables must be active and WE must be LOW to initiate a write and the transition of any of these signals terminates the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 001-08351 Rev. *G Page 5 of 12 CY7C1034DV33 Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14] tRC RC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATA OUT VALID Figure 4. Read Cycle No. 2 (OE Controlled) [3, 14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA I/O tHZCE tLZOE HIGH IMPEDANCE DATA OUT VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA IN VALID Notes 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE transition LOW. 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-08351 Rev. *G Page 6 of 12 CY7C1034DV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATA IN VALID NOTE 18 tHZOE Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATA IN VALID tLZWE tHZWE Truth Table CE1 CE2 CE3 OE WE IO0 – IO23 Mode Power H X X X X High Z Power-down Standby (ISB) X L X X X High Z Power-down Standby (ISB) X X H X X High Z Power-down Standby (ISB) L H L L H Full Data Out Read Active (ICC) L H L X L Full Data In Write Active (ICC) L H L H H High Z Selected, outputs disabled Active (ICC) Note 18. During this period, the IOs are in the output state and input signals are not applied. 19. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. Document Number: 001-08351 Rev. *G Page 7 of 12 CY7C1034DV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1034DV33-10BGXI Package Name Package Type 51-85115 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 03 4 D V33 - 10 BGX I Temperature Range: I = Industrial Package Type: BGX = 119-ball PBGA (Pb-free) Speed: 10 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 4 = Data width × 24-bits 03 = 6-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document Number: 001-08351 Rev. *G Page 8 of 12 CY7C1034DV33 Package Diagram Figure 8. 119-ball PBGA (14 x 22 x 2.4 mm) 51-85115 Rev. *D Document Number: 001-08351 Rev. *G Page 9 of 12 CY7C1034DV33 Acronyms Acronym Description CMOS complementary metal oxide semiconductor I/O input/output SRAM static random access memory TSOP thin small outline package TTL transistor-transistor logic Document Conventions Units of Measure Symbol Unit of Measure °C degrees Celsius A microamperes mA milliamperes MHz megahertz ns nanoseconds pF picofarads V volts ohms W watts Document Number: 001-08351 Rev. *G Page 10 of 12 CY7C1034DV33 Document History Page Document Title: CY7C1034DV33 6-Mbit (256K X 24) Static RAM Document Number: 001-08351 REV. ECN NO. Orig. of Change Submission Date Description of Change ** 469517 NXR See ECN New data sheet *A 499604 NXR See ECN Added note 1 for NC pins Changed ICC specification from 150 mA to 185 mA Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics Table on page 4 *B 1462586 VKN/SFV See ECN Converted from preliminary to final Updated block diagram Changed ICC specification from 185 mA to 225 mA Updated thermal specs *C 2644842 VKN/PYRS 01/23/09 Replaced Commercial range with the Industrial Replaced 8 ns speed with 10 ns *D 3109199 PRAS 12/13/2010 Added Ordering Code Definitions. Updated Package Diagram. *E 3388455 TAVA 09/29/2011 Minor text edits. Added Acronyms and Document Conventions. Updated template. *F 4548836 MEMJ 10/22/2014 Updated Package Diagram: spec 51-85115 – Changed revision from *C to *D Completing Sunset Review. *G 4576478 MEMJ 11/21/2014 Added related documentation hyperlink in page 1. Added Note 19 in Switching Waveforms. Added note reference 19 in Figure 7. Document Number: 001-08351 Rev. *G Page 11 of 12 CY7C1034DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2005-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-08351 Rev. *G Revised November 28, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 12 of 12