CY7C10212CV33 1-Mbit (64 K × 16) Static RAM 1-Mbit (64 K × 16) Static RAM Features Functional Description ■ Temperature ranges ❐ Automotive-E: –40 °C to 125 °C ■ Pin and function compatible with CY7C10212CV33 ■ High speed ❐ tAA = 12 ns (Automotive-E) ■ CMOS for optimum speed and power ■ Low active power: 325 mW (max) ■ Automatic power down when deselected ■ Independent control of upper and lower bits ■ Available in Pb-free 48-ball FBGA package The CY7C10212CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. For more information, see the Truth Table on page 9 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For a complete list of related documentation, click here. Logic Block Diagram 64K x 16 RAM Array SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE Cypress Semiconductor Corporation Document Number: 001-82303 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2014 CY7C10212CV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Document Number: 001-82303 Rev. *B Package Diagrams .......................................................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC® Solutions ...................................................... 14 Cypress Developer Community ................................. 14 Technical Support ..................................................... 14 Page 2 of 14 CY7C10212CV33 Selection Guide Description -12 Unit Maximum Access Time 12 ns Maximum Operating Current 90 mA Maximum CMOS Standby Current 10 mA Pin Configuration Figure 1. 48-ball FBGA pinout [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O2 I/O1 C VSS I/O11 NC A7 VCC D VCC NC NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O12 I/O3 I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Note 1. NC pins are not connected on the die. Document Number: 001-82303 Rev. *B Page 3 of 14 CY7C10212CV33 DC Input Voltage [2] ............................ –0.3 V to VCC + 0.3 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Storage Temperature ............................... –65 C to +150 C Latch Up Current ................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 C to +125 C Operating Range Supply Voltage on VCC Relative to GND [2] ...............................–0.3 V to +4.6 V DC Voltage Applied to Outputs in High Z State [2] ................................ –0.3 V to VCC + 0.3 V Range Ambient Temperature (TA) VCC Automotive-E –40 C to +125 C 3.3 V 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA -12 Min Max 2.4 – Unit V VOL Output LOW Voltage – 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 V VIL Input LOW Voltage [2] –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –12 +12 A I/OZ Output Leakage Current GND < VI < VCC, Output disabled –12 +12 A ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC – 90 mA ISB1 Automatic CE Power Down Current — TTL Inputs Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX – 20 mA ISB2 Automatic CE Power Down Current — CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 10 mA Note 2. VIL(min) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns. Document Number: 001-82303 Rev. *B Page 4 of 14 CY7C10212CV33 Capacitance Parameter [3] Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max Unit 8 pF 8 pF Test Conditions 48-ball FBGA Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 95.32 C/W 10.68 C/W TA = 25 C, f = 1 MHz, VCC = 3.3 V Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Speed is tested using the Thevenin load shown in Figure 2 (a). High Z characteristics are tested using the test load shown in Figure 2 (b). Document Number: 001-82303 Rev. *B Page 5 of 14 CY7C10212CV33 Switching Characteristics Over the Operating Range Parameter [5] Description -12 Min Max Unit Read Cycle tpower[6] VCC(Typical) to the First Access 100 – s tRC Read Cycle Time 12 – ns tAA Address to Data Valid – 12 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 12 ns tDOE OE LOW to Data Valid – 6 ns 0 – ns – 6 ns 3 – ns – 6 ns tLZOE OE LOW to Low Z[7] Z[7, 8] tHZOE OE HIGH to High tLZCE CE LOW to Low Z[7] Z[7, 8] tHZCE CE HIGH to High tPU[9] tPD[9] CE LOW to Power Up 0 – ns CE HIGH to Power Down – 12 ns tDBE Byte Enable to Data Valid – 6 ns tLZBE Byte Enable to Low Z 0 – ns Byte Disable to High Z – 6 ns tHZBE Write Cycle[10, 11] tWC Write Cycle Time 12 – ns tSCE CE LOW to Write End 9 – ns tAW Address Setup to Write End 9 – ns tHA Address Hold from Write End 0 – ns tSA Address Setup to Write Start 0 – ns tPWE WE Pulse Width 8 – ns tSD Data Setup to Write End 6 – ns tHD Data Hold from Write End 0 – ns tLZWE WE HIGH to Low Z[7] 3 – ns – 6 ns 8 – ns [7, 8] tHZWE WE LOW to High Z tBW Byte Enable to End of Write Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2 on page 5. Transition is measured 500 mV from steady state voltage. 9. This parameter is guaranteed by design and is not tested. 10. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE is LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle pulse width for write cycle 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 001-82303 Rev. *B Page 6 of 14 CY7C10212CV33 Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled) [12, 13] tRC RC ADDRESS tOHA DATA OUT tAA PREVI/OUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Notes 12. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document Number: 001-82303 Rev. *B Page 7 of 14 CY7C10212CV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE t BW BHE, BLE tSD tHD DATA I/O Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes 15. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-82303 Rev. *B Page 8 of 14 CY7C10212CV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE BLE BHE H X X X X High Z L L H L L L H H L X L I/O0 – I/O7 I/O8 – I/O15 Mode Power Standby (ISB) High Z Power Down Data Out Data Out Read – All Bits Active (ICC) Data Out High Z Read – Lower Bits Only Active (ICC) L High Z Data Out Read – Upper Bits Only Active (ICC) L L Data In Data In Write – All Bits Active (ICC) L H Data In High Z Write – Lower Bits Only Active (ICC) H L High Z Data In Write – Upper Bits Only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document Number: 001-82303 Rev. *B Page 9 of 14 CY7C10212CV33 Ordering Information Speed (ns) 12 Ordering Code CY7C10212CV33-12BAXE Package Diagram Package Type 51-85106 48-ball FBGA (Pb-free) Operating Range Automotive-E Ordering Code Definitions CY 7 C 1 02 1 2 C V33 - 12 BA X E Temperature Range: E = Automotive-E Pb-free Package Type: BA = 48-ball FBGA Speed: 12 ns Voltage range: V33 = 3 V to 3.6 V Process Technology: C = 0.16 µm Technology Fixed Value Data width: 1 = × 16-bits Density: 02 = 1-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-82303 Rev. *B Page 10 of 14 CY7C10212CV33 Package Diagrams Figure 8. 48-ball FBGA (7 × 8.5 × 1.2 mm) BA48A Package Outline, 51-85106 51-85106 *G Document Number: 001-82303 Rev. *B Page 11 of 14 CY7C10212CV33 Acronyms Acronym Document Conventions Description Units of Measure BGA Ball Grid Array CE Chip Enable °C degree Celsius CMOS Complementary Metal Oxide Semiconductor µA microampere FBGA Fine-Pitch Ball Grid Array µs microsecond I/O Input/Output mA milliampere OE Output Enable mm millimeter SRAM Static Random Access Memory mW milliwatt TQFP Thin Quad Flat Pack MHz megahertz TTL Transistor-Transistor Logic ns nanosecond WE Write Enable % percent pF picofarad V volt W watt Document Number: 001-82303 Rev. *B Symbol Unit of Measure Page 12 of 14 CY7C10212CV33 Document History Page Document Title: CY7C10212CV33, 1-Mbit (64 K × 16) Static RAM Document Number: 001-82303 Rev. ECN No. Submission Date Orig. of Change ** 3723052 10/29/2012 TAVA New data sheet. *A 4178071 10/30/2013 VINI Updated in new template. Completing Sunset Review. *B 4571877 11/18/2014 VINI Added related documentation hyperlink in page 1. Added Note 11 in Switching Characteristics. Added note reference 11 in the Switching Characteristics table. Updatd Figure 7 title. Document Number: 001-82303 Rev. *B Description of Change Page 13 of 14 CY7C10212CV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing cypress.com/go/memory cypress.com/go/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-82303 Rev. *B Revised November 18, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 14 of 14