CY7C1021BN 1-Mbit (64 K × 16) Static RAM 1-Mbit (64 K × 16) Static RAM Features ■ Functional Description Temperature ranges ❐ Commercial: 0 °C to 70 °C ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ❐ Automotive-E: –40 °C to 125 °C The CY7C1021BN is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. ■ High speed ❐ tAA = 15 ns (Automotive) ■ Complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Low active power ❐ 825 mW (maximum) ■ Automatic power down when deselected ■ Independent control of upper and lower bits ■ Available in Pb-free and non Pb-free 44-pin TSOP II and 44-pin 400-mil-wide SOJ Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from the input/output (I/O) pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking CE and Output Enable (OE) LOW while forcing WE HIGH. If BLE is LOW, then data from the memory location specified by the address pins appears on I/O1 to I/O8. If BHE is LOW, then data from memory appears on I/O9 to I/O16. See the Truth Table on page 11 for a complete description of read and write modes. The I/O pins (I/O1 through I/O16) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, WE LOW). The CY7C1021BN is available in standard 44-pin TSOP type II and 44-pin 400-mil-wide SOJ packages. Use part number CY7C1021BN when ordering 15 ns tAA. For a complete list of related resources, click here. Logic Block Diagram 64K x 16 RAM Array 512 X 2048 Sense Amps A7 A6 A5 A4 A3 A2 A1 A0 Row Decoder Data In Drivers I/O1–I/O8 I/O9–I/O16 Column Decoder A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE Cypress Semiconductor Corporation Document Number: 001-06494 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 23, 2015 CY7C1021BN Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Document Number: 001-06494 Rev. *I Package Diagrams .......................................................... 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1021BN Selection Guide Description CY7C1021B-15 Maximum access time (ns) Maximum operating current (mA) Maximum CMOS standby current (mA) 15 Commercial/Industrial 130 Automotive-A 130 Automotive-E 130 Commercial/Industrial 10 Commercial/Industrial (L version) 0.5 Automotive-A (L version) 0.5 Automotive-E 15 Pin Configuration Figure 1. 44-pin SOJ/TSOP II pinout (Top View) A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC Document Number: 001-06494 Rev. *I 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC Page 3 of 16 CY7C1021BN Pin Definitions Pin Name Pin Number I/O Type A0–A15 1–5,18–21, 24–27, 42–44 Input Description Address inputs used to select one of the address locations. I/O1–I/O16 7–10, 13–16, Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation. 29–32, 35–38 NC 22, 23, 28 WE 17 Input/Control Write enable input, active LOW. When selected LOW, a write is conducted. When deselected HIGH, a read is conducted. No Connect Not connected to the die. CE 6 Input/Control Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 40, 39 Input/Control Byte enable select inputs, active LOW. BHE controls I/O16–I/O9, BLE controls I/O8–I/O1. OE 41 VSS 12, 34 VCC 11, 33 Input/Control Output enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. Power Supply Power supply inputs to the device. Document Number: 001-06494 Rev. *I Page 4 of 16 CY7C1021BN Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Latch-up current .................................................... > 200 mA Ambient temperature with power applied .......................................... –55C to +125 C Operating Range Range Supply voltage on VCC relative to GND [1] ................................–0.5 V to +7.0 V Ambient Temperature (TA)[2] VCC 0 C to +70 C 5 V 10% Commercial DC voltage applied to outputs in High Z state [1] ................................ –0.5 V to VCC + 0.5 V Industrial DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V –40 C to +85 C Automotive-A –40 C to +85 C Automotive-E –40 C to +125 C Electrical Characteristics Over the operating range Parameter Description Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage voltage[1] VIL Input LOW IIX Input leakage current IOZ ICC ISB1 ISB2 Output leakage current VCC operating supply current Automatic CE power down current – TTL inputs Automatic CE power down current – CMOS inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC -15 Min Max Unit 2.4 – V – 0.4 V 2.2 6.0 V –0.5 0.8 V Commercial / Industrial –1 +1 A Automotive-A –1 +1 A Automotive-E –4 +4 A Commercial / Industrial –1 +1 A Automotive-A –1 +1 A Automotive-E –4 +4 A Commercial / Industrial – 130 mA Automotive-A – 130 – 130 Max VCC, CE > VIH, Commercial / Industrial VIN > VIH or VIN < VIL, Automotive-A f = fMAX Automotive-E Automotive-E – 40 – 40 – 50 Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Commercial / Industrial – 10 Commercial / Industrial (L) – 0.5 Automotive-A (L) – 0.5 Automotive-E – 15 mA mA Notes 1. VIL (min.) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. Document Number: 001-06494 Rev. *I Page 5 of 16 CY7C1021BN Capacitance Parameter [3] Description Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V CIN Input capacitance COUT Output capacitance Max Unit 8 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 44-pin SOJ 44-pin TSOP II Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 64.32 76.89 C/W 31.03 14.28 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R 481 5V OUTPUT R 481 5V 3.0 V OUTPUT 30 pF R2 255 INCLUDING JIG AND SCOPE (a) OUTPUT Equivalent to: THÉVENIN EQUIVALENT 5 pF R2 GND 255 INCLUDING JIG AND SCOPE (b) 167 Rise Time: 1 V/ns ALL INPUT PULSES 90% 10% 90% 10% Fall Time: 1 V/ns 1.73 V 30 pF Note 3. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-06494 Rev. *I Page 6 of 16 CY7C1021BN Switching Characteristics Over the operating range Parameter [4] Description -15 Min Max Unit Read Cycle tRC Read cycle time 15 – ns tAA Address to data valid – 15 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 15 ns tDOE OE LOW to data valid – 7 ns [4] 0 – ns Z[5, 6] – 7 ns tLZOE tHZOE OE LOW to low Z OE HIGH to high Z[5] tLZCE CE LOW to low 3 – ns tHZCE CE HIGH to high Z[5, 6] – 7 ns tPU CE LOW to power up 0 – ns tPD CE HIGH to power down – 15 ns tDBE Byte enable to data valid – 7 ns tLZBE Byte enable to low Z[5] 0 – ns – 7 ns tHZBE Write Cycle Byte disable to high Z[5, 6] [7, 8] tWC Write cycle time 15 – ns tSCE CE LOW to write end 10 – ns tAW Address setup to write end 10 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 12 – ns tSD Data setup to write end 8 – ns tHD Data hold from write end 0 – ns [5] tLZWE WE HIGH to low Z 3 – ns tHZWE WE LOW to high Z[5, 6] – 7 ns tBW Byte enable to write end 9 – ns Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30 pF load capacitance. 5. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2 on page 6. Transition is measured 500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE / BLE LOW. CE, WE, and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle pulse width for the Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE. Document Number: 001-06494 Rev. *I Page 7 of 16 CY7C1021BN Switching Waveforms Figure 3. Read Cycle No. 1 [9, 10] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% IICC CC IISB SB Notes 9. Device is continuously selected. OE, CE, BHE, and BHE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document Number: 001-06494 Rev. *I Page 8 of 16 CY7C1021BN Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [12, 13] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes 12. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-06494 Rev. *I Page 9 of 16 CY7C1021BN Switching Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Document Number: 001-06494 Rev. *I Page 10 of 16 CY7C1021BN Truth Table CE OE WE BLE BHE I/O1–I/O8 I/O9–I/O16 H X X X X High Z High Z L L H L L Data out Data out L H Data out H L L L X L Mode Power down Power Standby (ISB) Read - All bits Active (ICC) High Z Read - Lower bits only Active (ICC) High Z Data out Read - Upper bits only Active (ICC) L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L H H X X High Z High Z Selected, outputs disabled Active (ICC) L X X H H High Z High Z Selected, outputs disabled Active (ICC) Document Number: 001-06494 Rev. *I Page 11 of 16 CY7C1021BN Ordering Information Cypress offers other versions of this product type in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 15 Ordering Code Package Diagram Package Type Operating Range CY7C1021BNL-15VXC 51-85082 44-pin (400-mil) Molded SOJ (Pb-free) Commercial CY7C1021BNL-15ZXI 51-85087 44-pin TSOP Type II (Pb-free) Industrial CY7C1021BNL-15ZSXA 51-85087 44-pin TSOP Type II (Pb-free) Automotive-A Automotive-E CY7C1021BN-15ZSXE Ordering Code Definitions CY 7 C 1 02 1 X BN L - 15 XX X X Temperature Range: X = C or I or A or E C = Commercial; I = Industrial; A = Automotive-A; E = Automotive-E Pb-free Package Type: XX = V or Z or ZS V = 44-pin (400-mil) Molded SOJ Z or ZS = 44-pin TSOP Type II Speed: 15 ns Low Power BN = 250 nm Technology X = blank or 1 blank = 12 ns or 15 ns; 1 = 10 ns Bus Width: × 16 bits 02 = 2-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-06494 Rev. *I Page 12 of 16 CY7C1021BN Package Diagrams Figure 8. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082 51-85082 *E Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 001-06494 Rev. *I Page 13 of 16 CY7C1021BN Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output mA milliampere OE Output Enable mm millimeter SOJ Small Outline J-lead mW milliwatt SRAM Static Random Access Memory ns nanosecond TSOP Thin Small Outline Package ohm TTL Transistor-Transistor Logic % percent WE Write Enable pF picofarad V volt W watt Document Number: 001-06494 Rev. *I Symbol Unit of Measure Page 14 of 16 CY7C1021BN Document History Page Document Title: CY7C1021BN, 1-Mbit (64 K × 16) Static RAM Document Number: 001-06494 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 423877 See ECN NXR New data sheet. *A 505726 See ECN NXR Removed IOS parameter from DC Electrical Characteristics table. Updated Ordering Information (Added Automotive products). *B 2897061 03/22/10 AJU Updated Ordering Information (Removed obsolete parts). Updated Package Diagrams. *C 2947254 06/08/10 RAME Updated Pin Definitions (Replaced “Byte write select inputs” with “Byte Enable select inputs” in description of pin BHE, BLE). Updated AC Test Loads and Waveforms (Updated Figure 2 (Added ohm () symbol in Thevenin equivalent circuit)). Updated Switching Characteristics (Updated Note 5 (Included tHZBE and tLZBE in the note)). Updated Ordering Information (Included operating range for CY7C1021BNL-15ZXI in ordering information table). *D 3328634 26/07/2011 AJU Updated Features (Removed the information associated with speed bins -10 and -12). Removed the note “For best practice recommendations, refer to the Cypress application note, SRAM System Design Guidelines-AN1064.” in page 1 and its reference in Functional Description. Updated Functional Description (Removed the information associated with speed bins -10 and -12). Updated Selection Guide (Removed the information associated with speed bins -10 and -12). Updated Electrical Characteristics (Removed the information associated with speed bins -10 and -12). Updated Switching Characteristics (Removed the information associated with speed bins -10 and -12). Updated Ordering Information. Added Acronyms and Units of Measure. Updated to new template. *E 4125119 09/16/2013 VINI Updated Package Diagrams: spec 51-85082 – Changed revision from *C to *E. spec 51-85087 – Changed revision from *C to *E. Updated to new template. Completing Sunset Review. *F 4545523 10/20/2014 VINI Updated Document Title to read as “CY7C1021BN, 1-Mbit (64 K × 16) Static RAM”. Removed CY7C10211BN related information in all instances across the document. Updated Switching Characteristics: Removed “CY7C1021B” and retained “-15” in column heading “CY7C1021B-15”. Added Note 8 and referred the same note in “Write Cycle”. Added tPWE parameter and its details. Completing Sunset Review. *G 4557296 10/31/2014 VINI Updated Switching Characteristics: Updated minimum and maximum values of tPWE parameter. *H 4578500 12/16/2014 VINI Updated Ordering Information: Removed the prune part number CY7C1021BN-15VXE. *I 4984333 10/23/2015 NILE Updated to new template. Completing Sunset Review. Document Number: 001-06494 Rev. *I Page 15 of 16 CY7C1021BN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06494 Rev. *I Revised October 23, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16