CY7C1021BNV33 64 K × 16 Static RAM 64 K × 16 Static RAM Features Functional Description The CY7C1021BNV33 [1] is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. ■ 3.3 V operation (3.0 V–3.6 V) ■ High speed ❐ tAA = 15 ns ■ CMOS for optimum speed/power ■ Low Active Power ❐ 576 mW (max) ■ Low CMOS Standby Power ❐ 1.80 mW (max) ■ Automatic power-down when deselected ■ Independent control of upper and lower bits ■ Available in 44-pin TSOP II and 48-ball Mini BGA package Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021BNV33 is available in standard 44-pin TSOP Type II and 48-ball mini BGA packages.a For a complete list of related documentation, click here. Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document Number: 001-06433 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 16, 2015 CY7C1021BNV33 Logic Block Diagram 64K x 16 RAM Array SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 A8 A9 A10 A11 A12 A13 A14 A15 COLUMN DECODER BHE WE CE OE BLE Selection Guide -15 Maximum Access Time (ns) 15 Maximum Operating Current (mA) 160 Maximum CMOS Standby Current (mA) 0.5 Document Number: 001-06433 Rev. *F Page 2 of 18 CY7C1021BNV33 Contents Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 7 Data Retention Characteristics ....................................... 8 Data Retention Waveform ................................................ 8 Switching Waveforms ...................................................... 9 Truth Table ...................................................................... 12 Document Number: 001-06433 Rev. *F Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Page 3 of 18 CY7C1021BNV33 Pin Configurations TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 37 36 35 34 33 32 31 30 29 28 27 13 14 15 16 17 18 19 20 21 22 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Mini BGA Top View Document Number: 001-06433 Rev. *F 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O6 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A9 A10 A11 H A8 NC Page 4 of 18 CY7C1021BNV33 DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-Up Current ................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Operating Range Supply Voltage on VCC to Relative GND [2] ...............................–0.5 V to +4.6 V Range DC Voltage Applied to Outputs in High Z State [2] ................................ –0.5 V to VCC + 0.5 V Ambient Temperature VCC –40 °C to +85 °C 3.3 V 10% Industrial Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage [2] -15 Unit Min Max 2.4 – V – 0.4 V 2.2 VCC + 0.3 V VIL Input LOW Voltage –0.3 0.8 V IIX Input Load Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC – 160 mA ISB1 Automatic CE Power Down Current – TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 mA ISB2 Automatic CE Power Down Current – CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 500 A Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz Max Unit 6 pF 8 pF Notes 2. Minimum voltage is –2.0 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-06433 Rev. *F Page 5 of 18 CY7C1021BNV33 AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms R 317 3.3 V R 317 3.3 V OUTPUT 3.0 V OUTPUT 30 pF R2 351 INCLUDING JIG AND SCOPE (a) 5 pF INCLUDING JIG AND SCOPE (b) OUTPUT Equivalent to: THÉVENIN EQUIVALENT Document Number: 001-06433 Rev. *F R2 351 167 GND Rise Time: 1 V/ns ALL INPUT PULSES 90% 10% 90% 10% Fall Time: 1 V/ns 1.73 V 30 pF Page 6 of 18 CY7C1021BNV33 Switching Characteristics Over the Operating Range Parameter [4] Description -15 Min Max Unit READ CYCLE tRC Read Cycle Time 15 – ns tAA Address to Data Valid – 15 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 15 ns tDOE OE LOW to Data Valid – 7 ns tLZOE OE LOW to Low Z 0 – ns tHZOE OE HIGH to High Z [5, 6] – 7 ns [6] tLZCE CE LOW to Low Z 3 – ns tHZCE CE HIGH to High Z [5, 6] – 7 ns tPU CE LOW to Power-Up 0 – ns tPD CE HIGH to Power-Down – 15 ns tDBE Byte Enable to Data Valid – 7 ns tLZBE Byte Enable to Low Z 0 – ns tHZBE Byte Disable to High Z – 7 ns WRITE CYCLE [7, 8] tWC Write Cycle Time 15 – ns tSCE CE LOW to Write End 10 – ns tAW Address Set-Up to Write End 10 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 10 – ns tSD Data Set-Up to Write End 8 – ns tHD Data Hold from Write End 0 – ns [6] tLZWE WE HIGH to Low Z 3 – ns tHZWE WE LOW to High Z [5, 6] – 7 ns tBW Byte Enable to End of Write 9 – ns Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 1 on page 6. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and LOW to HIGH transition on any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 001-06433 Rev. *F Page 7 of 18 CY7C1021BNV33 Data Retention Characteristics Over the Operating Range (L version only) Parameter Conditions [9] Description Min Max Unit 2.0 – V – 100 A Chip Deselect to Data Retention Time 0 – ns Operation Recovery Time 15 – ns VDR VCC for Data Retention ICCDR Data Retention Current tCDR[10] tR[11] VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Data Retention Waveform Figure 2. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V VDR > 2 V tCDR 3.0 V tR CE Notes 9. No input may exceed VCC + 0.5 V. 10. Tested initially and after any design or process changes that may affect these parameters. 11. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. Document Number: 001-06433 Rev. *F Page 8 of 18 CY7C1021BNV33 Switching Waveforms Figure 3. Read Cycle No. 1 [12, 13] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% IICC CC IISB SB Notes 12. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document Number: 001-06433 Rev. *F Page 9 of 18 CY7C1021BNV33 Switching Waveforms(continued) Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 18 tHZOE Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) [15, 16, 17] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 18 tSD tHD DATAIN tLZWE Notes 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 16. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-06433 Rev. *F Page 10 of 18 CY7C1021BNV33 Switching Waveforms(continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [19, 20, 21] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Notes 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 21. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. Document Number: 001-06433 Rev. *F Page 11 of 18 CY7C1021BNV33 Truth Table CE OE WE H X L L L X BLE BHE X X X High Z High Z Power-Down Standby (ISB) H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L I/O0–I/O7 I/O8–I/O15 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document Number: 001-06433 Rev. *F Page 12 of 18 CY7C1021BNV33 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 15 Package Diagram Ordering Code Package Type CY7C1021BNV33L-15BAI 51-85096 48-ball Mini BGA (7 mm × 7 mm) CY7C1021BNV33L-15ZXI 51-85087 44-pin TSOP Type II (Pb-free) Operating Range Industrial Please contact local sales representative regarding availability of these parts. Ordering Code Definitions CY 7 C 1 02 1 BN V33 L - 15 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = BA or Z BA = 48-ball Mini BGA Z = 44-pin TSOP Type II Speed: 15 ns L = Low power Voltage range: V33 = 3 V to 3.6 V Process Technology: BN = 0.25 µm Technology Data Width: 1 = × 16-bits Density: 02 = 1-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-06433 Rev. *F Page 13 of 18 CY7C1021BNV33 Package Diagrams Figure 8. 48-ball FBGA (7 mm × 7 mm × 1.2 mm) BA48 Package Outline, 51-85096 51-85096 *J Document Number: 001-06433 Rev. *F Page 14 of 18 CY7C1021BNV33 Package Diagrams(continued) Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 001-06433 Rev. *F Page 15 of 18 CY7C1021BNV33 Acronyms Acronym Document Conventions Description Units of Measure BGA Ball Grid Array CE Chip Enable °C degree Celsius CMOS Complementary Metal Oxide Semiconductor MHz megahertz FBGA Fine-pitch Ball Grid Array µA microampere I/O Input/Output µs microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small-Outline Package mW milliwatt TTL Transistor-Transistor Logic ns nanosecond WE Write Enable ohm % percent pF picofarad V volt W watt Document Number: 001-06433 Rev. *F Symbol Unit of Measure Page 16 of 18 CY7C1021BNV33 Document History Page Document Title: CY7C1021BNV33, 64 K × 16 Static RAM Document Number: 001-06433 ECN No. Issue Date Orig. of Change ** 423847 See ECN NXR New data sheet. *A 2897061 03/22/10 AJU Updated Ordering Information (Removed obsolete parts from ordering information table). Updated Package Diagrams. Rev. Description of Change *B 3109897 12/14/2010 AJU *C 3103073 03/08/2011 PRAS *D 3403051 10/12/2011 AJU *E 3937949 03/19/2013 MEMJ Removed all references of 400-mil SOJ package in the document. Updated Switching Characteristics: Updated Note 7. Updated Switching Waveforms: Updated Figure 5, Figure 6. Added Note 15, 18 and referred the same notes in Figure 5, Figure 6. Referred Note 16, 17 in Figure 6. Referred Note 19, 20 in Figure 7. Updated Package Diagrams: spec 51-85087 – Changed revision from *D to *E. *F 4578447 01/16/2015 MEMJ Added related documentation hyperlink in page 1. Updated Figure 8 in Package Diagrams (spec 51-85096 *I to *J). Added Note 8 in Switching Characteristics. Added note reference 8 in the Switching Characteristics table. Added Note 21 in Switching Waveforms. Added note reference 21 in Figure 7. Document Number: 001-06433 Rev. *F Added Ordering Code Definitions. Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. Updated Ordering Information (Removed prune part number CY7C1021BNV33L-15VXI). Updated Package Diagrams. Page 17 of 18 CY7C1021BNV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2015. 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Document Number: 001-06433 Rev. *F Revised January 16, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18