CY7C1059DV33 8-Mbit (1M × 8) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns The CY7C1059DV33 is a high performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). ■ Low active power ❐ ICC = 110 mA at f = 100 MHz ■ Low CMOS standby power ❐ ISB2 = 20 mA ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 44-pin TSOP-II package ■ Offered in standard and high reliability (Q) grades To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input or output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE LOW and WE LOW). The CY7C1059DV33 is available in 44-pin TSOP-II package with center power and ground (revolutionary) pinout. Logic Block Diagram IO0 INPUT BUFFER IO1 IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1M x 8 ARRAY IO3 IO4 IO5 IO6 CE COLUMN DECODER WE Cypress Semiconductor Corporation Document Number: 001-00061 Rev. *I A11 A12 A13 A14 A15 A16 A17 A18 A19 OE IO7 POWER DOWN • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 9, 2014 CY7C1059DV33 Pin Configuration Figure 1. 44-Pin TSOP II Top View NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 A19 NC NC Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current Document Number: 001-00061 Rev. *I –10 10 110 20 –12 12 100 20 Unit ns mA mA Page 2 of 11 CY7C1059DV33 DC input voltage[1] ............................... –0.3 V to VCC + 0.3 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 C to +150 C Current into outputs (LOW) ......................................... 20 mA Static discharge voltage............. ...............................>2001 V (MIL-STD-883, Method 3015) Latch-up current ...................................................... >200 mA Ambient temperature with power applied ........................................... –55 C to +125 C Operating Range Supply voltage on VCC to relative GND[1] ....–0.5 V to + 4.6 V DC voltage applied to outputs in high-Z state[1] ................................... –0.3 V to VCC + 0.3 V Range Ambient Temperature VCC Industrial –40 C to +85 C 3.3 V 0.3 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min IOL = 8.0 mA VIH Input HIGH voltage voltage[1] –10 Min –12 Unit Max Min Max 2.4 – 2.4 – V – 0.4 – 0.4 V 2.0 VCC + 0.3 2.0 VCC + 0.3 V –0.3 0.8 –0.3 0.8 V VIL Input LOW IIX Input leakage current GND < VIN < VCC –1 +1 –1 +1 A IOZ Output leakage current GND < VOUT < VCC, output disabled –1 +1 –1 +1 A ICC VCC operating supply current VCC = Max., f = fMAX = 1/tRC – 110 – 100 mA ISB1 Automatic CE power-down current — TTL inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 – 35 mA ISB2 Automatic CE power-down current — CMOS inputs Max. VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 20 – 20 mA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 12 pF 12 pF Test Conditions TSOP II Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 51.43 C/W 15.8 C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Notes 1. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-00061 Rev. *I Page 3 of 11 CY7C1059DV33 AC Test Loads and Waveforms AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load shown in Figure 2 (c). Figure 2. AC Test Loads and Waveforms Z = 50 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT ALL INPUT PULSES 3.0 V OUTPUT 30 pF* 1.5 V 90% 10% 10% (b) Rise Time: 1 V/ns (a) High-Z characteristics: GND 90% Fall Time: 1 V/ns R 317 3.3 V OUTPUT R2 351 5 pF (c) Data Retention Characteristics Over the Operating Range Parameter Conditions[3] Description VDR VCC for data retention ICCDR Data retention current tCDR[2] Chip deselect to data retention time tR[4] Operation recovery time Min VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Max Unit 2.0 – V – 20 mA 0 tRC – – ns ns Figure 3. Data Retention Waveform DATA RETENTION MODE 3.0 V VCC VDR > 2 V tCDR 3.0 V tR CE Notes 3. No inputs may exceed VCC + 0.3 V. 4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 001-00061 Rev. *I Page 4 of 11 CY7C1059DV33 AC Switching Characteristics Over the Operating Range[5] Parameter Description –10 Min –12 Max Min Max Unit Read Cycle tpower[6] VCC(typical) to the first access 100 – 100 – s tRC Read cycle time 10 – 12 – ns tAA Address to data valid – 10 – 12 ns tOHA Data hold from address change 2.5 – 2.5 – ns tACE CE LOW to data valid – 10 – 12 ns tDOE OE LOW to data valid – 5 – 6 ns tLZOE OE LOW to low-Z tHZOE 0 – 0 – ns high-Z[7, 8] – 5 – 6 ns low-Z[8] OE HIGH to tLZCE CE LOW to 3 – 3 – ns tHZCE CE HIGH to high-Z[7, 8] – 5 – 6 ns tPU CE LOW to power-up 0 – 0 – ns CE HIGH to power-down – 10 – 12 ns tPD Write Cycle [9, 10] tWC Write cycle time 10 – 12 – ns tSCE CE LOW to write end 7 – 8 – ns tAW Address setup to write end 7 – 8 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 8 – ns tSD Data setup to write end 5 – 6 – ns tHD Data hold from write end 0 – 0 – ns tLZWE WE HIGH to low-Z[8] 3 – 3 – ns tHZWE WE LOW to high-Z[7, 8] – 5 – 6 ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 6. tPOWER is the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 4. Transition is measured when the outputs enter a high impedance state. 8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data setup and hold timing must refer to the leading edge of the signal that terminates the Write. 10. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-00061 Rev. *I Page 5 of 11 CY7C1059DV33 Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled)[11, 12] tRC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATA OUT VALID Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA I/O tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA OUT VALID tPD tPU 50% 50% ICC ISB Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for Read cycle. 13. Address valid before or coincident with CE transition LOW. Document Number: 001-00061 Rev. *I Page 6 of 11 CY7C1059DV33 Switching Waveforms(continued) Figure 6. Write Cycle No. 1 (WE Controlled, OE High During Write)[14, 15] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATA IN VALID NOTE 16 tHZOE Figure 7. Write Cycle No. 2 (WE Controlled, OE Low)[15, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 16 tHD DATA IN VALID tHZWE tLZWE Notes 14. Data I/O is high-impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals must not be applied. 17. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-00061 Rev. *I Page 7 of 11 CY7C1059DV33 Truth Table CE H OE X WE X I/O0–I/O7 High-Z Mode Power-down Power Standby (ISB) L L H Data out Read Active (ICC) L X L Data in Write Active (ICC) L H H High-Z Selected, outputs disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range Grade 10 CY7C1059DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free) Industrial Standard 12 CY7C1059DV33-12ZSXQ 51-85087 44-pin TSOP II (Pb-free) Industrial High reliability (< 100 ppm) Ordering Code Definitions CY 7 C 1 05 9 D V33 - XX ZSX X Temperature Range: X = I or Q I = Industrial; Q = High reliability (< 100 ppm) Package Type: ZSX = 44-pin TSOP II (Pb-free) Speed: XX = 10 ns or 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 9 = Data width × 8-bits 05 = 8-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Contact your local Cypress sales representative for availability of these parts. Document Number: 001-00061 Rev. *I Page 8 of 11 CY7C1059DV33 Package Diagram Figure 8. 44-Pin TSOP II (51-85087) 51-85087 *E Acronyms Document Conventions Table 1. Acronyms Used in this Document Units of Measure Acronym Description Table 2. Units of Measure CMOS complementary metal–oxide–semiconductor SRAM static random-access memory C degree Celsius TSOP thin small-outline package MHz megahertz TTL transistor–transistor logic mA milliampere ns nanosecond ohm pF picofarad Document Number: 001-00061 Rev. *I Symbol Unit of Measure Page 9 of 11 CY7C1059DV33 Document History Page Document Title: CY7C1059DV33, 8-Mbit (1M × 8) Static RAM Document Number: 001-00061 Revision ECN Orig. of Change Submission Date Description of Change ** 342195 PCI See ECN New data sheet *A 380574 SYT See ECN Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10 and 12 ns speed bins respectively ICC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10 and 12 ns speed bins respectively Changed the Capacitance values from 8 pF to 10 pF on Page # 3 *B 485796 NXR See ECN Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed -8 and -12 Speed bins from product offering, Removed Commercial Operating Range option, Modified Maximum Ratings for DC input voltage from -0.5 V to -0.3 V and VCC + 0.5 V to VCC + 0.3 V Updated footnote #7 on High-Z parameter measurement Added footnote #11 Changed the Description of IIX from Input Load Current to Input Leakage Current. Updated the Ordering Information table and Replaced Package Name column with Package Diagram. *C 1513285 VKN/AESA See ECN Converted from preliminary to final Added 12 ns speed bin Changed CIN and COUT specs from 16 pF to 12 pF Changed tOHA spec from 3 ns to 2.5 ns Updated Ordering information table *D 2594352 NXR/PYRS 10/21/08 Added Q-Grade part *E 2764423 AJU 09/16/2009 Corrected typo in the ordering information table *F 2902563 AJU 03/31/2010 Removed inactive part from Ordering Information table. Updated package diagram. *G 3109147 AJU 12/13/2010 Added Ordering Code Definitions. *H 3369075 TAVA 09/12/2011 Changed Features section: “ICC = 110 mA at 10 ns” to “110 mA at f = 100 MHz”. Removed reference to “AN1064, SRAM System Guidelines” on page 1. Removed reference to 36-ball FBGA from Functional Description section. Updated figures under Switching Waveforms section. Updated package diagram revision to *D. Added acronyms and units of measure. *I 4530384 MEMJ 10/09/2014 Updated Switching Waveforms: Added Note 17 and referred the same note in Figure 7. Updated Package Diagram: spec 51-85087 – Changed revision from *D to *E. Updated in new template. Completing Sunset Review. Document Number: 001-00061 Rev. *I Page 10 of 11 CY7C1059DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2005-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-00061 Rev. *I Revised October 9, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 11 of 11