CY7C10612DV33 16-Mbit (1 M × 16) Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns The CY7C10612DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 100 MHz ■ Low CMOS standby power ❐ ISB2 = 25 mA ■ Operating voltages of 3.3 ± 0.3 V To write to the device, take Chip Enables (CE) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). ■ 2.0 V data retention ■ Automatic Power-down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 54-pin TSOP II package To read from the device, take Chip Enables (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 10 for a complete description of Read and Write modes. The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The CY7C10612DV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout. For a complete list of related documentation, click here. Logic Block Diagram 1M x 16 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O0 – I/O7 I/O8 – I/O15 A10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A18 A19 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation Document Number: 001-49315 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 19, 2014 CY7C10612DV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Document Number: 001-49315 Rev. *D Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Page 2 of 14 CY7C10612DV33 Selection Guide Description -10 Unit Maximum Access Time 10 ns Maximum Operating Current 175 mA Maximum CMOS Standby Current 25 mA Pin Configuration Figure 1. 54-pin TSOP II (Top View) [1] I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE VCC WE NC A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 54 53 52 51 50 49 48 47 46 Note 1. NC pins are not connected on the die. Document Number: 001-49315 Rev. *D Page 3 of 14 CY7C10612DV33 DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) ..... ............................> 2001 V Latch Up Current ................................................... > 200 mA Operating Range Supply Voltage on VCC Relative to GND [2] ...............................–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State [2] ................................ –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Industrial –40 C to +85 C 3.3 V 0.3 V DC Electrical Characteristics Over the Operating Range -10 Parameter Description Test Conditions VOH Output HIGH voltage Min VCC, IOH = –4.0 mA VOL Output LOW voltage Min VCC, IOL = 8.0 mA VIH Input HIGH voltage [2] Unit Min Max 2.4 – V – 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V VIL Input LOW voltage IIX Input leakage current GND VIN VCC –1 +1 A IOZ Output leakage current GND VOUT VCC, Output disabled –1 +1 A ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA, CMOS levels – 175 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE VIH, VIN VIH or VIN VIL, f = fMAX – 30 mA ISB2 Automatic CE power-down current – CMOS Inputs Max VCC, CE VCC – 0.3 V, VIN VCC – 0.3 V, or VIN 0.3 V, f = 0 – 25 mA Capacitance Parameter [3] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V 54-pin TSOP II Unit 6 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 54-pin TSOP II Unit 24.18 C/W 5.40 C/W Note 2. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-49315 Rev. *D Page 4 of 14 CY7C10612DV33 AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] HIGH Z CHARACTERISTICS: R1 317 3.3 V 50 VTH = 1.5 V OUTPUT Z0 = 50 OUTPUT 30 pF* INCLUDING JIG AND SCOPE (b) (a) * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R2 351 5 pF* ALL INPUT PULSES 3.0 V 90% 90% 10% GND RISE TIME: > 1 V/ns 10% (c) FALL TIME: > 1 V/ns Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for data retention ICCDR Data retention current tCDR [6] Chip deselect to data retention time tR [7] VCC = 2 V, CE VCC – 0.2 V, VIN VCC – 0.2 V or VIN 0.2 V Operation recovery time Min Typ [5] Max Unit 2 – – V – – 25 mA 0 – – ns tRC – – ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V tCDR VDR > 2 V 3.0 V tR CE Notes 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full device operation requires linear VCC ramp from VDR to VCC(min.) 50 s or stable at VCC(min.) 50 s. Document Number: 001-49315 Rev. *D Page 5 of 14 CY7C10612DV33 AC Switching Characteristics Over the Operating Range Parameter [4] Description -10 Min Max – Unit Read Cycle tpower VCC(typical) to the first access [5] 100 s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 5 ns tLZOE OE LOW to low Z 1 – ns – 5 ns 3 – ns – 5 ns 0 – ns – 10 ns – 5 ns tHZOE tLZCE OE HIGH to high Z CE LOW to low Z [6] [6] [6] tHZCE CE HIGH to high Z tPU CE LOW to power-up [7] [7] tPD CE HIGH to power-down tDBE Byte enable to data valid tLZBE Byte enable to low Z 1 – ns tHZBE Byte disable to high Z – 5 ns 10 – ns Write Cycle [8, 9] tWC Write cycle time tSCE CE LOW to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width tSD Data setup to write end tHD Data hold from write end WE HIGH to low Z [6] tHZWE WE LOW to high Z [6] tBW Byte enable to end of write tLZWE 7 – ns 5.5 – ns 0 – ns 3 – ns – 5 ns 7 – ns Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part a) of Figure 2 on page 5, unless specified otherwise. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. tHZOE, tHZCE, tHZWE, tHZBE , tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 2 on page 5. Transition is measured 200 mV from steady state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal write time of the memory is defined by the overlap of WE, CE = VIL. Chip enable must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-49315 Rev. *D Page 6 of 14 CY7C10612DV33 Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [10, 11] tRC RC ADDRESS tAA tOHA DATA I/O PREVIOUS DATA VALID DATA OUT VALID Figure 5. Read Cycle No. 2 (OE Controlled) [11, 12] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA I/O HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA OUT VALID tPD tPU 50% IICC CC 50% IISB SB Notes 10. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 11. WE is HIGH for read cycle. 12. Address valid before or similar to CE transition LOW. Document Number: 001-49315 Rev. *D Page 7 of 14 CY7C10612DV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [13, 14] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IN VALID DATA I/O Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [13, 14] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE DATA I/O tSD tHD DATA IN VALID tLZWE Notes 13. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-49315 Rev. *D Page 8 of 14 CY7C10612DV33 Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (BLE or BHE Controlled) [15] tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD DATA I/O tHD DATA IN VALID Note 15. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. Document Number: 001-49315 Rev. *D Page 9 of 14 CY7C10612DV33 Truth Table I/O0–I/O7 BHE X High Z CE H OE X WE X BLE X L L H L L L L H L L L H L X L L X L L I/O8–I/O15 Mode Power High Z Power-down Standby (ISB) Data Out Data Out Read all bits Active (ICC) H Data Out High Z Read lower bits only Active (ICC) H L High Z Data Out Read upper bits only Active (ICC) L L Data In Data In Write all bits Active (ICC) L L H Data In High Z Write lower bits only Active (ICC) X L H L High Z Data In Write upper bits only Active (ICC) H H X X High Z High Z Selected, outputs disabled Active (ICC) Ordering Information Speed (ns) 10 Package Diagram Ordering Code CY7C10612DV33-10ZSXI Package Type 51-85160 54-pin TSOP II (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 06 1 2 D V33 - 10 ZS X I Temperature Grade: I = Industrial Pb-free Package Type: ZS = 54-pin TSOP II Speed Grade: 10 ns Voltage range: 3 V to 3.6 V Process Technology: C9, 90 nm Single chip enable Bus width = × 16 Density = 16-Mbit Fast asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-49315 Rev. *D Page 10 of 14 CY7C10612DV33 Package Diagrams Figure 9. 54-pin TSOP Type II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160 51-85160 *E Document Number: 001-49315 Rev. *D Page 11 of 14 CY7C10612DV33 Acronyms Document Conventions Table 1. Acronyms Used in this Document Units of Measure Acronym Description Table 2. Units of Measure BHE byte high enable BLE byte low enable °C degree Celsius CE chip enable MHz megahertz CMOS complementary metal oxide semiconductor µA microampere I/O input/output s microsecond OE output enable mA milliampere SRAM static random access memory mm millimeter TSOP thin small outline package mV millivolt TTL transistor-transistor logic ns nanosecond WE write enable ohm % percent pF picofarad V volt W watt Document Number: 001-49315 Rev. *D Symbol Unit of Measure Page 12 of 14 CY7C10612DV33 Document History Page Document Title: CY7C10612DV33, 16-Mbit (1 M × 16) Static RAM Document Number: 001-49315 Rev. ECN No. Orig. of Change Submission Date ** 2589743 VKN / PYRS 10/15/08 New datasheet *A 2718906 VKN 06/15/09 Post to external web *B 3128718 PRAS 01/05/11 Template updates. Style changes. IO changed to I/O through out the document. Under Data Retention Characteristics on Page 6, “Typ” is associated with a new footnote # 10. Included ordering code definitions, Acronyms and units of measure tables. Updated package diagram from ** to *A. *C 3412972 TAVA 10/18/2011 Updated Features. Updated DC Electrical Characteristics. Updated Switching Waveforms. Updated Package Diagrams. Updated in new template. *D 4574311 TAVA 11/19/2014 Added related documentation hyperlink in page 1. Updated Figure 9 in Package Diagrams (spec 51-85160 *C to *E). Document Number: 001-49315 Rev. *D Description of Change Page 13 of 14 CY7C10612DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-49315 Rev. *D Revised November 19, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 14 of 14