CY7C1061DV18 16-Mbit (1M × 16) Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description ■ High Speed ❐ tAA = 15 ns The CY7C1061DV18 is a high performance CMOS Static RAM (SRAM) organized as 1,048,576 words by 16 bits. ■ Low Active Power ❐ ICC = 150 mA at 67 MHz ■ Low complementary metal oxide semiconductor (CMOS) Standby Power ❐ ISB2 = 25 mA ■ Operating voltages of 1.7 V to 2.2 V To write to the device, enable the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). ■ 1.5 V data retention ■ Automatic power-down when deselected ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ Easy memory expansion with CE1 and CE2 features ■ Available in Pb-free 54-pin thin small outline package (TSOP) Type II package To read from the device, enable the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1061DV18 is available in a 54-pin TSOP II pinout. For a complete list of related documentation, click here. Logic Block Diagram 1M x 16 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O0–I/O7 I/O8–I/O15 A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 COLUMN DECODER BHE WE OE BLE Cypress Semiconductor Corporation Document Number: 001-08350 Rev. *K • 198 Champion Court • CE2 CE1 San Jose, CA 95134-1709 • 408-943-2600 Revised October 26, 2015 CY7C1061DV18 Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 AC Switching Characteristics ......................................... 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 001-08350 Rev. *K Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY7C1061DV18 Selection Guide -15 Unit Maximum access time Description 15 ns Maximum operating current 150 mA Maximum CMOS standby current 25 mA Pin Configurations Figure 1. 54-pin TSOP II pinout (Top View) I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 Document Number: 001-08350 Rev. *K 1 2 3 54 53 4 52 51 5 6 50 49 7 8 9 10 11 12 48 47 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 Page 3 of 17 CY7C1061DV18 DC input voltage [1] ....................................–0.2 V to +2.45 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied ................................... –55 C to +125 C Supply voltage on VCC to relative GND [1] .........................–0.2 V to +2.45 V DC voltage applied to outputs in High Z state [1] .......................................–0.2 V to +2.45 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) ........................... >2001 V Latch-up current ..................................................... >200 mA Operating Range Range Industrial Ambient Temperature VCC –40 C to +85 C 1.7 V to 2.2 V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH voltage Min VCC, IOH = –0.1 mA VOL Output LOW voltage Min VCC, IOL = 0.1 mA VIH Input HIGH voltage voltage[1] -15 Unit Min Max 1.4 – V – 0.2 V 1.4 VCC + 0.2 V VIL Input LOW –0.2 0.4 V IIX Input leakage current GND < VIN < VCC –1 +1 A IOZ Output leakage current GND < VOUT < VCC, output disabled –1 +1 A ICC VCC operating supply current Max VCC, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels – 150 mA ISB1 Automatic CE power-down current – TTL inputs CE1 > VIH, CE2 < VIL, Max VCC, VIN > VIH or VIN < VIL, f = fMAX – 30 mA ISB2 Automatic CE power-down current – CMOS inputs CE1 > VCC – 0.2 V, CE2 < 0.2 V, Max VCC, VIN > VCC – 0.2 V, or VIN < 0.2 V, f = 0 – 25 mA Note 1. VIL (min) = –2.0 V for pulse durations of less than 20 ns. Document Number: 001-08350 Rev. *K Page 4 of 17 CY7C1061DV18 Capacitance Parameter [2] Description CIN Input capacitance COUT I/O capacitance Test Conditions 54-pin TSOP II Unit TA = 25 C, f = 1 MHz, VCC = 1.8 V. 6 pF 8 pF Thermal Resistance Parameter [2] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 54-pin TSOP II Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 76.15 C/W 14.15 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [3] 50 Z0 = 50 OUTPUT 30 pF* * Capacitive Load consists of all components of the test environment. (a) 1.8V GND Rise time > 1 V/ns R1 1667 1.8V VTH = VDD/2 OUTPUT 5 pF* ALL INPUT PULSES 90% 90% R2 1538 INCLUDING JIG AND SCOPE (b) 10% 10% (c) Fall time: > 1 V/ns Notes 2. Tested initially and after any design or process changes that may affect these parameters. 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (1.5 V). 150s (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5 V) voltage. Document Number: 001-08350 Rev. *K Page 5 of 17 CY7C1061DV18 Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for data retention ICCDR Data retention current Conditions Min Typ [4] Max Unit 1.5 – – V 25 mA VCC = 1.5 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V, – – 0 – – ns tRC – – ns VIN > VCC – 0.2 V, or VIN < 0.2 V tCDR[5] Chip deselect to data retention time tR[6] Operation recovery time Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE 1.65V VCC tCDR VDR > 1.5 V 1.65 V tR CE Notes 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 5. Tested initially and after any design or process changes that may affect these parameters. 6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document Number: 001-08350 Rev. *K Page 6 of 17 CY7C1061DV18 AC Switching Characteristics Over the Operating Range Parameter [7] Description -15 Min Max Unit Read Cycle tpower VCC(typical) to the first access [8] 150 – s tRC Read cycle time 15 – ns tAA Address to data valid – 15 ns tOHA Data hold from address change 3 – ns tACE CE1 LOW/CE2 HIGH to data valid – 15 ns tDOE OE LOW to data valid – 7 ns tLZOE OE LOW to Low Z 1 – ns – 7 ns 3 – ns – 7 ns 0 – ns [9] tHZOE OE HIGH to High Z tLZCE CE1 LOW/CE2 HIGH to Low Z [9] tHZCE [9] tPU CE1 HIGH/CE2 LOW to High Z CE1 LOW/CE2 HIGH to Power-up [10] [10] tPD CE1 HIGH/CE2 LOW to Power-down – 15 ns tDBE Byte Enable to data valid – 7 ns tLZBE Byte Enable to Low Z 1 – ns Byte Disable to High Z – 7 ns tHZBE Write Cycle [11, 12] tWC Write cycle time 15 – ns tSCE CE1 LOW/CE2 HIGH to write end 10 – ns tAW Address setup to write end 10 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 10 – ns tSD Data setup to write end 7 – ns tHD Data hold from write end 0 – ns tLZWE WE HIGH to Low Z[13] 3 – ns tHZWE WE LOW to High Z [13] – 7 ns tBW Byte enable to end of write 10 – ns Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 0.9 V, input pulse levels of 0 to 1.8 V. Test conditions for the Read cycle use output loading shown in part a) of the Figure 2, unless specified otherwise. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 9. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 2. Transition is measured 200 mV from steady-state voltage. 10. These parameters are guaranteed by design and are not tested. 11. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 13. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 2. Transition is measured 200 mV from steady-state voltage. Document Number: 001-08350 Rev. *K Page 7 of 17 CY7C1061DV18 Switching Waveforms Figure 4. Read Cycle No. 1 [14, 15] tRC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATA OUT VALID Figure 5. Read Cycle No. 2 (OE Controlled) [16, 17] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA I/O HIGH IMPEDANCE tHZBE DATA OUT VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% 50% IICC CC ISB Notes 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 15. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. CE2 = VIH. 16. WE is HIGH for Read cycle. 17. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document Number: 001-08350 Rev. *K Page 8 of 17 CY7C1061DV18 Switching Waveforms(continued) Figure 6. Write Cycle No. 1 (CE Controlled) [18, 19, 20] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IN VALID DATA I/O Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD DATA I/O tHD DATA IN VALID Notes 18. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 19. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 20. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-08350 Rev. *K Page 9 of 17 CY7C1061DV18 Switching Waveforms(continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE Low) [21, 22, 23] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE DATA I/O tSD tHD DATA IN VALID tLZWE Notes 21. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 22. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 23. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW. Document Number: 001-08350 Rev. *K Page 10 of 17 CY7C1061DV18 Truth Table CE1 CE2 OE WE BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power H X X X X X High Z High Z Power-down Standby (ISB) X L X X X X High Z High Z Power-down Standby (ISB) L H L H L L Data out Data out Read all bits Active (ICC) L H L H L H Data out High Z Read lower bits only Active (ICC) L H L H H L High Z Data out Read upper bits only Active (ICC) L H X L L L Data in Data in Write all bits Active (ICC) L H X L L H Data in High Z Write lower bits only Active (ICC) L H X L H L High Z Data in Write upper bits only Active (ICC) L H H H X X High Z High Z Selected, outputs disabled Active (ICC) Document Number: 001-08350 Rev. *K Page 11 of 17 CY7C1061DV18 Ordering Information Speed (ns) Ordering Code 15 CY7C1061DV18-15ZSXI Package Diagram Package Type 51-85160 54-pin TSOP II (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 06 1 D V18 - 15 ZS X I Temperature Grade: I = Industrial Pb-free Package Type: ZS = 54-pin TSOP II Speed Grade: 15 ns Voltage range: V18 = 1.7 V to 2.2 V Process Technology: D = C9, 90 nm Technology Data Width: 1 = 16-bits Density: 06 = 16-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-08350 Rev. *K Page 12 of 17 CY7C1061DV18 Package Diagram Figure 9. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Package Outline, 51-85160 51-85160 *E Document Number: 001-08350 Rev. *K Page 13 of 17 CY7C1061DV18 Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor I/O Input/Output °C degree Celsius SRAM Static Random Access Memory MHz megahertz TSOP Thin Small Outline Package A microampere Transistor-Transistor Logic mA milliampere ns nanosecond ohm pF picofarad V volt W watt TTL Document Number: 001-08350 Rev. *K Symbol Unit of Measure Page 14 of 17 CY7C1061DV18 Document History Page Document Title: CY7C1061DV18, 16-Mbit (1M × 16) Static RAM Document Number: 001-08350 Rev. ECN No. Submission Date Orig. of Change ** 469420 See ECN NXR *A 2761557 09/09/2009 VKN Rearranged sections for better clarity. *B 2800121 11/06/2009 VKN Changed status from Final to Preliminary. Updated Selection Guide: Changed value of “Maximum operating current” from 100 mA to 150 mA. Updated Thermal Resistance: Replaced TBD with values for both JA and JC parameters. Updated Data Retention Characteristics: Changed minimum value of VDR parameter from 1.2 V to 1.5 V. Updated AC Switching Characteristics: Changed minimum value of tLZOE parameter from 0 ns to 1 ns. Changed minimum value of tLZBE parameter from 0 ns to 1 ns. Changed minimum value of tLZCE parameter from 0 ns to 3 ns. Updated Package Diagram: Replaced “6 × 8 × 1 mm FBGA package” with “8 × 9.5 × 1 mm FBGA package” (Removed spec 51-85150 *D and added spec 51-85178 *A). *C 2915361 04/16/2010 VKN Changed status from Preliminary to Final. Removed 48-ball FBGA package related information in all instances across the document. Updated links in Sales, Solutions, and Legal Information *D 2923463 04/27/2010 RAME *E 3109102 12/13/2010 PRAS Added Ordering Code Definitions. *F 3147322 01/19/2011 PRAS Added Acronyms and Units of Measure. Updated to new template. *G 3387026 09/29/2011 TAVA Minor technical edits. Updated Package Diagram. *H 4217075 12/11/2013 MEMJ Updated Features: Added 48-ball VFBGA package related information. Updated Functional Description: Added 48-ball VFBGA package related information. Updated Pin Configurations: Added 48-ball VFBGA package related information. Updated Ordering Information (Updated part numbers). Updated Package Diagram: spec 51-85160 – Changed revision from *C to *D. Added 48-ball VFBGA package related information. Updated to new template. *I 4548836 10/22/2014 MEMJ Updated Package Diagram: spec 51-85160 – Changed revision from *D to *E. Completing Sunset Review. *J 4573121 11/18/2014 MEMJ Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Document Number: 001-08350 Rev. *K Description of Change New data sheet. Post to external web. Page 15 of 17 CY7C1061DV18 Document History Page(continued) Document Title: CY7C1061DV18, 16-Mbit (1M × 16) Static RAM Document Number: 001-08350 Rev. ECN No. Submission Date Orig. of Change Description of Change *K 4987892 10/26/2015 NILE Removed 48-ball VFBGA package related information in all instances across the document. Updated Thermal Resistance: Changed value of JA parameter corresponding to TSOP II package from 24.18 C/W to 76.15 C/W. Changed value of JC parameter corresponding to TSOP II package from 5.40 C/W to 14.15 C/W. Updated Ordering Information: Updated part numbers. Updated Package Diagram: Removed spec 51-85178 *C. Updated to new template. Completing Sunset Review. Document Number: 001-08350 Rev. *K Page 16 of 17 CY7C1061DV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2015. The information contained herein is subject to change without notice. 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Document Number: 001-08350 Rev. *K Revised October 26, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 17