CY7C199N 32 K × 8 Static RAM 32 K × 8 Static RAM Features Functional Description ■ High speed ❐ 15 ns The CY7C199N is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199N is in the standard 300-mil-wide DIP, SOJ, and LCC packages. ■ Fast tDOE ■ CMOS for optimum speed/power ■ Low active power ❐ 550 mW (max, 15 ns “L” version) ■ Low standby power ❐ 0.275 mW (max, “L” version) ■ 2 V data retention (“L” version only) ■ Easy memory expansion with CE and OE features ■ TTL-compatible inputs and outputs ■ Automatic power-down when deselected An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity. For a complete list of related documentation, click here. Logic Block Diagram I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1024 x 32 x 8 ARRAY I/O3 I/O4 I/O5 CE WE I/O6 POWER DOWN COLUMN DECODER I/O7 Cypress Semiconductor Corporation Document Number: 001-06493 Rev. *E • A 14 A 12 A 13 A 11 A 10 OE 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2014 CY7C199N Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Typical DC and AC Characteristics ................................ 9 Truth Table ...................................................................... 10 Document Number: 001-06493 Rev. *E Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC® Solutions ...................................................... 14 Cypress Developer Community ................................. 14 Technical Support ..................................................... 14 Page 2 of 14 CY7C199N Pin Configuration Figure 1. 28-pin TSOP 1 pinout OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 14 A 13 A 12 Selection Guide Description Maximum Access Time -15 Unit 15 ns Maximum Operating Current L 100 mA Maximum CMOS Standby Current L 0.05 mA Document Number: 001-06493 Rev. *E Page 3 of 14 CY7C199N DC Input Voltage [1] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Output Current into Outputs (LOW) ............................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Storage Temperature ............................... –65 °C to +150 °C Latch-up Current ................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Operating Range Supply Voltage to Ground Potential (Pin 28 to Pin 14) .........................................–0.5 V to +7.0 V Range DC Voltage Applied to Outputs in High Z State [1] ................................ –0.5 V to VCC + 0.5 V Ambient Temperature [2] VCC 0 °C to +70 °C 5 V 10% Commercial Electrical Characteristics Over the Operating Range Parameter Description -15 Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage Unit Min Max 2.4 – V – 0.4 V 2.2 VCC + 0.3 V VIL Input LOW Voltage –0.5 0.8 V IIX Input Load Current GND < VI < VCC –5 +5 A IOZ Output Leakage Current GND < VO < VCC, Output Disabled –5 +5 A ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC L – 100 mA ISB1 Automatic CE Power-down Current – TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX L – 5 mA ISB2 Automatic CE Power-down Current – CMOS Inputs L Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 0.05 mA Notes 1. VIL (min) = –2.0 V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. Document Number: 001-06493 Rev. *E Page 4 of 14 CY7C199N Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max Unit 8 pF 8 pF AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] R1 481 5V R1 481 5V OUTPUT ALL INPUT PULSES OUTPUT R2 255 30 pF INCLUDING JIG AND SCOPE Equivalent to: 3.0 V R2 255 5 pF INCLUDING JIG AND SCOPE (a) GND 10% 90% 10% 90% tr tr (b) THÉVENIN EQUIVALENT 167 OUTPUT 1.73 V Data Retention Characteristics Over the Operating Range (L-version only) Parameter VDR VCC for Data Retention ICCDR tCDR tR Conditions [5] Description [3] [4] Data Retention Current L Chip Deselect to Data Retention Time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Operation Recovery Time Min Max Unit 2.0 – V – 10 A 0 – ns 200 – s Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE 3.0 V VCC VDR > 2 V tCDR 3.0 V tR CE Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. tR< 3 ns for -15 speed. 5. No input may exceed VCC + 0.5 V. Document Number: 001-06493 Rev. *E Page 5 of 14 CY7C199N Switching Characteristics Over the Operating Range Parameter [6] Description 7C199-15 Min Max Unit Read Cycle tRC Read Cycle Time 15 – ns tAA Address to Data Valid – 15 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 15 ns tDOE OE LOW to Data Valid – 7 ns 0 – ns – 7 ns tLZOE tHZOE OE LOW to Low Z [7] OE HIGH to High Z [7, 8] [7] tLZCE CE LOW to Low Z 3 – ns tHZCE CE HIGH to High Z [7, 8] – 7 ns tPU CE LOW to Power-up 0 – ns CE HIGH to Power-down – 15 ns tPD Write Cycle [9, 10] tWC Write Cycle Time 15 – ns tSCE CE LOW to Write End 10 – ns tAW Address Set-up to Write End 10 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-up to Write Start 0 – ns tPWE WE Pulse Width 9 – ns tSD Data Set-up to Write End 9 – ns tHD Data Hold from Write End 0 – ns tHZWE WE LOW to High Z [8] – 7 ns tLZWE [7] 3 – ns WE HIGH to Low Z Notes 6. Test conditions assume signal transition time of 3 ns or less for -15 speed, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of Figure 2 on page 5. Transition is measured 500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-06493 Rev. *E Page 6 of 14 CY7C199N Switching Waveforms Figure 4. Read Cycle No. 1 [11, 12] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 [12, 13] tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Figure 6. Write Cycle No. 1 (WE Controlled) [14, 15, 16] tWC ADDRESS CE tAW WE tSA tHA tPWE OE tSD tHD DATAIN VALID DATA I/O tHZOE Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document Number: 001-06493 Rev. *E Page 7 of 14 CY7C199N Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (CE Controlled) [17, 18, 19] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATA IN VALID Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [19, 20] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O Note 21 tHD DATAIN VALID tHZWE tLZWE Notes 17. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of Figure 2 on page 5. Transition is measured 500 mV from steady-state voltage. 18. Data I/O is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 20. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. 21. During this period, the I/Os are in the output state. Do not apply input signals. Document Number: 001-06493 Rev. *E Page 8 of 14 CY7C199N NORMALIZED ICC, ISB 1.2 ICC 0.8 0.6 VIN = 5.0 V TA = 25 °C 0.4 0.2 0.0 4.0 1.0 0.8 0.6 VCC = 5.0 V VIN = 5.0 V 0.4 0.2 ISB 4.5 5.0 5.5 ISB 0.0 –55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.4 1.6 1.3 1.4 NORMALIZED tAA NORMALIZED tAA NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.2 TA = 25 °C 1.0 1.2 1.0 VCC = 5.0 V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 0.6 –55 6.0 TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 100 80 VCC = 5.0 V 60 TA = 25 °C 40 20 0 0.0 25 2.5 25.0 DELTA t AA (ns) 30.0 2.0 1.5 1.0 0.5 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) 140 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 VCC = 5.0 V TA = 25 °C 40 20 0 0.0 125 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 3.0 0.0 0.0 120 AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) NORMALIZED IPO 125 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) 1.1 25 OUTPUT SINK CURRENT (mA) 1.0 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4 ICC 1.2 NORMALIZED ICC vs. CYCLE TIME 1.25 20.0 15.0 VCC = 4.5 V TA = 25 °C 10.0 NORMALIZED ICC NORMALIZED ICC, ISB 1.4 NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics 1.00 VCC = 5.0 V TA = 25 °C VIN = 0.5 V 0.75 5.0 1.0 2.0 3.0 4.0 5.0 SUPPLY VOLTAGE (V) Document Number: 001-06493 Rev. *E 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Page 9 of 14 CY7C199N Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Selected, Output disabled Active (ICC) Ordering Information Speed (ns) 15 Package Diagram Ordering Code CY7C199NL-15ZXC Package Type 51-85071 28-pin TSOP 1 (Pb-free) Operating Range Commercial Contact your Local Cypress sales representative for availability of these parts Ordering Code Definitions CY 7 C 1 99 NL - 15 Z X C Temperature Range: C = Commercial Pb-free Package Type: Z = 28-pin TSOP 1 Speed: 15 ns NL = Low Power 99 = 256 Kbit density with data width × 8 bits Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-06493 Rev. *E Page 10 of 14 CY7C199N Package Diagrams Figure 9. 28-pin TSOP 1 (8 × 13.4 × 1.2 mm) Package Outline, 51-85071 51-85071 *J Document Number: 001-06493 Rev. *E Page 11 of 14 CY7C199N Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal-Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SOJ Small Outline J-lead µs microsecond SRAM Static Random Access Memory mA milliampere TTL Transistor-Transistor Logic mW milliwatt TSOP Thin Small Outline Package WE Write Enable Document Number: 001-06493 Rev. *E Symbol Unit of Measure ns nanosecond ohm % percent pF picofarad V volt W watt Page 12 of 14 CY7C199N Document History Page Document Title: CY7C199N, 32 K × 8 Static RAM Document Number: 001-06493 Rev. ECN No. Issue Date Orig. of Change ** 423877 See ECN NXR New data sheet. *A 2892510 03/18/2010 VKN Removed speed bins from the data sheet: 12 ns, 20 ns, 25 ns, 35 ns, and 55 ns. Removed Industrial and Military product information Removed 28-pin (300-Mil) PDIP package Updated Ordering Information table Updated Package Diagram *B 3109199 12/13/2010 AJU Added Ordering Code Definitions. *C 3244591 04/29/2011 PRAS *D 4379476 05/14/2014 VINI Updated Switching Waveforms: Added Note 21 and referred the same note in DATA I/O in Figure 8. Updated Package Diagrams: spec 51-85071 – Changed revision from *I to *J. Updated in new template. Completing Sunset Review. *E 4573121 11/18/2014 VINI Added related documentation hyperlink in page 1. Document Number: 001-06493 Rev. *E Description of Change Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. 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