CY7C1071DV33 32-Mbit (2 M × 16) Static RAM 32-Mbit (2 M × 16) Static RAM Features Functional Description ■ High speed ❐ tAA = 12 ns ■ Low active power ❐ ICC = 250 mA at 83.3 MHz ■ Low Complementary Metal Oxide Semiconductor (CMOS) standby power ❐ ISB2 = 50 mA ■ Operating voltages of 3.3 ± 0.3 V ■ 2.0 V data retention The CY7C1071DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 16 bits. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Available in Pb-free 48-ball FBGA package ■ Deselected (CE HIGH) ■ Outputs are disabled (OE HIGH) ■ Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) ■ The write operation is active (CE LOW and WE LOW) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. For a complete list of related documentation, click here. Logic Block Diagram 2M × 16 RAM ARRAY SENSE AMPS A(10:0) ROW DECODER DATA IN DRIVERS IO0–IO7 IO8–IO15 COLUMN DECODER BHE WE CE OE A(20:11) BLE Cypress Semiconductor Corporation Document Number: 001-12063 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2014 CY7C1071DV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Document Number: 001-12063 Rev. *J Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Page 2 of 14 CY7C1071DV33 Selection Guide -12 Unit Maximum Access Time Description 12 ns Maximum Operating Current 250 mA Maximum CMOS Standby Current 50 mA Pin Configuration Figure 1. 48-ball FBGA [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A IO8 BHE A3 A4 CE IO0 B IO9 IO10 A5 A6 IO1 IO2 C VSS IO11 A17 A7 IO3 VCC D VCC IO12 NC A16 IO4 VSS E IO14 IO13 A14 A15 IO5 IO6 F IO15 A20 A12 A13 WE IO7 G A18 A8 A9 A10 A11 A19 H Note 1. NC pins are not connected to the die. Document Number: 001-12063 Rev. *J Page 3 of 14 CY7C1071DV33 DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ......................................... > 2001 V Storage Temperature ............................... –65 C to +150 C (MIL-STD-883, Method 3015) Ambient Temperature with Power Applied ......................................... –55 C to +125 C Latch up Current .................................................... > 200 mA Supply Voltage on VCC Relative to GND [2] ...............................–0.3 V to +4.6 V Operating Range DC Voltage Applied to Outputs in High Z State [2] ................................. –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Industrial –40 C to +85C 3.3 V 0.3 V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage Min VCC, IOH = –4.0 mA VOL Output LOW Voltage Min VCC, IOL = 8.0 mA -12 Unit Min Max 2.4 – V – 0.4 V VIH [2] Input HIGH Voltage 2.0 VCC + 0.3 V VIL [2] Input LOW Voltage –0.3 0.8 V IIX Input Leakage Current GND < VIN < VCC –1 +1 A IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max, f = fmax = 1/tRC, IOUT = 0 mA CMOS levels – 250 mA ISB1 Automatic CE Power Down Current – TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax – 60 mA ISB2 Automatic CE Power Down Current – CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0, VCC = VCC(max) – 50 mA Capacitance Parameter[3] Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max Unit 16 pF 20 pF Test Conditions 48-ball FBGA Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 24.72 C/W 5.79 C/W TA = 25 C, f = 1 MHz, VCC = 3.3 V Thermal Resistance Parameter[3] Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Notes 2. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-12063 Rev. *J Page 4 of 14 CY7C1071DV33 AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] HIGH-Z CHARACTERISTICS: R1 317 3.3 V 50 VTH = 1.5 V OUTPUT Z0 = 50 OUTPUT 30 pF* R2 351 5 pF* INCLUDING JIG AND SCOPE (b) (a) * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT ALL INPUT PULSES 3.0 V 90% 90% 10% GND RISE TIME: > 1 V/ns 10% (c) FALL TIME: > 1 V/ns Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR[5] Chip Deselect to Data Retention Time tR[6] Operation Recovery Time VCC = 2 V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min Typ Max Unit 2 – – V – – 50 mA 0 – – ns tRC – – ns Figure 3. Data Retention Waveform DATA RETENTION MODE 3.0 V VCC tCDR VDR > 2 V 3.0 V tR CE Notes 4. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins to include reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 5. Tested initially and after any design or process changes that may affect these parameters. 6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 001-12063 Rev. *J Page 5 of 14 CY7C1071DV33 AC Switching Characteristics Over the Operating Range [7] Parameter Description -12 Min Max Unit Read Cycle tpower VCC(typ) to the first access [8] 100 – s tRC Read Cycle Time 12 – ns tAA Address to Data Valid – 12 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 12 ns tDOE OE LOW to Data Valid – 7 ns 1 – ns – 7 ns 3 – ns – 7 ns 0 – ns – 12 ns – 7 ns 1 – ns – 7 ns tLZOE tHZOE tLZCE tHZCE tPU OE LOW to Low Z [9] OE HIGH to High Z CE LOW to Low Z [9] [9] CE HIGH to High Z [9] [10] CE LOW to Power Up tPD CE HIGH to Power Down tDBE Byte Enable to Data Valid tLZBE tHZBE Write Cycle Byte Enable to Low Z [10] [9] Byte Disable to High Z [9] [11, 12] tWC Write Cycle Time 12 – ns tSCE CE LOW to Write End 9 – ns tAW Address Setup to Write End 9 – ns tHA Address Hold from Write End 0 – ns tSA Address Setup to Write Start 0 – ns tPWE WE Pulse Width 9 – ns tSD Data Setup to Write End 7 – ns tHD Data Hold from Write End 0 – ns WE HIGH to Low Z [9] 3 – ns tHZWE WE LOW to High Z [9] – 7 ns tBW Byte Enable to End of Write 9 – ns tLZWE Notes 7. Test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 V and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part (a) of Figure 2 on page 5, unless specified otherwise. 8. tpower is the minimum amount of time that the power supply must be at typical VCC values until the first memory access can be performed. 9. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 2 on page 5. Transition is measured at ±200 mV from steady-state voltage. 10. These parameters are guaranteed by design and are not tested. 11. The internal memory write time is defined by the overlap of CE, WE = VIL. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-12063 Rev. *J Page 6 of 14 CY7C1071DV33 Switching Waveforms Figure 4. Read Cycle 1 (Address Transition Controlled) [13, 14] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATA VALID DATA OUT VALID Figure 5. Read Cycle 2 (OE Controlled) [14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA I/O HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA OUT VALID HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Notes 13. Device is continuously selected. OE, CE, BHE or BHE or both = VIL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE transition LOW. Document Number: 001-12063 Rev. *J Page 7 of 14 CY7C1071DV33 Switching Waveforms (continued) Figure 6. Write Cycle 1 (CE Controlled) [16, 17] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IN VALID DATA I/O Figure 7. Write Cycle 2 (WE Controlled, OE LOW) [16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE DATA I/O tSD tHD DATA IN VALID tLZWE Notes 16. Data I/O is high impedance if OE or BHE, BLE or both = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-12063 Rev. *J Page 8 of 14 CY7C1071DV33 Switching Waveforms (continued) Figure 8. Write Cycle 3 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD DATA I/O Document Number: 001-12063 Rev. *J tHD DATA IN VALID Page 9 of 14 CY7C1071DV33 Truth Table CE OE WE BLE BHE I/O0–IO7 I/O8–I/O15 Mode Power H X X X X High Z High Z Power-down Standby (ISB) L L H L L Data Out Data Out Read All Bits Active (ICC) L L H L H Data Out High Z Read Lower Bits Only Active (ICC) L L H H L High Z Data Out Read Upper Bits Only Active (ICC) L X L L L Data In Data In Write All Bits Active (ICC) L X L L H Data In High Z Write Lower Bits Only Active (ICC) L X L H L High Z Data In Write Upper Bits Only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1071DV33-12BAXI Package Diagram Package Type 51-85191 48-ball FBGA (8 × 9.5 × 1.2 mm) (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 07 1 D V33 - 12 BA X I Temperature Range: I = Industrial Pb-free Package Type: BA = 48-ball FBGA Speed: 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 1 = Data width × 16-bits 07 = 32-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document Number: 001-12063 Rev. *J Page 10 of 14 CY7C1071DV33 Package Diagram Figure 9. 48-ball FBGA (8 × 9.5 × 1.2 mm) BA48J Package Outline, 51-85191 51-85191 *C Document Number: 001-12063 Rev. *J Page 11 of 14 CY7C1071DV33 Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degree Celsius FPBGA fine-pitch ball grid array MHz megahertz I/O input/output µA microampere OE output enable µs microsecond SRAM static random access memory mA milliampere TTL transistor-transistor logic mm millimeter WE write enable ms millisecond mV millivolt ns nanosecond ohm % percent Document Number: 001-12063 Rev. *J Symbol Unit of Measure pF picofarad V volt W watt Page 12 of 14 CY7C1071DV33 Document History Page Document Title: CY7C1071DV33, 32-Mbit (2 M × 16) Static RAM Document Number: 001-12063 REV. ECN NO. Submission Date Orig. of Change ** 605460 See ECN *A 1192183 See ECN *B 2711136 05/29/2009 VKN / PYRS Added 10 ns speed bin In 12 ns speed bin, changed ISB1 from 70 to 60 mA and ISB2 from 60 to 50 mA Changed CIN from 8 pF to 16 pF and COUT from 10 pF to 20 pF Changed JA from 28.37 C/W to 24.72 C/W Removed 119-Ball PBGA package Added 48-Ball FBGA package *C 2759408 09/03/2009 VKN / AESA Removed 10ns speed Marked thermal specs as “TBD” Changed tDOE, tHZOE, tHZCE, tDBE, tHZBE, tHZWE specs from 6 ns to 7ns Added -12B2XI part (Dual CE option) *D 2813370 11/23/2009 VKN *E 2925803 04/30/2010 VKN / AESA *F 3109063 12/13/2010 AJU Added Ordering Code Definitions. *G 3132969 01/11/2011 AJU Added Acronyms and Units of Measure. Changed all instances of IO to I/O. Updated in new template. *H 3268861 05/28/2011 AJU Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). *I 3411360 10/17/2011 TAVA Updated Features. Updated DC Electrical Characteristics. Updated Switching Waveforms. Updated Package Diagram. *J 4573215 11/18/2014 TAVA Added related documentation hyperlink in page 1. Updated Figure 9 in Package Diagram (spec 51-85191 *B to *C). Document Number: 001-12063 Rev. *J VKN Description of Change New Data sheet VKN / Removed CE2 feature KKVTMP Updated block diagram Changed ICC spec from 160 mA to 225 mA Changed CIN spec from 8 pF to 10 pF Changed COUT spec from 10 pF to 12 pF Changed tBW spec from 8 ns to 9 ns Changed ICC spec from 225 mA to 250 mA. Converted from Preliminary to Final Removed Dual CE option from the data sheet Updated links in Sales, Solutions, and Legal Information Page 13 of 14 CY7C1071DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2014. 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Document Number: 001-12063 Rev. *J Revised November 18, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 14 of 14