PSoC® 5: CY8C52 Family Datasheet ® Programmable System-on-Chip (PSoC ) General Description With its unique array of configurable blocks, PSoC® 5 is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Library of standard peripherals Features • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs 32-bit ARM Cortex-M3 CPU core • SPI, UART, and I2C DC to 40 MHz operation • Many others available in catalog Flash program memory, up to 256 KB, 100,000 write cycles, Library of advanced peripherals 20-year retention and multiple security features • Cyclic redundancy check (CRC) Up to 64 KB SRAM memory • Pseudo random sequence (PRS) generator 128 bytes of cache memory • Local interconnect network (LIN) bus 2.0 2-KB electrically erasable programmable read-only memory • Quadrature decoder (EEPROM) memory, 1 million cycles, and 20 years retention Analog peripherals (2.7 V VDDA 5.5 V) 24-channel direct memory access (DMA) with multilayer AMBA high-performance bus (AHB) bus access 1.024 V ±1% internal voltage reference • Programmable chained descriptors and priorities Successive approximation register (SAR) analog-to-digital converter (ADC), 12-bit at 700 ksps • High bandwidth 32-bit transfer support One 8-bit, 5.5-Msps current DAC (IDAC) or 1-Msps voltage Low voltage, ultra low power DAC (VDAC) Operating voltage range: 2.7 V to 5.5 V Two comparators with 95-ns response time 6 mA at 6 MHz CapSense support Low power modes including: Programming, debug, and trace • 2-µA sleep mode Serial wire debug (SWD) and single-wire viewer (SWV) • 300-nA hibernate mode with RAM retention interfaces Versatile I/O system Cortex-M3 flash patch and breakpoint (FPB) block 46 to 70 I/Os (60 GPIOs, 8 SIOs, 2 USBIOs)) Cortex-M3 data watchpoint and trace (DWT) generates data Any GPIO to any digital or analog peripheral routability trace information LCD direct drive from any GPIO, up to 46 × 16 segments Cortex-M3 Instrumentation Trace Macrocell (ITM) can be ® used for printf-style debugging CapSense support from any GPIO 1.2 V to 5.5 V I/O interface voltages, up to four domains DWT and ITM blocks communicate with off-chip debug and trace systems via the SWV interface Maskable, independent IRQ on any pin or port 2 Schmitt trigger transistor-transistor logic (TTL) inputs Bootloader programming supportable through I C, SPI, UART, USB, and other interfaces All GPIOs configurable as open drain high/low, pull up/down, High-Z, or strong output Precision, programmable clocking 25 mA sink on SIO 3 to 24 MHz internal oscillator over full temperature and voltage range Digital peripherals 4 to 25 MHz crystal oscillator for crystal PPM accuracy 20 to 24 programmable logic device (PLD) based universal Internal PLL clock generation up to 40 MHz digital blocks (UDBs) 32.768 kHz watch crystal oscillator Full-Speed (FS) USB 2.0 12 Mbps using a 24 MHz external Low power internal oscillator at 1, 33, and 100 kHz oscillator Four 16-bit configurable timer, counter, and PWM blocks Temperature and packaging –40 °C to +85 °C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options Cypress Semiconductor Corporation Document Number: 001-66236 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 15, 2012 PSoC® 5: CY8C52 Family Datasheet Contents 1. Architectural Overview ................................................. 3 2. Pinouts ........................................................................... 5 3. Pin Descriptions ............................................................ 8 4. CPU ................................................................................. 9 4.1 ARM Cortex-M3 CPU .............................................9 4.2 Cache Controller ..................................................11 4.3 DMA and PHUB ...................................................11 4.4 Interrupt Controller ...............................................14 5. Memory ......................................................................... 16 5.1 Static RAM ...........................................................16 5.2 Flash Program Memory ........................................16 5.3 Flash Security .......................................................16 5.4 EEPROM ..............................................................16 5.5 Memory Map ........................................................17 6. System Integration ...................................................... 18 6.1 Clocking System ...................................................18 6.2 Power System ......................................................21 6.3 Reset ....................................................................24 6.4 I/O System and Routing .......................................25 7. Digital Subsystem ....................................................... 32 7.1 Example Peripherals ............................................32 7.2 Universal Digital Block ..........................................36 7.3 UDB Array Description .........................................39 7.4 DSI Routing Interface Description ........................39 7.5 USB ......................................................................41 7.6 Timers, Counters, and PWMs ..............................41 7.7 I2C ........................................................................42 8. Analog Subsystem ...................................................... 43 8.1 Analog Routing .....................................................44 8.2 Successive Approximation ADC ...........................46 8.3 Comparators .........................................................46 8.4 LCD Direct Drive ..................................................47 8.5 CapSense .............................................................48 8.6 Temp Sensor ........................................................48 8.7 DAC ......................................................................48 Document Number: 001-66236 Rev. *D 9. Programming, Debug Interfaces, Resources ............ 49 9.1 Debug Port Acquisition .........................................49 9.2 SWD Interface ......................................................49 9.3 Debug Features ....................................................51 9.4 Trace Features .....................................................51 9.5 SWV Interface ......................................................51 9.6 Programming Features .........................................51 9.7 Device Security ....................................................51 10. Development Support ............................................... 52 10.1 Documentation ...................................................52 10.2 Online .................................................................52 10.3 Tools ...................................................................52 11. Electrical Specifications ........................................... 53 11.1 Absolute Maximum Ratings ................................53 11.2 Device Level Specifications ................................54 11.3 Power Regulators ...............................................56 11.4 Inputs and Outputs .............................................57 11.5 Analog Peripherals .............................................66 11.1 Digital Peripherals ..............................................78 11.2 Memory ..............................................................81 11.3 PSoC System Resources ...................................83 11.4 Clocking ..............................................................85 12. Ordering Information ................................................. 89 12.1 Part Numbering Conventions .............................89 13. Packaging ................................................................... 90 14. Acronyms ................................................................... 92 15. Reference Documents ............................................... 93 16. Document Conventions ............................................ 94 16.1 Units of Measure ................................................94 17. Revision History ........................................................ 95 18. Sales, Solutions, and Legal Information ................. 97 Page 2 of 97 PSoC® 5: CY8C52 Family Datasheet 1. Architectural Overview Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Analog Interconnect Clock Tree IMO Digital System 8- Bit Timer Quadrature Decoder UDB UDB UDB UDB I 2C Slave Sequencer Universal Digital Block Array (24 x UDB) 16 -Bit PWM UDB UDB UDB UDB 8- Bit Timer Logic UDB UDB UDB UDB UDB UDB UDB UDB UDB 8- Bit SPI UDB I2C Master/ Slave 16- Bit PRS 22 UDB UDB FS USB 2.0 4x Timer Counter PWM 12- Bit SPI Logic UDB UDB UDB UART UDB USB PHY GPIOs 32.768 KHz ( Optional) GPIOs Xtal Osc SIO System Wide Resources Usage Example for UDB 4 to 25 MHz ( Optional) GPIOs Digital Interconnect 12- Bit PWM RTC Timer Memory System WDT and Wake Program & Debug CPU System SRAM 8051or Cortex M3 CPU Interrupt Controller FLASH Cache PHUB DMA GPIOs System Bus Program GPIOs EEPROM ILO Debug Trace GPIOs Clocking System LCD Direct Drive ADC POR and LVD SAR ADC 2.7 to 5.5 V Sleep Power 1.8 V LDO + Temperature Sensor CapSense 2x CMP DAC Figure 1-1 on page 3 illustrates the major components of the CY8C52 family. They are: ARM Cortex-M3 CPU subsystem Nonvolatile subsystem Programming, debug, and test subsystem Inputs and outputs Clocking Power Digital subsystem - GPIOs SIOs Analog System Power Management System PSoC’s digital subsystem provides half of its unique configurability. It connects a digital signal from any peripheral to any pin through the digital system interconnect (DSI). It also provides functional flexibility through an array of small, fast, low power UDBs. PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. The designer can also easily create a digital circuit using boolean primitives by means of graphical design entry. Each UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state machine engine to support a wide variety of peripherals. Analog subsystem Document Number: 001-66236 Rev. *D Page 3 of 97 PSoC® 5: CY8C52 Family Datasheet In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C52 family these blocks can include four 16-bit timers, counters, and PWM blocks; I2C slave, master, and multimaster and Full-Speed USB. For more details on the peripherals see the “Example Peripherals” section on page 32 of this data sheet. For information on UDBs, DSI, and other digital blocks, see the “Digital Subsystem” section on page 32 of this data sheet. PSoC’s analog subsystem is the second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage reference with less than 1% error over temperature and voltage. The configurable analog subsystem includes: Analog muxes Comparators Voltage references ADC DAC All GPIO pins can route analog signals into and out of the device using the internal analog bus. This allows the device to interface up to 62 discrete analog signals. The CY8C52 family offers a SAR ADC. Featuring 12-bit conversions at up to 700 k samples per second, it also offers low nonlinearity and offset errors. It is well suited for a variety of higher speed analog applications. A high-speed voltage or current DAC supports 8-bit output signals at an update rate of 5.5 Msps in IDAC and 1 Msps in VDAC. It can be routed out of any GPIO pin. You can create higher resolution voltage PWM DAC outputs using the UDB array. This can be used to create a pulse width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each UDB support PWM, PRS, or delta-sigma algorithms with programmable widths. In addition to the ADC and DAC, the analog subsystem provides multiple comparators. See the “Analog Subsystem” section on page 43 of this data sheet for more details. PSoC’s CPU subsystem is built around a 32-bit three-stage pipelined ARM Cortex-M3 processor running at up to 40 MHz. The Cortex-M3 includes a tightly integrated nested vectored interrupt controller (NVIC) and various debug and trace modules. The overall CPU subsystem includes a DMA controller, cache, and interrupt controller. The NVIC provides low latency, nested interrupts, and tail-chaining of interrupts and other features to increase the efficiency of interrupt handling. The DMA controller enables peripherals to exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those CPU cycles to improve the performance of firmware algorithms. The presence of cache improves the access speed of instructions by the CPU. PSoC’s nonvolatile subsystem consists of flash and byte-writeable EEPROM. It provides up to 256 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling boot loaders. A powerful and flexible protection model Document Number: 001-66236 Rev. *D secures the user's sensitive information, allowing selective memory block locking for read and write protection. Two KB of byte-writable EEPROM is available on-chip to store application data. The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the VDDIO pins. Every GPIO has analog I/O, LCD drive, flexible interrupt generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow VOH to be set independently of VDDIO when used as outputs. When SIOs are in input mode they are high impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes the SIO ideally suited for use on an I2C bus where the PSoC may not be powered when other devices on the bus are. The SIO pins also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the SIO can be used to make the SIO function as a general purpose analog comparator. For devices with Full-Speed USB, the USB physical interface is also provided (USBIO). When not using USB these pins may also be used for limited digital functionality and device programming. All the features of the PSoC I/Os are covered in detail in the “I/O System and Routing” section on page 25 of this data sheet. The PSoC device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. The internal main oscillator (IMO) is the master clock base for the system and has 5% accuracy at 3 MHz. The IMO can be configured to run from 3 MHz up to 24 MHz. Multiple clock derivatives can be generated from the main clock frequency to meet application needs. The device provides a PLL to generate system clock frequencies up to 40 MHz from the IMO, external crystal, or external reference clock. It also contains a separate, very low-power internal low-speed oscillator (ILO) for the sleep and watchdog timers. A 32.768 kHz external watch crystal is also supported for use in RTC applications. The clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements. The CY8C52 family supports a wide supply operating range from 2.7 to 5.5 V. This allows operation from regulated supplies such as 3.3 V ± 10% or 5.0 V ± 10%, or directly from a wide range of battery types. PSoC supports a wide range of low power modes. These include a 300-nA hibernate mode with RAM retention and a 2-µA sleep mode. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low-power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 6 mA when the CPU is running at 6 MHz. The details of the PSoC power modes are covered in the “Power System” section on page 21 of this data sheet. Page 4 of 97 PSoC® 5: CY8C52 Family Datasheet PSoC uses a SWD interface for programming, debug, and test. Using this standard interface enables the designer to debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. The Cortex-M3 debug and trace modules include FPB, DWT, and ITM. These modules have many features to help solve difficult debug and trace problems. Details of the programming, test, and debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” section on page 49 of this data sheet. 2. Pinouts The VDDIO pin that supplies a particular set of pins is indicated by the black lines drawn on the pinout diagrams in Figure 2-1 and Figure 2-2. Using the VDDIO pins, a single PSoC can support multiple interface voltage levels, eliminating the need for off-chip level shifters. Each VDDIO may sink up to 20 mA total to its associated I/O pins and opamps, and each set of VDDIO associated pins may sink up to 100 mA. 55 54 53 52 58 57 56 P15[5] (GPIO) P15[4] (GPIO) VDDD VSSD VCCD P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO) P0[4] (GPIO, SAR0REF) VDDIO0 51 50 Lines show VDDIO to I/O supply association QFN 28 29 30 31 32 33 34 MHZ XTAL: XI (IDAC1, GPIO) P3[0] (IDAC3, GPIO) P3[1] (EXTREF1, GPIO) P3[2] (GPIO) P3[3] (GPIO) P3[4] (GPIO) P3[5] (TOP VIEW) 18 19 20 21 22 23 24 25 26 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] [2] (USBIO, D+, SWDIO) P15[6] [2] (USBIO, D-, SWDCK) P15[7] VDDD VSSD VCCD MHZ XTAL: XO (GPIO) P2[6] (GPIO) P2[7] (SIO) P12[4] (SIO) P12[5] VSSD [2] DNU VSSD VSSD VSSD XRES (SWDIO, GPIO) P1[0] (SWDCK, GPIO) P1[1] (GPIO) P1[2] (SWV, GPIO) P1[3] (GPIO) P1[4] (GPIO) P1[5] VDDIO1 66 65 64 63 62 61 60 59 68 67 P2[5] (GPIO) VDDIO2 P2[4] (GPIO) P2[3] (GPIO) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) Figure 2-1. 68-pin QFN Part Pinout[1] 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P0[3] (GPIO, EXTREF0) P0[2] (GPIO) P0[1] (GPIO) P0[0] (GPIO) P12[3] (SIO) P12[2] (SIO) VSSD VDDA VSSA VCCA P15[3] (GPIO, KHZ XTAL: XI) P15[2] (GPIO, KHZ XTAL: XO) P12[1] (SIO) P12[0] (SIO) P3[7] (GPIO) P3[6] (GPIO) VDDIO3 Notes 1. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. 2. Pins labeled Do Not Use (DNU) must be left floating. USB pins on devices without USB are DNU. Document Number: 001-66236 Rev. *D Page 5 of 97 PSoC® 5: CY8C52 Family Datasheet TQFP 77 76 P4[5] (GPIO) P4[4] (GPIO) P4[3] (GPIO) P4[2] (GPIO) P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO) P0[4] (GPIO, SAR0REF) 87 86 85 84 83 82 81 80 79 78 90 89 88 P15[4] (GPIO) P6[3] (GPIO) P6[2] (GPIO) P6[1] (GPIO) P6[0] (GPIO) VDDD VSSD VCCD P4[7] (GPIO) P4[6] (GPIO) 98 97 96 95 94 93 92 91 Lines show VDDIO to I/O supply association 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDDIO0 P0[3] (GPIO, EXTREF0) P0[2] (GPIO) P0[1] (GPIO) P0[0] (GPIO) P4[1] (GPIO) P4[0] (GPIO) P12[3] (SIO) P12[2] (SIO) VSSD VDDA VSSA VCCA NC NC NC NC NC NC P15[3] (GPIO, KHZ XTAL: XI) P15[2] (GPIO, KHZ XTAL: XO) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) P3[7] (GPIO) P3[6] (GPIO) (GPIO) P3[5] VDDIO3 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDD VSSD VCCD NC NC MHZ XTAL: XO MHZ XTAL: XI (IDAC1, GPIO) P3[0] (IDAC3, GPIO) P3[1] (EXTREF1, GPIO) P3[2] (GPIO) P3[3] (GPIO) P3[4] [3] (USBIO, D-, SWDCK) P15[7] 54 53 52 51 26 27 28 29 30 31 32 33 34 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDDIO1 (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (GPIO) P5[4] (GPIO) P5[5] (GPIO) P5[6] (GPIO) P5[7] [3] (USBIO, D+, SWDIO) P15[6] (GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] (GPIO) P6[4] (GPIO) P6[5] (GPIO) P6[6] (GPIO) P6[7] VSSD [3] DNU VSSD VSSD VSSD XRES (GPIO) P5[0] (GPIO) P5[1] (GPIO) P5[2] (GPIO) P5[3] (SWDIO, GPIO) P1[0] (SWDCK, GPIO) P1[1] (GPIO) P1[2] (SWV, GPIO) P1[3] (GPIO) P1[4] (GPIO) P1[5] 100 99 VDDIO2 P2[4] (GPIO) P2[3] (GPIO) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPIO) Figure 2-2. 100-pin TQFP Part Pinout Figure 2-3 and Figure 2-4 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a 2-layer board. The two pins labeled Vddd must be connected together. The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure 2-3 and Power System on page 21. The trace between the two Vccd pins should be as short as possible. The two pins labeled Vssd must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Note 3. Pins labeled Do Not Use (DNU) must be left floating. USB pins on devices without USB are DNU. Document Number: 001-66236 Rev. *D Page 6 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 2-3. Example Schematic for 100-pin TQFP Part with Power Connections VDDD C1 1 UF VDDD VDDD VSSD VDDD VSSD VSSD VDDIO0 REF0, P0[3] P0[2] P0[1] P0[0] P4[1] P4[0] SIO, P12[3] SIO, P12[2] VSSD VDDA VSSA VCCA NC NC NC NC NC NC KHZXIN, P15[3] KHZXOUT, P15[2] SIO, P12[1] SIO, P12[0] P3[7] P3[6] VDDIO1 P1[6] P1[7] P12[6], SIO P12[7], SIO P5[4] P5[5] P5[6] P5[7] USB D+, P15[6] USB D-, P15[7] VDDD VSSD VCCD NC NC MHZXOUT MHZXIN P3[0], IDAC1 P3[1], IDAC3 P3[2], REF1 P3[3] P3[4] P3[5] VDDIO3 P2[5] P2[6] P2[7] P12[4], SIO P12[5], SIO P6[4] P6[5] P6[6] P6[7] VSSD DNU VSSD VSSD VSSD XRES P5[0] P5[1] P5[2] P5[3] P1[0], SWDIO P1[1], SWDCK P1[2] P1[3], SWV P1[4] P1[5] VSSD VDDA VDDD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C8 0.1 UF C17 1 UF VSSD VSSA VSSD VSSD VDDA VSSA VCCA VDDA C9 4 1 UF C10 0.1 UF VSSA VDDD VDDD VCCD C11 0.1 UF C12 0.1 UF VSSD VDDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSSD VCCD VDDIO2 P2[4] P2[3] P2[2] P2[1] P2[0] P15[5] P15[4] P6[3] P6[2] P6[1] P6[0] VDDD VSSD VCCD P4[7] P4[6] P4[5] P4[4] P4[3] P4[2] IDAC2, P0[7] IDAC0, P0[6] P0[5] SAR0REF, P0[4] VSSD VSSD C2 0.1 UF 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 C6 0.1 UF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDDD C15 4 1 UF C16 0.1 UF VSSD VSSD Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-4. Note 4. 10 µF is required for sleep mode. See Table 11-3. Document Number: 001-66236 Rev. *D Page 7 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance Vssa Vddd Vssd Plane 3. Pin Descriptions IDAC0. Low resistance output pin for high IDAC. Vssd Vdda Vssa Plane of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. SAR0ref. External reference for SAR ADC. USBIO, D-. Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. GPIO. General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense. VCCA. Output of analog core regulator and input to analog core. Requires a 1 µF capacitor to VSSA (10 µF is required for sleep mode. See Table 11-3). Regulator output not for external use. kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin. VCCD. Output of digital core regulator and input to digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1-µF capacitor to VSSD (10 µF is required for sleep mode. See Table 11-3); see Power System on page 21. Regulator output not for external use. Extref0, Extref1. External reference input to the analog system. MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator pin. If a crystal is not used, then Xi must be shorted to ground and Xo must be left floating. SIO. Special I/O provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. SWDCK. Serial wire debug clock programming and debug port connection. When programming and debugging using SWD is done over USBIOs, the SWDCK pin of port P1[1] is not available for use as a general purpose I/O and should be externally pulled down using a resistor of less than 100 K SWDIO. Serial wire debug Input and output programming and debug port connection. SWV. Single wire viewer output. USBIO, D+. Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead VDDA. Supply for all analog peripherals and analog core regulator. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA.[5] VDDD. Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to VDDA.[5] VSSA. Ground for all analog peripherals. VSSD. Ground for all digital logic and I/O pins. VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (2.7 V to 5.5 V), and must be less than or equal to VDDA. XRES. External reset pin. Active low with internal pull-up. RSVD. Reserved pins. Note 5. VDDD and VDDA must be brought up in synchronization with each other, that is, at the same rates and levels. VDDA must be greater than or equal to all other supplies. Document Number: 001-66236 Rev. *D Page 8 of 97 PSoC® 5: CY8C52 Family Datasheet 4. CPU 4.1 ARM Cortex-M3 CPU The CY8C52 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling features. Figure 4-1. ARM Cortex-M3 Block Diagram Interrupt Inputs Nested Vectored Interrupt Controller (NVIC) Flash Patch and Breakpoint (FPB) I- Bus SWD D- Bus Instrumentation Trace Module (ITM) S-Bus Debug Block (SWD) Trace Port Interface Unit (TPIU) SWV Cortex M3 Wrapper C- Bus AHB 32 KB SRAM Data Watchpoint and Trace (DWT) Cortex M3 CPU Core AHB Bus Matrix Bus Matrix Cache 256 KB Flash AHB 32 KB SRAM Bus Matrix AHB Bridge and Bus Matrix DMA PHUB AHB Spokes GPIO Prog. Digital Prog. Analog Special Functions Peripherals The Cortex-M3 CPU subsystem includes these features: Cache controller with 128 bytes of memory ARM Cortex-M3 CPU Peripheral HUB (PHUB) Programmable nested vectored interrupt controller (NVIC), DMA controller tightly integrated with the CPU core Full-featured debug and trace module, tightly integrated with the CPU core Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB of SRAM Document Number: 001-66236 Rev. *D 4.1.1 Cortex-M3 Features The Cortex-M3 CPU features include: 4-GB address space. Predefined address regions for code, data, and peripherals. Multiple buses for efficient and simultaneous accesses of instructions, data, and peripherals. Page 9 of 97 PSoC® 5: CY8C52 Family Datasheet The Thumb®-2 instruction set, which offers ARM-level performance at Thumb-level code density. This includes 16-bit and 32-bit instructions. Advanced instructions include: Bit-field control Hardware multiply and divide Saturation If-Then Wait for events and interrupts Exclusive access and barrier Special register access The Cortex-M3 does not support ARM instructions. 4.1.3 CPU Registers The Cortex-M3 CPU registers are listed in Table 4-2. Registers R0-R15 are all 32 bits wide. Table 4-2. Cortex M3 CPU Registers Register R0-R12 General purpose registers R0-R12 have no special architecturally defined uses. Most instructions that specify a general purpose register specify R0-R12. Low Registers: Registers R0-R7 are accessible by all instructions that specify a general purpose register. High Registers: Registers R8-R12 are accessible by all 32-bit instructions that specify a general purpose register; they are not accessible by all 16-bit instructions. R13 R13 is the stack pointer register. It is a banked register that switches between two 32-bit stack pointers: the main stack pointer (MSP) and the process stack pointer (PSP). The PSP is used only when the CPU operates at the user level in thread mode. The MSP is used in all other privilege levels and modes. Bits[0:1] of the SP are ignored and considered to be 0, so the SP is always aligned to a word (4 byte) boundary. R14 R14 is the link register (LR). The LR stores the return address when a subroutine is called. R15 R15 is the program counter (PC). Bit 0 of the PC is ignored and considered to be 0, so instructions are always aligned to a half word (2 byte) boundary. xPSR The program status registers are divided into three status registers, which are accessed either together or separately: Application program status register (APSR) holds program execution status bits such as zero, carry, negative, in bits[27:31]. Interrupt program status register (IPSR) holds the current exception number in bits[0:8]. Execution program status register (EPSR) holds control bits for interrupt continuable and IF-THEN instructions in bits[10:15] and [25:26]. Bit 24 is always set to 1 to indicate Thumb mode. Trying to clear it causes a fault exception. PRIMASK A 1-bit interrupt mask register. When set, it allows only the nonmaskable interrupt (NMI) and hard fault exception. All other exceptions and interrupts are masked. Bit-band support for the SRAM region. Atomic bit-level write and read operations for SRAM addresses. Unaligned data storage and access. Contiguous storage of data of different byte lengths. Operation at two privilege levels (privileged and user) and in two modes (thread and handler). Some instructions can only be executed at the privileged level. There are also two stack pointers: Main (MSP) and Process (PSP). These features support a multitasking operating system running one or more user-level processes. Extensive interrupt and system exception support. 4.1.2 Cortex-M3 Operating Modes The Cortex-M3 operates at either the privileged level or the user level, and in either the thread mode or the handler mode. Because the handler mode is only enabled at the privileged level, there are actually only three states, as shown in Table 4-1. Table 4-1. Operational Level Condition Privileged User Running an exception Handler mode Not used Running main program Thread mode Thread mode Description At the user level, access to certain instructions, special registers, configuration registers, and debugging components is blocked. Attempts to access them cause a fault exception. At the privileged level, access to all instructions and registers is allowed. The processor runs in the handler mode (always at the privileged level) when handling an exception, and in the thread mode when not. FAULTMASK A 1-bit interrupt mask register. When set, it allows only the NMI. All other exceptions and interrupts are masked. BASEPRI Document Number: 001-66236 Rev. *D A register of up to nine bits that define the masking priority level. When set, it disables all interrupts of the same or higher priority value. If set to 0 then the masking function is disabled. Page 10 of 97 PSoC® 5: CY8C52 Family Datasheet Table 4-2. Cortex M3 CPU Registers (continued) Register CONTROL Description A 2-bit register for controlling the operating mode. Bit 0: 0 = privileged level in thread mode, 1 = user level in thread mode. Bit 1: 0 = default stack (MSP) is used, 1 = alternate stack is used. If in thread mode or user level then the alternate stack is the PSP. There is no alternate stack for handler mode; the bit must be 0 while in handler mode. 4.2 Cache Controller The CY8C52 family 128 bytes of direct mapped instruction cache between the CPU and the flash memory. This allows the CPU to access instructions much faster. The cache is enabled by default but user have the option to disable it. Simultaneous DMA source and destination burst transactions on different spokes Supports 8-, 16-, 24-, and 32-bit addressing and data Table 4-3. PHUB Spokes and Peripherals PHUB Spokes Peripherals 0 SRAM 1 IOs, PICU 2 PHUB local configuration, Power manager, Clocks, IC, EEPROM, Flash programming interface 3 Analog interface and trim, Decimator 4 USB, I2C, Timers, Counters, and PWMs 5 Reserved 6 UDBs group 1 7 UDBs group 2 4.3 DMA and PHUB The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of: A central hub that includes the DMA controller, arbiter, and router Multiple spokes that radiate outward from the hub to most peripherals 4.3.2 DMA Features 24 DMA channels Each channel has one or more transaction descriptors (TDs) to configure channel behavior. Up to 127 total TDs can be defined TDs can be dynamically updated Eight levels of priority per channel There are two PHUB masters: the CPU and the DMA controller. Both masters may initiate transactions on the bus. The DMA channels can handle peripheral communication without CPU intervention. The arbiter in the central hub determines which DMA channel is the highest priority if there are multiple requests. Any digitally routable signal, the CPU, or another DMA channel, 4.3.1 PHUB Features Supports transaction size of infinite or 1 to 64 k bytes CPU and DMA controller are both bus masters to the PHUB Large transactions may be broken into smaller bursts of 1 to Eight multi-layer AHB bus parallel access paths (spokes) for peripheral access can trigger a transaction Each channel can generate up to two interrupts per transfer Transactions can be stalled or canceled 127 bytes TDs may be nested and/or chained for complex transactions Simultaneous CPU and DMA access to peripherals located on different spokes Document Number: 001-66236 Rev. *D Page 11 of 97 PSoC® 5: CY8C52 Family Datasheet Table 4-4. Priority Levels 4.3.3 Priority Levels The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority number) may interrupt current DMA transfers. In the case of an interrupt, the current transfer is allowed to complete its current transaction. To ensure latency limits when multiple DMA accesses are requested simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. Priority levels 0 and 1 do not take part in the fairness algorithm and may use 100% of the bus bandwidth. If a tie occurs on two DMA requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. The round robin allocation can be disabled for each DMA channel, allowing it to always be at the head of the line. Priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in Table 4-4 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements. When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees are made. Priority Level % Bus Bandwidth 0 100.0 1 100.0 2 50.0 3 25.0 4 12.5 5 6.2 6 3.1 7 1.5 4.3.4.1 Simple DMA In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). The basic timing diagrams of DMA read and write cycles are shown in Figure 4-2. For more description on other transfer modes, refer to the Technical Reference Manual. 4.3.4 Transaction Modes Supported The flexible configuration of each DMA channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. General use cases include, but are not limited to: Figure 4-2. DMA Timing Diagram ADDRESS Phase DATA Phase ADDRESS Phase CLK ADDR 16/32 DATA Phase CLK A B ADDR 16/32 WRITE A B WRITE DATA (A) DATA READY DATA (A) DATA READY Basic DMA Read Transfer without wait states Basic DMA Write Transfer without wait states 4.3.4.2 Auto Repeat DMA 4.3.4.5 Indexed DMA Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a peripheral. This is done with a single TD that chains to itself. In an indexed DMA case, an external master requires access to locations on the system bus as if those locations were shared memory. As an example, a peripheral may be configured as an SPI or I2C slave where an address is received by the external master. That address becomes an index or offset into the internal system bus memory space. This is accomplished with an initial “address fetch” TD that reads the target address location from the peripheral and writes that value into a subsequent TD in the chain. This modifies the TD chain on the fly. When the “address fetch” TD completes it moves on to the next TD, which has the new address information embedded in it. This TD then carries out the data transfer with the address location required by the external master. 4.3.4.3 Ping Pong DMA A ping pong DMA case uses double buffering to allow one buffer to be filled by one client while another client is consuming the data previously received in the other buffer. In its simplest form, this is done by chaining two TDs together so that each TD calls the opposite TD when complete. 4.3.4.4 Circular DMA Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last TD is complete it chains back to the first TD. Document Number: 001-66236 Rev. *D Page 12 of 97 PSoC® 5: CY8C52 Family Datasheet 4.3.4.6 Scatter Gather DMA In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using multiple TDs in a chain. The chain gathers the data from the multiple locations. A similar concept applies for the reception of data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software processing convenience. Each TD in the chain specifies the location for each discrete element in the chain. 4.3.4.7 Packet Queuing DMA Packet queuing DMA is similar to scatter gather DMA but specifically refers to packet protocols. With these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, Document Number: 001-66236 Rev. *D specifying the overall length of the ensuing data phase. The CPU can set up this configuration information anywhere in system memory and copy it with a simple TD to the peripheral. After the configuration phase, a data phase TD (or a series of data phase TDs) can begin (potentially using scatter gather). When the data phase TD(s) finish, a status phase TD can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory specified by the CPU for later inspection. Multiple sets of configuration, data, and status phase “subchains” can be strung together to create larger chains that transmit multiple packets in this way. A similar concept exists in the opposite direction to receive the packets. 4.3.4.8 Nested DMA One TD may modify another TD, as the TD configuration space is memory mapped similar to any other peripheral. For example, a first TD loads a second TD’s configuration and then calls the second TD. The second TD moves data as required by the application. When complete, the second TD calls the first TD, which again updates the second TD’s configuration. This process repeats as often as necessary. Page 13 of 97 PSoC® 5: CY8C52 Family Datasheet 4.4 Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5. Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Number 1 2 3 Reset NMI Hard fault –3 (highest) –2 –1 Exception Table Address Offset 0x00 0x04 0x08 0x0C 4 MemManage Programmable 0x10 5 Bus fault Programmable 0x14 6 Usage fault Programmable 0x18 7 – 10 11 12 13 14 15 16 – 47 – SVC Debug monitor – PendSV SYSTICK IRQ – Programmable Programmable – Programmable Programmable Programmable 0x1C – 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 – 0x3FC Exception Type Priority Bit 0 of each exception vector indicates whether the exception is executed using ARM or Thumb instructions. Because the Cortex-M3 only supports Thumb instructions, this bit must always be 1. The Cortex-M3 non maskable interrupt (NMI) input can be routed to any pin, via the DSI, or disconnected from all pins. See “DSI Routing Interface Description” section on page 39. The Nested Vectored Interrupt Controller (NVIC) handles interrupts from the peripherals, and passes the interrupt vectors to the CPU. It is closely integrated with the CPU for low latency interrupt handling. Features include: 32 interrupts. Multiple sources for each interrupt. Configurable number of priority levels: from 3 to 8. Dynamic reprioritization of interrupts. Priority grouping. This allows selection of preempting and non preempting interrupt levels. Function Starting value of R13 / MSP Reset Non maskable interrupt All classes of fault, when the corresponding fault handler cannot be activated because it is currently disabled or masked Memory management fault, for example, instruction fetch from a nonexecutable region Error response received from the bus system; caused by an instruction prefetch abort or data access error Typically caused by invalid instructions or trying to switch to ARM mode Reserved System service call via SVC instruction Debug monitor Reserved Deferred request for system service System tick timer Peripheral interrupt request #0 – #31 Support for tail-chaining, and late arrival, of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. If the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. The DMA interrupt sources provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors is from the UDB digital routing array. This allows any digital signal available to the UDB array to be used as an interrupt source. All interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections. Table 4-6. Interrupt Vector Table Interrupt # 0 1 2 3 4 5 6 7 8 Cortex-M3 Exception # 16 17 18 19 20 21 22 23 24 Document Number: 001-66236 Rev. *D Fixed Function Low voltage detect (LVD) Cache Reserved Pwr Mgr PICU[0] PICU[1] PICU[2] PICU[3] PICU[4] DMA phub_termout0[0] phub_termout0[1] phub_termout0[2] phub_termout0[3] phub_termout0[4] phub_termout0[5] phub_termout0[6] phub_termout0[7] phub_termout0[8] UDB udb_intr[0] udb_intr[1] udb_intr[2] udb_intr[3] udb_intr[4] udb_intr[5] udb_intr[6] udb_intr[7] udb_intr[8] Page 14 of 97 PSoC® 5: CY8C52 Family Datasheet Table 4-6. Interrupt Vector Table (continued) Interrupt # 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Cortex-M3 Exception # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Document Number: 001-66236 Rev. *D Fixed Function PICU[5] PICU[6] PICU[12] PICU[15] Comparators Combined Reserved I2C Reserved Reserved Reserved Reserved Reserved USB SOF Int USB Arb Int USB Bus Int USB Endpoint[0] USB Endpoint Data Reserved Reserved Reserved Decimator Int phub_err_int eeprom_fault_int DMA phub_termout0[9] phub_termout0[10] phub_termout0[11] phub_termout0[12] phub_termout0[13] phub_termout0[14] phub_termout0[15] phub_termout1[0] phub_termout1[1] phub_termout1[2] phub_termout1[3] phub_termout1[4] phub_termout1[5] phub_termout1[6] phub_termout1[7] phub_termout1[8] phub_termout1[9] phub_termout1[10] phub_termout1[11] phub_termout1[12] phub_termout1[13] phub_termout1[14] phub_termout1[15] UDB udb_intr[9] udb_intr[10] udb_intr[11] udb_intr[12] udb_intr[13] udb_intr[14] udb_intr[15] udb_intr[16] udb_intr[17] udb_intr[18] udb_intr[19] udb_intr[20] udb_intr[21] udb_intr[22] udb_intr[23] udb_intr[24] udb_intr[25] udb_intr[26] udb_intr[27] udb_intr[28] udb_intr[29] udb_intr[30] udb_intr[31] Page 15 of 97 PSoC® 5: CY8C52 Family Datasheet 5. Memory 5.1 Static RAM CY8C52 Static RAM (SRAM) is used for temporary data storage. Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower from SRAM above 0x20000000. The device provides up to 64 KB of SRAM. The CPU or the DMA controller can access all of SRAM. The SRAM can be accessed simultaneously by the Cortex-M3 CPU and the DMA controller if accessing different 32-KB blocks. 5.2 Flash Program Memory Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configuration data and bulk data storage. The main flash memory area contains up to 256 KB of user program space. Up to an additional 32 KB of flash space is available for storing device configuration data and bulk user data. User code may not be run out of this flash memory section. The flash output is 9 bytes wide with 8 bytes of data and 1 additional byte. The flash programming interface performs flash erasing, programming and setting code protection levels. Flash In System Serial Programming (ISSP), typically used for production programming, is possible through the SWD interface. In-system programming, typically used for bootloaders, is also possible using serial interfaces such as I2C, USB, UART, and SPI, or any communications protocol. 5.3 Flash Security All PSoC devices include a flexible flash protection model that prevents access and visibility to on-chip flash memory. This prevents duplication or reverse engineering of proprietary code. Flash memory is organized in blocks, where each block contains 256 bytes of program or data and 32 bytes of configuration or general-purpose data. The device offers the ability to assign one of four protection levels to each row of flash. Table 5-1 lists the protection modes available. Flash protection levels can only be changed by performing a complete flash erase. The Full Protection and Field Upgrade settings disable external access (through a debugging tool such as PSoC Creator, for example). If your application requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no security is needed in your application. The PSoC device also offers an advanced security feature called Device Security which permanently disables all test, programming, and debug ports, protecting your application from external access (see the Document Number: 001-66236 Rev. *D “Device Security” section on page 51). For more information on how to take full advantage of the security features in PSoC, see the PSoC 5 TRM. Table 5-1. Flash Protection Protection Setting Allowed Not Allowed Unprotected External read and write + – internal read and write Factory Upgrade External write + internal External read read and write Field Upgrade Internal read and write External read and write Full Protection Internal read External read and write + internal write Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress data sheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. 5.4 EEPROM PSoC EEPROM memory is a byte addressable nonvolatile memory. The CY8C52 has 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the byte level. Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable and writeable at the row level. The EEPROM is divided into two sections, each containing 64 rows of 16 bytes each. The CPU cannot execute out of EEPROM. Page 16 of 97 PSoC® 5: CY8C52 Family Datasheet Table 5-3. Peripheral Data Address Map (continued) 5.5 Memory Map The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.5.1 Address Map Address Range Purpose 0x40004700 – 0x400047FF Flash programming interface 0x40004800 – 0x400048FF Cache controller 0x40004900 – 0x400049FF I2C controller The 4-GB address space is divided into the ranges shown in Table 5-2: 0x40004E00 – 0x40004EFF Decimator Table 5-2. Address Map 0x40005000 – 0x400051FF I/O ports control Address Range 0x00000000 – 0x1FFFFFFF 0x20000000 – 0x3FFFFFFF 0x40004F00 – 0x40004FFF Fixed timer/counter/PWMs 0x40005800 – 0x40005FFF Analog Subsystem Interface Size Use 0.5 GB Program code. This includes the exception vector table at power up, which starts at address 0. 0x40006000 – 0x400060FF USB Controller Static RAM. This includes a 1 MByte bit-band region starting at 0x20000000 and a 32 Mbyte bit-band alias region starting at 0x22000000. 0x40008000 – 0x400087FF EEPROM 0.5 GB 0x40000000 – 0x5FFFFFFF 0.5 GB Peripherals. 0x60000000 – 0x9FFFFFFF 1 GB External RAM. 0xA0000000 – 0xDFFFFFFF 1 GB External peripherals. 0xE0000000 – 0xFFFFFFFF 0.5 GB Internal peripherals, including the NVIC and debug and trace modules. Table 5-3. Peripheral Data Address Map Address Range Purpose 0x00000000 – 0x0003FFFF 256 K Flash 0x1FFF8000 – 0x1FFFFFFF 32 K SRAM in Code region 0x20000000 – 0x20007FFF 32 K SRAM in SRAM region 0x40004000 – 0x400042FF Clocking, PLLs, and oscillators 0x40004300 – 0x400043FF Power management 0x40004500 – 0x400045FF Ports interrupt control Document Number: 001-66236 Rev. *D 0x40006400 – 0x40006FFF UDB Configuration 0x40007000 – 0x40007FFF PHUB Configuration 0x40010000 – 0x4001FFFF Digital Interconnect Configuration 0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers, including NVIC, debug, and trace The bit-band feature allows individual bits in SRAM to be read or written as atomic operations. This is done by reading or writing bit 0 of corresponding words in the bit-band alias region. For example, to set bit 3 in the word at address 0x20000000, write a 1 to address 0x2200000C. To test the value of that bit, read address 0x2200000C and the result is either 0 or 1 depending on the value of the bit. Most memory accesses done by the Cortex-M3 are aligned, that is, done on word (4-byte) boundary addresses. Unaligned accesses of words and 16-bit half-words on nonword boundary addresses can also be done, although they are less efficient. 5.5.2 Address Map and Cortex-M3 Buses The ICode and DCode buses are used only for accesses within the Code address range, 0 - 0x1FFFFFFF. The system bus is used for data accesses and debug accesses within the ranges 0x20000000 - 0xDFFFFFFF and 0xE0100000 - 0xFFFFFFFF. Instruction fetches can also be done within the range 0x20000000 - 0x3FFFFFFF, although these can be slower than instruction fetches via the ICode bus. The private peripheral bus (PPB) is used within the Cortex-M3 to access system control registers and debug and trace module registers. Page 17 of 97 PSoC® 5: CY8C52 Family Datasheet Key features of the clocking system include: 6. System Integration Seven general purpose clock sources 6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. The IMO and PLL together can generate up to a 40 MHz clock, accurate to ±5% over voltage and temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and cost. All of the system clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for anything you want, for example a UART baud rate generator. Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based on the complete system’s requirements. It greatly speeds the design process. PSoC Creator allows designers to build clocking systems with minimal input. The designer can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. This is possible because of the programmability inherent PSoC. 3 to 24 MHz IMO, ±5% at 3 MHz 4 to 25 MHz external crystal oscillator (MHzECO) Clock doubler provides a doubled clock frequency output for the USB block, see USB Clock Domain on page 21. DSI signal from an external I/O pin or other logic 24 to 40 MHz fractional phase-locked loop (PLL) sourced from IMO, MHzECO, or DSI 1 kHz, 33 kHz, 100 kHz ILO for watchdog timer (WDT) and Sleep Timer 32.768 kHz external crystal oscillator (ECO) for RTC Independently sourced clock dividers in all clocks Eight 16-bit clock dividers for the digital system Four 16-bit clock dividers for the analog system Dedicated 16-bit divider for the CPU bus and CPU clock Automatic clock configuration in PSoC Creator Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin Fmax Tolerance at Fmax Startup Time IMO 3 MHz ±5% over voltage and temperature 24 MHz ±8% 12 µs max MHzECO 4 MHz Crystal dependent 25 MHz Crystal dependent 5 ms typ, max is crystal dependent DSI 0 MHz Input dependent 40 MHz Input dependent Input dependent PLL 24 MHz Input dependent 40 MHz Input dependent 250 µs max Doubler 48 MHz Input dependent 48 MHz Input dependent 1 µs max ILO 1 kHz –50%, +100% 100 kHz –55%, +100% 15 ms max in lowest power mode kHzECO 32 kHz Crystal dependent 32 kHz Crystal dependent 500 ms typ, max is crystal dependent Document Number: 001-66236 Rev. *D Page 18 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 6-1. Clocking Subsystem 3-24 MHz IMO 4-25 MHz ECO External IO or DSI 0-40 MHz 32 kHz ECO 1,33,100 kHz ILO CPU Clock 48 MHz Doubler for USB 24-40 MHz PLL System Clock Mux Bus Clock Bus Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w 7 6.1.1 Internal Oscillators 6.1.1.1 Internal Main Oscillator The IMO operates with no external components and outputs a stable clock. A factory trim for each frequency range is stored in the device. With the factory trim, tolerance varies from ±5% at 3 MHz, up to ±8% at 24 MHz. The IMO, in conjunction with the PLL, allows generation of CPU and system clocks up to the device's maximum frequency. The IMO provides clock outputs at 3, 6, 12, and 24 MHz. 6.1.1.2 Clock Doubler The clock doubler outputs a clock at twice the frequency of the input clock. The doubler works at input frequency of 24 MHz, providing 48 MHz for the USB. It can be configured to use a clock from the MHzECO or the DSI (external pin). The doubler is typically used to clock the USB. 6.1.1.3 Phase-Locked Loop The PLL allows low frequency, high accuracy clocks to be multiplied to higher frequencies. This is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time. The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range of 24 to 40 MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired system clock Document Number: 001-66236 Rev. *D frequency. The accuracy of the PLL output depends on the accuracy of the PLL input source. The most common PLL use is to multiply the IMO clock at 3 MHz, where it is most accurate, to generate the CPU and system clocks up to the device’s maximum frequency. The PLL achieves phase lock within 250 µs (verified by bit setting). It can be configured to use a clock from the IMO, MHzECO, or DSI (external pin). The PLL clock source can be used until lock is complete and signaled with a lock bit. The lock signal can be routed through the DSI to generate an interrupt. Disable the PLL before entering low power modes. 6.1.1.4 Internal Low Speed Oscillator The ILO provides clock frequencies for low power consumption, including the sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and 100 kHz. The 1 kHz clock (CLK1K) is typically used for a background ‘heartbeat’ timer. This clock inherently lends itself to long sleep intervals using the central timewheel (CTW). The central timewheel is a free running counter clocked by the ILO 1 kHz output. The central timewheel is always enabled except in hibernate mode and when the CPU is stopped during debug on chip mode. It can be used to generate periodic interrupts for timing purposes or to wake the system from a low power mode. Firmware can reset the central timewheel. Page 19 of 97 PSoC® 5: CY8C52 Family Datasheet The central timewheel can be programmed to wake the system periodically and optionally issue an interrupt. This enables flexible, periodic wakeups from low power modes or coarse timing applications. Systems that require accurate timing should use the RTC capability instead of the central timewheel. The 100 kHz clock (CLK100K) works as a low-power system clock to run the CPU. It can also generate fast time intervals using the fast timewheel. The fast timewheel is a 100 kHz, 5-bit counter clocked by the ILO that can also be used to generate periodic interrupts. The fast timewheel settings are programmable, and the counter automatically resets when the terminal count is reached. This enables flexible, periodic interrupts to the CPU at a higher rate than is allowed using the central timewheel. The fast timewheel can generate an optional interrupt each time the terminal count is reached. The 33 kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy version of the 32.768 kHz ECO clock with no need for a crystal. The fast timewheel cannot be used as a wakeup source and must be turned off before entering sleep or hibernate mode. 6.1.2 External Oscillators 6.1.2.2 32.768 kHz ECO The 32.768 kHz external crystal oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768 kHz watch crystal (see Figure 6-3). The RTC uses a 1-second interrupt to implement the RTC functionality in firmware. The oscillator works in two distinct power modes. This allows you to trade off power consumption with noise immunity from neighboring circuits. The GPIO pins connected to the external crystal and capacitors are fixed. Figure 6-3. 32kHzECO Block Diagram 4 - 25 MHz Crystal Osc Xi XCLK_ MHZ Xo 6.1.2.1 MHz External Crystal Oscillator The MHzECO provides high frequency, high precision clocking using an external crystal (see Figure 6-2). It supports crystals in the range of 4 to 25 MHz. When used in conjunction with the PLL, it can generate CPU and system clocks up to the device's maximum frequency (see Phase-Locked Loop on page 19). The MHzECO with a 24 MHz crystal can be used with the clock doubler to generate a 48 MHz clock for the USB. If a crystal is not used then Xi must be shorted to ground and Xo must be left floating. MHzECO accuracy depends on the crystal chosen. Figure 6-2. MHzECO Block Diagram 4 - 25 MHz Crystal Osc XCLK_ MHZ External Components 4 – 25 MHz crystal Capacitors It is recommended that the external 32.768-kHz watch crystal have a load capacitance (CL) of 6 pF or 12.5 pF. Check the crystal manufacturer's datasheet. The two external capacitors, CL1 and CL2, are typically of the same value, and their total capacitance, CL1CL2 / (CL1 + CL2), including pin and trace capacitance, should equal the crystal CL value. For more information, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. See also pin capacitance specifications in the “GPIO” section on page 57. 6.1.2.3 Digital System Interconnect The DSI provides routing for clocks taken from external clock oscillators connected to I/O. The oscillators can also be generated within the device in the digital system and UDBs. Xi External Components Xo 4 – 25 MHz crystal While the primary DSI clock input provides access to all clocking resources, up to eight other DSI clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. This is only possible if there are multiple precision clock sources. Capacitors Document Number: 001-66236 Rev. *D Page 20 of 97 PSoC® 5: CY8C52 Family Datasheet 6.1.3 Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found with limited resolution prescalers attached to peripherals. The clock distribution system generates several types of clock trees. The system clock is used to select and supply the fastest clock in the system for general system clock requirements and clock synchronization of the PSoC device. Bus Clock 16-bit divider uses the system clock to generate the system’s bus clock used for data transfers and the CPU. The CPU clock is directly derived from the bus clock. Eight fully programmable 16-bit clock dividers generate digital system clocks for general use in the digital system, as configured by the design’s requirements. Digital system clocks can generate custom clocks derived from any of the seven clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, and many others. If more than eight digital clock dividers are required, the Universal Digital Blocks (UDBs) and fixed function timer/counter/PWMs can also generate clocks. Four 16-bit clock dividers generate clocks for the analog system components that require clocking, such as the ADC. The analog clock dividers include skew control to ensure that critical Document Number: 001-66236 Rev. *D analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise. Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50% duty cycle clocks, system clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock chaining of up to 32 bits. 6.1.4 USB Clock Domain The USB clock domain is unique in that it operates largely asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process USB data. The USB logic requires a 48 MHz frequency. This frequency is generated from the doubled value of 24 MHz from the MHzECO or DSI signal. 6.2 Power System The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and Vddiox, respectively. It also includes two internal 1.8 V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The output pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4 (10 µF is required for sleep mode. See Table 11-3). The two VCCD pins must be shorted together, with as short a trace as possible. The power system also contains a hibernate regulator. Page 21 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 6-4. PSoC Power System 1 µF Vddio2 6 Vddd Vddd I/O Supply Vssd Vccd Vddio2 Vddio0 0.1 µ F 0.1 µF I/ O Supply Vddio0 0.1 µF Digital Domain Vdda Vdda Vcca Analog Regulator Digital Regulators 0.1 µF 6 1 µF . Vssa Analog Domain 0.1 µF I/O Supply Vddio3 Vddd Vssd I/O Supply Vccd Vddio1 Hibernate Regulator 0.1 µ F 0.1 µ F Vddio1 Vddd Vddio3 Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-4. Note 6. 10 µF is required for sleep mode. See Table 11-3. Document Number: 001-66236 Rev. *D Page 22 of 97 PSoC® 5: CY8C52 Family Datasheet Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or disabled by using separate power configuration template registers. In alternate active mode, fewer subsystems are enabled, reducing power. In sleep mode most resources are disabled regardless of the template settings. Sleep mode is optimized to provide timed sleep intervals. The lowest power mode is hibernate, which retains register and SRAM state, but no clocks, and allows wakeup only from reset. Figure 6-5 on page 24 illustrates the allowable transitions between power modes. Sleep and hibernate modes should not be entered until all VDDIO supplies are at valid voltage levels and interrupts are enabled. 6.2.1 Power Modes PSoC 5 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low power and portable devices. PSoC 5 power modes, in order of decreasing power consumption are: Active Alternate Active Sleep Hibernate Table 6-2. Power Modes Power Modes Description Active Primary mode of operation, all peripherals available (programmable) Alternate Similar to Active mode, and is Active typically configured to have fewer peripherals active to reduce power. One possible configuration is to use the UDBs for processing, with the CPU turned off Sleep All subsystems automatically disabled Hibernate Entry Condition Wakeup Source Wakeup, reset, Any interrupt manual register entry Manual register Any interrupt entry Manual register entry CTW[8] Active Clocks Regulator Any (programAll regulators available. mable) Any (programmable) All regulators available. ILO All regulators available. Manual register All subsystems automatically entry disabled Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained Only hibernate regulator active. Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Modes Wakeup Time Current (Typ) Code Execution Digital Resources Analog Resources Clock Sources Available Wakeup Sources Reset Sources Active – 6 mA[7] Yes All All All – All Alternate Active – – User defined All All All – All 125 µs typ 2 µA[8] No None None ILO CTW XRES – 300 nA No None None None – XRES Sleep Hibernate Notes 7. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 54 8. During sleep mode, the CTW generates periodic interrupts to wake up the device. This affects the average current, which is a composite of the sleep mode current and active mode current, and the time spent in each mode. With the maximum wakeup interval of 128 ms, and at wakeup the CPU executes only the standard PSoC Creator sleep API (for a duty cycle of 0.2%), the average current draw is typically 35 µA. Document Number: 001-66236 Rev. *D Page 23 of 97 PSoC® 5: CY8C52 Family Datasheet 6.2.1.5 Wakeup Events Figure 6-5. Power Mode Transitions Wakeup events can come from the central timewheel or device reset. A wakeup event restores the system to active mode. The central timewheel allows the system to periodically wake up, poll peripherals, do voltage monitoring, or perform real-time functions. Reset event sources include the external reset pin (XRES). Active 6.3 Reset Manual Sleep Hibernate Alternate Active 6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or disabled. When a resource is disabled, the digital clocks are gated, analog bias currents are disabled, and leakage currents are reduced as appropriate. User firmware can dynamically control subsystem power by setting and clearing bits in the active configuration template. The CPU can disable itself, in which case the CPU is automatically reenabled at the next wakeup event. When a wakeup event occurs, the global mode is always returned to active, and the CPU is automatically enabled, regardless of its template settings. Active mode is the default global power mode upon boot. 6.2.1.2 Alternate Active Mode Alternate Active mode is very similar to Active mode. In alternate active mode, fewer subsystems are enabled, to reduce power consumption. One possible configuration is to turn off the CPU and flash, and run peripherals at full speed. 6.2.1.3 Sleep Mode Sleep mode powers down the CPU and other internal circuitry to reduce power consumption. However, supervisory services such as the central timewheel (CTW) remain available in this mode. The device can wake up using CTW or system reset. The wake up time from sleep mode is 125 µs (typical). CY8C52 has multiple internal and external reset sources available. The reset sources are: Power source monitoring: The analog and digital power voltages, VDDA, VDDD, VCCA, and VCCD are monitored in several different modes during power up and active mode. The monitors are programmable to generate an interrupt to the processor under certain conditions. External: The device can be reset from an external source by pulling the reset pin (XRES) low. The XRES pin includes an internal pull up to VDDIO1. VDDD, VDDA, and VDDIO1 must all have voltage applied before the part comes out of reset. Watchdog timer: A watchdog timer monitors the execution of instructions by the processor. If the watchdog timer is not reset by firmware within a certain period of time, the watchdog timer generates a reset. The watchdog timer can be used only when the part remains in active mode. Software: The device can be reset under program control. Figure 6-6. Resets Vddd Vdda Power Voltage Level Monitors Reset Pin External Reset Processor Interrupt Reset Controller System Reset Watchdog Timer Software Reset Register 6.2.1.4 Hibernate Mode In hibernate mode nearly all of the internal functions are disabled. Internal voltages are reduced to the minimal level to keep vital systems alive. Configuration state is preserved in hibernate mode and SRAM memory is retained. GPIOs configured as digital outputs maintain their previous values and external GPIO pin interrupt settings are preserved. The device can only return from hibernate mode in response to an external reset (XRES). Document Number: 001-66236 Rev. *D Page 24 of 97 PSoC® 5: CY8C52 Family Datasheet The term system reset indicates that the processor as well as analog and digital peripherals and registers are reset. A reset status register shows some of the resets or power voltage monitoring interrupts. The program may examine this register to detect and report certain exception conditions. This register is cleared after a power-on reset. For details see the Technical Reference Manual. 6.3.1 Power Voltage Level Monitors IPOR - Initial Power on Reset At initial power on, IPOR monitors the power voltages VDDD and VDDA, both directly at the pins and at the outputs of the corresponding internal regulators. The trip level is not precise. It is set to approximately 1 volt, which is below the lowest specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. The monitor generates a reset pulse that is at least 100 ns wide. It may be much wider if one or more of the voltages ramps up slowly. To save power the IPOR circuit is disabled when the internal digital supply is stable. When the voltage is high enough, the IMO starts. ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when VDDA and VDDD go outside a voltage range. For AHVI, VDDA is compared to a fixed trip level. For ALVI and DLVI, VDDA and VDDD are compared to trip levels that are programmable, as listed in Table 6-4. Table 6-4. Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt DLVI VDDD Normal Voltage Range 2.7 V-5.5 V ALVI VDDA 2.7 V-5.5 V AHVI VDDA 2.7 V-5.5 V Interrupt Supply Available Trip Settings 2.45 V-5.45 V in 250 mV increments. The 2.45 V setting is used for LVD. 2.45 V-5.45 V in 250 mV increments. The 2.45 V setting is used for LVD. 5.75 V The monitors are disabled until after IPOR. The monitors are not available in low-power modes. To monitor voltages in sleep mode, wake up periodically using the CTW. After wakeup, the 2.45 V LVI interrupt may trigger. Voltage monitoring is not available in hibernate mode. 6.3.2 Other Reset Sources XRES - External Reset CY8C52 has a dedicated XRES pin which holds the part in reset while held active (low). The response to an XRES is the same as to an IPOR reset. The external reset is active low. It includes an internal pull up resistor. XRES is active during sleep and hibernate modes. Document Number: 001-66236 Rev. *D SRES - Software Reset A reset can be commanded under program control by setting a bit in the software reset register. This is done either directly by the program or indirectly by DMA access. The response to a SRES is the same as after an IPOR reset. Another register bit exists to disable this function. WRES - Watchdog Timer Reset The watchdog reset detects when the software program is no longer being executed correctly. To indicate to the watchdog timer that it is running correctly, the program must periodically reset the timer. If the timer is not reset before a user-specified amount of time, then a reset is generated. Note IPOR disables the watchdog function. The program must enable the watchdog function at an appropriate point in the code by setting a register bit. When this bit is set, it cannot be cleared again except by an IPOR power on reset event. The watchdog timer can be used only when the part remains in active mode. 6.4 I/O System and Routing PSoC I/Os are extremely flexible. Every GPIO has analog and digital I/O capability. All I/Os have a large number of drive modes, which are set at POR. PSoC also provides up to four individual I/O voltage domains through the VDDIO pins. There are two types of I/O pins on every device; those with USB provide a third type. Both General Purpose I/O (GPIO) and Special I/O (SIO) provide similar digital functionality. The primary differences are their analog capability and drive strength. Devices that include USB also provide two USBIO pins that support specific USB functionality as well as limited GPIO capability. All I/O pins are available for use as digital inputs and outputs for both the CPU and digital peripherals. In addition, all I/O pins can generate an interrupt. The flexible and advanced capabilities of the PSoC I/O, combined with any signal to any pin routability, greatly simplify circuit design and board layout. All GPIO pins can be used for analog input, CapSense, and LCD segment drive, while SIO pins are used for voltages in excess of VDDA and for programmable output voltages. Features supported by both GPIO and SIO: Separate I/O supplies and voltages for up to four groups of I/O Digital peripherals use DSI to connect the pins Input or output or both for CPU and DMA Eight drive modes Every pin can be an interrupt source configured as rising edge, falling edge or both edges. If required, level sensitive interrupts are supported through the DSI Dedicated port interrupt vector for each port Slew rate controlled digital output drive mode Access port control and configuration registers on either port basis or pin basis Separate port read (PS) and write (DR) data registers to avoid read modify write errors Special functionality on a pin by pin basis Page 25 of 97 PSoC® 5: CY8C52 Family Datasheet Additional features only provided on the GPIO pins: LCD segment drive on LCD equipped devices CapSense on CapSense equipped devices Analog input and output capability Continuous 100 µA clamp current capability Standard drive strength down to 2.7 V Additional features only provided on SIO pins: Higher drive strength than GPIO Hot swap capability (5 V tolerance at any operating VDD) Programmable and regulated high input and output drive levels down to 1.2 V No analog input or LCD capability Document Number: 001-66236 Rev. *D Over voltage tolerance up to 5.5 V SIO can act as a general purpose analog comparator USBIO features: Full speed USB 2.0 I/O Highest drive strength for general purpose use Input, output, or both for CPU and DMA Input, output, or both for digital peripherals Digital output (CMOS) drive mode Each pin can be an interrupt source configured as rising edge, falling edge, or both edges Page 26 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 6-7. GPIO Block Diagram Digital Input Path Naming Convention ‘x’ = Port Number ‘y’ = Pin Number PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] Input Buffer Disable PICU[x]INTSTAT Interrupt Logic Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT Vddio Vddio PRT[x]DR 0 Digital System Output In 1 Vddio PRT[x]BYP Drive Logic PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Slew Cntl PIN OE 1 Capsense Global Control 0 1 0 1 CAPS[x]CFG1 Switches PRT[x]AG Analog Global PRT[x]AMUX Analog Mux LCD Display Data PRT[x]LCD_COM_SEG Logic & MUX PRT[x]LCD_EN LCD Bias Bus Document Number: 001-66236 Rev. *D 5 Page 27 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 6-8. SIO Input/Output Block Diagram Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN Naming Convention ‘x’ = Port Number ‘y’ = Pin Number Buffer Thresholds PRT[x]PS Digital System Input PICU[x]INTTYPE[y] Input Buffer Disable PICU[x]INTSTAT Interrupt Logic Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Driver Vhigh 0 Digital System Output In 1 PRT[x]BYP Drive Logic PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Slew Cntl PIN OE Figure 6-9. USBIO Block Diagram Digital Input Path Naming Convention ‘x’ = Port Number ‘y’ = Pin Number USB Receiver Circuitry PRT[x]DBL_SYNC_IN USBIO_CR1[0,1] Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Interrupt Logic Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SYNC_OUT D+ pin only USBIO_CR1[7] USB or I/O USB SIE Control for USB Mode USBIO_CR1[4,5] Digital System Output PRT[x]BYP Vddd 0 1 In Drive Logic Vddd 5k Vddd Vddd 1.5 k PIN USBIO_CR1[2] USBIO_CR1[3] USBIO_CR1[6] Document Number: 001-66236 Rev. *D D+ 1.5 k D+D- 5 k Open Drain Page 28 of 97 PSoC® 5: CY8C52 Family Datasheet 6.4.1 Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-5. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-10 depicts a simplified pin view based on each of the eight drive modes. Table 6-5 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For example, if a GPIO pin is configured for resistive pull up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state. Figure 6-10. Drive Mode Vddio DR PS 0. Pin High Impedance Analog DR PS Pin 1. High Impedance Digital DR PS Pin 2. Resistive Pull-Up Vddio DR PS Pin 4. Open Drain, Drives Low DR PS Vddio DR PS 3. Resistive Pull-Down Vddio Pin 5. Open Drain, Drives High DR PS Vddio Pin 6. Strong Drive Pin DR PS Pin 7. Resistive Pull-Up and Pull-Down Table 6-5. Drive Modes Diagram Drive Mode PRTxDM2 PRTxDM1 PRTxDM0 PRTxDR = 1 PRTxDR = 0 0 High impedence analog 0 0 0 High-Z High-Z 1 High Impedance digital 0 0 1 High-Z High-Z 2 Resistive pull-up[9] 0 1 0 Res High (5K) Strong Low 3 Resistive pull-down[9] 0 1 1 Strong High Res Low (5K) 4 Open drain, drives low 1 0 0 High-Z Strong Low 5 Open drain, drive high 1 0 1 Strong High High-Z 6 Strong drive 1 1 0 Strong High Strong Low 7 Resistive pull-up and pull-down[9] 1 1 1 Res High (5K) Res Low (5K) High Impedance Analog The default reset state with both the output driver and digital input buffer turned off. This prevents any current from flowing in the I/O’s digital input buffer due to a floating voltage. This state is recommended for pins that are floating or that support an analog voltage. High impedance analog pins do not provide digital input functionality. To achieve the lowest chip current in sleep modes, all I/Os must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the PSoC device or by external circuitry. High Impedance Digital The input buffer is enabled for digital signal input. This is the standard high impedance (HiZ) state recommended for digital inputs. Note 9. Resistive pull up and pull down are not available with SIO in regulated output mode. Document Number: 001-66236 Rev. *D Page 29 of 97 PSoC® 5: CY8C52 Family Datasheet Resistive Pull Up or Resistive Pull Down Resistive pull up or pull down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. Interfacing to mechanical switches is a common application for these modes. Resistive pull up and pull down are not available with SIO in regulated output mode. Open Drain, Drives High and Open Drain, Drives Low Open drain modes provide high impedance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. A common application for these modes is driving the I2C bus signal lines. Strong Drive Provides a strong CMOS output drive in either high or low state. This is the standard output mode for pins. Strong Drive mode pins must not be used as inputs under normal circumstances. This mode is often used to drive digital output signals or external FETs. Resistive Pull Up and Pull Down Similar to the resistive pull up and resistive pull down modes except the pin is always in series with a resistor. The high data state is pull up while the low data state is pull down. This mode is most often used when other signals that may cause shorts can drive the bus. Resistive pull up and pull down are not available with SIO in regulated output mode. 6.4.2 Pin Registers Registers to configure and interact with pins come in two forms that may be used interchangeably. All I/O registers are available in the standard port form, where each bit of the register corresponds to one of the port pins. This register form is efficient for quickly reconfiguring multiple port pins at the same time. I/O registers are also available in pin form, which combines the eight most commonly used port register bits into a single register for each pin. This enables very fast configuration changes to individual pins with a single register write. 6.4.3 Bidirectional Mode High speed bidirectional capability allows pins to provide both the high impedance digital drive mode for input signals and a second user selected drive mode such as strong drive (set using PRTxDM[2:0] registers) for output signals on the same pin, based on the state of an auxiliary control bus signal. The bidirectional capability is useful for processor busses and communications interfaces such as the SPI Slave MISO pin that requires dynamic hardware control of the output buffer. The auxiliary control bus routes up to 16 UDB or digital peripheral generated output enable signals to one or more pins. and 33 MHz. The slew rate is individually configurable for each pin, and is set by the PRTxSLW registers. 6.4.5 Pin Interrupts All GPIO and SIO pins are able to generate interrupts to the system. All eight pins in each port interface to their own port interrupt control unit (PICU) and associated interrupt vector. Each pin of the port is independently configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an interrupt. Depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the interrupt status register is set to “1” and an interrupt request is sent to the interrupt controller. Each PICU has its own interrupt vector in the interrupt controller and the pin status register providing easy determination of the interrupt source down to the pin level. While level sensitive interrupts are not directly supported; UDBs provide this functionality to the system when needed. 6.4.6 Input Buffer Mode GPIO and SIO input buffers can be configured at the port level for the default CMOS input thresholds or the optional LVTTL input thresholds. All input buffers incorporate Schmitt triggers for input hysteresis. Additionally, individual pin input buffers can be disabled in any drive mode. 6.4.7 I/O Power Supplies Up to four I/O pin power supplies are provided depending on the device and package. Each I/O supply must be less than or equal to the voltage on the chip’s analog (VDDA) pin. This feature allows you to provide different I/O voltage levels for different pins on the device. Refer to the specific device package pinout to determine VDDIO capability for a given port and pin. The SIO port pins support an additional regulated high output capability, as described in Adjustable Output Level. 6.4.8 Analog Connections These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs. Each GPIO may connect to one of the analog global busses or to one of the analog mux buses to connect any pin to any internal analog resource such as ADC or comparators. In addition, one select pin provides direct connection to the high current DAC. 6.4.9 CapSense This section applies only to GPIO pins. All GPIO pins may be used to create CapSense buttons and sliders. See the “CapSense” section on page 48 for more information. 6.4.4 Slew Rate Limited Mode 6.4.10 LCD Segment Drive GPIO and SIO pins have fast and slow output slew rate options for strong and open drain drive modes, not resistive drive modes. Because it results in reduced EMI, the slow edge rate option is recommended for signals that are not speed critical, generally less than 1 MHz. The fast slew rate is for signals between 1 MHz This section applies only to GPIO pins. All GPIO pins may be used to generate Segment and Common drive signals for direct glass drive of LCD glass. See the “LCD Direct Drive” section on page 47 for details. Document Number: 001-66236 Rev. *D Page 30 of 97 PSoC® 5: CY8C52 Family Datasheet 6.4.11 Adjustable Output Level 6.4.13 SIO as Comparator This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO’s respective VDDIO. SIO pins are individually configurable to output either the standard VDDIO level or the regulated output, which is based on an internally generated reference. Typically the voltage DAC (VDAC) is used to generate the reference (see Figure 6-11). The DAC on page 48 has more details on VDAC use and reference routing to the SIO pins. Resistive pull up and pull down drive modes are not available with SIO in regulated output mode. This section applies only to SIO pins. The adjustable input level feature of the SIOs as explained in the Adjustable Input Level section can be used to construct a comparator. The threshold for the comparator is provided by the SIO's reference generator. The reference generator has the option to set the analog signal routed through the analog global line as threshold for the comparator. Note that a pair of SIO pins share the same threshold. 6.4.12 Adjustable Input Level This section applies only to SIO pins. SIO pins by default support the standard CMOS and LVTTL input levels but also support a differential mode with programmable levels. SIO pins are grouped into pairs. Each pair shares a reference generator block which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from VDDIO. The reference sets the pins voltage threshold for a high logic level (see Figure 6-11). Available input thresholds are: 0.5 VDDIO 0.4 VDDIO The digital input path in Figure 6-8 on page 28 illustrates this functionality. In the figure, ‘Reference level’ is the analog signal routed through the analog global. The hysteresis feature can also be enabled for the input buffer of the SIO, which increases noise immunity for the comparator. 6.4.14 Hot Swap This section applies only to SIO pins. SIO pins support ‘hot swap’ capability to plug into an application without loading the signals that are connected to the SIO pins even when no power is applied to the PSoC device. This allows the unpowered PSoC to maintain a high impedance load to the external device while also preventing the PSoC from being powered through a GPIO pin’s protection diode. 6.4.15 Over Voltage Tolerance 0.5 VREF All I/O pins provide an over voltage (VDDIO < VIN < VDDA) tolerance feature at any operating VDD. VREF Typically the voltage DAC (VDAC) generates the VREF reference. The DAC on page 48 has more details on VDAC use and reference routing to the SIO pins. Figure 6-11. SIO Reference for Input and Output There are no current limitations for the SIO pins as they present a high impedance load to the external circuit. The GPIO pins must be limited to 100 µA using a current limiting resistor. GPIO pins clamp the pin voltage to approximately one diode above the VDDIO supply. Input Path In case of a GPIO pin configured for analog input/output, the analog voltage on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs. Digital Input Vinref Reference Generator SIO_Ref Voutref Output Path Driver Vhigh PIN A common application for this feature is connection to a bus such as I2C where different devices are running from different supply voltages. In the I2C case, the PSoC chip is configured into the Open Drain, Drives Low mode for the SIO pin. This allows an external pull up to pull the I2C bus voltage above the PSoC pin supply. For example, the PSoC chip could operate at 2.7 V, and an external device could run from 5 V. Note that the SIO pin’s VIH and VIL levels are determined by the associated VDDIO supply pin. The I/O pin must be configured into a high impedance drive mode, open drain low drive mode, or pull down drive mode, for over voltage tolerance to work properly. Absolute maximum ratings for the device must be observed for all I/O pins. 6.4.16 Reset Configuration Digital Output At reset, all I/Os are reset to the High Impedance Analog state. Drive Logic 6.4.17 Low Power Functionality In all low power modes the I/O pins retain their state until the part is awakened and changed or reset. Document Number: 001-66236 Rev. *D Page 31 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 7-1. CY8C52 Digital Programmable Architecture Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in “Pinouts” on page 5. The special features are: 32.768 kHz crystal oscillator SWD and SWV interface pins External reset DSI Routing Interface UDB Array Analog High current IDAC output External reference inputs IO Port 7. Digital Subsystem The digital programmable system creates application specific combinations of both standard and advanced digital peripherals and custom logic functions. These peripherals and logic are then interconnected to each other and to any pin on the device, providing a high level of design flexibility and IP security. The features of the digital programmable system are outlined here to provide an overview of capabilities and architecture. Designers do not need to interact directly with the programmable digital system at the hardware and register level. PSoC Creator provides a high level schematic capture graphical interface to automatically place and route resources similar to PLDs. The main components of the digital programmable system are: Universal digital blocks (UDB) - These form the core functionality of the digital programmable system. UDBs are a collection of uncommitted logic (PLD) and structural logic (Datapath) optimized to create all common embedded peripherals and customized functionality that are application or design specific. Universal digital block array - UDB blocks are arrayed within a matrix of programmable interconnect. The UDB array structure is homogeneous and allows for flexible mapping of digital functions onto the array. The array supports extensive and flexible routing interconnects between UDBs and the digital system interconnect. Digital system interconnect (DSI) - Digital signals from UDBs, fixed function peripherals, I/O pins, interrupts, DMA, and other system core signals are attached to the DSI to implement full featured device connectivity. The DSI allows any digital function to any pin or other feature routability when used with the UDB array. Document Number: 001-66236 Rev. *D UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB DSI Routing Interface IO Port Digital IO Port IO Port Digital Core System and Fixed Function Peripherals UDB Array 6.4.18 Special Pin Functionality Digital Core System and Fixed Function Peripherals 7.1 Example Peripherals The flexibility of the CY8C52 family’s UDBs and analog blocks allow you to create a wide range of components (peripherals). The most common peripherals were built and characterized by Cypress and are shown in the PSoC Creator component catalog. However, you may also create your own custom components using PSoC Creator. Using PSoC Creator, you may also create their own components for reuse within their organization, for example sensor interfaces, proprietary algorithms, and display interfaces. The number of components available through PSoC Creator is too numerous to list in the data sheet, and the list is always growing. An example of a component available for use in CY8C52 family, but, not explicitly called out in this data sheet is the UART component. 7.1.1 Example Digital Components The following is a sample of the digital components available in PSoC Creator for the CY8C52 family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. Communications I2C (1 to 3 UDBs) UART (1 to 3 UDBs) Functions PWM (1 to 2 UDBs) Logic (x CPLD product terms per logic function) NOT OR XOR AND Page 32 of 97 PSoC® 5: CY8C52 Family Datasheet 7.1.2 Example Analog Components PSoC Creator is that design tool. The following is a sample of the analog components available in PSoC Creator for the CY8C52 family. The exact amount of hardware resources (SC/CT blocks, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. PSoC Creator is a full featured Integrated Development Environment (IDE) for hardware and software design. It is optimized specifically for PSoC devices and combines a modern, powerful software development platform with a sophisticated graphical design tool. This unique combination of tools makes PSoC Creator the most flexible embedded design platform available. ADC Successive Approximation (SAR ADC) DACs Current Voltage PWM Comparators 7.1.3 Example System Function Components The following is a sample of the system function components available in PSoC Creator for the CY8C52 family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. CapSense LCD drive LCD control Filters 7.1.4 Designing with PSoC Creator 7.1.4.1 More Than a Typical IDE Graphical design entry simplifies the task of configuring a particular part. You can select the required functionality from an extensive catalog of components and place it in your design. All components are parameterized and have an editor dialog that allows you to tailor functionality to your needs. PSoC Creator automatically configures clocks and routes the I/O to the selected pins and then generates APIs to give the application complete control over the hardware. Changing the PSoC device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. At any stage of development you are free to change the hardware configuration and even the target processor. To retarget your application (hardware and software) to new devices, even from 8- to 32-bit families, just select the new device and rebuild. You also have the ability to change the C compiler and evaluate an alternative. Components are designed for portability and are validated against all devices, from all families, and against all supported tool chains. Switching compilers is as easy as editing from the project options and rebuilding the application with no errors from the generated APIs or boot code. A successful design tool allows for the rapid development and deployment of both simple and complex designs. It reduces or eliminates any learning curve. It makes the integration of a new design into the production stream straightforward. Document Number: 001-66236 Rev. *D Page 33 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 7-2. PSoC Creator Framework Document Number: 001-66236 Rev. *D Page 34 of 97 PSoC® 5: CY8C52 Family Datasheet 7.1.4.2 Component Catalog 7.1.4.4 Software Development Figure 7-3. Component Catalog Figure 7-4. Code Editor Anchoring the tool is a modern, highly customizable user interface. It includes project management and integrated editors for C and assembler source code, as well the design entry tools. The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device. It is populated with an impressive selection of content; from simple primitives such as logic gates and device registers, through the digital timers, counters and PWMs, plus analog components such as ADC and DAC, and communication protocols such as I2C and USB. See “Example Peripherals” section on page 32 for more details about available peripherals. All content is fully characterized and carefully documented in data sheets with code examples, AC/DC specifications, and user code ready APIs. Project build control leverages compiler technology from top commercial vendors such as ARM® Limited, Keil™, and CodeSourcery (GNU). Free versions of Keil C51 and GNU C Compiler (GCC) for ARM, with no restrictions on code size or end product distribution, are included with the tool distribution. Upgrading to more optimizing compilers is a snap with support for the professional Keil C51 product and ARM RealView™ compiler. 7.1.4.5 Nonintrusive Debugging Figure 7-5. PSoC Creator Debugger 7.1.4.3 Design Reuse The symbol editor gives you the ability to develop reusable components that can significantly reduce future design time. Just draw a symbol and associate that symbol with your proven design. PSoC Creator allows for the placement of the new symbol anywhere in the component catalog along with the content provided by Cypress. You can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit the details of the implementation. With SWD debug connectivity available on all devices, the PSoC Creator debugger offers full control over the target device with minimum intrusion. Breakpoints and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows—register, locals, watch, call stack, memory and peripherals – make for an unparalleled level of visibility into the system. Document Number: 001-66236 Rev. *D Page 35 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 7-6. UDB Block Diagram PLD Chaining Clock and Reset Control PLD 12C4 (8 PTs) PLD 12C4 (8 PTs) Status and Control Datapath Datapath Chaining Routing Channel The main component blocks of the UDB are: PLD blocks: There are two small PLDs per UDB. These blocks take inputs from the routing array and form registered or combinational sum-of-products logic. PLDs are used to implement state machines, state bits, and combinational logic equations. PLD configuration is automatically generated from graphical primitives. Datapath module: This 8-bit wide datapath contains structured logic to implement a dynamically configurable ALU, a variety of compare configurations and condition generation. This block also contains input/output FIFOs, which are the primary parallel data interface between the CPU/DMA system and the UDB. Status and control module: The primary role of this block is to provide a way for CPU firmware to interact and synchronize with UDB operation. Clock and reset module: This block provides the UDB clocks and reset selection and control. Document Number: 001-66236 Rev. *D PT4 PT5 PT6 PT7 To achieve this, UDBs consist of a combination of uncommitted logic (PLD), structured logic (datapath), and a flexible routing scheme to provide interconnect between these elements, I/O connections, and other peripherals. UDB functionality ranges from simple self contained functions that are implemented in one UDB, or even a portion of a UDB (unused resources are available for other functions), to more complex functions that require multiple UDBs. Examples of basic functions are timers, counters, CRC generators, PWMs, dead band generators, and communications functions, such as UARTs, SPI, and I2C. Also, the PLD blocks and connectivity provide full featured general purpose programmable logic within the limits of the available resources. PT3 Figure 7-7. PLD 12C4 Structure PT2 The universal digital block (UDB) represents an evolutionary step to the next generation of PSoC embedded digital peripheral functionality. The architecture in first generation PSoC digital blocks provides coarse programmability in which a few fixed functions with a small number of options are available. The new UDB architecture is the optimal balance between configuration granularity and efficient implementation. A cornerstone of this approach is to provide the ability to customize the devices digital operation to match application requirements. The primary purpose of the PLD blocks is to implement logic expressions, state machines, sequencers, look up tables, and decoders. In the simplest use model, consider the PLD blocks as a standalone resource onto which general purpose RTL is synthesized and mapped. The more common and efficient use model is to create digital functions from a combination of PLD and datapath blocks, where the PLD implements only the random logic and state portion of the function while the datapath (ALU) implements the more structured elements. PT1 7.2 Universal Digital Block 7.2.1 PLD Module PT0 PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. IN0 TC TC TC TC TC TC TC TC IN1 TC TC TC TC TC TC TC TC IN2 TC TC TC TC TC TC TC TC IN3 TC TC TC TC TC TC TC TC IN4 TC TC TC TC TC TC TC TC IN5 TC TC TC TC TC TC TC TC IN6 TC TC TC TC TC TC TC TC IN7 TC TC TC TC TC TC TC TC IN8 TC TC TC TC TC TC TC TC IN9 TC TC TC TC TC TC TC TC IN10 TC TC TC TC TC TC TC TC IN11 TC TC TC TC TC TC TC TC AND Array SELIN (carry in) OUT0 MC0 T T T T T T T T OUT1 MC1 T T T T T T T T OUT2 MC2 T T T T T T T T OUT3 MC3 T T T T T T T T SELOUT (carry out) OR Array One 12C4 PLD block is shown in Figure 7-7. This PLD has 12 inputs, which feed across eight product terms. Each product term (AND function) can be from 1 to 12 inputs wide, and in a given product term, the true (T) or complement (C) of each input can be selected. The product terms are summed (OR function) to create the PLD outputs. A sum can be from 1 to 8 product terms wide. The 'C' in 12C4 indicates that the width of the OR gate (in this case 8) is constant across all outputs (rather than variable as in a 22V10 device). This PLA like structure gives maximum flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. There are two 12C4 PLDs in each UDB. 7.2.2 Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators and many others. Page 36 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 7-8. Datapath Top Level PHUB System Bus R/W Access to All Registers F1 F0 A0 A1 D0 D1 D1 Data Registers D0 To/From Previous Datapath A1 Conditions: 2 Compares, 2 Zero Detect, 2 Ones Detect Overflow Detect 6 Datapath Control Input from Programmable Routing Input Muxes Control Store RAM 8 Word X 16 Bit FIFOs Chaining Output Muxes 6 Output to Programmable Routing To/From Next Datapath Accumulators A0 PI Parallel Input/Output (To/From Programmable Routing) PO ALU Shift Mask 7.2.2.6 Working Registers The datapath contains six primary working registers, which are accessed by CPU firmware or DMA during normal operation. Table 7-1. Working Datapath Registers Name Function A0 and A1 Accumulators Description These are sources and sinks for the ALU and also sources for the compares. D0 and D1 Data Registers These are sources for the ALU and sources for the compares. F0 and F1 FIFOs These are the primary interface to the system bus. They can be a data source for the data registers and accumulators or they can capture data from the accumulators or ALU. Each FIFO is four bytes deep. UDB routing matrix, most typically PLD logic, I/O pins, or from the outputs of this or other datapath blocks. ALU The ALU performs eight general purpose functions. They are: Increment Decrement Add Subtract Logical AND Logical OR Logical XOR Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Independent of the ALU operation, these functions are available: 7.2.2.7 Dynamic Datapath Configuration RAM Shift left Dynamic configuration is the ability to change the datapath function and internal configuration on a cycle-by-cycle basis, under sequencer control. This is implemented using the 8-word × 16-bit configuration RAM, which stores eight unique 16-bit wide configurations. The address input to this RAM controls the sequence, and can be routed from any block connected to the Shift right Document Number: 001-66236 Rev. *D Nibble swap Bitwise OR mask Page 37 of 97 PSoC® 5: CY8C52 Family Datasheet 7.2.2.8 Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These conditions are the primary datapath outputs, a selection of which can be driven out to the UDB routing matrix. Conditional computation can use the built in chaining to neighboring UDBs to operate on wider data widths without the need to use routing resources. 7.2.2.9 Variable MSB The most significant bit of an arithmetic and shift function can be programmatically specified. This supports variable width CRC and PRS functions, and in conjunction with ALU output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.2.10 Built in CRC/PRS The datapath has built in support for single cycle Cyclic Redundancy Check (CRC) computation and Pseudo Random Sequence (PRS) generation of arbitrary width and arbitrary polynomial. CRC/PRS functions longer than 8 bits may be implemented in conjunction with PLD logic, or built in chaining may be use to extend the function into neighboring UDBs. shared with two sets of registers and condition generators. Carry and shift out data from the ALU are registered and can be selected as inputs in subsequent cycles. This provides support for 16-bit functions in one (8-bit) datapath. 7.2.2.14 Datapath I/O There are six inputs and six outputs that connect the datapath to the routing matrix. Inputs from the routing provide the configuration for the datapath operation to perform in each cycle, and the serial data inputs. Inputs can be routed from other UDB blocks, other device peripherals, device I/O pins, and so on. The outputs to the routing can be selected from the generated conditions, and the serial data outputs. Outputs can be routed to other UDB blocks, device peripherals, interrupt and DMA controller, I/O pins, and so on. 7.2.3 Status and Control Module The primary purpose of this circuitry is to coordinate CPU firmware interaction with internal UDB operation. Figure 7-10. Status and Control Registers System Bus 8-bit Status Register (Read Only) 7.2.2.11 Input/Output FIFOs Each datapath contains two four-byte deep FIFOs, which can be independently configured as an input buffer (system bus writes to the FIFO, datapath internal reads the FIFO), or an output buffer (datapath internal writes to the FIFO, the system bus reads from the FIFO). The FIFOs generate status that are selectable as datapath outputs and can therefore be driven to the routing, to interact with sequencers, interrupts, or DMA. Figure 7-9. Example FIFO Configurations System Bus System Bus F0 F0 F1 D0/D1 A0/A1/ALU A0/A1/ALU A0/A1/ALU D0 A0 D1 A1 F1 F0 F1 System Bus System Bus TX/RX Dual Capture Dual Buffer 8-bit Control Register (Write/Read) Routing Channel The bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of UDB processing. The status register is read-only and it allows internal UDB state to be read out onto the system bus directly from internal routing. This allows firmware to monitor the state of UDB processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are made depending on the requirements of the application. 7.2.3.15 Usage Examples As an example of control input, a bit in the control register can be allocated as a function enable bit. There are multiple ways to enable a function. In one method the control bit output would be routed to the clock control block in one or more UDBs and serve as a clock enable for the selected UDB blocks. A status example is a case where a PLD or datapath block generated a condition, such as a “compare true” condition that is captured and latched by the status register and then read (and cleared) by CPU firmware. 7.2.3.16 Clock Generation 7.2.2.12 Chaining The datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to create higher precision arithmetic, shift, CRC/PRS functions. 7.2.2.13 Time Multiplexing Each subcomponent block of a UDB including the two PLDs, the datapath, and Status and Control, has a clock selection and control block. This promotes a fine granularity with respect to allocating clocking resources to UDB component blocks and allows unused UDB resources to be used by other functions for maximum system efficiency. In applications that are over sampled, or do not need high clock rates, the single ALU block in the datapath can be efficiently Document Number: 001-66236 Rev. *D Page 38 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 7-11 shows an example of a 16 UDB array. In addition to the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The UDB array includes multiple horizontal and vertical routing channels each comprised of 96 wires. The wire connections to UDBs, at horizontal/vertical intersection and at the DSI interface are highly permutable providing efficient automatic routing in PSoC Creator. Additionally the routing allows wire by wire segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. Figure 7-11. Digital System Interface Structure System Connections utilize the unused PLD blocks in the 8-bit timer UDB. Programmable resources in the UDB array are generally homogeneous so functions can be mapped to arbitrary boundaries in the array. Figure 7-12. Function Mapping Example in a Bank of UDBs 8-B it Tim er Q uadrature D ecoder UDB UDB HV A HV A UDB UDB UDB UDB HV A HV B UDB 8-B it Tim er Logic UDB 12-B it S P I UDB UDB UDB HV A HV B UDB 16-B it P Y R S 8-B it SP I I2C S lave HV B 16-B it PW M HV B UDB UDB UDB HV B Sequencer 7.3 UDB Array Description HV A HV B HV A UDB Logic HV A HV B HV A HV B UDB UDB UART UDB UDB UDB UDB UDB UDB UDB UDB HV B UDB HV A UDB HV A HV B UDB HV B UDB HV B System Connections 7.3.1 UDB Array Programmable Resources Figure 7-12 shows an example of how functions are mapped into a bank of 16 UDBs. The primary programmable resources of the UDB are two PLDs, one datapath and one status/control register. These resources are allocated independently, because they have independently selectable clocks, and therefore unused blocks are allocated to other unrelated functions. An example of this is the 8-bit timer in the upper left corner of the array. This function only requires one datapath in the UDB, and therefore the PLD resources may be allocated to another function. A function such as a Quadrature Decoder may require more PLD logic than one UDB can supply and in this case can Document Number: 001-66236 Rev. *D UDB 7.4 DSI Routing Interface Description HV A HV A UDB 12-B it P W M The DSI routing interface is a continuation of the horizontal and vertical routing channels at the top and bottom of the UDB array core. It provides general purpose programmable routing between device peripherals, including UDBs, I/Os, analog peripherals, interrupts, DMA and fixed function peripherals. Figure 7-13 illustrates the concept of the digital system interconnect, which connects the UDB array routing matrix with other device peripherals. Any digital core or fixed function peripheral that needs programmable routing is connected to this interface. Signals in this category include: Interrupt requests from all digital peripherals in the system. DMA requests from all digital peripherals in the system. Digital peripheral data signals that need flexible routing to I/Os. Digital peripheral data signals that need connections to UDBs. Connections to the interrupt and DMA controllers. Connection to I/O pins. Connection to analog system digital signals. Page 39 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 7-13. Digital System Interconnect Timer Counters Interrupt Controller I2C DMA Controller IO Port Pins Global Clocks single synchronized (pipelined) and a data input signal has the option to be double synchronized. The synchronization clock is the system clock (see Figure 6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational PLD logic from input pins to output pins. Figure 7-15. I/O Pin Synchronization Routing Digital System Routing I/F DO UDB ARRAY DI Digital System Routing I/F Figure 7-16. I/O Pin Output Connectivity 8 IO Data Output Connections from the UDB Array Digital System Interface Global Clocks IO Port Pins Del-Sig SC/CT Blocks DACs Comparators Interrupt and DMA routing is very flexible in the CY8C52 programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. Figure 7-14 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). DO PIN 0 DO PIN1 DO PIN2 DO PIN3 DO PIN4 DO PIN5 DO PIN6 DO PIN7 Port i Figure 7-14. Interrupt and DMA Processing in the IDMUX Interrupt and DMA Processing in IDMUX Fixed Function IRQs 0 1 IRQs UDB Array 2 Edge Detect Interrupt Controller There are four more DSI connections to a given I/O port to implement dynamic output enable control of pins. This connectivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. The output enable signal is useful for creating tristate bidirectional pins and buses. Figure 7-17. I/O Pin Output Enable Connectivity 3 DRQs DMA termout (IRQs) 4 IO Control Signal Connections from UDB Array Digital System Interface 0 Fixed Function DRQs 1 Edge Detect DMA Controller 2 7.4.1 I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary connections available, an input and an output. In conjunction with drive strength control, this can implement a bidirectional I/O pin. A data output signal has the option to be Document Number: 001-66236 Rev. *D OE PIN 0 OE PIN1 OE PIN2 OE PIN3 OE PIN4 OE PIN5 OE PIN6 OE PIN7 Port i Page 40 of 97 PSoC® 5: CY8C52 Family Datasheet 7.5 USB 7.6 Timers, Counters, and PWMs PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, and isochronous. PSoC Creator provides full configuration support. USB interfaces to hosts through two dedicated USBIO pins, which are detailed in the “I/O System and Routing” section on page 25. The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been included on this PSoC device family. Additional and more advanced functionality timers, counters, and PWMs can also be instantiated in Universal Digital Blocks (UDBs) as required. PSoC Creator allows designers to choose the timer, counter, and PWM features that they require. The tool set utilizes the most optimal resources available. When using USB, either a crystal must be used (24 MHz with MHzECO) or a similar high-accuracy clock source must be provided externally through a pin and the DSI. Also, bus clock must be equal to 33 MHz. See Section 6.1 on page 18 for details. USB includes the following features: Eight unidirectional data endpoints One bidirectional control endpoint 0 (EP0) Shared 512-byte buffer for the eight data endpoints Dedicated 8-byte buffer for EP0 Two memory modes Manual Memory Management with No DMA Access Manual Memory Management with Manual DMA Access The Timer/Counter/PWM peripheral can select from multiple clock sources, with input and output signals connected through the DSI routing. DSI routing allows input and output connections to any device pin and any internal digital signal accessible through the DSI. Each of the four instances has a compare output and terminal count output (optional complementary compare output). The Timer/Counter/PWMs are configurable as free running, one shot, or Enable input controlled. The peripheral has timer reset and capture inputs, and a kill input for control of the comparator outputs. The peripheral supports full 16-bit capture. Timer/Counter/PWM features include: Internal 3.3 V regulator for transceiver Interrupts on bus and each endpoint event USB Reset, Suspend, and Resume operations 16-bit timer/counter/PWM (down count only) Selectable clock source PWM comparator (configurable for LT, LTE, EQ, GTE, GT) Bus powered and self powered modes Period reload on start, reset, and terminal count Figure 7-18. USB Dynamic counter reads System Bus Arbiter 512 X 8 SRAM Timer capture mode D+ SI E (Serial Interface Engine) External 22 Resistors USB I/O Interrupts 48 MHz Count while enable signal is asserted mode Free run mode One Shot mode (stop at end of period) D– Complementary PWM outputs with deadband PWM output kill Figure 7-19. Timer/Counter/PWM Clock Reset Enable Capture Kill Document Number: 001-66236 Rev. *D Timer / Counter / PWM 16-bit TC / Compare! Compare Page 41 of 97 PSoC® 5: CY8C52 Family Datasheet 7.7 I2C I2C features include: The I2C peripheral provides a synchronous two wire interface designed to interface the PSoC device with a two wire I2C serial communication bus. The bus is compliant with Philips ‘The I2C Specification’ version 2.1. Additional I2C interfaces can be instantiated using Universal Digital Blocks (UDBs) in PSoC Creator, as required. Slave and master, transmitter, and receiver operation To eliminate the need for excessive CPU intervention and overhead, I2C specific support is provided for status detection and generation of framing bits. I2C operates as a slave, a master, or multimaster (Slave and Master)[10]. In slave mode, the unit always listens for a start condition to begin sending or receiving data. Master mode supplies the ability to generate the Start and Stop conditions and initiate transactions. Multimaster mode provides clock synchronization and arbitration to allow multiple masters on the same bus. If Master mode is enabled and Slave mode is not enabled, the block does not generate interrupts on externally generated Start conditions. I2C interfaces through the DSI routing and allows direct connections to any GPIO or SIO pins. 7 or 10-bit addressing (10-bit addressing requires firmware Byte processing for low CPU overhead Interrupt or polling CPU interface Support for bus speeds up to 400 Kbps support) SMBus operation (through firmware support - SMBus supported in hardware in UDBs) Data transfers follow the format shown in Figure 7-20. After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a 'zero' indicates a transmission (WRITE), a 'one' indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer. Figure 7-20. I2C Complete Transfer Timing SDA 1-7 SCL START Condition ADDRESS 8 9 R/W ACK 1-7 8 DATA 9 ACK 1-7 8 DATA 9 ACK STOP Condition Note 10. Fixed-block I2C does not support undefined bus conditions. These conditions should be avoided, or the UDB-based I2C component should be used instead. Document Number: 001-66236 Rev. *D Page 42 of 97 PSoC® 5: CY8C52 Family Datasheet Successive approximation (SAR) ADC 8. Analog Subsystem The analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. These blocks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and IP security. The features of the analog subsystem are outlined here to provide an overview of capabilities and architecture. One 8-bit DAC that provides either voltage or current output Two comparators with optional connection to configurable LUT outputs CapSense subsystem to enable capacitive touch sensing Precision reference for generating an accurate analog voltage for internal analog blocks Flexible, configurable analog routing architecture provided by analog globals, analog mux bus, and analog local buses Figure 8-1. Analog Subsystem Block Diagram SAR ADC A N A L O G Precision Reference DAC A N A L O G GPIO Port R O U T I N G CMP CapSense Subsystem Analog Interface DSI Array Document Number: 001-66236 Rev. *D R O U T I N G Comparators CMP Clock Distribution Config & Status Registers GPIO Port PHUB CPU Decimator Page 43 of 97 PSoC® 5: CY8C52 Family Datasheet The PSoC Creator software program provides a user-friendly interface to configure the analog connections between the GPIO and various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to configure the various analog blocks to perform application specific functions. The tool also generates API interface libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory. 8.1 Analog Routing The PSoC 5 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong points of this flexible routing architecture is that it allows dynamic routing of input and output connections to the different analog blocks. All analog routing switches are open when the device is in sleep or hibernate mode. For information on how to make pin selections for optimal analog routing, refer to the application note, AN58304 - PSoC® 3 and PSoC® 5 - Pin Selection for Analog Designs. Document Number: 001-66236 Rev. *D 8.1.1 Features Flexible, configurable analog routing architecture 16 Analog globals (AG) and two analog mux buses (AMUXBUS) to connect GPIOs and the analog blocks Each GPIO is connected to one analog global and one analog mux bus 8 Analog local buses (abus) to route signals between the different analog blocks Multiplexers and switches for input and output selection of the analog blocks 8.1.2 Functional Description Analog globals (AGs) and analog mux buses (AMUXBUS) provide analog connectivity between GPIOs and the various analog blocks. There are 16 AGs in the PSoC 5 family. The analog routing architecture is divided into four quadrants as shown in Figure 8-2. Each quadrant has four analog globals (AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is connected to the corresponding AG through an analog switch. The analog mux bus is a shared routing resource that connects to every GPIO through an analog switch. There are two AMUXBUS routes in PSoC 5, one in the left half (AMUXBUSL) and one in the right half (AMUXBUSR), as shown in Figure 8-2. Page 44 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 8-2. CY8C52 Analog Interconnect * * * * * * AGR[6] AGR[7] * * AGL[7] AGL[6] AGL[7] * AGR[4] AGR[5] AGL[4] AGL[5] AGL[6] AGL[4] AGL[5] * * * * Vio3 GPIO P3[6] GPIO P3[7] SIO P12[0] SIO P12[1] GPIO P15[2] GPIO P15[3] AMUXBUSL Upper Right Quadrant * Vssd Vssio Vio0 SIO P12[2] SIO P12[3] GPIO P4[0] GPIO P4[1] GPIO P0[0] GPIO P0[1] GPIO P0[2] GPIO P0[3] AMUXBUSR AMUXBUSL ExVrefL SAR0ref 44 0123 GPIO P3[5] GPIO P3[4] GPIO P3[3] GPIO P3[2] GPIO P3[1] GPIO P3[0] 3210 76543210 * GPIO P0[4] GPIO P0[5] GPIO P0[6] GPIO P0[7] Vcca Vsab Vssa Vdda Vdab Upper Left Quadrant * out1 comp0 COMPARATOR cmp0_vref (1.024V) GPXT 90 cmp_muxvn[1:0] *MHz Xi cmp1_vref bg_vda_swabusl0 CAPSENSE out ref in refbufl refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) refsel[1:0] out ref refbufr in GPXT *MHz Xo refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) refsel[1:0] Vssa vssa AGR[4] AMUXBUSR Vdda Vdda/2 AGR[7] AGR[6] AGR[5] vref_cmp1 (0.256V) bg_vda_res_en ExVrefR comp1 + - cmp1_vref cmp1_vref + - swout swin refbufr_ cmp in1 5 Vccd Vssio * * * * P15[7] VIDAC SAR ADC SAR0ref 01 23456 7 0123 3210 76543210 AGR[3] AGR[2] AGR[1] VBE Vss ref AGR[3] AGR[2] AGR[1] AGR[0] AMUXBUSR Size 266 Small (higher z) 93/122 Large (lower z) Document Number: 001-66236 Rev. *D Other: DFT 24 Small LCD 15 Small Vssio # Vssd * Lower Left Quadrant XRES_N Connection Vio1 13 * GPIO P2[5] GPIO P2[6] GPIO P2[7] SIO P12[4] SIO P12[5] GPIO P6[4] GPIO P6[5] GPIO P6[6] GPIO P6[7] * * AGL[3] AGL[2] AGL[1] AGL[0] AMUXBUSL * Mux Group Switch Group TS ADC GPIO P5[0] GPIO P5[1] GPIO P5[2] GPIO P5[3] GPIO P1[0] GPIO P1[1] GPIO P1[2] GPIO P1[3] GPIO P1[4] GPIO P1[5] AGL[1] AGL[2] AGL[3] : AMUXBUSR ANALOG ANALOG BUS GLOBALS * AMUXBUSL AGL[0] ANALOG ANALOG GLOBALS BUS * AMUXBUSL AGR[0] AMUXBUSR refmux[2:0] * en_resvda GPIO P5[7] GPIO P5[6] GPIO P5[5] GPIO P5[4] SIO P12[7] SIO P12[6] GPIO *P1[7] GPIO *P1[6] Vp (+) Vn (-) SAR0 Vrefhi_out refs * Vdda Vdda/2 USB IO * P15[6] * * Vddio2 USB IO v0 DAC0 i0 SAR_vref1 (1.024V) SAR_vref2 (1.2V) Vddd Vusb * GPIO P6[0] GPIO P6[1] GPIO P6[2] GPIO P6[3] GPIO P15[4] GPIO P15[5] GPIO P2[0] GPIO P2[1] GPIO P2[2] GPIO P2[3] * GPIO P2[4] * ABUSR0 ABUSR1 ABUSR2 ABUSR3 Vssd * Vddd ABUSL0 ABUSL1 ABUSL2 ABUSL3 * Vssd refbufl_ cmp * cmp0_vref (1.024V) LPF out0 swin GPIO P4[2] GPIO P4[3] GPIO P4[4] GPIO P4[5] GPIO P4[6] GPIO P4[7] Vccd in0 swout i0 * * Notes: * Denotes pins on all packages LCD signals are not shown. Lower Right Quadrant Rev #51 2-April-2010 Page 45 of 97 PSoC® 5: CY8C52 Family Datasheet Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in PSoC 5, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in Figure 8-2. Using the abus saves the analog globals and analog mux buses from being used for interconnecting the analog blocks. Multiplexers and switches exist on the various buses to direct signals into and out of the analog blocks. A multiplexer can have only one connection on at a time, whereas a switch can have multiple connections on simultaneously. In Figure 8-2, multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals. 8.2 Successive Approximation ADC The CY8C52 family of devices has a SAR ADC. This ADC is 12-bit at up to 700 ksps, with single-ended or differential inputs, making it useful for a wide variety of sampling and control applications. 8.2.1 Functional Description 8.2.2 Conversion Signals Writing a start bit or assertion of a start of frame (SOF) signal is used to start a conversion. SOF can be used in applications where the sampling period is longer than the conversion time, or when the ADC needs to be synchronized to other hardware. This signal is optional and does not need to be connected if the SAR ADC is running in a continuous mode. A digital clock or UDB output can be used to drive this input. When the SAR is first powered up or awakened from any of the sleeping modes, there is a power up wait time of 10 µs before it is ready to start the first conversion. When the conversion is complete, a status bit is set and the output signal end of frame (EOF) asserts and remains asserted until the value is read by either the DMA controller or the CPU. The EOF signal may be used to trigger an interrupt or a DMA request. 8.2.3 Operational Modes A ONE_SHOT control bit is used to set the SAR ADC conversion mode to either continuous or one conversion per SOF signal. DMA transfer of continuous samples, without CPU intervention, is supported. In a SAR ADC an analog input signal is sampled and compared with the output of a DAC. A binary search algorithm is applied to the DAC and used to determine the output bits in succession from MSB to LSB. A block diagram of the SAR ADC is shown in Figure 8-3. 8.3 Comparators Figure 8-3. SAR ADC Block Diagram Input offset factory trimmed to less than 15 mV vrefp vrefn S/H DAC array D0:D11 vin comparator SAR digital Rail-to-rail common mode input range (VSSA to VCCA) D0:D11 power filtering Speed and power can be traded off by using one of three modes: fast, slow, or ultra low power autozero reset clock clock POWER GROUND The CY8C52 family of devices contains two comparators in a device. Comparators have these features: vrefp vrefn Comparator outputs can be routed to look up tables to perform simple logic functions and then can also be routed to digital blocks The positive input of the comparators may be optionally passed through a low pass filter. Two filters are provided Comparator inputs can be connected to GPIO or DAC output 8.3.1 Input and Output Interface The input is connected to the analog globals and muxes. The maximum clock rate is 14 MHz. Document Number: 001-66236 Rev. *D The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The output of that LUT is routed to the UDB digital system interface. Page 46 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 8-4. Analog Comparator From Analog Routing ANAIF + comp0 _ + comp1 4 4 LUT0 4 4 4 LUT1 4 LUT2 4 _ From Analog Routing 4 LUT3 UDBs 8.3.2 LUT 8.4 LCD Direct Drive The CY8C52 family of devices contains two LUTs. The LUT is a two input, one output lookup table that is driven by one or two of the comparators in the chip. The output of any LUT is routed to the digital system interface of the UDB array. From the digital system interface of the UDB array, these signals can be connected to UDBs, DMA controller, I/O, or the interrupt controller. The LUT control word written to a register sets the logic function on the output. The available LUT functions and the associated control word is shown in Table 8-1. Table 8-1. LUT Function vs. Program Word and Inputs The PSoC LCD driver system is a highly configurable peripheral designed to allow PSoC to directly drive a broad range of LCD glass. All voltages are generated on chip, eliminating the need for external components. With a high multiplex ratio of up to 1/16, the CY8C52 family LCD driver system can drive a maximum of 736 segments. The PSoC LCD driver module was also designed with the conservative power budget of portable devices in mind, enabling different LCD drive modes and power down modes to conserve power. Control Word 0000b Output (A and B are LUT inputs) FALSE (‘0’) 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b A AND B A AND (NOT B) A (NOT A) AND B B A XOR B A OR B A NOR B A XNOR B NOT B A OR (NOT B) NOT A (NOT A) OR B A NAND B TRUE (‘1’) Document Number: 001-66236 Rev. *D PSoC Creator provides an LCD segment drive component. The component wizard provides easy and flexible configuration of LCD resources. You can specify pins for segments and commons along with other options. The software configures the device to meet the required specifications. This is possible because of the programmability inherent to PSoC devices. Key features of the PSoC LCD segment system are: LCD panel direct driving Type A (standard) and Type B (low power) waveform support Wide operating voltage range support (2 V to 5 V) for LCD panels Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels Internal bias voltage generation through internal resistor ladder Up to 62 total common and segment outputs Up to 1/16 multiplex for a maximum of 16 backplane/common outputs Up to 62 front plane/segment outputs for direct drive Drives up to 736 total segments (16 backplane × 46 front plane) Up to 64 levels of software controlled contrast Ability to move display data from memory buffer to LCD driver through DMA (without CPU intervention) Adjustable LCD refresh rate from 10 Hz to 150 Hz Page 47 of 97 PSoC® 5: CY8C52 Family Datasheet Ability to invert LCD display for negative image 8.4.4 LCD DAC Three LCD driver drive modes, allowing power optimization The LCD DAC generates the contrast control and bias voltage for the LCD system. The LCD DAC produces up to five LCD drive voltages plus ground, based on the selected bias ratio. The bias voltages are driven out to GPIO pins on a dedicated LCD bias bus, as required. LCD driver configurable to be active when PSoC is in limited active mode Figure 8-5. LCD System LCD DAC Global Clock UDB LCD Driver Block DMA 8.5 CapSense PIN Display RAM The CapSense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity detection, etc. The CapSense system uses a configuration of system resources, including a few hardware functions primarily targeted for CapSense. Specific resource usage is detailed in the CapSense component in PSoC Creator. A capacitive sensing method using a delta-sigma modulator (CSD) is used. It provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code. PHUB 8.4.1 LCD Segment Pin Driver Each GPIO pin contains an LCD driver circuit. The LCD driver buffers the appropriate output of the LCD DAC to directly drive the glass of the LCD. A register setting determines whether the pin is a common or segment. The pin’s LCD driver then selects one of the six bias voltages to drive the I/O pin, as appropriate for the display data. 8.4.2 Display Data Flow The LCD segment driver system reads display data and generates the proper output voltages to the LCD glass to produce the desired image. Display data resides in a memory buffer in the system SRAM. Each time you need to change the common and segment driver voltages, the next set of pixel data moves from the memory buffer into the Port Data Registers via DMA. 8.4.3 UDB and LCD Segment Control A UDB is configured to generate the global LCD control signals and clocking. This set of signals is routed to each LCD pin driver through a set of dedicated LCD global routing channels. In addition to generating the global LCD control signals, the UDB also produces a DMA request to initiate the transfer of the next frame of LCD data. Document Number: 001-66236 Rev. *D 8.6 Temp Sensor Die temperature is used to establish programming parameters for writing flash. Die temperature is measured using a dedicated sensor based on a forward biased transistor. The temperature sensor has its own auxiliary ADC. 8.7 DAC The CY8C52 parts contain a DAC. The DAC is 8-bit and can be configured for either voltage or current output. The DAC supports CapSense, power supply regulation, and waveform generation. The DAC has the following features: Adjustable voltage or current output in 255 steps Programmable step size (range selection) Eight bits of calibration to correct ± 25% of gain error Source and sink option for current output 5.5-Msps conversion rate for current output 1-Msps conversion rate for voltage output Monotonic in nature Data and strobe inputs can be provided by the CPU or DMA, or routed directly from the DSI Dedicated low-resistance output pin for high-current mode Note that a write of a new value to the DAC may result in an indeterminate value on the DAC output. To output the desired value, write or strobe the DAC twice with the same value. Since the first write may result in an indeterminate output, the time between the two writes should be minimized. This applies to writes by CPU, DMA, and strobe. Page 48 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 8-6. DAC Block Diagram I source Range 1x , 8x , 64x Reference Source Scaler Vout R 3R Iout I sink Range 1x , 8x , 64x 8.7.1 Current DAC The IDAC can be configured for the ranges 0 to 31.875 µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be configured to source or sink current. 8.7.2 Voltage DAC For the VDAC, the current DAC output is routed through resistors. The two ranges available for the VDAC are 0 to 1.02 V and 0 to 4.08 V. In voltage mode any load connected to the output of a DAC should be purely capacitive (the output of the VDAC is not buffered). 9. Programming, Debug Interfaces, Resources The Cortex-M3 has internal debugging components, tightly integrated with the CPU, providing the following features: SWD access FPB block for implementing breakpoints and code patches DWT block for implementing watchpoints, trigger resources, and system profiling ITM for support of printf-style debugging PSoC devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. SWD supports all programming and debug features of the device. The SWV provides trace output from the DWT and ITM. For more information on PSoC 5 programming, refer to the application note AN64359 - In-System Programming for PSoC® 5. Cortex-M3 debug and trace functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE software provides fully integrated programming and debug support for PSoC devices. The low cost MiniProg3 programmer and debugger is designed to provide full programming and debug support of PSoC devices in conjunction with the PSoC Creator IDE. PSoC interfaces are fully compatible with industry standard third party tools. Document Number: 001-66236 Rev. *D All Cortex-M3 debug and trace modules are disabled by default and can only be enabled in firmware. If not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables them. Disabling debug and trace features, robust flash protection, and hiding custom analog and digital functionality inside the PSoC device provide a level of security not possible with multichip application solutions. Additionally, all device interfaces can be permanently disabled (Device Security) for applications concerned about phishing attacks due to a maliciously reprogrammed device. Permanently disabling interfaces is not recommended in most applications because the designer then cannot access the device. Because all programming, debug, and test interfaces are disabled when Device Security is enabled, PSoCs with Device Security enabled may not be returned for failure analysis. 9.1 Debug Port Acquisition Prior to programming or debugging, the debug port must be acquired. There is a time window after reset within which the Port Acquire must be completed. This window is initially 8 µs; if eight clocks are detected on the SWDCK line within the 8 µs period, the time window will then be extended to 400 µs to complete the port acquire operation. The port acquire key must be transmitted over one of the two SWD pin pairs; see SWD Interface on page 49. For a detailed description of the acquire key sequence, refer to the Technical Reference Manual. 9.2 SWD Interface SWD uses two pins, either two port 1 pins or the USBIO D+ and D- pins. The USBIO pins are useful for in system programming of USB solutions that would otherwise require a separate programming connector. One pin is used for the data clock (SWDCK) and the other is used for data input and output (SWDIO). SWD can be enabled on only one of the pin pairs at a time. When USB pins D+ and D- are used for SWD function, the SWDCK pin of port P1[1] is not available for use as a general purpose I/O and it should be externally pulled down using a resistor of less than 100 KSWD is used for debugging or for programming the flash memory. In addition, the SWD interface supports the SWV trace output. The SWD interface also includes the SWV interface, see “SWV Interface” on page 51. When using the SWD/SWV pins as standard GPIO, make sure that the GPIO functionality and PCB circuits do not interfere with SWD/SWV use. The SWV trace output is automatically activated whenever the SWD is activated. Page 49 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 9-1. SWD Interface Connections between PSoC 5 and Programmer VDD Host Programmer VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3 VDD SWDCK (P1[1] or P15[7]) 4 SWDCK SWDIO SWDIO (P1[0] or P15[6]) XRES XRES GND PSoC 5 GND VSSD, VSSA 1 The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in programming should be the same. XRES pin is powered by VDDIO1. The USB SWD pins are powered by VDDD. So for programming using the USB SWD pins with XRES pin, the VDDD, VDDIO1 of PSoC 5 should be at the same voltage level as Host VDD. Rest of PSoC 5 voltage domains (VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are powered by VDDIO1. So VDDIO1 of PSoC 5 should be at same voltage level as host VDD for Port 1 SWD programming. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. 4 When USB SWD pins are used for Programming, the P1[1] SWDCK pin must be externally connected to Ground using external pull-down resistor (around 100 K resistor). This is required for P15[7] SWDCK signal to be seen by PSoC 5's internal logic. Document Number: 001-66236 Rev. *D Page 50 of 97 PSoC® 5: CY8C52 Family Datasheet 9.3 Debug Features The CY8C52 supports the following debug features: Halt and single-step the CPU View and change CPU and peripheral registers, and RAM addresses Six program address breakpoints and two literal access breakpoints Data watchpoint events to CPU Patch and remap instruction from flash to SRAM Debugging at the full speed of the CPU Compatible with PSoC Creator and MiniProg3 programmer and debugger 9.4 Trace Features The following trace features are supported: Data watchpoint on access to data address, address range, or data value Software event monitoring, “printf-style” debugging 9.5 SWV Interface The SWV interface provides trace data to a debug host via the Cypress MiniProg3 or an external trace port analyzer. . 9.6 Programming Features The SWD interface provides full programming support. The entire device can be erased, programmed, and verified. Designers can increase flash protection levels to protect firmware IP. Flash protection can only be reset after a full device erase. Individual flash blocks can be erased, programmed, and verified, if block security settings permit. 9.7 Device Security PSoC 5 offers an advanced security feature called device security, which permanently disables all test, programming, and debug ports, protecting your application from external access. The device security is activated by programming a 32-bit key (0x50536F43) to a Write Once Latch (WOL). The WOL must be programmed at VDDD 3.3 V and TJ = 25 °C ±15 °C. The Write Once Latch is a type of nonvolatile latch (NVL). The cell itself is an NVL with additional logic wrapped around it. Each WOL device contains four bytes (32 bits) of data. The wrapper outputs a ‘1’ if a super-majority (28 of 32) of its bits match a Document Number: 001-66236 Rev. *D pre-determined pattern (0x50536F43); it outputs a ‘0’ if this majority is not reached. When the output is 1, the Write Once NV latch locks the part out of Debug and Test modes; it also permanently gates off the ability to erase or alter the contents of the latch. Matching all bits is intentionally not required, so that single (or few) bit failures do not deassert the WOL output. The state of the NVL bits after wafer processing is truly random with no tendency toward 1 or 0. The WOL only locks the part after the correct 32-bit key (0x50536F43) is loaded into the NVL's volatile memory, programmed into the NVL's nonvolatile cells, and the part is reset. The output of the WOL is only sampled on reset and used to disable the access. This precaution prevents anyone from reading, erasing, or altering the contents of the internal memory. You can write the key into the WOL to lock out external access only if no flash protection is set (see “Flash Security” section on page 16). However, after setting the values in the WOL, you still have access to the part until it is reset. Therefore, you can write the key into the WOL, program the flash protection data, and then reset the part to lock it. If the device is protected with a WOL setting, Cypress cannot perform failure analysis and, therefore, cannot accept RMAs from customers. The WOL can be read out via Serial Wire Debug (SWD) port to electrically identify protected parts. You can write the key in WOL to lock out external access only if no flash protection is set. For more information on how to take full advantage of the security features in PSoC see the PSoC 5 TRM. Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress data sheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. Page 51 of 97 PSoC® 5: CY8C52 Family Datasheet 10. Development Support The CY8C52 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. Technical Reference Manual: PSoC Creator makes designing with PSoC as easy as dragging a peripheral onto a schematic, but, when low level details of the PSoC device are required, use the technical reference manual (TRM) as your guide. Note Visit www.arm.com for detailed documentation about the Cortex-M3 CPU. 10.1 Documentation 10.2 Online A suite of documentation, to ensure that you can find answers to your questions quickly, supports the CY8C52 family. This section contains a list of some of the key documents. In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component data sheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. 10.3 Tools With industry standard cores, programming, and debugging interfaces, the CY8C52 family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Document Number: 001-66236 Rev. *D Page 52 of 97 PSoC® 5: CY8C52 Family Datasheet 11. Electrical Specifications Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component data sheets for full AC/DC specifications of individual functions. See the “Example Peripherals” section on page 32 for further explanation of PSoC Creator components. 11.1 Absolute Maximum Ratings Table 11-1. Absolute Maximum Ratings DC Specifications Parameter Description Min Typ Max Units –55 – 110 °C –55 25 100 °C Analog supply voltage relative to VSSA –0.5 – 6 V VDDD Digital supply voltage relative to VSSD –0.5 – 6 V VDDIO I/O supply voltage relative to VSSD –0.5 – 6 V VCCA Direct analog core voltage input –0.5 – 1.95 V VCCD Direct digital core voltage input VSSA Analog ground voltage VGPIO[11] VSIO TJ Operating die temperature TSTG Storage temperature VDDA IVDDIO Conditions Recommended storage temperature is +25 °C ±25 °C. Extended duration storage temperatures above 85 °C degrade reliability. –0.5 – 1.95 V VSSD – 0.5 – VSSD + 0.5 V DC input voltage on GPIO Includes signals sourced by VDDA VSSD – 0.5 and routed internal to the pin. – VDDIO + 0.5 V DC input voltage on SIO Output disabled VSSD – 0.5 – 7 V Output enabled VSSD – 0.5 – 6 V Source – – 20 mA Sink – – 100 Current per VDDIO supply pin LU Latch up current[12] –100 – 100 mA ESDHBM Electrostatic discharge voltage Human body model 500 – – V ESDCDM Electrostatic discharge voltage Charge device model 500 – – V Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above normal operating conditions the device may not operate to specification. Notes 11. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin VDDIO VDDA 12. Meets or exceeds JEDEC Spec EIA/JESD78 IC latch up test, at up to 85 °C. Document Number: 001-66236 Rev. *D Page 53 of 97 PSoC® 5: CY8C52 Family Datasheet 11.2 Device Level Specifications Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Min Typ Max Units VDDA Parameter Analog supply voltage and input to analog core regulator Description Analog core regulator enabled Conditions 2.7 – 5.5 V VDDD Digital supply voltage relative to VSSD Digital core regulator enabled 2.7 – VDDA[13] V VDDIO[14] I/O supply voltage relative to VSSIO 1.71 – VDDA[13] V mA Device Configuration IDD[15] Active Mode VDDX FCPU Temp Only IMO and CPU clock 2.7 V to enabled. CPU executing 5.5 V simple loop from cache 6 MHz –40 °C – 2.2 3 25 °C – 2.4 3.5 85 °C – 2.8 3.5 IMO enabled, bus clock and CPU clock enabled. CPU executing complex program from flash 3 MHz 2.7 V to 5.5 V 6 MHz 12 MHz 24 MHz 48 MHz 63 MHz –40 °C – 3.4 4 25 °C – 3.6 4.5 85 °C – 4.2 5 –40 °C – 5.6 6 25 °C – 6 7 85 °C – 6.6 7.5 –40 °C – 10 11 25 °C – 11 12 85 °C – 12 13 –40 °C – 17 19 25 °C – 18 20 85 °C – 20 22 –40 °C – 31 34 25 °C – 33 35 85 °C – 36 39 –40 °C – 36 39 25 °C – 37 40 85 °C – 40 44 Notes 13. VDDD and VDDA must be brought up in synchronization with each other, that is, at the same rates and levels. VDDA must be greater than or equal to all other supplies. 14. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin VDDIO VDDA. 15. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device data sheet and component data sheets. Document Number: 001-66236 Rev. *D Page 54 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-2. DC Specifications (continued) Parameter Description Conditions Device Configuration Sleep Mode[17] CPU = OFF Sleep Timer = ON POR = ON All oscillators and regulators off, except hibernate regulator. SRAM retention IDDDR Max Units –40 °C – 1.4 – μA 25 °C – 1.2 – 85 °C – 11 – –40 °C – 1.2 – 25 °C – 2 – 85 °C – 10 – –40 °C – 0.3 – 25 °C – 0.6 – 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V IDDAR Typ Temp 2.7 V to 3.6 V Hibernate Mode Min VDD = VDDIO 85 °C – 10 – –40 °C – 0.2 – 25 °C – 0.3 – 85 °C – 8 – μA Analog current consumption while device is reset[16] VDDA 3.6 V – 0.3 – mA VDDA 3.6 V – 1.4 – mA Digital current consumption while device is reset[16] VDDD 3.6 V – 1.1 – mA VDDD 3.6 V – 0.7 – mA Figure 11-1. Active Mode Device IDD, mA/MHz Note 16. Based on device characterization (not production tested). USBIO pins tied to ground (VSSD). Document Number: 001-66236 Rev. *D Page 55 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-3. AC Specifications[18] Parameter FCPU FBUSCLK Svdd TSTARTUP Description Conditions CPU frequency Bus frequency VDD ramp rate Time from VDDD/VDDA/VCCD/VCCA No PLL used, IMO boot mode min operating voltage to CPU 12 MHz typ executing code at reset vector Wakeup from sleep – CTW timeout TSLEEP to beginning of execution of next CPU instruction TSLEEP_INT Sleep timer periodic wakeup interval Min DC DC – – Typ – – – 45 Max 40.01 40.01 0.066 80 Units MHz MHz V/µs µs – 125 – µs – – 128 ms 11.3 Power Regulators Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description VDDD Input voltage VCCD Output voltage Regulator output capacitor[19] Figure 11-2. Regulators VCC vs VDD Conditions ±10%, X5R ceramic or better. The two VCCD pins must be shorted together, with as short a trace as possible, see Power System on page 21 Min 2.7 – – Typ – 1.80 1 Max 5.5 – 10 Units V V µF Figure 11-3. Digital Regulator PSRR vs Frequency and VDD Notes 17. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off. 18. Based on device characterization (Not production tested). 19. 10 µF is required for sleep mode. See Table 11-3. Document Number: 001-66236 Rev. *D Page 56 of 97 PSoC® 5: CY8C52 Family Datasheet 11.3.2 Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description VDDA Input voltage VCCA Output voltage Regulator output capacitor[22] Conditions Min 2.7 – – ±10%, X5R ceramic or better Typ – 1.80 1 Max 5.5 – 10 Units V V µF Figure 11-4. Analog Regulator PSRR vs Frequency and VDD 11.4 Inputs and Outputs Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.4.1 GPIO Table 11-6. GPIO DC Specifications Parameter VIH VIL Description Input voltage high threshold Input voltage low threshold Conditions CMOS Input, PRT[x]CTL = 0 CMOS Input, PRT[x]CTL = 0 Min 0.7 VDDIO – Typ – – VIH VIL VOH VOL Rpullup Rpulldown IIL Input voltage high threshold Input voltage low threshold Output voltage high Output voltage low Pull up resistor Pull down resistor Input leakage current (absolute value)[20] Input capacitance[20] LVTTL Input, PRT[x]CTL = 1 LVTTL Input, PRT[x]CTL = 1 IOH = 4 mA at 3.3 VDDIO IOL = 8 mA at 3.3 VDDIO 2.0 – VDDIO – 0.6 – 3.5 3.5 – CIN VH Input voltage hysteresis (Schmitt-Trigger)[20] 25 °C, VDDIO = 3.0 V GPIOs not shared with kHzECO or SAR ADC external reference input GPIOs shared with kHzECO[21] GPIOs shared with SAR ADC external reference input Units V V – – – – 5.6 5.6 – Max – 0.3 VDDIO – 0.8 – 0.6 8.5 8.5 2 – 4 7 pF – – 5 – 7 30 pF pF – 150 – mV V V V V k k nA Notes 20. Based on device characterization (Not production tested). 21. For information on designing with PSoC 3 oscillators, refer to the application note, AN54439 - PSoC® 3 and PSoC 5 External Oscillator. 22. 10 µF is required for sleep mode. See Table 11-3. Document Number: 001-66236 Rev. *D Page 57 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-6. GPIO DC Specifications (continued) Parameter Idiode Rglobal Rmux Description Conditions Current through protection diode to VDDIO and VSSIO Resistance pin to analog 25 °C, VDDIO = 3.0 V global bus Resistance pin to analog mux 25 °C, VDDIO = 3.0 V bus Figure 11-5. GPIO Output High Voltage and Current Document Number: 001-66236 Rev. *D Min – Typ – Max 100 Units µA – 320 – – 220 – Figure 11-6. GPIO Output Low Voltage and Current Page 58 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-7. GPIO AC Specifications Parameter TriseF TfallF TriseS TfallS Fgpioout Fgpioin Description Rise time in Fast Strong Mode[23] Fall time in Fast Strong Mode[23] Rise time in Slow Strong Mode[23] Fall time in Slow Strong Mode[23] GPIO output operating frequency Fast strong drive mode 3.3 V < VDDIO < 5.5 V, slow strong drive mode 2.7 V < VDDIO < 3.3 V, slow strong drive mode GPIO input operating frequency 2.7 V < VDDIO < 5.5 V Conditions 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF Min – – – – Typ – – – – Max 12 12 60 60 Units ns ns ns ns 90/10% VDDIO into 25 pF 90/10% VDDIO into 25 pF – – – – 33 7 MHz MHz 90/10% VDDIO into 25 pF – – 3.5 MHz 90/10% VDDIO – – 40 MHz Figure 11-7. GPIO Output Rise and Fall Times, Fast Strong Mode, VDDIO = 3.3 V, 25 pF Load Figure 11-8. GPIO Output Rise and Fall Times, Slow Strong Mode, VDDIO = 3.3 V, 25 pF Load Note 23. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 59 of 97 PSoC® 5: CY8C52 Family Datasheet 11.4.2 SIO Note that under certain conditions an SIO pin may cause up to 1 mA of additional current to be drawn from the related VDDIO pin. If an SIO pin's voltage exceeds its VDDIO supply by 0.5 V, the trigger condition is set. After the trigger condition is set, the SIO pin causes increased current when its voltage is between VSSD + 0.5 V and VDDIO – 0.5 V. The trigger condition is reset when the SIO pin is brought within the range of VSSD to VSSD + 0.5 V. The trigger condition may unknowingly be met during device power-up due to differences in supply ramps. Table 11-8. SIO DC Specifications Parameter Vinmax Description Maximum input voltage Vinref Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) VDDIO > 3.7 Voutref Conditions All allowed values of Vddio and Vddd, see Section 11.2.1 Min – Typ – Max 5.5 Units V 0.5 – 0.52 VDDIO V 1 1 – – VDDIO – 1 VDDIO – 0.5 V V CMOS input Hysteresis disabled 0.7 VDDIO SIO_ref + 0.2 – – – – V V CMOS input Hysteresis disabled – – – – 0.3 VDDIO SIO_ref – 0.2 V V VDDIO – 0.4 SIO_ref – 0.65 SIO_ref – 0.3 – 3.5 3.5 – – – – 5.6 5.6 – SIO_ref + 0.2 SIO_ref + 0.2 0.8 8.5 8.5 V V V V k k – – 14 nA – – – – – 150 10 7 – µA pF mV – 35 – mV – – 100 µA VDDIO < 3.7 VIH VIL VOH VOL Rpullup Rpulldown IIL Input voltage high threshold GPIO mode Differential input mode[24] Input voltage low threshold GPIO mode Differential input mode[24] Output voltage high Unregulated mode Regulated mode[24] Regulated mode[24] Output voltage low Pull up resistor Pull down resistor Input leakage current (absolute value)[25] VIH < Vddsio CIN VH Idiode VIH > Vddsio Input Capacitance[25] Input voltage hysteresis (Schmitt-Trigger)[25] IOH = 4 mA, VDDIO = 3.3 V IOH = 1 mA IOH = 0.1 mA VDDIO = 3.30 V, IOL = 25 mA 25 °C, Vddsio = 3.0 V, VIH = 3.0 V 25 °C, Vddsio = 0 V, VIH = 3.0 V Single ended mode (GPIO mode) Differential mode Current through protection diode to VSSIO Notes 24. See Figure 6-8 on page 28 and Figure 6-11 on page 31 for more information on SIO reference. 25. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 60 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 11-9. SIO Output High Voltage and Current, Unregulated Mode Figure 11-11. SIO Output Low Voltage and Current, Unregulated Mode Figure 11-10. SIO Output High Voltage and Current, Regulated Mode Table 11-9. SIO AC Specifications Parameter TriseF TfallF TriseS TfallS Description Rise time in Fast Strong Mode (90/10%)[26] Fall time in Fast Strong Mode (90/10%)[26] Conditions Cload = 25 pF, VDDIO = 3.3 V Min – Typ – Max 12 Units ns Cload = 25 pF, VDDIO = 3.3 V – – 12 ns Rise time in Slow Strong Mode (90/10%)[26] Fall time in Slow Strong Mode (90/10%)[26] Cload = 25 pF, VDDIO = 3.0 V – – 75 ns Cload = 25 pF, VDDIO = 3.0 V – – 60 ns Note 26. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 61 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-9. SIO AC Specifications (continued) Parameter Fsioout Fsioin Description Conditions SIO output operating frequency Unregulated output (GPIO) mode, 90/10% VDDIO into 25 pF fast strong drive mode 3.3 V < VDDIO < 5.5 V, Unregulated 90/10% VDDIO into 25 pF output (GPIO) mode, slow strong drive mode 2.7 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow strong drive mode Regulated output mode, fast strong drive mode Regulated output mode, slow strong drive mode SIO input operating frequency Min Typ Max Units – – 33 MHz – – 5 MHz 90/10% VDDIO into 25 pF – – 4 MHz Output continuously switching into 25 pF Output continuously switching into 25 pF 90/10% VDDIO – – 20 MHz – – 2.5 MHz – – 40 MHz Figure 11-12. SIO Output Rise and Fall Times, Fast Strong Mode, VDDIO = 3.3 V, 25 pF Load Document Number: 001-66236 Rev. *D Figure 11-13. SIO Output Rise and Fall Times, Slow Strong Mode, VDDIO = 3.3 V, 25 pF Load Page 62 of 97 PSoC® 5: CY8C52 Family Datasheet 11.4.3 USBIO For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 54. Table 11-10. USBIO DC Specifications Parameter Rusbi Description USB D+ pull-up resistance Min Typ Max Units With idle bus Conditions 0.900 – 1.575 k Rusba USB D+ pull-up resistance While receiving traffic 1.425 – 3.090 k Vohusb Static output high 15 k ±5% to Vss, internal pull-up enabled 2.8 – 3.6 V Volusb Static output low 15 k ±5% to Vss, internal pull-up enabled – – 0.3 V Vihgpio Input voltage high, GPIO mode VDDD 3 V 2 – – V Vilgpio Input voltage low, GPIO mode VDDD 3 V – – 0.8 V Vohgpio Output voltage high, GPIO mode IOH = 4 mA, VDDD 3 V 2.4 – – V Volgpio Output voltage low, GPIO mode IOL = 4 mA, VDDD 3 V – – 0.3 V Vdi Differential input sensitivity |(D+)–(D–)| – – 0.2 V Vcm Differential input common mode range 0.8 – 2.5 V Vse Single ended receiver threshold 0.8 – 2 V Rps2 PS/2 pull-up resistance In PS/2 mode, with PS/2 pull-up enabled 3 – 7 k Rext External USB series resistor In series with each USB pin 21.78 (–1%) 22 22.22 (+1%) Zo USB driver output impedance[27] Including Rext 28 – 44 CIN USB transceiver input capacitance – – 20 pF IIL[28] Input leakage current (absolute value) 25 °C, VDDD = 3.0 V – – 2 nA Figure 11-14. USBIO Output High Voltage and Current, GPIO Mode Figure 11-15. USBIO Output Low Voltage and Current, GPIO Mode Notes 27. This parameter is not production tested and cannot be guaranteed over all temperatures. 28. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 63 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-11. USBIO AC Specifications Parameter Description Conditions Using external 24 MHz crystal Min Typ Max Units 12 – 0.25% 12 12 + 0.25% MHz Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition –8 – 8 ns Tjr2 Receiver data jitter tolerance to pair transition –5 – 5 ns Tdj1 Driver differential jitter to next transition –3.5 – 3.5 ns Tdj2 Driver differential jitter to pair transition –4 – 4 ns Tfdeop Source jitter for differential transition to SE0 transition –2 – 5 ns Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – – ns Tfst Width of SE0 interval during differential transition – – 14 ns Fgpio_out GPIO mode output operating frequency 3 V VDDD 5.5 V – – 20 MHz – – 6 MHz VDDD = 2.7 V Tr_gpio Rise time, GPIO mode, 10%/90% VDDD VDDD > 3 V, 25 pF load VDDD = 2.7 V, 25 pF load Tf_gpio Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load VDDD = 2.7 V, 25 pF load – – 12 ns – – 40 ns – – 12 ns – – 40 ns Figure 11-16. USBIO Output Rise and Fall Times, GPIO Mode, VDDD = 3.3 V, 25 pF Load Document Number: 001-66236 Rev. *D Page 64 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-12. USB Driver AC Specifications Parameter Description Conditions Min Typ Max Units Tr Transition rise time – – 20 ns Tf Transition fall time – – 20 ns TR Rise/fall time matching 80% – 135% Vcrs Output signal crossover voltage 1.1 – 2.3 V Min Typ Max Units VUSB_5, VUSB_3.3, see USB DC Specifications on page 80 11.4.4 XRES Table 11-13. XRES DC Specifications Parameter Description Conditions VIH Input voltage high threshold 0.7 VDDIO – – V VIL Input voltage low threshold – – 0.3 VDDIO V Rpullup Pull up resistor 3.5 5.6 8.5 k capacitance[29] CIN Input – 3 VH Input voltage hysteresis (Schmitt-Trigger)[29] – 100 – mV pF Idiode Current through protection diode to VDDIO and VSSIO – – 100 µA Min Typ Max Units 1 – – µs Table 11-14. XRES AC Specifications Parameter TRESET Description Reset pulse width Conditions Note 29. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 65 of 97 PSoC® 5: CY8C52 Family Datasheet 11.5 Analog Peripherals Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. 11.5.1 Voltage Reference Table 11-15. Voltage Reference Specifications Parameter VREF Description Min Typ Max Units 1.017 (–0.7%) 1.024 1.033 (+0.9%) V Temperature drift[30] – – 57 ppm/°C Long term drift – 100 – ppm/Khr Thermal cycling drift (stability)[30] – 100 – ppm Min Typ Max Units bits Precision reference voltage Conditions Initial trimming 11.5.2 SAR ADC Unless otherwise specified, operating conditions are: Operation in continuous sample mode Fclk = 14 MHz Input range = ± VREF Bypass capacitor of 10 µF Table 11-16. SAR ADC DC Specifications Parameter Description Conditions Resolution – – 12 Number of channels – single-ended – – No of GPIO – – No of GPIO/2 Yes – – Number of channels – differential Differential pair is formed using a pair of neighboring GPIO. Monotonicity[30] Ge Gain error External reference – – ±0.2 % VOS Input offset voltage VCM = 0 V – – ±2 mV IDD Current consumption – – 1 mA Input voltage range – single-ended[30] VSSA – VDDA V Input voltage range – differential[30] VSSA – VDDA V 70 – – dB VCM = VDD/2 ±6 PSRR Power supply rejection ratio[30] CMRR Common mode rejection ratio 35 – – dB INL Integral non linearity30] Internal reference from VBG – – ±2 LSB DNL Differential non linearity[30] Internal reference from VBG – – ±2 LSB Note 30. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 66 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 11-17. SAR ADC DNL vs Output Code, Bypassed Internal Reference Mode Figure 11-19. SAR ADC INL vs Output Code, Bypassed Internal Reference Mode Figure 11-18. SAR ADC IDD vs sps, VDDA = 5 V, Continuous Sample Mode, External Reference Mode Document Number: 001-66236 Rev. *D Page 67 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-17. SAR ADC AC Specifications Parameter Description Sample rate[31] Conditions Min Typ Max Units With bypass capacitor – – 700 ksps Without bypass capacitor – – 100 – – 10 µs VDDA 3.6 V, VREF 3.6 V 57 – – dB 3.6 V < VDDA 5.5 V VREF < 1.3 V or VREF > 1.8 V 57 – – VDDA 3.6 V, VREF 3.6 V – – 0.1 3.6 V < VDDA 5.5 V VREF < 1.3 V or VREF > 1.8 V – – 0.1 Startup time[31] SINAD THD Signal-to-noise ratio[31] Total harmonic distortion[31] Figure 11-20. SAR ADC Noise Histogram, 1000 samples, 700 ksps, Internal Reference No Bypass, VIN = VREF/2 % Figure 11-22. SAR ADC Noise Histogram, 1000 samples, 700 ksps, Internal Reference Bypassed, VIN = VREF/2 Figure 11-21. SAR ADC Noise Histogram, 1000 samples, 700 ksps, External Reference, VIN = VREF/2 Note 31. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 68 of 97 PSoC® 5: CY8C52 Family Datasheet 11.5.3 Analog Globals Table 11-18. Analog Globals DC Specifications Parameter Description Conditions Min Typ Max Units Rppag Resistance pin-to-pin through analog global VDDA = 3.0 V – 1200 1500 Rppmuxbus Resistance pin-to-pin through analog mux bus VDDA = 3.0 V – 700 1000 11.5.4 Comparator Table 11-19. Comparator DC Specifications Parameter VOS Description Conditions Min Typ Max Units Input offset voltage in fast mode Factory trim, VIN 0.5 V – 15 mV Input offset voltage in slow mode Factory trim, VIN 0.5 V – 15 mV – mV VOS Input offset voltage in ultra low power mode VHYST Hysteresis VICM Input common mode voltage – ±12 Hysteresis enable mode – 10 32 mV High current / fast mode VSSA – VDDA – 0.1 V Low current / slow mode VSSA – VDDA V Ultra low power mode VSSA – VDDA – 0.9 CMRR Common mode rejection ratio – 50 – dB ICMP High current mode/fast mode[31] – – 400 µA Low current mode/slow mode[31] – – 100 µA Ultra low power mode[31] – 6 – µA Table 11-20. Comparator AC Specifications Parameter TRESP Min Typ Max Units Response time, high current mode[31] Description 50 mV overdrive, measured pin-to-pin – 75 110 ns Response time, low current mode[31] 50 mV overdrive, measured pin-to-pin – 155 200 ns Response time, ultra low power mode[31] 50 mV overdrive, measured pin-to-pin – 55 – µs Document Number: 001-66236 Rev. *D Conditions Page 69 of 97 PSoC® 5: CY8C52 Family Datasheet 11.5.5 Current Digital-to-analog Converter (IDAC) All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 8 for details). See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-21. IDAC DC Specifications Parameter Description Conditions Min Typ Max Units – – 8 bits Range = 2.04 mA, code = 255, Rload = 600 – 2.04 – mA Range = 255 µA, code = 255, Rload = 600 – 255 – µA Range = 31.875 µA, code = 255, Rload = 600 – 31.875 – µA Resolution IOUT Output current at code = 255 Monotonicity – – Yes Ezs Zero scale error – 0 ±2.5 Eg Gain error TC_Eg Temperature coefficient of gain error LSB – – ±5 % Range = 2.04 mA – – 0.04 % / °C Range = 255 µA – – 0.04 % / °C Range = 31.875 µA – – 0.05 % / °C INL Integral nonlinearity Range = 255 µA, Codes 8 – 255, Rload = 600 , Cload = 15 pF – – ±3 LSB DNL Differential nonlinearity, non-monotonic Range = 255 µA, Rload = 600 , Cload = 15 pF – – ±1.6 LSB Vcompliance Dropout voltage, source or sink mode Voltage headroom at max current, Rload to Vdda or Rload to Vssa, Vdiff from Vdda 1 – – V IDD Operating current, code = 0 Slow mode, source mode, range = 31.875 µA – 44 100 µA Slow mode, source mode, range = 255 µA, – 33 100 µA Slow mode, source mode, range = 2.04 mA – 33 100 µA Slow mode, sink mode, range = 31.875 µA – 36 100 µA Slow mode, sink mode, range = 255 µA – 33 100 µA Slow mode, sink mode, range = 2.04 mA – 33 100 µA Fast mode, source mode, range = 31.875 µA – 310 500 µA Fast mode, source mode, range = 255 µA – 305 500 µA Fast mode, source mode, range = 2.04 mA – 305 500 µA Fast mode, sink mode, range = 31.875 µA – 310 500 µA Fast mode, sink mode, range = 255 µA – 300 500 µA Fast mode, sink mode, range = 2.04 mA – 300 500 µA Document Number: 001-66236 Rev. *D Page 70 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 11-23. IDAC INL vs Input Code, Range = 255 µA, Source Mode Figure 11-25. IDAC INL vs Input Code, Range = 255 µA, Sink Mode Figure 11-24. IDAC DNL vs Input Code, Range = 255 µA, Source Mode Figure 11-26. IDAC DNL vs Input Code, Range = 255 µA, Sink Mode Document Number: 001-66236 Rev. *D Page 71 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 11-27. IDAC INL vs Temperature, Range = 255 µA, Fast Mode Figure 11-30. IDAC DNL vs Temperature, Range = 255 µA, Fast Mode Figure 11-28. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode Figure 11-31. IDAC Full Scale Error vs Temperature, Range = 255 µA, Sink Mode Figure 11-29. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Figure 11-32. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Sink Mode Document Number: 001-66236 Rev. *D Page 72 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-22. IDAC AC Specifications Parameter Description Conditions 55 Min Typ Max Units FDAC Update rate – – 5.5 Msps TSETTLE Settling time to 0.5 LSB Range = 31.875 µA or 255 µA, full scale transition, fast mode, 600 15-pF load – – 180 ns Current noise Range = 255 µA, source mode, fast mode, Vdda = 5 V, 10 kHz – 340 – pA/sqrtHz Figure 11-33. IDAC Step Response, Codes 0x40 - 0xC0, 255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V Figure 11-35. IDAC Glitch Response, Codes 0x7F - 0x80, 255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V Figure 11-34. IDAC PSRR vs Frequency Figure 11-36. IDAC Current Noise, 255 µA Mode, Source Mode, Fast Mode, VDDA = 5 V Document Number: 001-66236 Rev. *D Page 73 of 97 PSoC® 5: CY8C52 Family Datasheet 11.5.6 Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-23. VDAC DC Specifications Parameter Description Conditions Resolution Min 8 – bits ±2.1 ±2.5 LSB 1 V scale – ±0.3 ±1 LSB 1 V scale – 4 – k 16 – k 1.02 – V 4.08 – V – Yes – DNL1 Differential nonlinearity Rout Output resistance 4 V scale – VOUT Output voltage range, code = 255 1 V scale – 1 V scale – – 4 V scale, Vdda = 5 V Monotonicity Zero scale error Gain error TC_Eg IDD Operating current Units – Integral nonlinearity Eg Max – INL1 VOS Typ – 0 ±0.9 LSB 1 V scale – – ±5 % 4 V scale – – ±5 % Temperature coefficient, gain error 1 V scale – – 0.03 %FSR / °C Figure 11-37. VDAC INL vs Input Code, 1 V Mode Document Number: 001-66236 Rev. *D 4 V scale – – 0.03 %FSR / °C 4 V slow mode – – 100 µA 4 V fast mode – – 500 µA 1 V slow mode – – 300 µA 1 V fast mode – – 600 µA Figure 11-38. VDAC DNL vs Input Code, 1 V Mode Page 74 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 11-39. VDAC INL vs Temperature, 1 V Mode Figure 11-42. VDAC DNL vs Temperature, 1 V Mode Figure 11-40. VDAC Full Scale Error vs Temperature, 1 V Mode Figure 11-43. VDAC Full Scale Error vs Temperature, 4 V Mode Figure 11-41. VDAC Operating Current vs Temperature, 1 V Mode, Slow Mode Figure 11-44. VDAC Operating Current vs Temperature, 1 V Mode, Fast Mode Document Number: 001-66236 Rev. *D Page 75 of 97 PSoC® 5: CY8C52 Family Datasheet Table 11-24. VDAC AC Specifications Parameter FDAC Description Update rate Conditions Min Typ Max Units 1 V scale – – 1000 ksps 4 V scale – – 250 ksps – 0.45 1 µs TsettleP Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF 75% 4 V scale, Cload = 15 pF – 0.8 4 µs TsettleN Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF 25% – 0.45 1 µs 4 V scale, Cload = 15 pF – 0.7 4 µs Range = 1 V, fast mode, Vdda = 5 V, 10 kHz – 750 – nV/sqrtHz Voltage noise Figure 11-45. VDAC Step Response, Codes 0x40 - 0xC0, 1 V Mode, Fast Mode, Vdda = 5 V Figure 11-47. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V Mode, Fast Mode, Vdda = 5 V Figure 11-46. VDAC PSRR vs Frequency Figure 11-48. VDAC Voltage Noise, 1 V Mode, Fast Mode, VDDA = 5 V Document Number: 001-66236 Rev. *D Page 76 of 97 PSoC® 5: CY8C52 Family Datasheet 11.5.7 LCD Direct Drive Table 11-25. LCD Direct Drive DC Specifications Parameter Description Conditions Min Typ Max Units Bus clock = 3 MHz, Vddio = Vdda = 3 V, 4 commons, 16 segments, 1/4 duty cycle, 50 Hz frame rate, no glass connected – 63 – A – 148 – µA 2.09 – 5.2 V ICC LCD system operating current ICC_SEG Current per segment driver VBIAS LCD bias range (VBIAS refers to the 3 V VBIAS VDDIO for the drive pin main output voltage(V0) of LCD DAC) IOUT LCD bias step size 3 V VBIAS VDDIO for the drive pin – 25.8 – mV LCD capacitance per segment/common driver Drivers may be combined – 500 5000 pF Long term segment offset VBIAS VDDA – 0.5 V – – 20 mV Output drive current per segment driver Vddio = 5.5V 90 – 165 µA Min 10 Typ 50 Max 150 Units Hz Table 11-26. LCD Direct Drive AC Specifications Parameter Description LCD frame rate fLCD Document Number: 001-66236 Rev. *D Conditions Page 77 of 97 PSoC® 5: CY8C52 Family Datasheet 11.6 Digital Peripherals Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. 11.6.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for more information, see the Timer component data sheet in PSoC Creator. Table 11-27. Timer DC Specifications Parameter Description 16-bit timer block current consumption Min Typ Max Units Input clock frequency – 3 MHz Conditions – 65 – µA Input clock frequency –12 MHz – 170 – µA Input clock frequency – 40 MHz – 650 – µA Min Typ Max Units DC – 40.01 MHz Table 11-28. Timer AC Specifications Parameter Description Conditions Operating frequency Capture pulse width (Internal) 25 – – ns Capture pulse width (external) 30 – – ns Timer resolution 25 – – ns Enable pulse width 25 – – ns Enable pulse width (external) 30 – – ns Reset pulse width 25 – – ns Reset pulse width (external) 30 – – ns 11.6.2 Counter The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in UDBs; for more information, see the Counter component data sheet in PSoC Creator. Table 11-29. Counter DC Specifications Parameter Description Block current consumption Conditions 16-bit counter, at listed input clock frequency 3 MHz 12 MHz 40 MHz Min – Typ – Max – Units µA – – – 15 60 260 – – – µA µA µA Min DC 25 25 25 30 25 30 25 30 Typ – – – – Max 40.01 – – – – – – – – – – – Units MHz ns ns ns ns ns ns ns ns Table 11-30. Counter AC Specifications Parameter Description Operating frequency Capture pulse Resolution Pulse width Pulse width (external) Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) Document Number: 001-66236 Rev. *D Conditions Page 78 of 97 PSoC® 5: CY8C52 Family Datasheet 11.6.3 Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component data sheet in PSoC Creator. Table 11-31. PWM DC Specifications Parameter Description Min Typ Max Units Input clock frequency – 3 MHz – 65 – µA Input clock frequency –12 MHz – 170 – µA Input clock frequency – 40 MHz – 650 – µA Min Typ Max Units Operating frequency DC – 40.01 MHz Pulse width 25 – – ns Pulse width (external) 30 – – ns Kill pulse width 25 – – ns Kill pulse width (external) 30 – – ns Enable pulse width 25 – – ns Enable pulse width (external) 30 – – ns Reset pulse width 25 – – ns Reset pulse width (external) 30 – – ns 16-bit PWM block current consumption Conditions Table 11-32. PWM AC Specifications Parameter Description Conditions 11.6.4 I2C Table 11-33. Fixed I2C DC Specifications Parameter Description Block current consumption Conditions Min Typ Max Units Enabled, configured for 100 kbps – 90 250 µA Enabled, configured for 400 kbps – 100 250 µA Conditions Min Typ Max Units – – 400 Kbps Table 11-34. Fixed I2C AC Specifications Parameter Description Bit rate Document Number: 001-66236 Rev. *D Page 79 of 97 PSoC® 5: CY8C52 Family Datasheet 11.6.5 USB Table 11-35. USB DC Specifications Parameter Description VUSB_5 Device supply for USB operation VUSB_3.3 IUSB_Configured IUSB_Suspended Conditions Min Typ Max Units USB configured, USB regulator enabled 4.35 – 5.25 V USB configured, USB regulator bypassed 3.15 – 3.6 V – 55 – mA – 40 – mA Device supply current in device active VDDD = 5 V, bus clock 33 MHz mode VDDD = 3.3 V, bus clock 33 MHz Device supply current in device sleep VDDD = 5 V, connected to USB host mode VDDD = 3.3 V, connected to USB host – 0.5 – mA – 0.5 – mA 11.6.6 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Table 11-36. UDB AC Specifications Parameter Description Conditions Min Typ Max Units FMAX_TIMER Maximum frequency of 16-bit timer in a UDB pair – – 40.01 MHz FMAX_ADDER Maximum frequency of 16-bit adder in a UDB pair – – 40.01 MHz – – 40.01 MHz – – 40.01 MHz Datapath Performance FMAX_CRC Maximum frequency of 16-bit CRC/PRS in a UDB pair PLD Performance FMAX_PLD Maximum frequency of a two-pass PLD function in a UDB pair Clock to Output Performance tCLK_OUT Propagation delay for clock in to data 25 °C out, see Figure 11-49. – 20 28 ns tCLK_OUT Propagation delay for clock in to data Worst-case placement, routing, out, see Figure 11-49. and pin selection – – 55 ns Document Number: 001-66236 Rev. *D Page 80 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 11-49. Clock to Output Performance 11.7 Memory Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. 11.7.1 Flash Table 11-37. Flash DC Specifications Parameter Description Erase and program voltage Conditions VDDD pin Min Typ Max Units 2.7 – 5.5 V Min Typ Max Units Table 11-38. Flash AC Specifications Parameter Description Conditions TWRITE Row write time (erase + program) – 8.3 32 ms TBULK Bulk erase time (256 KB) 10 °C < average ambient temp. TA < 40 °C – 117 440 ms Sector erase time (16 KB) 10 °C < average ambient temp. TA < 40 °C – 6.3 26 ms Total device programming time No overhead[32] – 9 32.5 seconds Flash data retention time, retention period measured from last erase cycle Average ambient temp. TA 55 °C, 100 K erase/program cycles 20 – – years Average ambient temp. TA 70 °C, 10 K erase/program cycles 10 – – TPROG Note 32. See application note AN64359 for a description of a low-overhead method of programming PSoC 5 flash. Document Number: 001-66236 Rev. *D Page 81 of 97 PSoC® 5: CY8C52 Family Datasheet 11.7.2 EEPROM Table 11-39. EEPROM DC Specifications Parameter Description Conditions Erase and program voltage Min Typ Max Units 2.7 – 5.5 V Table 11-40. EEPROM AC Specifications Parameter TWRITE Min Typ Max Units Single row erase/write cycle time Description Conditions – 8.3 32 ms EEPROM data retention time, retention Average ambient temp, TA 55 °C, period measured from last erase cycle 1M erase/program cycles 20 – – years Min Typ Max Units SRAM retention voltage 1.2 – – V EEPROM data retention time, retention Average ambient temp, TA 25 °C, period measured from last erase cycle 1M erase/program cycles 20 – – years Average ambient temp, TA 55 °C, 100 K erase/program cycles 20 – – Average ambient temp. TA 85 °C, 10 K erase/program cycles 10 – – Conditions Min Typ Max Units DC – 40.01 MHz 11.7.3 SRAM Table 11-41. SRAM DC Specifications Parameter VSRAM Description Conditions Table 11-42. SRAM AC Specifications Parameter FSRAM Description SRAM operating frequency 11.7.4 Write Once Latch (WOL) Table 11-43. WOL DC Specifications Parameter Min Typ Max Units Program voltage Description VDDD pin 2.7 – 3.3 V Program temperature TJ 10 25 40 °C Document Number: 001-66236 Rev. *D Conditions Page 82 of 97 PSoC® 5: CY8C52 Family Datasheet 11.8 PSoC System Resources Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. 11.8.1 Voltage Monitors Table 11-44. Voltage Monitors DC Specifications Parameter LVI HVI Description Conditions Min Typ Max Units LVI_A/D_SEL[3:0] = 0011b 2.38 2.45 2.53 V LVI_A/D_SEL[3:0] = 0100b 2.62 2.71 2.79 V LVI_A/D_SEL[3:0] = 0101b 2.87 2.95 3.04 V LVI_A/D_SEL[3:0] = 0110b 3.11 3.21 3.31 V LVI_A/D_SEL[3:0] = 0111b 3.35 3.46 3.56 V LVI_A/D_SEL[3:0] = 1000b 3.59 3.70 3.81 V LVI_A/D_SEL[3:0] = 1001b 3.84 3.95 4.07 V LVI_A/D_SEL[3:0] = 1010b 4.08 4.20 4.33 V LVI_A/D_SEL[3:0] = 1011b 4.32 4.45 4.59 V LVI_A/D_SEL[3:0] = 1100b 4.56 4.70 4.84 V LVI_A/D_SEL[3:0] = 1101b 4.83 4.98 5.13 V LVI_A/D_SEL[3:0] = 1110b 5.05 5.21 5.37 V LVI_A/D_SEL[3:0] = 1111b 5.30 5.47 5.63 V 5.57 5.75 5.92 V Min Typ Max Units – 1 – µs Trip voltage Trip voltage Table 11-45. Voltage Monitors AC Specifications Parameter Description Conditions Response time[33] 11.8.2 Interrupt Controller Table 11-46. Interrupt Controller AC Specifications Parameter Description Conditions Min Typ Max Units Delay from interrupt signal input to ISR code execution from main line code[34] – – 12 Tcy CPU Delay from interrupt signal input to ISR code execution from ISR code (tail-chaining)[34] – – 6 Tcy CPU Notes 33. Based on device characterization (Not production tested). 34. ARM Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU. Document Number: 001-66236 Rev. *D Page 83 of 97 PSoC® 5: CY8C52 Family Datasheet 11.8.3 SWD Interface Figure 11-50. SWD Interface Timing (1/f_SWDCK) SWDCK T_SWDI_setup T_SWDI_hold SWDIO (PSoC 5 reading on SWDIO ) T_SWDO_valid SWDIO (PSoC 5 writing to SWDIO) Table 11-47. SWD Interface AC Specifications[35] Parameter Description Conditions Min Typ Max Units MHz 3.3 V VDDD 5 V – – 12[37] 2.7 V VDDD < 3.3 V – – 6.5[37] MHz – – 5[37] MHz T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDI_hold T = 1/f_SWDCK max T/4 – – T = 1/f_SWDCK max – – 2T/5 Min Typ Max Units – – 33[38] Mbit f_SWDCK SWDCLK frequency 2.7 V VDDD < 3.3 V, SWD over USBIO pins SWDIO input hold after SWDCK high T_SWDO_valid SWDCK high to SWDIO output 11.8.4 TPIU Interface Table 11-48. TPIU Interface AC Specifications[35] Parameter Description Conditions SWV bit rate Notes 35. Based on device characterization (Not production tested). 36. f_TCK must also be no more than 1/3 CPU clock frequency. 37. f_SWDCK must also be no more than 1/3 CPU clock frequency. 38. SWV signal frequency and bit rate are limited by GPIO output frequency, see “GPIO AC Specifications” on page 59. Document Number: 001-66236 Rev. *D Page 84 of 97 PSoC® 5: CY8C52 Family Datasheet 11.9 Clocking Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.9.1 kHz External Crystal Oscillator (kHzECO) For more information on crystal selection for the kHzECO, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. Table 11-49. kHz ECO DC Specifications Parameter Description IDD Oscillator operating current Capacitance at Pins kHz-XTAL:Xi and CIN kHz-XTAL:Xo[39] Conditions Low power mode; CL = 6 pF Min – – Typ 0.25 5 Max – 7 Units µA pF Min – – 1 Typ 32.768 6 or 12.5 – Max – – – Units kHz pF µW Min Typ Max Units – – – – 195 150 120 105 500 450 400 300 µA µA µA µA Table 11-50. kHz ECO Crystal Specifications Parameter Description F Crystal frequency Crystal load capacitance CL Crystal drive level tolerance DL Conditions Recommended values 11.9.2 Internal Main Oscillator Table 11-51. IMO DC Specifications Parameter Description Supply current 24 MHz 12 MHz 6 MHz 3 MHz Conditions Note 39. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 85 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 11-51. IMO Current vs. Frequency Table 11-52. IMO AC Specifications Parameter Description Conditions Min Typ Max Units 24 MHz –8 – 8 % 12 MHz –6.25 – 6.25 % 6 MHz –5.8 – 5.8 % –5 – 5 % – – 12 µs F = 24 MHz – 0.5 – ns F = 3 MHz – 2.3 – ns IMO frequency stability (with factory trim) FIMO 3 MHz Startup time[40] From enable (during normal system operation) or wakeup from low power state Jitter (peak to peak)[40] Jp-p Figure 11-52. IMO Frequency Variation vs. Temperature Figure 11-53. IMO Frequency Variation vs. VDDD Note 40. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 86 of 97 PSoC® 5: CY8C52 Family Datasheet 11.9.3 Internal Low Speed Oscillator Table 11-53. ILO AC Specifications Parameter Description Min Typ Max Units – – 2.5 ms 100 kHz 45 100 200 kHz 1 kHz 0.5 1 2 kHz 100 kHz 30 100 300 kHz 1 kHz 0.3 1 3.5 kHz Startup time, all frequencies Conditions Turbo mode ILO frequencies (trimmed) FILO ILO frequencies (untrimmed) Figure 11-54. ILO Frequency Variation vs. Temperature Figure 11-55. ILO Frequency Variation vs. VDD 11.9.4 MHz External Crystal Oscillator (MHzECO) For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. Table 11-54. MHzECO Crystal Specifications Parameter Description F Crystal frequency CL Crystal load capacitance C0 Crystal shunt capacitance ESR Crystal effective series resistance DL Crystal drive level tolerance CIN Capacitance at Pins MHz-XTAL:Xi and MHz-XTAL:Xo[41] Conditions Min Typ Max Units 4 – 25 MHz – – 20 pF – – 7 pF 4 MHz ≤ F < 8 MHz – – 125 Ω 8 MHz ≤ F < 12 MHz – – 75 Ω 12 MHz ≤ F ≤ 25 MHz – – 50 Ω No Rs, see AN54439 500 – – 4 – – μW pF Note 41. Based on device characterization (Not production tested). Document Number: 001-66236 Rev. *D Page 87 of 97 PSoC® 5: CY8C52 Family Datasheet 11.9.5 External Clock Reference Table 11-55. External Clock Reference AC Specifications[42] Parameter Description Conditions External frequency range Min Typ Max Units 0 – 33 MHz Input duty cycle range Measured at VDDIO/2 30 50 70 % Input edge rate VIL to VIH 0.5 – – V/ns Min Typ Max Units – 200 – µA Min Typ Max Units 1 – 40 MHz 1 – 3 MHz 24 – 40 MHz 11.9.6 Phase-Locked Loop Table 11-56. PLL DC Specifications Parameter IDD Description PLL operating current Conditions In = 3 MHz, Out = 24 MHz Table 11-57. PLL AC Specifications Parameter Fpllin Description PLL intermediate Fpllout Conditions PLL input frequency[43] PLL output frequency[44] frequency[43] Lock time at startup Jperiod-rms Jitter (rms)[42] Output of prescaler – – 250 µs – – 400 ps Notes 42. Based on device characterization (Not production tested). 43. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 44. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. Document Number: 001-66236 Rev. *D Page 88 of 97 PSoC® 5: CY8C52 Family Datasheet 12. Ordering Information In addition to the features listed in Table 12-1, every CY8C52 device includes: up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C52 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details. Table 12-1. CY8C52 Family with ARM Cortex-M3 CPU I/O[46] Digital FS USB Total I/O GPIO SIO USBIO ✔ 24 4 ✔ 46 36 8 2 ✔ 24 4 ✔ 70 60 8 2 UDBs[45] – – CapSense – – DFB – – Opamps 2 2 Comparators 1 1 DAC 1x12-bit SAR 1x12-bit SAR ADC ✔ ✔ EEPROM (KB) 2 2 SRAM (KB) 40 256 64 40 256 64 Flash (KB) CY8C5248LTI-030 CY8C5248AXI-047 Part Number CPU Speed (MHz) 16-bit Timer/PWM SC/CT Analog Blocks Analog LCD Segment Drive MCU Core Device ID[47] Package CY8C5247LTI-089 40 128 32 2 ✔ 1x12-bit SAR 1 2 – – – ✔ 24 4 ✔ 46 36 8 2 CY8C5247AXI-051 40 128 32 2 ✔ 1x12-bit SAR 1 2 – – – ✔ 24 4 ✔ 70 60 8 2 CY8C5246LTI-029 40 64 16 2 ✔ 1x12-bit SAR 1 2 – – – ✔ 24 4 ✔ 46 36 8 2 CY8C5246AXI-054 40 64 16 2 ✔ 1x12-bit SAR 1 2 – – – ✔ 24 4 ✔ 70 60 8 2 68-pin QFN 0x0E11E069 100-pin TQFP 0x0E12F069 68-pin QFN 0x0E159069 100-pin TQFP 0x0E133069 68-pin QFN 0x0E11D069 100-pin TQFP 0x0E136069 12.1 Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A, B, …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC 5 b: Family group within architecture 2: CY8C52 family 3: CY8C53 family 4: CY8C54 family 5: CY8C55 family c: Speed grade 4: 40 MHz 6: 67 MHz ef: Package code Two character alphanumeric AX: TQFP LT: QFN g: Temperature range C: commercial I: industrial A: automotive xxx: Peripheral set Three character numeric No meaning is associated with these three characters d: Flash capacity 5: 32 KB 6: 64 KB 7: 128 KB 8: 256 KB Notes 45. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 32 for more information on how UDBs can be used. 46. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 25 for details on the functionality of each of these types of I/O. 47. The device ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Document Number: 001-66236 Rev. *D Page 89 of 97 PSoC® 5: CY8C52 Family Datasheet Examples CY8C 5 2 4 8 AX /LT I - x x x Cypress Prefix 5: PSoC 5 Architecture 2: CY8C52 Family Family Group within Architecture 4: 40 MHz Speed Grade 8: 256 KB Flash Capacity AX: TQFP, LT: QFN Package Code Temperature Range I: Industrial Peripheral Set All devices in the PSoC 5 CY8C52 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration data sheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of life” requirements. 13. Packaging Table 13-1. Package Characteristics Parameter TA TJ Tja Tja Tjc Tjc Description Operating ambient temperature Operating junction temperature Package JA (68-pin QFN) Package JA (100-pin TQFP) Package JC (68-pin QFN) Package JC (100-pin TQFP) Conditions Min –40 –40 – – – – Typ 25 – 15 34 13 10 Max 85 100 – – – - Units °C °C °C/Watt °C/Watt °C/Watt °C/Watt Table 13-2. Solder Reflow Peak Temperature Package 68-pin QFN 100-pin TQFP Maximum Peak Temperature 260 °C 260 °C Maximum Time at Peak Temperature 30 seconds 30 seconds Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 68-pin QFN MSL 3 100-pin TQFP MSL 3 Document Number: 001-66236 Rev. *D Page 90 of 97 PSoC® 5: CY8C52 Family Datasheet Figure 13-1. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version) 001-09618 *D Figure 13-2. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline 51-85048 *E Document Number: 001-66236 Rev. *D Page 91 of 97 PSoC® 5: CY8C52 Family Datasheet Table 14-1. Acronyms Used in this Document (continued) 14. Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB Acronym Description HVI high-voltage interrupt, see also LVI, LVD IC integrated circuit IDAC current DAC, see also DAC, VDAC IDE integrated development environment AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus I2C, or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse response, see also FIR ALU arithmetic logic unit ILO internal low-speed oscillator, see also IMO AMUXBUS analog multiplexer bus IMO internal main oscillator, see also ILO API application programming interface INL integral nonlinearity, see also DNL APSR application program status register I/O input/output, see also GPIO, DIO, SIO, USBIO ARM® advanced RISC machine, a CPU architecture IPOR initial power-on reset ATM automatic thump mode IPSR interrupt program status register BW bandwidth IRQ interrupt request CMRR common-mode rejection ratio ITM instrumentation trace macrocell CPU central processing unit LCD liquid crystal display CRC cyclic redundancy check, an error-checking protocol LIN Local Interconnect Network, a communications protocol. DAC digital-to-analog converter, see also IDAC, VDAC LR link register DFB digital filter block LUT lookup table DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. LVD low-voltage detect, see also LVI DMA direct memory access, see also TD LVI low-voltage interrupt, see also HVI DNL differential nonlinearity, see also INL LVTTL low-voltage transistor-transistor logic DNU do not use MAC multiply-accumulate DR port write data registers MCU microcontroller unit DSI digital system interconnect DWT data watchpoint and trace ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin Document Number: 001-66236 Rev. *D MISO master-in slave-out NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board PGA programmable gain amplifier PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array Page 92 of 97 PSoC® 5: CY8C52 Family Datasheet Table 14-1. Acronyms Used in this Document (continued) Acronym Description PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration data sheet POR power-on reset PRS pseudo random sequence PS port read data register PSoC® Programmable System-on-Chip™ PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RSVD reserved RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT Table 14-1. Acronyms Used in this Document (continued) Acronym SPI Description Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA THD total harmonic distortion TIA transimpedance amplifier TRM technical reference manual TTL transistor-transistor logic TX transmit UART Universal Asynchronous Transmitter Receiver, a communications protocol UDB universal digital block USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to a USB port switched capacitor/continuous time VDAC voltage DAC, see also DAC, IDAC SCL I2C WDT watchdog timer SDA I2C serial data WOL write once latch, see also NVL S/H sample and hold WRES watchdog timer reset SIO special input/output, GPIO with advanced features. See GPIO. XRES external reset I/O pin SNR signal-to-noise ratio XTAL crystal SOC start of conversion 15. Reference Documents SOF start of frame PSoC® 3, PSoC® 5 Architecture TRM serial clock PSoC® 5 Registers TRM Document Number: 001-66236 Rev. *D Page 93 of 97 PSoC® 5: CY8C52 Family Datasheet 16. Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz k kilohms ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M megaohms Msps megasamples per second µA microamperes µF microfarads µH microhenrys µs microseconds µV microvolts µW microwatts mA milliamperes ms milliseconds mV millivolts nA nanoamperes ns nanoseconds nV nanovolts ohms pF picofarads ppm parts per million ps picoseconds s seconds sps samples per second sqrtHz square root of hertz V volts Document Number: 001-66236 Rev. *D Page 94 of 97 PSoC® 5: CY8C52 Family Datasheet 17. Revision History Description Title: PSoC® 5: CY8C52 Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-66236 Revision ECN Submission Date Orig. of Change Description of Change ** 3198501 03/17/2011 MKEA New data sheet. *A 3279676 06/10/2011 MKEA Changed MHzECO range Updated Flash and EEPROM AC specs Added solder reflow peak temperature table Changed IDAC IDD numbers and VDAC Added flash retention specs Added JTAG and SWD interface diagrams Removed mention of comparator wakeup from sleep Updated PSoC Power system diagram Updated opamp DC specs table Updated SAR electrical specs Updated clocking sections Removed references to JTAG interface Updated and I/O graphs Added note that Interrupt Specs are ARM Specs Changed JTAG and SWD max speeds Modified ILO startup time Removed references to ETM and TRACEPORT Updated IDAC range limits Updated Vddio pin description Updated Power Modes section Added note on watchdog timer in the Reset section Updated ESDHBM value Updated Boost Converter section *B 3359654 09/01/2011 MKEA Removed Boost regulator Removed Temperature Sensor specifications Updated device DC and AC specifications Updated Cortex-M3 bitband information Updated cache controller information Updated GPIO and SIO DC specifications Updated IDAC AC specifications Updated Analog global specifications Updated Fixed function PWM and Timer DC specifications Changed fixed function I2C max bus speed Added note on undefined I2C bus conditions Updated USB DC specifications Updated USB driver AC specification Updated information to include 24 MHz ECO and 33 MHz bus clock for USB function Updated kHzECO and MHzECO Specifications Updated IMO AC specifications Updated PLL AC specifications Updated SWD interface section Updated Device IDs *C 3422215 10/25/2011 MKEA Changed ESDHBM value to 750 Changed Min value of Input Edge Rate to 0.5 V/ns. Updated Low Power mode information throughout document Document Number: 001-66236 Rev. *D Page 95 of 97 PSoC® 5: CY8C52 Family Datasheet Description Title: PSoC® 5: CY8C52 Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-66236 *D 3428148 02/15/2012 Document Number: 001-66236 Rev. *D WKA/MKEA Moved status from Preliminary to Final. Changed pins 5, 7, and 8 to VSSD and pin 6 to DNU in 68-pin QFN pinout. Changed pins 10, 12, and 13 to VSSD and pin 11 to DNU in 100-pin TQFP pinout. Changed pins 10, 12, and 13 to VSSD and pin 11 to DNU in Typical Application Schematic. Updated latch up spec in Table 11-1. Updated IDD parameter (Active mode) in Table 11-2. Updated sleep and hibernate current. Updated pinout diagrams (Figure 2-1, Figure 2-2, and Figure 2-3) Updated latch up current specification (Table 11-1) Updated ESDHBM specification (Table 11-1) Updated active, sleep and hibernate modes current specifications (Table 11-2, Table 6-3). Added active mode current graph. (Figure 11-1). Updated Table 11-2. Updated Table 11-2 to include rows for IDDAR and IDDDR. Updated “DAC” section on page 48. Added note on strobing DAC twice. Updated “SIO” section on page 60. Added note on conditions for SIO to draw excess current. Updated “USB” section on page 41. Added note on required clock sources for using USB. Updated LVI / HVI table in Section 6 (Table 6-4, Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt). Updated GPIO block diagram (Figure 6-7). Updated Table 11-1 IVDDIO spec to have two sub-rows Updated note about max VDDIO current sink capability Updated GPIO, SIO and USBIO graphs (Figure 11-5, Figure 11-6, Figure 11-7, Figure 11-8, Figure 11-9, Figure 11-10, Figure 11-11, Figure 11-12, Figure 11-13, Figure 11-14, Figure 11-15, Figure 11-16) Updated IDAC and VDAC graphs Updated SAR ADC graphs Updated “Reset” section on page 24. More details given to distinguish External Reset (XRES) from Power-on Reset Fixed typos: Replaced “CY8C38” with “PSoC 5" and “CY8C32” to “CY8C52”. Updated the graphs under “Internal Main Oscillator” section on page 85 section. Updated f_SWDCK, SWDCLK frequency max values Table 11-3, Updated TSLEEP parameter . Updated and clarified specifications and conditions for sleep mode. Page 96 of 97 PSoC® 5: CY8C52 Family Datasheet 18. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC Solutions Automotive Clocks & Buffers Interface cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. 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