PSoC 4 Scanning SAR ADC (Scan_ADC) 1.10.pdf

PSoC® Creator™ Component Datasheet
PSoC 4 Scanning SAR ADC (Scan_ADC)
1.10
Features
 Selectable 8-, 10-, or 12-bit resolution
 Interleaved or channel-sequential averaging in hardware
 Up to 16-bit resolution with averaging
 Aggregate sample rate up to 1 Msps
 Single-ended and Differential input modes
 Optional 2nd order switched-cap filter on channel 0
 Scheduler optimizes settling time and clock to fit scan rate
 Scan up to sixteen analog signals automatically
General Description
The Scanning SAR ADC component gives configuration-, schematic-, and firmware-level support
for the version of the SAR (‘Successive Approximation Register’) ADC present on some
members of the PSoC family. Up to sixteen analog channels (from sources dependent on the
specific device) can be automatically scanned, either on demand or continuously, with the results
placed in individual result registers. One of the channels may be routed through a 2nd order
switched-cap filter. The scan scheduler adjusts internal sampling behavior and clock to
accommodate specific settling time and overall scan rate requirements. Averaging can be
applied to any channel in a scan.
When to Use a Scanning SAR ADC
The Scanning SAR ADC is the component used to access the ADC functionality in members of
the ‘PSoC Analog Coprocessor’ family. It is flexible and versatile in both high sample rate
continuous-sampling applications (timed entirely in hardware), and lower-rate ad-hoc triggered
scan applications.
The offset and span of the ADC depend on the parameters configured for the component.
Regardless of these settings, the analog signals connected to the PSoC’s pins must be between
VSSA and VDDA. For some settings, ‘rail-to-rail’ conversion is possible.
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Document Number: 002-13264 Rev. **
Revised May 26, 2016
PSoC® Creator™ Component Datasheet
PSoC 4 Scanning SAR ADC (Scan_ADC)
Input/Output Connections
This section describes the various input and output connections for the Scanning SAR ADC that
may appear as terminals on the component symbol. An asterisk (*) after the terminal name
indicates that the terminal may not be present on the symbol under certain conditions.
Note Throughout this document when signal connections are abbreviated, ‘s/e’ means singleended, ‘diff’ means differential.
Note During the sampling time for a given channel, its +Input, -Input, and/or vneg input signals
connect directly to the input capacitor of the ADC core, and must charge that capacitor up before
the actual conversion. An input settling time value can be entered into each channel’s parameter
selections to allow for that channel’s source impedance.
+Input – Analog
This input (not marked; it is always the upper terminal of a differential input pair on the symbol) is
the ‘positive’ (also called non-inverting) analog signal input to the ADC. There are always the
same number of ‘positive’ analog signal input terminals as there are channels selected, whether
they are specified as differential or single-ended.
–Input – Analog *
This input (not marked; it is always the lower terminal of a differential input pair on the symbol) is
the ‘negative’ (also called inverting) analog signal input to the ADC. It is only present for
channels that have been declared as differential. On all channels declared as single-ended
channels, the inverting input of the ADC is connected instead to the Vneg signal, described
below. There are always the same number of ‘negative’ analog signal input terminals as there
are differential channels selected.
vneg – Analog Input*
This is a common negative input reference. This terminal is present only if one or more analog
channels are declared as a single-ended input and the Vneg for S/E parameter is set to
External.
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PSoC 4 Scanning SAR ADC (Scan_ADC)
soc – Digital Input *
This terminal is present if the “Use signal on soc terminal” box is checked. See the Sample
Mode section for a description of how the soc terminal is used by the component.
PSoC Creator components can be stopped and started with firmware API calls. To allow for
circuit stabilization, the first soc rising edge should be generated at least 10 us after calling the
ADC_Start() function.
vagnd – Analog Input *
This terminal appears on the symbol if the filter function available on channel 0 is enabled. It is
intended to be connected to the locally-generated voltage used for referencing analog signals
(sometimes called Analog ground) and is connected by the user.
vref – Analog Input *
This terminal appears on the symbol if the Vref parameter is set to Symbol terminal voltage.
aclk – Clock Input *
This terminal allows a PSoC clock to be connected to the component. This mode is used when it
is important that the clock used by the ADC is identical to that used by another component on
the schematic.
You can add this optional terminal if you check the ‘Show analog clock (aclk) terminal’
selection, otherwise, the terminal is hidden. Without this terminal, the component will auto-select
the ADC clock frequency, which may allow closer matching of user-specified sample rate.
sdone – Digital Output
This signal goes high for two ADC clock cycles to indicate that the ADC has sampled the current
input channel. Internally, this signal is used to advance the signal multiplexer onto the next
channel.
eos – Digital Output
A rising edge on the end of scan (eos) output means that the current scan is complete. At this
moment, conversion result registers contain valid sample data for all enabled channels. Internally,
it is used to provide an interrupt.
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PSoC 4 Scanning SAR ADC (Scan_ADC)
Component Parameters
This section covers the various parameters that can be altered or inspected through the setup
customizer of the component, grouped within a series of tabs. To explore this, drag a Scanning
SAR ADC onto your design and double click it to open the Configure dialog. For any selectable
parameter, the option shown here in bold is the default.
Config Tab – Scan Sub-Tab
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PSoC 4 Scanning SAR ADC (Scan_ADC)
Timing
Free-run scan rate (SPS)
This is the fundamental parameter for the Scanning SAR ADC; the desired rate at which
completed scans should be executed when the component is running in Continuous mode. It is
the rate at which each signal included in the scan is sampled. The Scanning SAR ADC
component customizer has a schedule calculator that works to get this sample rate as close as
possible to the value that is entered. It does this by intelligent selection of ADC clock frequency
(when an internal clock source is selected) and channel sampling times, taking all the other userentered requirements into account.
When selected, the ADC clock rate is automatically calculated based on the number of channels,
averaging, resolution, and acquisition time parameters to meet the entered sample rate.
Achieved (display only)
This field displays the currently-achieved scan rate that the component will implement in a
running system. The scheduler adjusts everything available to get as close as it can to the
desired scan rate, but this is not always possible.
Available rates (display only)
This field shows the approximate minimum to maximum range of scan rates that can currently be
attained with the setup as defined. This field will change based on channel parameters, such as
acquisition time and whether averaging is used. If the desired free-running rate is less than the
minimum rate shown here, the solution is to set up a TC/PWM timer on the schematic and use it
to trigger the ADC periodically (in single shot triggered mode).
ADC clock rate (display only)
This field displays the currently-selected actual ADC clock frequency. It is an integer divide from
the PSoC’s main high frequency clock.
Scan Duration (display only)
This field gives the duration of the achieved overall scan, in ns.
Sample Mode
The Scanning SAR ADC can operate in one of two modes:
Sample mode
Description
Continuous
Once started, Scanning SAR ADC runs continuously until stopped
Single shot
Scanning SAR ADC takes one scan per valid firmware or hardware trigger
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PSoC 4 Scanning SAR ADC (Scan_ADC)
Use soc terminal
The Scanning SAR ADC can always be started and stopped in firmware with the
ADC_StartConvert() and ADC_StopConvert() functions.
If this box is checked, hardware triggering via the start-of-conversion (soc) terminal on the
component is enabled. The soc terminal is created on the component symbol by checking the
“Use signal on soc terminal” on the Scan sub tab.
With this hardware triggering enabled, in single-shot mode a single complete scan of the
Scanning SAR ADC is triggered by a positive-going edge applied to the soc terminal. In
continuous mode, the ADC takes scans back-to-back if a ‘1’ level is applied to the soc terminal.
Enabling hardware triggering does not suppress the firmware triggering function. Exercise
caution in interpreting data sets resulting from a combination of both forms of triggering, since
the trigger source is not reflected in the output data.
Input range
Vref select
The Vref parameter selects the reference voltage source that is used for the ADC core, and
optionally enables a numeric value to be given to it if the customizer does not know it.
Reference
Description
Design-wide reference
This is the reference voltage that is assigned by Creator for multiple use in the design.
System Bandgap
Dedicated internal connection to the main 1.2 V reference
Symbol terminal
The voltage fed to this terminal on the symbol is used as the reference
External device pin
Depending on the device part number, this pin is a dedicated or shared pin, used both
for the Vref off-chip bypass capacitor and for the injection of a reference external to the
chip.
Vdda/2
An internal resistor divider produces Vdda/2 as a reference
Vdda
Uses the internal Vdda. An off-chip bypass capacitor has no effect in this mode.
The internal Vref startup time varies with different bypass capacitors. This table lists two
common values for the bypass capacitor and its startup time specification.
Internal Vref Startup Time
Maximum Specification
Startup time for reference with external capacitor (1 µF)
2 ms
Startup time for reference with external capacitor (100 nF)
200 µs
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PSoC 4 Scanning SAR ADC (Scan_ADC)
Vref value (user entry or parameter display)
To the right of the Vref select pull-down, this parameter either displays the reference voltage
value that is being used for the SAR ADC (if this is ‘known’ to PSoC Creator) or enables the
entry of a value for display purposes, if only the user knows this value.
Vref bypass
Checking this box indicates to the component customizer that you have attached an off-chip
bypass capacitor to the specific device pin set aside for this. It permits the component to select
higher ADC clock rates and therefore significantly higher overall scan rates.
The use of an off-chip reference bypass capacitor (33 nF or greater, X7R dielectric or better) is
recommended in all systems. It should only be omitted when there is really no room for it on the
build. When omitted, the maximum aggregate sample rate is reduced by at least a factor of
eighteen, and conversions are more prone to digital noise on the circuit board.
Vneg for S/E
This parameter selects where the negative input to the SAR ADC is connected if any channels
are configured for single-ended operation.
Negative input
Description
Vssa
Input range is 0.0 to Vref, effective resolution will be one bit less than selected in
the customizer.
Vref
Input range is 0.0 to Vref*2.
External
This mode is configured for “quasi-differential” inputs. Multiple channels share one
common –ve (inverting) connection. This is often used for common-mode rejection
of ground noise in multi-channel systems.
12-bit code range (display only)
This field displays what code ranges will be returned by the SAR ADC. The values displayed are
truncated at 12-bits. However, the results returned will be sign extended to the 16 or 32 bit
format depending on which GetResult function is used.
Volt range (display only)
This field displays the voltage range of the SAR ADC using the selected Vref. For single ended
channels the selection of Vneg is also used to determine the range.
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PSoC 4 Scanning SAR ADC (Scan_ADC)
Result Data Format
Differential (Diff.) result format
This parameter determines whether or not the result from a differential measurement is Signed
or Unsigned. This is a global setting for all differential channels. Results are always rightjustified.
S/E result format
This parameter determines whether or not the result from a single-ended measurement is
Signed or Unsigned. This is a global setting for all single-ended channels. Results are always
right-justified.
The following table shows how these parameters affect conversion of the input voltage to the 12
bit digital sample value.
s/e or diff
s/e
s/e
s/e
s/e
s/e
diff
diff
Signed /
Unsigned
Single-ended
negative input
Unsigned: Use
this mode only
with caution
Vssa
Signed
Vssa
Signed
Unsigned
Signed
Unsigned
Signed
External
Vref
Vref
N/A
N/A
-Input
Vssa
Vssa
Vneg
Vref
Vref
Vx
Vx
+Input
Result Register
Vref
0x0FFF
Vssa
0x0800
-noise
0x07xx (this causes a wrap-round
in calculations)
Vref
0x07FF
Vssa
0x0000
-noise
0xFFxx
Vneg+Vref
0x07FF
Vneg
0x0000
Vneg-Vref
0xF800
2*Vref
0x0FFF
Vref
0x0800
Vssa
0x0000
2*Vref
0x07FF
Vref
0x0000
Vssa
0xF800
Vx+Vref
0x0FFF
Vx
0x0800
Vx-Vref
0x0000
Vx+Vref
0x07FF
Vx
0x0000
Vx-Vref
0xF800
For single-ended conversions with the Vneg for S/E parameter set to Vssa, the usable
conversion is effectively 11-bit. Noise or offset on the +Input terminal with a level slightly below
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PSoC 4 Scanning SAR ADC (Scan_ADC)
Vssa produces a result that appears more positive than full scale. This can cause severe system
problems, so this mode should be used with caution.
Samples averaged
This parameter sets the averaging rate for any channel with the averaging option enabled. This
is a global setting for all channels that have averaging enabled. Default value is 2.
Note that the interleaved averaging option does not support result realignment, it is a simple
accumulation. For average counts of greater than 16, it is possible (under large-signal
conditions) for the result register to overflow and wrap round. This error is not detected by the
hardware. Only use more than 16 sample averaging in interleaved mode if you are satisfied that
this wrap-round will not occur on your particular signals.
Averaging mode
This parameter sets how the hardware averaging mode operates. If Sequential, Sum is selected,
each ADC conversion result is added to a running sum. It’s then shifted so that it fits into a 16-bit
result word. If the Sequential, Fixed mode is selected, accumulated result is shifted back into a
12-bit result.
In either sequential mode, the scan pauses on the channel being averaged and all the samples
for the average are taken before moving onto the next channel in the scan. This can reduce the
maximum available scan rate substantially when any channel in the scan is averaged in this way.
For this reason, the Interleaved, Sum mode is also available. In Interleaved mode, only one
conversion is taken on each channel before moving on, but channels that have averaging
enabled get the preset number of samples accumulated in their result register.
In Interleaved, Sum mode the overall scan rate is not reduced. This means that channels not
requiring averaging can still be sampled at the original scan rate. An end of scan interrupt is still
produced at the end of every scan; channels that utilize interleaved averaging are not marked as
‘valid’ until the correct number of scans have been taken.
If every channel is set to use averaging and the mode is set to Interleaved, Sum then the rate of
end-of-scan interrupts is significantly reduced.
Alternate resolution
This parameter sets the alternate ADC resolution to either 8 or 10 bits. This alternate resolution
can be selected for any channel instead of the native 12-bit. Note that averaging always uses 12bit resolution, ignoring this parameter. The component will issue a warning if the two modes are
set together on any channel.
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Interrupt Limits
Compare mode
The Scanning SAR ADC supports range detection to allow for the automatic detection of sample
values compared to two programmable thresholds without CPU involvement. A range detect is
defined by two global thresholds and a condition.
This parameter sets the condition under which a limit condition will occur and trigger a maskable
range detect interrupt.
Compare Mode
Description
Result < Low
Below range
Low <= Result < High
Inside range
High <= Result
Above range
(Result < Low) or (High <= Result)
Outside range
Low (hex)
This parameter sets the low threshold in hex for a limit compare. Default value is 0x0200. For
Signed modes, the SAR results are two’s-complement.
High (hex)
This parameter sets the high threshold in hex for a limit compare. Default value is 0x0E00.
A range detect is done after averaging, alignment, and sign extension (if applicable). In other
words, the thresholds values must have the same data format as the final 16-bit conversion
result.
Equivalent input voltages:
Directly beneath the low and high limit entry fields, the corresponding voltage values are
displayed for individual and averaged differential and single-ended measurements.
Channels
Number of channels
This parameter selects how many input signal channels are scanned. By default, there are 2
channels. The maximum number of channels is either 8 or 16 depending on the device. It
depends also on mode (differential or single-ended) and available resources outside of the SAR.
The minimum number of channels is always 1.
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A set of parameters is available for each entry. The actual number of entries depends on the
Number of channels parameter. The symbol shows as many channels as are selected by the
Number of channels parameter even if the channel is not enabled.
Ch.
Shows the number of the channel, starting from 0. The number of entries here is determined by
the Number of Channels parameter.
En
If checked, the channel is enabled in the scan. If unchecked, no time is consumed and the scan
jumps immediately to the next enabled channel in the scan list.
Resolution
This parameter selects either 12 bits or the alternative (ALT) resolution setting.
Input mode
For any channel, this parameter selects the input mode to the ADC as either Differential or
Single ended. In addition, channel 0 can be configured to take its signal through a dedicated 2nd
order filter whose frequency response parameters can be set over a wide range. The filter has a
single-ended input, and the output of the filter is measured with respect to the voltage applied to
the vagnd terminal. See the Switched-capacitor filter section for more information about the
filter.
Avg
This option selects whether or not the channel is averaged. When selected and a sequential
averaging mode is selected, the SAR sequencer stays on the channel and takes N readings,
then adds the results together. The number of samples taken is determined by the Samples
averaged parameter. Averaging is available only for the maximum Resolution selected in a
particular channel. Select ALT resolution for all channels to allow averaging on fewer than 12 bits
resolution. Averaging is always right-aligned.
Minimum acq. time (ns)
The user can enter a minimum acquisition time (in ns) that the input sampling process will dwell
on this channel before actually making the conversion. The field is editable but is pre-populated
with the shortest value currently possible with the system clock parameters.
Achieved acq. time (ns)
This display field shows the acquisition time (in ns) that the scheduler has selected. It is always
equal to or higher (longer duration) than the user-requested value.
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Limit interrupt
This option allows you to enable an interrupt if any of the channels trigger the limit criteria set by
the Low or High thresholds and the Compare mode parameter. This interrupt triggers at the
end of the current scan.
Sat. interrupt
This option allows you to enable an interrupt from any channel where the result is saturated at
either the lowest or the highest value for the given resolution and format. This interrupt triggers
immediately.
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Config Tab – Filter Sub-Tab
This tab sets up the behavior of the 2nd order switched-capacitor filter that can optionally be
connected to channel 0 (the first channel in the scan).
Filter type
The filter implements four different response types: lowpass, highpass, bandpass and notch
(also called bandstop). The lowpass and highpass filters have a programmable stopband notch
frequency. All the filter types are calculated with the so-called maximally-flat response form, of
which the well-known Butterworth filter is a simple example.
All filters have a peak passband gain of unity, i.e. 0 dB.
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Frequency entry fields
Underneath the pull-down for filter type are two frequency entry fields, whose titles and purpose
change with the filter types.
For the lowpass and highpass filter, the user specifies the desired frequency of the -3 dB point,
and also the desired frequency of the ‘notch’ in the stopband. That can be useful for achieving
additional attenuation at a specific frequency.
For the bandpass filter, the user enters the desired frequencies for the lower and upper -3 dB
response points. This is more direct than entering a center frequency and a bandwidth, which
would not make clear where those -3 dB frequencies actually are.
For the Notch filter, the user specifies the frequency of the notch, and a -3 dB shoulder. The 3 dB shoulder can be below or above the notch frequency.
The customizer will issue appropriate errors if the user enters frequency combinations that are
not meaningful for the type of filter. Each filter type has its own stored frequency settings, so the
frequencies in the user entry boxes may change when the filter type selection is changed.
In this version of the Scanning SAR ADC there is no API function for changing the filter behavior.
This is due to the close integration of the filter clocking requirements with the acquisition timing
needs of the ADC core.
Note The filter has a single-ended input, which is referred to an ‘analog ground’ voltage which is
applied to the vagnd terminal, which is always present on the schematic if the filter has been
selected. The optimum value for this voltage is half the analog supply voltage. This voltage is
typically available through a reference voltage component on the PSoC Creator schematic. A
suitable voltage must be connected to this terminal if it is present.
Sample Frequency (kHz) (display only)
This display field shows the selected sample frequency of the filter. The maximum sample
frequency is 1MHz. The minimum sample frequency is set by the filter requirements. The
minimum sample frequency will be at least the Nyquist Rate. The filter sample frequency will
also be an integer multiple of the ADC clock rate to ensure proper alignment between the ADC
and the filter.
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Common Tab
Show analog clock (aclk) terminal
If this box is checked, the external analog clock (aclk) terminal will appear on the symbol.
Application Programming Interface
Application Programming Interface (API) routines allow you to configure the component using
software. This table lists and describes the interface to each function. The following sections
cover each function in more detail.
By default, PSoC Creator assigns the instance name "ADC_1" to the first instance of a
component in a given design. You can rename it to any unique value that follows the syntactic
rules for identifiers. The instance name becomes the prefix of every global function name,
variable, and constant symbol. For readability, the instance name used in the following table is
"ADC".
Note Do not use the ADC_Stop() API to halt conversions. Instead use the ADC_StopConvert()
API. If you use the ADC_Stop() API to halt conversions then later use the ADC_Start() and
ADC_StartConvert() APIs to resume conversions, the first channel of the scan may be corrupt.
The StopConvert() API will enable the Scanning SAR ADC to complete the current scan of
channels. After the channel scan is complete, the Scanning SAR ADC will stop all conversions,
which can be detected by the use of an ISR or the ADC_IsEndConversion() flag.
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Note that no explicit functions for saving and loading the hardware state are provided. Everything
needed to set up the SAR hardware is provided in the main API functions.
Functions
Function
Description
ADC_Start()
Performs all required initialization for this component and enables the power. The
power will be set to the appropriate power based on the clock frequency.
ADC_StartEx()
Performs the same function as ADC_Start() as well as setting the interrupt vector to
a user defined address.
ADC_Stop()
This function stops ADC conversions and puts the ADC into its lowest power mode.
ADC_StartConvert()
For continuous mode, this API starts the conversion process and it runs
continuously. In a triggered mode, this routine triggers every conversion.
ADC_StopConvert()
Forces the ADC to stop conversions. If a conversion is currently executing, that
conversion will complete, but no further conversions will occur.
ADC_SetConvertMode()
Sets the conversion mode to either Single-Shot or continuous.
ADC_IRQ_Enable()
Enables interrupts to occur at the end of a conversion. Global interrupts must also
be enabled for the ADC interrupts to occur.
ADC_IRQ_Disable()
Disables interrupts at the end of a conversion.
ADC_SetEosMask()
This function sets or clears the End of Scan (EOS) interrupt mask bit.
ADC_SetChanMask()
Sets enable/disable mask for all channels.
ADC_IsEndConversion()
Immediately returns the status of the conversion or does not return (blocking) until
the conversion completes, depending on the retMode parameter.
ADC_GetResult16()
Gets the data available in the SAR result register, returns 16-bit
ADC_GetResult32()
Gets the data available in the SAR result register, returns 32-bit
ADC_SetLowLimit()
This parameter sets the low limit for a limit compare.
ADC_SetHighLimit()
This parameter sets the high limit for a limit compare.
ADC_SetLimitMask()
Sets which channels may cause a limit condition interrupt.
ADC_SetSatMask()
Sets which channels may cause a saturation event interrupt.
ADC_SetOffset()
Sets the offset of the ADC channel.
ADC_SetGain()
Sets the gain in counts per 10 volt for the ADC channel.
ADC_CountsTo_Volts()
Converts the ADC output to volts as a floating point number.
ADC_CountsTo_mVolts()
Converts the ADC output to millivolts.
ADC_CountsTo_uVolts()
Converts the ADC output to microvolts.
ADC_Sleep()
Stops the ADC operation and saves the configuration registers and component
enable state.
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Function
Description
ADC_Wakeup()
Restores the component enable state and configuration registers.
void ADC_Start(void)
Description:
Performs all required initialization for this component and enables the power. The power will
be set to the appropriate power based on the clock frequency.
Parameters:
None
Return Value:
None
Side Effects:
None
void ADC_StartEx(cyisaddress address)
Description:
This function starts the ADC and sets the Interrupt Service Routine to the provided address
using the ADC_IRQ_StartEx() function. Refer to the Interrupt component datasheet for more
information on the ADC_IRQ_StartEx() function.
Parameters:
address: This is the address of a user defined function for the ISR .
Return Value:
None
Side Effects:
None
void ADC_Stop(void)
Description:
This function stops ADC conversions and puts the ADC into its lowest power mode.
Parameters:
None
Return Value:
None
Side Effects:
Don’t use the Stop() API to halt conversions. Instead use the StopConvert() API. If you use
the Stop() API to halt conversions then later use the ADC_Start() and ADC_StartConvert()
APIs to resume conversions, the first channel of the scan may be corrupt. The StopConvert()
API will enable the Scanning SAR ADC to complete the current scan of channels. After the
channel scan is complete, the Scanning SAR ADC will stop all conversions, which can be
detected by the use of an ISR or the ADC_IsEndConversion() flag.
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void ADC_StartConvert(void)
Description:
In continuous mode, this API starts the conversion process and it runs continuously.
In Single Shot mode, the function triggers a single scan and every scan requires a call of this
function. The mode is set with the Sample Mode parameter in the customizer. The
customizer setting can be overridden at run time with the ADC_SetConvertMode() function.
Parameters:
None
Return Value:
None
Side Effects:
None
void ADC_StopConvert(void)
Description:
Forces the ADC to stop conversions. If a conversion is currently executing, that conversion
will complete, but no further conversions will occur.
Parameters:
None
Return Value:
None
Side Effects:
None
void ADC_SetConvertMode(uint32 mode)
Description:
Sets the conversion mode to either Single-Shot or continuous. This function overrides the
settings applied in the customizer. Changing configurations will restore the values set in the
customizer.
Parameters:
mode: Sets the conversion mode. See table below for details.
Options
Description
ADC_SINGLE_SHOT
Calling the ADC_StartConvert() function after setting mode
this will trigger a single scan. Sets the SOC signal to be edge
sensitive, each edge will trigger a single scan.
ADC_CONTINUOUS
Calling the ADC_StartConvert() function after setting this
mode trigger continuous scanning. This mode sets the SOC
signal to be level sensitive. The ADC will continuously scan
while soc is active.
Return Value:
None
Side Effects:
None
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void ADC_IRQ_Enable(void)
Description:
Enables interrupts to occur at the end of a conversion. Global interrupts must also be
enabled for the ADC interrupts to occur.
Parameters:
None
Return Value:
None
Side Effects:
None
void ADC_IRQ_Disable(void)
Description:
Disables end of conversion interrupts.
Parameters:
None
Return Value:
None
Side Effects:
None
void ADC_SetEosMask(uint32 mask)
Description:
Sets of clears the End of Scan (EOS) interrupt mask.
Parameters:
mask: 1 to set the mask, 0 to clear the mask.
Return Value:
None
Side Effects:
All other bits in the INTR register are cleared by this function.
void ADC_SetChanMask(uint32 mask)
Description:
Sets enable/disable mask for all channels.
Parameters:
mask: 1 to set the mask, 0 to clear the mask.
Return Value:
None
Side Effects:
Enabling or disabling a channel disrupts the scheduled timing and changes the sample rate.
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uint32 ADC_IsEndConversion(uint32 retMode)
Description:
Immediately returns the status of the conversion or does not return (blocking) until the
conversion completes, depending on the retMode parameter.
Parameters:
retMode: Check conversion return mode. See the following table for options.
Options
Description
ADC_RETURN_STATUS
Immediately returns the conversion status for sequential
channels. If the value returned is zero, the conversion is not
complete, and this function should be retried until a nonzero
result is returned.
ADC_WAIT_FOR_RESULT
Does not return a result until the ADC conversion of all
sequential channels is complete.
ADC_RETURN_STATUS_INJ
Immediately returns the conversion status for the injection
channel. If the value returned is zero, the conversion is not
complete, and this function should be retried until a nonzero
result is returned.
ADC_WAIT_FOR_RESULT_INJ
Does not return a result until the ADC completes injection
channel conversion.
Return Value: uint8: If a nonzero value is returned, the last conversion is complete. If the returned value is
zero, the ADC is still calculating the last result.
Side Effects:
This function reads the end of conversion status, and clears it afterward.
int16 ADC_GetResult16(uint32 chan)
Description:
Gets the data available in the channel result data register.
Parameters:
chan: The ADC channel to read the result from. The first channel is 0 and the injection
channel if enabled is the number of valid channels.
Return Value:
Returns converted data as a signed 16-bit integer
Side Effects:
None.
int16 ADC_GetResult32(uint32 chan)
Description:
Gets the data available in the channel result data register.
Parameters:
chan: The ADC channel to read the result from. The first channel is 0 and the injection
channel if enabled is the number of valid channels.
Return Value:
Returns converted data as a signed 32-bit integer
Side Effects:
None.
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void ADC_SetLowLimit(uint32 lowLimit)
Description:
Sets the low limit parameter for a limit condition.
Parameters:
lowLimit: The low limit for a limit condition.
Return Value:
None
Side Effects:
None
void ADC_SetHighLimit(uint32 highLimit)
Description:
Sets the high limit parameter for a limit condition.
Parameters:
highLimit: The high limit for a limit condition.
Return Value:
None
Side Effects:
None
void ADC_SetLimitMask(uint32 mask)
Description:
Sets the channel limit condition mask.
Parameters:
mask: Sets which channels that may cause a limit condition interrupt. Setting bits for
channels that do not exist will have no effect. For example, if only 6 channels were enabled,
setting a mask of 0x0103 would only enable the last two channels (0 and 1).
Return Value:
None
Side Effects:
None
void ADC_SetSatMask(uint32 mask)
Description:
Sets the channel saturation event mask.
Parameters:
mask: Sets which channels that may cause a saturation event interrupt. Setting bits for
channels that do not exist will have no effect. For example, if only 8 channels were enabled,
setting a mask of 0x01C0 would only enable two channels (6 and 7).
Return Value:
None
Side Effects:
None
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void ADC_SetOffset(uint32 chan, int16 offset)
Description:
Sets the ADC offset that is used by the functions ADC_CountsTo_uVolts,
ADC_CountsTo_mVolts and ADC_CountsTo_Volts to subtract the offset from the given
reading before calculating the voltage conversion.
Parameters:
chan: ADC channel number.
offset: This value is a measured value when the inputs are shorted or connected to the
same input voltage.
Return Value:
None
Side Effects:
None.
void ADC_SetGain(uint32 chan, int32 adcGain)
Description:
Sets the ADC gain in counts per 10 volt for the voltage conversion functions below.
This value is set by default by the reference and input range settings. It should only
be used to further calibrate the ADC with a known input or if an external reference is
used. Affects the ADC_CountsTo_uVolts, ADC_CountsTo_mVolts and
ADC_CountsTo_Volts functions by supplying the correct conversion between ADC
counts and voltage.
Parameters:
chan: ADC channel number.
adcGain: ADC gain in counts per 10 volt.
Return Value: None
Side Effects:
None.
float32 ADC_CountsTo_Volts(uint32 chan, int16 adcCounts)
Description:
Converts the ADC output to Volts as a floating point number. For example, if the ADC
measured 0.534 volts, the return value would be 0.534. The calculation of voltage depends
on the value of the voltage reference. When the Vref is based on Vdda, the value used for
Vdda is set for the project in the System tab of the DWR.
Parameters:
chan: ADC channel number.
adcCounts: Result from the ADC conversion
Return Value: Result in Volts
Side Effects:
None
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int16 ADC_CountsTo_mVolts(uint32 chan, int16 adcCounts)
Description:
Converts the ADC output to millivolts as a 16-bit integer. For example, if the ADC measured
0.534 volts, the return value would be 534. The calculation of voltage depends on the value
of the voltage reference. When the Vref is based on Vdda, the value used for Vdda is set for
the project in the System tab of the DWR.
Parameters:
chan: ADC channel number.
adcCounts: Result from the ADC conversion.
Return Value: Result in mV.
Side Effects:
None
int32 ADC_CountsTo_uVolts(uint32 chan, int16 adcCounts)
Description:
Converts the ADC output to microvolts as a 32-bit integer. For example, if the ADC
measured 0.534 volts, the return value would be 534000. The calculation of voltage
depends on the value of the voltage reference. When the Vref is based on Vdda, the value
used for Vdda is set for the project in the System tab of the DWR.
Parameters:
chan: ADC channel number.
adcCounts: Result from the ADC conversion
Return Value:
Result in µV
Side Effects:
None
void ADC_Sleep(void)
Description:
This is the preferred routine to prepare the component for sleep. The ADC_Sleep()
routine saves the current component state. Then it calls the ADC_Stop() function and
calls ADC_SaveConfig() to save the hardware configuration.
Call the ADC_Sleep() function before calling the CySysPmDeepSleep() or the
CySysPmHibernate() function. See the PSoC Creator System Reference Guide for more
information about power-management functions.
Parameters:
None
Return Value:
None
Side Effects:
If this function is called twice in the enable state of the component, the disabled state of
the component will be stored. So ADC_Enable() and ADC_StartConvert() must be called
after ADC_Wakeup() in this case.
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void ADC_Wakeup(void)
Description:
This is the preferred routine to restore the component to the state when ADC_Sleep() was
called. The ADC_Wakeup() function calls the ADC_RestoreConfig() function to restore the
configuration. If the component was enabled before the ADC_Sleep() function was called,
the ADC_Wakeup() function also re-enables the component.
Parameters:
None
Return Value:
None
Side Effects:
Calling this function without previously calling ADC_Sleep() may lead to unpredictable
results.
Global Variables
Function
ADC_initVar
Description
The initVar variable is used to indicate initial configuration of this component. The
variable is initialized to zero and set to 1 the first time ADC_Start() is called. This
allows for component initialization without reinitialization in all subsequent calls to the
ADC_Start() routine.
If reinitialization of the component is required, then the ADC_Init() function can be
called before the ADC_Start() or ADC_Enable() functions.
ADC_offset[]
This array calibrates the offset for each channel. It is set to 0 the first time
ADC_Start() is called and can be modified using ADC_SetOffset(). The array affects
the ADC_CountsTo_Volts(), ADC_CountsTo_mVolts(), and ADC_CountsTo_uVolts()
functions by subtracting the given offset.
ADC_countsPer10Volt[]
This array is used to calibrate the gain for each channel. It is calculated the first time
ADC_Start() is called. The value depends on channel resolution and voltage
reference. It can be changed using ADC_SetGain().
This array affects the ADC_CountsTo_Volts(), ADC_CountsTo_mVolts(), and
ADC_CountsTo_uVolts() functions by supplying the correct conversion between ADC
counts and the applied input voltage.
Usable Constants
Function
ADC_TOTAL_CHANNELS_NUM
Description
This constant represents the amount of input channels available for
scanning.
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Sample Firmware Source Code
PSoC Creator provides numerous example projects that include schematics and example code
in the Find Example Project dialog. For component-specific examples, open the dialog from the
Component Catalog or an instance of the component in a schematic. For general examples,
open the dialog from the Start Page or File menu. As needed, use the Filter Options in the
dialog to narrow the list of projects available to select.
Refer to the "Find Example Project" topic in the PSoC Creator Help for more information.
Interrupt Service Routine
The Scanning SAR ADC contains a blank interrupt service routine in the file ADC_INT.c. You
can place custom code in the designated areas to perform whatever function is required at the
end of a conversion. A copy of the blank interrupt service routine is shown below. Place custom
code between the “/* `#START MAIN_ADC_ISR` */” and “/* `#END` */” comments. This
ensures that the code will be preserved, when a project is regenerated.
CY_ISR( ADC_ISR )
{
uint32 intr_status;
/* Rear interrupt status register */
intr_status = ADC_1_SAR_INTR_REG;
/************************************************************************
* Custom Code
* - add user ISR code between the following #START and #END tags
*************************************************************************/
/* `#START MAIN_ADC_ISR` */
/* `#END`
*/
/* Clear handled interrupt */
ADC_1_SAR_INTR_REG = intr_status;
}
A second designated area is available to place variable definitions and constant definitions.
/* System variables */
/* `#START ADC_SYS_VAR` */
/* Place user code here. */
/* `#END` */
An example of code that uses an interrupt to capture data follows.
#include <project.h>
int16 result = 0;
uint8 dataReady = 0;
void main()
{
int16 newReading = 0;
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CYGlobalIntEnable; /* Enable Global interrupts */
ADC_1_Start(); /* Initialize ADC */
ADC_1_IRQ_Enable(); /* Enable ADC interrupts */
ADC_1_StartConvert(); /* Start ADC conversions */
for(;;)
{
if (dataReady != 0)
{
dataReady = 0;
newReading = result;
/* More user code */
}
}
}
Note that you may use an alternative Interrupt service routine, located in your main.c file. In this
case use the following template:
Implement interrupt service routine in main.c:
CY_ISR( ADC_ISR_LOC )
{
uint32 intr_status;
/* Read interrupt status register */
intr_status = ADC_1_SAR_INTR_REG;
/* Place your code here */
/* Clear handled interrupt */
ADC_1_SAR_INTR_REG = intr_status;
}
Enable ADC interrupt and set interrupt handler to local routine:
ADC_StartEx(ADC_ISR_LOC);
MISRA Compliance
This section describes the MISRA-C:2004 compliance and deviations for the component. There
are two types of deviations defined:


project deviations – deviations that are applicable for all PSoC Creator components
specific deviations – deviations that are applicable only for this component
This section provides information on component-specific deviations. Project deviations are
described in the MISRA Compliance section of the System Reference Guide along with
information on the MISRA compliance verification environment.
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The Scanning SAR ADC component has the following specific deviation:
Rule Class
(Required/
Advisory)
MISRA-C:
2004 Rule
Rule Description
Description of Deviation(s)
8.7
R
Objects shall be defined at block
scope if they are only accessed from
within a single function.
The object 'ADC_channelsConfig' is always accessed
from ADC_Init() function and optionally, depend on
component configuration, from
ADC_CountsTo_mVolts(), ADC_CountsTo_uVolts,
ADC() and ADC_CountsTo_Volts() functions. The
intention of this publicly available static variable is to
allow more efficient code.
10.1
R
The value of an expression of integer The CFG*_HALF_A_CF_VAL constant is cast to an
type shall not be implicitly converted enumerated type limited to a maximum value of 64. In
to a different underlying type if:
Low-Pass, High-Pass and Notch filters, this value can be
up to 127. However, this constant is in place for multia) it is not a conversion to a wider
integer type of the same signedness, configuration support, a feature that is not yet enabled.
or
b) the expression is complex, or
c) the expression is not constant and
is a function argument, or
d) the expression is not constant and
is a return expression.
This component has the following embedded components: Interrupt, Clock and Opamp when the
filter is used. Refer to the corresponding component datasheet for information on their MISRA
compliance and specific deviations.
API Memory Usage
The component memory usage varies significantly, depending on the compiler, device, number
of APIs used, and component configuration. This table illustrates the memory usage for all APIs
available in the default component configuration.
The measurements were done with the associated compiler configured in release mode with
optimization set for size. For a specific design analyze the map file generated by the compiler to
determine the memory usage.
PSoC Analog Coprocessor
Configuration
Flash Bytes
Default
TBD
SRAM Bytes
TBD
Functional Description
The Scanning SAR ADC Component is implemented on a hardware block that contains the
following elements:

SAR ADC
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
□
SARMUX
□
SARADC core
□
SARREF
□
SARSEQ
Switched-capacitor filter
□
CTB
□
UAB
SAR ADC
Block Diagram
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The SARADC core is a fast 12-bit ADC with SAR architecture. Preceding the SARADC is the
SARMUX, which can route a combination of external pins and internal signals to inputs of the
SARADC core. SARREF is a buffer used for multiple reference voltage selection. The SARSEQ
sequencer block controls the SARMUX and the SARADC and does an automatic scan on all
enabled channels as well as post-processing, such as averaging the output data.
Each channel has 16-bit conversion-result storage registers. At the end of the scan, a maskable
interrupt is asserted. The sequencer also flags overflow and saturation errors that can be
configured to assert an interrupt.
Switched-capacitor filter
Block Diagram
The switched-capacitor filter is an inverting 2nd-order filter. To protect the analog ground (vagnd
terminal) signal from disturbances on the SARMUX, it is first buffered by a half-CTB’s opamp set
as a follower. Because the filter is inverting, vagnd is routed to the SAR’s positive terminal, and
the filter output is routed to the negative terminal. Filter measurements are therefore made with
the correct polarity.
The filter operates in two phases, and the output is only valid during the first. To ensure the filter
measurement is always correct, the customizer configures the SAR and UAB specifically to
synchronize the two, based on the initial parameters. Any change to timing, such as disabling
channels at runtime, may cause the SAR sample to desynchronize from the UAB’s valid
output.
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Input Modes and Signedness
The input mode (S/E or Differential) determines the range of input voltages, and the signedness
determines the digital codes to which the input range corresponds.
The smallest voltage in the range always corresponds to the lowest code.
The diagrams in this section show the various input ranges and their corresponding codes,
represented in both 12-bit hexadecimal and decimal.
Note, it is recommended to use settings with intuitive results, such as S/E with Vneg = Vref and
such as Signed Differential.
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DMA Support
The DMA component can be used to transfer data from the component registers to RAM or
another component.
Name of DMA Source
Width
Direction
(ADC_SAR_CHAN_RESULT_PTR + (X << 2u)) *
32
Source
DMA Req DMA Trigger
Signal
Type
eoc
or
Pulse
Description
Channel result data register.
This 32-bit register contains 16-bit ADC
results.
ADC_SAR_CHANX_RESULT_PTR *
* where X – is a channel number. The first channel is 0.
Note The component has a DMA bus interface that supports 32-bit (word) transfers only. If the
data element size used for DMA transfer is less than a word, set the DMA descriptor with the
correct width; for example, data element size is halfword (2 bytes). The component register is
used as Source; make sure the DMA descriptor is configured as "Word to Halfword."
Registers
Channel result data registers
This 32-bit register contains 16-bit ADC results from channel 0 along with 3 status bits that
describe the results correctness.
ADC_SAR_CHAN_RESULT_REG
Bits
Name
Description
15:0
Data
SAR conversion result of the first channel. The data is copied here
from the work field after all enabled channels in this scan have
been sampled.
29
ADC_SATURATE_INTR_MIR
Mirror bit of corresponding bit in
ADC_SAR_SATURATE_INTR_REG register
30
ADC_RANGE_INTR_MIR
Mirror bit of corresponding bit in ADC_SAR_RANGE_INTR_REG
register
31
ADC_CHAN_RESULT_VALID_MIR
Mirror bit of corresponding bit in
ADC_SAR_CHAN_RESULT_VALID_REG register
Result registers for the remaining channels are located sequentially in the memory. Direct
defines for each channel are provided: ADC_SAR_CHANX_RESULT_REG, were X is the
channel number from 0 to 7(15).
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Interrupt request registers
Each of the interrupts described in this section has an interrupt mask in the
ADC_SAR_INTR_MASK_REG register. By making the interrupt mask low, the corresponding
interrupt source is ignored. The SAR interrupt is raised any time the intersection (logic AND) of
the interrupt flags in ADC_SAR_INTR_REG registers and the corresponding interrupt masks in
ADC_SAR_INTR_MASK_REG register is non zero.
When servicing an interrupt, the interrupt service routine (ISR) clears the interrupt source by
writing a ‘1’ to the interrupt bit after picking up the related data.
For firmware convenience, the intersection (logic AND) of the interrupt flags and the interrupt
masks are also made available in the SADC_SAR_INTR_MASKED_REG register.
ADC_SAR_INTR_REG
Bits
Name
Description
0
ADC_EOS_MASK*
End Of Scan Interrupt: hardware sets this interrupt after completing a
scan of all the enabled channels. Write with '1' to clear bit after picking
up the data from the ADC_SAR_CHAN_RESULT_REG register.
1
ADC_OVERFLOW_MASK
Overflow Interrupt: hardware sets this interrupt when it sets a new
ADC_EOS_MASK while that bit was not yet cleared by the firmware.
Write with '1' to clear bit.
2
ADC_FW_COLLISION_MASK
Firmware Collision Interrupt: hardware sets this interrupt when in
Hardware trigger sample mode firmware triggers the conversion
using ADC_StartConvert() API while the SAR is BUSY. Raising this
interrupt is delayed to when the scan caused by the
ADC_StartConvert() API has been completed, i.e. not when the
preceding scan with which this trigger collided is completed. When this
interrupt is set it implies that the channels were sampled later than was
intended (jitter). Write with '1' to clear bit.
3
ADC_DSI_COLLISION_MASK
DSI Collision Interrupt: hardware sets this interrupt when the hardware
SOC trigger signal is asserted while the SAR is BUSY. Raising this
interrupt is delayed to when the scan caused by the hardware SOC
trigger has been completed, i.e. not when the preceding scan with
which this trigger collided is completed. When this interrupt is set it
implies that the channels were sampled later than was intended (jitter).
Write with '1' to clear bit.
These bits are enabled by the component by default in ADC_SAR_INTR_MASK_REG register
and generate an interrupt.
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ADC_SAR_SATURATE_INTR_REG
Bits
15:0
Name
SATURATE_INTR
Description
Saturate interrupt request register.
Hardware sets saturate interrupt for each channel if a conversion
result (before averaging) of that channel is either 0x000 or 0xFFF
(for 12-bit resolution), this is an indication that the ADC likely
saturated. When a 10-bit or 8-bit resolution is selected for the
channel, then the upper bits are ignored. Write with '1' to clear bit.
ADC_SAR_SATURATE_INTR_MASK_REG
Bits
15:0
Name
SATURATE_MASK
Description
Saturate interrupt mask register.
It is set by default according to selection of the Saturation
parameter. Use ADC_SetSatMask() API to change this mask
register.
ADC_SAR_SATURATE_INTR_MASKED_REG
Bits
15:0
Name
SATURATE_MASKED
Description
Saturate interrupt masked request register.
If the value is not zero then the SAR interrupt is raised. When read,
this register reflects a bitwise AND between the saturate interrupt
request and mask registers.
ADC_SAR_RANGE_INTR_REG
Bits
15:0
Name
RANGE_INTR
Description
Range detect interrupt request register.
Hardware sets range detect interrupt for each channel if the
conversion result (after averaging) of that channel met the condition
specified by the Compare Mode parameter. Write with '1' to clear bit.
ADC_SAR_RANGE_INTR_MASK_REG
Bits
15:0
Name
RANGE_MASK
Description
Range detect interrupt mask register.
It is set by default according to selection of the Limit detect
parameter. Use ADC_SetLimitMask() API to change this mask
register.
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ADC_SAR_RANGE_INTR_MASKED_REG
Bits
15:0
Name
RANGE_MASKED
Description
Range interrupt masked request register.
If the value is not zero then the SAR interrupt is raised. When read,
this register reflects a bitwise AND between the range detect
interrupt request and mask registers.
Resources
The Scanning SAR ADC is implemented as a fixed-function block. The component also uses one
Interrupt.
DC and AC Electrical Characteristics
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted.
Specifications are valid for 1.71 V to 5.5 V, except where noted.
Note Final characterization data for PSoC 4000S, PSoC 4100S and PSoC Analog Coprocessor
devices is not available at this time. Once the data is available, the component datasheet will be
updated on the Cypress web site.
DC Specifications
Parameter
Description
Min
Typ
Max
Units
bits
Conditions
A_RES
Resolution
8
12
12
native, without averaging
A_CHNIS_S
Number of channels – single-ended
–
–
16
A-CHNKS_D
Number of channels - differential
–
–
16
Diff inputs use neighboring I/O
A-MONO
Monotonicity
–
–
–
. Based on characterization
A_GAINERR
Gain error
–
–
+/-0.1
%
A_OFFSET
Input offset voltage
–
–
2
mV
A_ISAR
Current consumption
–
–
A_VINS
Input voltage range – single-ended
VSS
–
VDDA
V
permissible range – conversion
range depends on Vref value
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
permissible range – conversion
range depends on Vref value
A_INRES
Input path series resistance
–
–
2.2
KΩ
Based on characterization
A_INCAP
Input capacitance
-
-
10
pF
Based on characterization
With external reference
mA
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AC Specifications
Parameter
Description
Min
Typ
Max
Units
Conditions
A_PSRR
Power supply rejection ratio
70
–
–
dB
A_CMRR
Common mode rejection ratio
66
–
–
dB
A_SAMP_1
Sample rate with external reference
bypass cap
–
–
1
Msps
A_SAMP_3
Sample rate with no bypass cap.
Internal reference
–
–
–
Ksps
A_SNDR
Signal-to-noise and distortion ratio
(SINAD)
65
–
–
dB
A_INL
Integral non linearity
-1.7
–
2
LSB
VDD = 1.71 to 5.5, 1 Msps, Vref = 1
to 5.5
A_INL
Integral non linearity
-1.5
–
1.7
LSB
VDDD = 1.71 to 3.6, 1 Msps, Vref =
1.71 to VDDD
A_INL
Integral non linearity
-1
–
2.2
LSB
VDDD = 1.71 to 5.5, 500 Ksps, Vref =
1 to 5.5
A_DNL
Differential non linearity
-1
–
2.2
LSB
VDDD = 1.71 to 5.5, 1 Msps, Vref = 1
to 5.5
A_DNL
Differential non linearity
-1
–
2
LSB
VDDD = 1.71 to 3.6, 1 Msps, Vref =
1.71 to VDDD
A_THD
Total harmonic distortion
–
–
-65
dB
Description
Min
Typ
Max
Units
Trimmed internal reference to SAR
-1
–
+1
%
Measured at 1 V
requires 36 MHz sys_clk to be
available
FIN = 10 kHz
FIN = 10 kHz.
Block Specs
Parameter
VREFSAR
Conditions
Percentage of Vbg (1.2 V).
Component Errata
ID
Version
Problem
Workaround
232792
1.0, 1.10
Achieved scan rate labels take too long to refresh
None.
242682
1.10
Filter operation is limited to Vdda 3V-5V. Vdda must
remain constant during filter use.
None.
242809
1.10
MISRA violation in unused code.
None.
234909
1.10
Values for averaged compare values are incorrect for
Sequential, Fixed mode.
In Sequential, Fixed mode, use the
non-averaged values because they
are correct for this averaging mode.
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Document Number: 002-13264 Rev. **
Page 35 of 36
PSoC® Creator™ Component Datasheet
PSoC 4 Scanning SAR ADC (Scan_ADC)
Component Changes
This section lists the major changes in the component from the previous version.
Version
Description of Changes
Reason for Changes / Impact
1.10
Added optional switched-capacitor filter to
channel zero.
This feature provides additional signal processing
before the ADC measurement.
1.0
Initial version of the component.
Final characterization data for PSoC 4000S, PSoC
4100S and PSoC Analog Coprocessor devices is not
available at this time. Once the data is available, the
component datasheet will be updated on the Cypress
web site.
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PRELIMINARY
Page 36 of 36
Document Number: 002-13264 Rev. **