[ /Title (CD74 HC112 , CD74 HCT11 2) /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. • Asynchronous Set and Reset • Complementary Outputs These flip-flops have independent J, K, Set, Reset, and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs. • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pincompatible with the standard LS logic family. . • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Balanced Propagation Delay and Transition Times PART NUMBER • Significant Power Reduction Compared to LSTTL Logic ICs TEMP. RANGE (oC) PACKAGE CD54HC112F3A -55 to 125 16 Ld CERDIP • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD54HCT112F3A -55 to 125 16 Ld CERDIP CD74HC112E -55 to 125 16 Ld PDIP CD74HC112MT -55 to 125 16 Ld SOIC • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HC112M96 -55 to 125 16 Ld SOIC CD74HC112NSR -55 to 125 16 Ld SOP CD74HC112PW -55 to 125 16 Ld TSSOP CD74HC112PWR -55 to 125 16 Ld TSSOP CD74HC112PWT -55 to 125 16 Ld TSSOP CD74HCT112E -55 to 125 16 Ld PDIP Pinout NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CD54HC112, CD54HCT112 (CERDIP) CD74HC112 (PDIP, SOIC, SOP, TSSOP) CD74HCT112 (PDIP) TOP VIEW 1CP 1 16 VCC 1K 2 15 1R 1J 3 14 2R 1S 4 13 2CP 1Q 5 12 2K 1Q 6 11 2J 2Q 7 10 2S GND 8 9 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Functional Diagram 1S 1J 1K 1CP 1R 2S 2J 2K 2CP 2R 4 3 5 1Q 2 F/F 1 6 1Q 1 15 10 11 9 2Q 12 F/F 2 7 2Q 13 GND = 8 VCC = 16 14 TRUTH TABLE INPUTS OUTPUTS S R CP J K Q Q L H X X X H L H L X X X L H L L X X X H (Note 1) H (Note 1) H H ↓ L L H H ↓ H L H L H H ↓ L H L H H H ↓ H H Toggle H H H X X No Change No Change H= High Level (Steady State) L= Low Level (Steady State) X= Don’t Care ↓= High-to-Low Transition NOTE: 1. Output states unpredictable if both S and R go High simultaneously after both being low at the same time. 2 CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 2): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature (Hermetic Package or Die) . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time, tr, tf 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND - - -0.02 2 1.9 - - 1.9 - 1.9 - V 4.5 4.4 - - 4.4 - 4.4 - V 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 4.5 - - 0.1 - 0.1 - 0.1 V 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 3 CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 4 - 40 - 80 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND - 5.5 - ICC VCC or GND 0 5.5 - - 4 - 40 - 80 µA ∆ICC (Note 3) VCC - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS 1S, 2S 0.5 1K, 2K 0.6 1R, 2R 0.65 1J, 2J, 1CP, 2CP 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns HC TYPES Pulse Width CP 4 CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Prerequisite For Switching Specifications PARAMETER Pulse Width R, S Setup Time J, K, to CP Hold Time J, K, to CP Removal Time R to CP, S to CP CP Frequency (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 0 - - 0 - 0 - ns 4.5 0 - - 0 - 0 - ns 6 0 - - 0 - 0 - ns 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 6 - - 5 - 4 - MHz tSU - tH - tREM - fMAX - 4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz HCT TYPES Pulse Width CP tSU - 4.5 16 - - 20 - 24 - ns Pulse Width R, S tW - 4.5 18 - - 23 - 27 - ns Setup Time J, K, to CP tH - 4.5 16 - - 20 - 24 - ns Hold Time J, K, to CP tREM - 4.5 3 - - 3 - 3 - ns tW - 4.5 20 - - 25 - 30 - ns fMAX - 4.5 30 - - 25 - 20 - MHz SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 175 - 220 - 265 ns CL = 50pF 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns Removal Time R to CP, S to CP CP Frequency Switching Specifications Input tr, tf = 6ns PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC HC TYPES Propagation Delay, CP to Q, Q Propagation Delay, S to Q, Q Propagation Delay, R to Q, Q tPLH, tPHL tPLH, tPHL CL = 50pF 2 - - 155 - 195 - 235 ns CL = 50pF 4.5 - - 31 - 39 - 47 ns CL = 15pF 5 - 13 - - - - - ns CL = 50pF 6 - - 26 - 33 - 40 ns CL = 50pF 2 - - 180 - 225 - 270 ns CL = 50pF 4.5 - - 36 - 45 - 54 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 38 - 46 ns 5 CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Switching Specifications Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL TEST CONDITIONS Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns CL = 50pF 4.5 - - 15 - 19 - 22 ns CL = 50pF 6 - - 13 - 16 - 19 ns - - - 10 - 10 - 10 pF 5 - 60 - - - - - MHz 5 - 12 - - - - - pF CL = 50pF 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 4.5 - - 32 - 40 - 48 ns CL = 15pF 5 - 13 - - - - - ns CL = 50pF 4.5 - - 37 - 46 - 56 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CI VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS - CP Frequency fMAX Power Dissipation Capacitance (Notes 4, 5) CPD CL = 15pF - HCT TYPES Propagation Delay, CP to Q, Q tPLH, tPHL Propagation Delay, S to Q, Q tPLH, tPHL Propagation Delay, R to Q, Q tPLH, tPHL Output Transition Time tTLH, tTHL Input Capacitance CI - - - - 10 - 10 - 10 pF CP Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz Power Dissipation Capacitance (Notes 4, 5) CPD - 5 - 20 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per flip-flop. 5. PD = CPD VCC2 fi + Σ CL fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms tfCL trCL CLOCK 90% 10% tWL + tWH = I tWL 50% tfCL = 6ns fCL I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns CLOCK 50% 2.7V 0.3V GND 1.3V 0.3V tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. 1.3V 1.3V GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH 6 CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Test Circuits and Waveforms tr = 6ns (Continued) tf = 6ns 90% 50% 10% INPUT GND tTLH 90% INVERTING OUTPUT tPHL FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL VCC 90% GND tH(H) 3V 2.7V 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET tfCL CLOCK INPUT 50% 10% tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tfCL trCL tTLH 1.3V 10% tPLH tPHL GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL CLOCK INPUT tf = 6ns tr = 6ns VCC CL 50pF FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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