AD AD9853-45PCB Programmable digital opsk/16-qam modulator Datasheet

a
Programmable Digital
QPSK/16-QAM Modulator
AD9853
FEATURES
Universal Low Cost Solution for HFC Network
Return-Channel TX Function: 5 MHz–42 MHz/
5 MHz–65 MHz
165 MHz Internal Reference Clock Capability
Includes Programmable Pulse-Shaping FIR Filters and
Programmable Interpolating Filters
FSK/QPSK/DQPSK/16-QAM/D16-QAM Modulation
Formats
6ⴛ Internal Reference Clock Multiplier
Integrated Reed-Solomon FEC Function
Programmable Randomizer/Preamble Function
Supports Interoperable Cable Modem Standards
Internal SINx/x Compensation
>50 dB SFDR @ 42 MHz Output Frequency (Single Tone)
Controlled Burst Mode Operation
+3.3 V to +5 V Single Supply Operation
Low Power: 750 mW @ Full Clock Speed (3.3 V Supply)
Space Saving Surface Mount Packaging
GENERAL DESCRIPTION
The AD9853 integrates a high speed direct-digital synthesizer
(DDS), a high performance, high speed digital-to-analog converter (DAC), digital filters and other DSP functions onto a
single chip, to form a complete and flexible digital modulator
device. The AD9853 is intended to function as a modulator in
network applications such as interactive HFC, WLAN and
MMDS, where cost, size, power dissipation, functional integration and dynamic performance are critical attributes.
The AD9853 is fabricated on an advanced CMOS process and
it sets a new standard for CMOS digital modulator performance.
The device is loaded with programmable functionality and
provides a direct interface port to the AD8320, digitallyprogrammable cable driver amplifier. The AD9853/AD8320
chipset forms a highly integrated, low power, small footprint
and cost-effective solution for the HFC return-path requirement
and other more general purpose modulator applications.
The AD9853 is available in a space saving surface mount package and is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
APPLICATIONS
HFC Data, Telephony and Video Modems
Wireless LAN
FUNCTIONAL BLOCK DIAGRAM
SERIAL
DATA IN
R-S
FEC
XOR
DATA
DELAY
& MUX
PREAMBLE
INSERTION
RANDOMIZER
ENCODER:
FSK
QPSK
DQPSK
16-QAM
D16-QAM
FIR
FILTER
INTERPOLATION
FILTER
AD9853
10
FIR
FILTER
INV
SYNC
FILTER
10
INTERPOLATION
FILTER
SINE
COSINE
10-BIT
DAC
AOUT
GAIN
CONTROL TO
DRIVER AMP
TO LP FILTER
AND AD8320
CABLE DRIVER
AMPLIFER
DDS
CLOCK
63
REF CLOCK IN
CONTROL FUNCTIONS
FEC
TXENABLE RESET
ENABLE/
DISABLE
SERIAL CONTROL BUS:
32-BIT OUTPUT FREQUENCY TUNING WORD
INPUT DATA RATE/MODULATION FORMAT
FEC/RANDOMIZER/PREAMBLE ENABLE/CONFIGURATION
FIR FILTER COEFFICIENTS
REF CLOCK MULTIPLIER ENABLE
I/Q PHASE INVERT
SLEEP MODE
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
(VS = +3.3 V ⴞ 5%, RSET = 3.9 k⍀, Reference Clock Frequency = 20.48 MHz with
AD9853–SPECIFICATIONS 6ⴛ REFCLK Enabled, Symbol Rate = 2.56 MS/s, ␣ = 0.25, unless otherwise noted)
Parameter
Temp
Test Level
Min
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
6× REFCLK Disabled (+3.3 V Supply)
6× REFCLK Enabled (+3.3 V Supply)
6× REFCLK Disabled (+5 V Supply)
6× REFCLK Enabled (+5 V Supply)
Duty Cycle
Input Capacitance
Input Impedance
Full
Full
Full
Full
+25°C
+25°C
+25°C
IV
IV
IV
IV
IV
V
V
42
7
108
18
40
+25°C
+25°C
+25°C
Full
+25°C
+25°C
+25°C
IV
I
I
V
I
I
V
5
–10
+25°C
+25°C
+25°C
V
V
I
–0.5
+25°C
+25°C
+25°C
+25°C
IV
IV
IV
IV
62
52
48
42
+25°C
+25°C
+25°C
IV
IV
IV
48
44
+25°C
+25°C
+25°C
IV
IV
V
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
10
10
100
10
10
10
10
MHz
ns
ns
ns
ns
ns
ns
ns
Full
Full
IV
IV
10
10
ns
ns
Full
Full
IV
IV
0
0
ns
ns
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Output Offset Temperature Coefficient
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Phase Noise @ 1 kHz Offset, 40 MHz AOUT
6× REFCLK Enabled
6× REFCLK Disabled
Voltage Compliance Range
Wideband SFDR (Single Tone):
1 MHz AOUT
20 MHz AOUT
42 MHz AOUT
65 MHz AOUT1
MODULATOR CHARACTERISTICS
I/Q Offset
Adjacent Channel Power
Error Vector Magnitude
In-Band Spurious Emission
5 MHz–42 MHz AOUT
5 MHz–65 MHz AOUT1
Passband Amplitude Ripple
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulsewidth Low (tPWL)
Minimum Clock Pulsewidth High (tPWH)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (tDS)
Minimum Data Hold Time (tDH)
Minimum Clock Setup—Stop Condition (tCS)
Minimum Clock Hold—Start Condition (tCH)
RESET
Minimum TXENABLE Low to RESET Low (tTR)
Minimum RESET High to Start Condition (tRH)
FEC ENABLE
Minimum FEC ENABLE/DISABLE to TXENABLE High (tFH)
Minimum FEC ENABLE/DISABLE to TXENABLE Low (tFL)
–2–
Typ
Max
Units
126
21
168
28
60
MHz
MHz
MHz
MHz
%
pF
MΩ
3
100
10
10
50
0.5
0.5
5
20
+10
10
0.75
1.5
–100
–110
+1.5
Bits
mA
% FS
µA
nA/°C
LSB
LSB
pF
dBc
dBc
V
68
54
50
44
dBc
dBc
dBc
dBc
1
dB
dBm
%
2
42
40
± 0.3
dBc
dBc
dB
25
REV. C
AD9853
Parameter
Temp
Test Level
TIMING CHARACTERISTICS (Continued)
Wake-Up Time–PLL Power-Down
Wake-Up Time–DAC Power-Down
Wake-Up Time–Digital Power-Down
Data Latency (tDL)
Minimum RESET Pulsewidth Low (tRL)
+25°C
+25°C
+25°C
+25°C
+25°C
IV
IV
IV
IV
IV
CMOS LOGIC INPUTS
Logic “1” Voltage, +5 V Supply
Logic “1” Voltage, +3.3 V Supply
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
I
I
I
I
V
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
I
I
I
I
I
Min
Typ
Max
Units
1
200
5
6
10
ms
µs
µs
Symbols
ns
3
V
V
V
µA
µA
pF
+3.5
+3.0
+0.4
12
12
2
POWER SUPPLY
+VS Current (+3.3 V + 5%)
Full Operating Conditions
With PLL Power-Down Enabled
With DAC Power-Down Enabled
With Digital Power-Down Enabled
With All Power-Down Enabled
+VS Current (+5 V + 5%)
184
178
170
36
16
400
230
224
216
54
20
595
mA
mA
mA
mA
mA
mA
NOTES
1
Reference clock = 28 MHz with clock multiplier enabled; supply voltage = +5 V.
2
Maximum values are obtained under worst case operating modes. Typical values are valid for most applications.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Test Level
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (10 sec Soldering) . . . . . . . . . . . . +300°C
MQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . . 36°C/W
I
– 100% Production Tested.
III – Sample Tested Only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – Devices are 100% production tested at +25°C and
guaranteed by design and characterization testing for
industrial operating temperature range.
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect device
reliability.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD9853AS –40°C to +85°C Metric Quad Flatpack S-44A
(MQFP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
WARNING!
ESD SENSITIVE DEVICE
AD9853
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
CA CLOCK
DGND
CA DATA
REF CLK IN
DVDD
DVDD
DGND
TX ENABLE
Digital Supply Voltage
Bit Clock for Control Bus
Data
4
Control Bus Data In Control Bus Data In
5
FEC Enable
Enables/Disables FEC
6
Address Bit
Address Bit for Control Bus
11, 26, 31 Test Data Out
Factory Use—Serial Test Data
Out
12, 13
PLL GND
PLL Ground
14
PLL VCC
Supply Voltage for PLL
15
PLL Filter
PLL Loop Filter Connection
16, 19, 23 AGND
Analog Ground
17
NC
No Connect
18
DAC Rset
Rset Resistor Connection
20, 22
AVDD
Analog Supply Voltage
21
DAC Baseline
DAC Baseline Voltage
24
IOUT
Analog Current Output of the
DAC
25
IOUTB
Complementary Analog Current Output of the DAC
27
Test CLK
Factory Use—Scan Clock
28
Test Latch
Factory Use—Scan Latch
29
Test Data In
Factory Use—Serial Test Data
In
30
Test Data Enable
Factory Use—Serial Test Data
Enable, Grounded for Normal
Operation
32
RESET
Master Device Reset Function
33
CA Enable
Cable Amplifier Enable
34
CA Clock
Cable Amplifier Serial Control
Clock
35
CA Data
Cable Amplifier Serial Control
Data
38
REF CLK IN
Reference Clock Input
41
Data In
Input Serial Data Stream
42
TXENABLE
Pulse that Frames the Valid
Input Data Stream
DATA IN
DGND
Digital Ground
DVDD
44 43 42 41 40 39 38 37 36 35 34
33 CA ENABLE
DGND 1
DVDD
CONTROL
BUS CLOCK
CONTROL
BUS DATA IN
FEC ENABLE
2
PIN 1
IDENTIFIER
32 RESET
3
31 TEST DATA OUT
4
30 TEST DATA
ENABLE
29 TEST DATA IN
5
AD9853
ADDRESS BIT 6
DGND
28 TEST LATCH
TOP VIEW
(Not to Scale)
7
27 TEST CLK
26 TEST DATA OUT
DVDD 8
DGND 9
25 IOUTB
DGND 10
24 IOUT
TEST DATA 11
OUT
23 AGND
–4–
AVDD
AVDD
DAC BASELINE
AGND
DAC RSET
NC
AGND
NC = NO CONNECT
PLL VCC
12 13 14 15 16 17 18 19 20 21 22
PLL FILTER
1, 7, 9, 10,
36, 39, 44 DGND
2, 8, 37,
40, 43
DVDD
3
Control Bus Clock
44-Lead Metric Quad Flatpack
(S-44A)
Pin Function
PLL GND
Pin Name
PLL GND
Pin #
REV. C
AD9853
Table I. Modulator Function Description
Modulation Encoding Format
FSK*, QPSK, DQPSK, 16-QAM, D16-QAM, Selectable via Control Bus
Output Carrier Frequency Range
DC – 63 MHz with +3.3 V Supply Voltage
DC – 84 MHz with +5 V Supply Voltage
Serial Input Data Rate
Evenly Divisible Fraction of Reference Clock
Pulse-Shaping FIR Filter
41 Tap, Linear Phase, 10-Bit Coefficients Fully Programmable via Control Bus
Interpolation Range
Interpolation Rate = (4/M) × (ICIC1) × (ICIC2) where: M = 2 for QPSK, M = 4 for 16-QAM
Minimum and Maximum Rates
Minimum Interpolation Rate—QPSK = 2 × 3 × 2 = 12
16-QAM = 1 × 4 × 3 = 12
Maximum Interpolation Rate—QPSK = 2 × 31 × 63 = 3906
16-QAM = 1 × 31 × 63 = 1953
These are the minimum and maximum interpolation ratios from the input data rate to the
system clock. The interpolation range is a function of the fixed interpolation factor of four
in the FIR filters, the programmed CIC filter interpolation rates (ICIC1, ICIC2), as well
as system timing constraints.
Maximum Reference Clock Frequency
+3.3 V Supply: 21 MHz with 6× REFCLK enabled, 126 MHz with 6× REFCLK disabled
+5 V Supply: 28 MHz with 6× REFCLK enabled, 168 MHz with 6× REFCLK disabled
6× REFCLK
Fixed 6× reference clock multiplier, enable/disable control via control bus
R-S FEC
Enable/disable via control bus and dedicated control pin. Control pin enable/disable function:
Logic “1” = Enable
Logic “0” = Disable
Primitive Polynomial: p(x) = x8 + x4 + x3 + x2 + 1
Code Generator Polynomial: g(x) = (x + α0)(x + α1)(x + α2) . . . (x + α2t –1)
Selectable via Control Bus
t = 0–10 (Programmable)
Codeword Length (N) = 255 max (Programmable)
N = K + 2 t (K Range = 16 ≤ K ≤ 255 – 2 t)
FEC/Randomizer can be transposed in signal chain via control bus.
I/Q Channel Spectrum
I × COS + Q × SIN (default) or I × COS – Q × SIN, selectable via control bus.
Preamble Insertion
0–96 Bits, Programmable Length and Content
Randomizer
Enable/Disable Control via Control Bus
Generating Polynomial:
x6 + x5 + 1, Programmable Seed (Davic/DVB-Compliant)
or
x15 + x14 + 1, Programmable Seed (DOCSIS-Compliant)
Randomizer and FEC blocks can be transposed in signal chain, via control bus.
*In FSK mode, F0:F1 are direct DDS Cosine output. The two interpolator stages of the AD9853 are not used in the FSK mode and should be programmed for
maximum interpolation rates to reduce unnecessary current consumption. This means that Interpolator #1 should be set to a decimal value of 31, and Interpolator
#2 should be set to decimal value of 63. This is easily accomplished by programming Registers 12 and 13 (hex) with the values of FF (hex).
REV. C
–5–
AD9853
Table II. Control Register Functional Assignment
Register
Address
(Note 1)
D7
D6
00h
MSB
Value of K (Message Length in Bytes) for Reed-Solomon Encoder, where 1610 ≤ K ≤ 25510 (Note 2)
LSB
01h
MSB
The Number of Correctable Byte
Errors (t) for the Reed-Solomon
Encoder, where 0 ≤ t ≤ 1010.
For t = 0, the RS encoder is
effectively disabled.
(Note 3)
DATA
D5
D4
LSB
D3
Randomizer
Insertion
0 = After RS
1 = Before RS
D2
D1
Randomizer Length
002 = 6 Bit
012 = 15 Bit
102 = Randomizer OFF
112 = Randomizer OFF
D0
02h
MSB
Lower Eight Bits of Seed Value for 15-Bit Randomizer (Not Used for 6-Bit Randomizer)
03h
MSB
Upper Seven Bits of Seed Value for 15-Bit Randomizer
– OR –
Seed Value for 6-Bit Randomizer (D1 not used in this case).
LSB
04h
MSB
Preamble Length (L) where 0 ≤ L ≤ 96 Bits (Note 4)
LSB
05h
Modulation Mode
0002 = QPSK , 0012 = DQPSK, 0102 = 16-QAM
0112 = D16-QAM , 1002 = FSK
06h
:
The MSB of the preamble always resides in D7 of Address 11h and is the first preamble bit to be clocked out of the device during transmission of
a packet. Up to 96 bits of preamble are available as specified in Register 04h. Unused bits are don’t care for L < 96.
11h
MSB
Preamble Data. (Note 5)
12h
MSB
Interpolator #1: RATE
Rate Change Factor (R) where 310 ≤ R ≤ 3110
13h
MSB
Interpolator #2: RATE
Rate Change Factor (R) where 210 ≤ R ≤ 6310
14h
MSB
Interpolator #1: SCALE
15h6
MSB
Interpolator #2: SCALE
16h
:
19h
LSB
LSB
LSB
LSB
2× Multiplier
0 = OFF
1 = ON
LSB
LSB
MSB
Frequency Tuning Word #1
FSK Mode: Specifies the “space” frequency (F0).
All Other Modes: Specifies the carrier frequency.
1Ah
:
1Dh
LSB
MSB
Frequency Tuning Word #2
FSK Mode: Specifies the “mark” frequency (F1).
(Addresses 1Ah–1Dh are only valid for FSK mode.)
1Eh5
MSB-2
MSB-3
1Fh
MSB0
MSB-1
:
:
:
10-Bit FIR End Tap Coefficient, a0
LSB0
<— —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ Unused Bits —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —>
FIR Intermediate Tap Coefficients, a1 – a19
46h
MSB-2
MSB-3
47h
MSB20
MSB-1
10-Bit FIR Center Tap Coefficient, a20
LSB20
<— —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ Unused Bits —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —␣ —>
48h
(Note 7)
Spectrum
0 = I × Cos + Q × Sin
1 = I × Cos – Q × Sin
Digital Power
0 = Normal
1 = Shutdown
6× RefClk
0 = Off
1 = On
49h
(Note 8)
MSB
AD8320 Cable Driver Gain Control Byte (GCB)
The absolute gain, AV, of the AD8320 is given by: AV = 0.316 + 0.077 × GCB (where 0 ≤ GCB ≤ 25510)
PLL Mode
0 = Awake
1 = Sleep
NOTES
1
The 8-bit Register Address is preceded by an 8-bit Device Address, which is given by
000001XY, where the value of Bits X and Y are determined as follows:
X
0
1
Voltage Applied to Pin 6
GND
+VS
Y
0
1
DAC Mode
0 = Awake
1 = Sleep
LSB
6
Readback of register 15h results in a value that is 2× the actual programmed value.
This is a design error in the readback function.
Assertion of RESET (Pin 32) sets the contents of this register to 0.
8
Registers 0h–48h may be written to using a single register address followed by a
contiguous data sequence (see Figure 27). Register 49h, however, must be written to
individually; i.e., a separately addressed 8-bit data sequence.
7
Desired Register Function
WRITE
READ
2
This register must be loaded with a nonzero value even if the RS encoder has been
disabled by setting T = 0 in register 01h.
Unused regions are don’t care bit locations.
4
If a preamble is not used this register must be initialized to a value of 0 by the user.
5
Addresses 06h–011h and 1Eh–47h are write only.
3
–6–
REV. C
Typical Performance Characteristics–AD9853
Modulated Output Spectrum with 3.3 V Supply, α = 0.25, 20.48 MHz REFCLK
0
0
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
START 0Hz
6MHz/
STOP 60MHz
Figure 1. QPSK, 320 kb/s, AOUT = 10 MHz
START 0Hz
6MHz/
STOP 60MHz
Figure 4. QPSK, 1.28 Mb/s, AOUT = 10 MHz
0
0
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
–10
–20
–20
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
START 0Hz
6MHz/
STOP 60MHz
Figure 2. QPSK, 640 kb/s, AOUT = 20 MHz
–20
START 0Hz
6MHz/
STOP 60MHz
Figure 5. QPSK, 2.56 Mb/s, AOUT = 20 MHz
0
–10
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
–10
–30
0
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
–10
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
START 0Hz
6MHz/
STOP60 MHz
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
START 0Hz
6MHz/
STOP60 MHz
Figure 6. QPSK, 5.12 Mb/s, AOUT = 42 MHz
Figure 3. QPSK, 1.28 Mb/s, AOUT = 42 MHz
REV. C
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
–10
–7–
AD9853
Modulated Output Spectrum with 5 V Supply, ␣ = 0.25, 27.5 MHz REFCLK
0
–10
–20
0
RBW = 3kHz
VBW = 3kHz
SWT = 22.5s
RF ATT = 10dB
REF LVL = –20dBm
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–10
0 START 0Hz
RBW = 3kHz
VBW = 3kHz
SWT = 22.5s
RF ATT = 10dB
REF LVL = –20dBm
–10
–100
STOP 80MHz
8MHz/
START 0 Hz
Figure 7. QPSK, 1.375 Mb/s, AOUT = 65 MHz
STOP 80 MHz
8 MHz/
Figure 10. QPSK, 5.5 Mb/s, AOUT = 65 MHz
Single Tone Output Spectrum with +3.3 V Supply, 20.48 MHz REFCLK
0
0
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 30dB
REF LVL = 0dBm
–10
0
0
–20
0
–20
0
–30
0
–30
0
–40
–40
0
0
–50
0
–50
0
–60
0
–60
0
–70
–70
0
0
–80
0
–80
0
–90
0
–90
–100
START 0Hz
6MHz/
–100
STOP 60MHz
0
–20
0
START 0Hz
6MHz/
STOP 60MHz
Figure 11. AOUT = 20 MHz
Figure 8. AOUT = 1 MHz
–10
0
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 30dB
REF LVL = 0dBm
–10
0
0
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 30dB
REF LVL = 0dBm
–10
0
–20
0
–30
0
–30
0
0
–40
0
–40
–50
0
–50
0
–60
0
–60
0
–70
0
–70
0
–80
0
–80
0
–90
0
–90
0
–100
–100
START 0Hz
6MHz/
STOP 60MHz
RBW = 5kHz
VBW = 5kHz
SWT = 8s
RF ATT = 30dB
REF LVL = 0dBm
CENTER 40Hz
8MHz/
SPAN 80MHz
Figure 12. AOUT = 65 MHz
(+5 V Supply, 27.5 MHz REFCLK)
Figure 9. AOUT = 42 MHz
–8–
REV. C
AD9853
Output Phase Noise Plots, AOUT = 40 MHz
0
–10
–20
0
RBW = 30Hz
VBW = 30Hz
SWT = 56s
RF ATT = 20dB
REF LVL = –1dBm
–10
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
CENTER 40Hz
1kHz/
–100
SPAN 10MHz
Figure 13. 6ⴛ REFCLK Enabled
RBW = 30Hz
VBW = 30Hz
SWT = 56s
RF ATT = 20dB
REF LVL = –1dBm
CENTER 40Hz
SPAN 10kHz
Figure 14. 6ⴛ REFCLK Disabled
CH PWR = –6.98dBm
ACP UP = –44.95dBm
ACP LOW = –44.66dBm
ALT1 UP = –65.96dBm
ALT1 LOW = –65.99dBm
Figure 15. Adjacent Channel Power, AOUT = 30 MHz,
2.56 MS/s, Channel BW = 3.2 MHz (α = 0.25)
REV. C
1kHz/
–9–
AD9853
Typical Plots of Eye Diagrams and Constellations
CF 42MHz MEAS SIGNAL
SR 1.28MHz EYE [1]
DEMOD QPSK
REF LVL
–7dBm
1.2
T1
T1
1.2
CF 42MHz MEAS SIGNAL
SR 1.28MHz EYE [1]
DEMOD 16QAM
REF LVL
–8dBm
–1.2
–1.2
0
0
3
SYMBOLS
Figure 16. QPSK Modulation
REF LVL
–7dBm
3
Figure 18. 16-QAM Modulation
CF 42MHz MEAS SIGNAL
SR 1.28MHz CONSTELLATION
DEMOD QPSK
REF LVL
–8dBm
CF 42MHz MEAS SIGNAL
SR 1.28MHz CONSTELLATION
DEMOD 16QAM
1.2
T1
T1
1.2
–1.2
–1.5
SYMBOLS
REAL
–1.2
–1.5
1.5
Figure 17. QPSK Modulation
REAL
1.5
Figure 19. 16-QAM Modulation
–10–
REV. C
AD9853
95
0.80
BIT RATE >2Mb/s
VCC = +5V
CONTINUOUS MODE
CLK = 122.88 MHz
VCC = +3.3V
CONTINUOUS MODE
0.75
POWER – Watts
AMBIENT TEMP – 8C
85
75
65
0.70
0.65
55
0.60
45
110 115 120 125 130 135 140 145 150 155 160 165 170
0.55
0
1
2
3
4
BIT RATE – Mb/s
MAX CLOCK RATE – MHz
Figure 20. Max CLK Rate vs. Ambient Temperature
(To Ensure Max Junction Temp is Not Exceeded)
5
6
Figure 23. PWR Consumption vs. Bit Rate
2.6
2.5
2.4
CLK = 165MHz
VCC = +5.0V
BIT RATE = 3.4Mb/s
2.4
VCC = +5.0V
POWER – Watts
POWER – Watts
2.2
2.0
CLK = 165MHz
CONTINUOUS MODE
1.8
2.3
2.2
2.1
1.6
1.4
2.0
VCC = +4.0V
1.2
0
0.5
1.0
1.5
2.0
2.5
3.0
1.9
3.5
0
BIT RATE – Mb/s
Figure 21. Power Consumption vs. Bit Rate
20
40
60
80
BURST MODE DUTY CYCLE – %
Figure 24. Power Consumption vs. Burst Duty Cycle
–40
–40
SPURIOUS IN-BAND EMISSION – dBc
SPURIOUS IN-BAND EMISSION – dBc
AOUT = 42MHz
AOUT = 32MHz
–45
–50
AOUT = 22MHz
–55
AOUT = 12MHz
AOUT = 65MHz
–42
–44
AOUT = 40MHz
–46
–48
AOUT = 20MHz
–50
CLK = 122.88 MHz
VCC = +3.3V
–60
5.12
2.56
CLK = 165MHz
VCC = +4.0V TO +5.0V
1.28
BIT RATE – Mb/s
–52
3.5
0.64
Figure 22. Spurious Emission vs. Bit Rate vs. AOUT
REV. C
100
1.75
0.88
BIT RATE – Mb/s
0.44
Figure 25. Spurious Emission vs. Bit Rate vs. AOUT
–11–
AD9853
FRAME STRUCTURE: MIN TXENABLE LOW TIME = PREAMBLE + 8 SYMBOLS. (EQUATES TO 8 SYMBOLS
MINIMUM SPACING BETWEEN BURSTS WITH NO CHANGE IN PROFILE)
TXENABLE
DATA IN
NOTE: DATA RATE MUST BE PRECISELY
SYNCHRONIZED WITH RISING EDGE
OF TXENABLE
D1
INTERNAL CODEWORD STRUCTURE
AT R-S OUTPUT
D2 D3
D4 D5
D6
D7 DN
DATA PACKET = K BYTES
DON'T CARE
D1
FEC PARITY
D2 D3
D4
D5 D6
D7 DN
DON'T CARE
FEC PARITY
DATA PACKET = K BYTES
(2T BYTES)
ONE CODEWORD
(2T BYTES)
ONE CODEWORD
TXENABLE TO
AOUT LATENCY
FRAME STRUCTURE FOR MULTIPLE CODE WORDS OR CONTINOUS TRANSMISSION:
TXENABLE
DATA IN
D1
D2 D3
D4 D5
D6
D7 DN
DATA PACKET = K BYTES
DON'T CARE
D1 D2
FEC PARITY
D3 D4
D5
D6 D7 DN
FEC PARITY
DATA PACKET = K BYTES
(2T BYTES)
DON'T CARE
(2T BYTES)
INPUT DATA PROCESSING:
TXENABLE
INTERNAL
BIT CLOCK
DATA IN
D1
D2
D3
D4
ENCODER
INPUT
D5
D59
D60
D61
D62
D63
PREAMBLE INSERTION
D64
D65
DN
D1
D2
DATA
PACKET
AND
FEC PARITY
PREAMBLE LENGTH = 96 BITS MAXIMUM
DURING THIS INTERVAL THE DATA IS R-S ENCODED, RANDOMIZED, AND
DELAYED TO SYNCHRONIZE WITH THE END OF THE PREAMBLE DATA.
COMPLETE FRAME AS PRESENTED TO MODULATOR ENCODER:
PREAMBLE
CODEWORD(S)
NOTES ON BURST TRANSMISSION OPERATION:
1. PACKET LENGTH = NUMBER OF INFORMATION BYTES, K
2. IN FEC MODE TXENABLE MUST BE KEPT HIGH FOR N 3 (K+2T) BYTES WHERE N IS THE NUMBER OF CODEWORDS
3. IF NECESSARY, ZERO FILL THE LAST CODEWORD TO REACH ASSIGNED K DATA BYTES PER CODEWORD
1
4. THE INPUT DATA IS SAMPLED AT THE BIT RATE FREQUENCY (fB) WITH THE FIRST SAMPLE TAKEN AT
RISING EDGE OF TXENABLE
2 3 (fB)
SECONDS AFTER THE
(# OF PREAMBLE BITS)
5. PREAMBLE DELAY =
(BIT RATE FREQUENCY)
6. DATA RATE MUST BE EXACT SUB-MULTIPLE OF REFERENCE CLOCK.
Figure 26. Data Framing and Processing
–12–
REV. C
AD9853
WRITE
DEVICE ADDRESS
S
A(S)
REGISTER ADDRESS
A(S)
DATA
LSB = 0
READ
DATA A(S)
P
LSB = 1
DEVICE ADDRESS
S
A(S)
A(S)
REGISTER ADDRESS
S = START CONDITION
P = STOP CONDITION
A(S)
S
DEVICE ADDRESS
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA A(M)
DATA A(M)
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 27. Serial Control Bus—Read and Write Sequences
MSB
0
0
0
0
0
1
A
R/W
LSB
0 = WRITE / 1 = READ
ADDRESS CONTROL
(SET VIA DEVICE PIN 6)
Figure 28. Serial Control Bus—8-Bit Device Address Detail
FEC DISABLE/
ENABLE CONTROL
TX ENABLE
t FL
t FH
tFH = FEC TO TXENABLE SETUP TIME = 0ns
tFL = FEC TO TXENABLE HOLD TIME = 0ns
Figure 29. FEC Enable/Disable Timing Diagram
TX ENABLE
t TR
t RL
t MP
RESET
t PWH
t PWL
CONTROL CLOCK
t RH
t CH
t DS
t DH
CONTROL DATA
tTR = MINIMUM TXENABLE LOW TO RESET LOW = 10ns
tRL = MINIMUM RESET PULSEWIDTH = 10ns
tRH = MINIMUM RESET TO START CONDITION = 10ns
tCH = MINIMUM CLOCK HOLD TIME START CONDITION = 10ns
tCS = MINIMUM CLOCK SETUP TIME STOP CONDITION = 10ns
tDS = MINIMUM DATA SETUP TIME = 10ns
tDH = MINIMUM DATA HOLD TIME = 10ns
tPWH = tPWL = MINIMUM CLOCK PULSEWIDTH HIGH/LOW = 10ns
tMP = MINIMUM CLOCK PERIOD = 40ns = 25MHz
Figure 30. Serial Control Interface Timing Diagram
REV. C
–13–
t CS
P
AD9853
t RL
RESET
CONTROL BUS
NOTE
2
NOTE 1
NOTE
2
START UP
SEQUENCE
TXENABLE
DAC OUT
t DL
tRL: MINIMUM RESET LOW TIME = 10ns
tDL: DATA LATENCY = 6 SYMBOLS
NOTE 1. DURING THIS INTERVAL ALL CONTROL BUS REGISTERS MUST BE PROGRAMMED.
NOTE 2. DURING THIS INTERVAL THE CONTROL REGISTER (48h) MAY NEED TO BE REPROGRAMMED DUE TO BEING CLEARED
BY THE PRECEDING RESET PULSE.
NOTE 3. THREE RESETS ARE REQUIRED TO ENSURE THAT THE DATA PATH IS ZERO'D.
Figure 31. Recommended Start-Up Sequence
NOTES ON THE RESET FUNCTION:
1. RESET IS ACTIVE LOW
2. RESET ZEROS THE CONTROL REGISTER AT ADDRESS 48 HEX WHICH CAUSES THE FOLLOWING DEFAULT
CONDITION TO EXIST:
A. 63 REFCLK IS DISABLED
B. OUTPUT SPECTRUM IS SET TO I3COS+Q3SIN
C. DIGITAL PLL POWER-DOWN IS DISABLED
D. PLL POWER-DOWN IS DISABLED
E. DAC PLL POWER-DOWN IS DISABLED
3. SERIAL CONTROL BUS IS RESET AND INITIALIZED.
4. OUTPUTS OF MODULATION ENCODERS ARE SET TO ZERO. THIS ALLOWS THE FIR FILTERS AND
SUBSEQUENT INTERPOLATION FILTERS TO BE FLUSHED WITH ZEROS AS LONG AS TXENABLE IS HELD LOW.
5. THE PREAMBLE IS CLEARED UPON EXECUTION OF THE RESET FUNCTION.
GAIN CONTROL BUS
DATA IN
REF
CLOCK IN
DIRECT
CONTROL
LINES
AD9853
DIGITAL
QPSK/16–QAM
MODULATOR
SERIAL
CONTROL
BUS
AD8320
COUPLING
CIRCUIT AND
LP FILTER
TO
DIPLEXER
PROGRAMMABLE
CABLE DRIVER
AMPLIFIER
POWER
DOWN
CONTROL
CONTROL
PROCESSOR
PROCESSOR
Figure 32. Basic Implementation of AD9853 Digital Modulator and AD8320 Programmable Cable Driver Amplifier in
Return-Path Application
–14–
REV. C
AD9853
THEORY OF OPERATION
The AD9853 is a highly integrated modulator function that has
been specifically designed to meet the requirements of the HFC
upstream function for both interoperable and proprietary system
implementations. The AD8320 is a companion cable driver
amplifier with a digitally-programmable gain function, that
interfaces to the AD9853 modulator and directly drives the
cable plant with the modulated carrier. Together, the AD9853
and AD8320 provide an easily implementable transmitter solution for the HFC return-path requirement.
CONTROL AND DATA INTERFACE
As shown in the device’s block diagram on the front page, the
various transmit parameters, which include the input data rate,
modulation format, FEC and randomizer configurations, as well
as all the other modulator functions, are programmed into the
AD9853 via a serial control bus. The AD8320 cable driver amp
gain can be programmed directly from the AD9853 via a 3-wire
bus by writing to the appropriate AD9853 register. The AD9853
also contains dedicated pins for FEC enable/disable and a RESET
function.
Note: TXENABLE pin must be held low for the duration of all
serial control bus operations.
The AD9853’s serial control bus consists of a bidirectional data
line and a clock line. Communication is initiated upon a start
condition, which is defined as a high-to-low transition of the
data line while the clock is held high. Communication terminates
upon a stop condition, which is defined as a low-to-high transition in the data line while the clock is held high. Ordinarily, the
data line transitions only while the clock line is low to avoid a
start or stop condition. Data is always written or read back in
8-bit bytes followed by a single acknowledge bit. The microcontroller or ASIC (i.e., the bus master) transfers eight data bits
and the AD9853 (i.e., the slave) issues the acknowledge bit. The
acknowledge bit is active low and is clocked out on every ninth
clock pulse. The bus master must three-state the data line during the ninth clock pulse and allow the AD9853 to pull it low.
A valid write sequence consists of a minimum of three bytes.
This means 27 clock pulses (three bytes with nine clock pulses
each) must be provided by the bus master. The first byte is a
chip address byte that is predefined except for Bit Positions 1
and 0. Bit Positions 7, 6, 5, 4 and 3 must be zero. Bit Position 2
must be a one. Bit 1 is set according to the external address pin
on the AD9853 (1 if the pin is connected to +VS; 0 if the pin
is grounded). Bit 0 is set to 1 if a read operation is desired, 0 if a
write operation is desired. The second byte is a register address
with valid addresses between 00h and 49h. An address which is
outside of this range will not be acknowledged. The third byte is
data for the address register. Multiple data bytes are allowed
and loaded sequentially. That is, the first data byte is written to
the addressed register and any subsequent data bytes are written
to subsequent register addresses. It is permissible to write all
registers by issuing a valid chip address byte, then an address
byte of 00h and then 72 (48h) data bytes. Address 49h must be
written independently, that is, not in conjunction with any other
address.
A valid read sequence consists of a minimum of four bytes (refer
to Figure 27). This means the bus master must provide 36 clock
pulses (four bytes with nine clock pulses each). Like the write
sequence, the first two bytes are the Chip Address Byte, with the
REV. C
read/write bit set to 0, and the readback register address. After
the slave provides an acknowledge at the end of the register
address, the master must present a START condition on the
bus, followed by the Chip Address Byte with the read/write bit
set to a 1. The slave proceeds to provide an acknowledge. During the next eight clocks the slave will write to the bus from the
register address. The master must provide an acknowledge on
the ninth clock of this byte. Any subsequent clocks from the
master will force the slave to read back from subsequent registers. At the end of the read-back cycle, the MASTER must force
a “no-acknowledge” and then a STOP condition. This will take
the SLAVE out of read-back mode. Not all of the serial control
bus registers can be read back. Registers (06h–11h) and (1Eh–
47h) are write only. Also, like the writing procedure, register
49h must be read from independently.
INPUT DATA SYNCHRONIZATION
The serial input data interface consists of two pins, the serial
data input pin and a TXENABLE pin. The input data arrives at
the bit rate and is framed by the TXENABLE signal as shown in
Figure 26. A high frequency sampling clock continuously
samples the TXENABLE signal to detect the rising edge. Once
the rising edge of TXENABLE is detected, an internal sampler
strobes the serial data at the correct point in time relative to the
positive TXENABLE transition and then continues to sample at
the correct interval based on the programmed Input Data rate.
For proper synchronization of the AD9853, 1) the input burst
data must be accurately framed by TXENABLE and 2) the
input data rate must be an exact even submultiple of the system
clock. Typically this will require that the input data rate clock be
synchronized with reference clock.
REED-SOLOMON ENCODER
The AD9853 contains a programmable Reed-Solomon (R-S)
encoder capable of generating an (N, K) code where N is the
code word length and K is the message length.
Error correction becomes vital to reliable communications when
the transmission channel conditions are less than ideal. The
original message can be precisely reconstructed from a corrupted transmission as long as the number of message errors is
within the encoder’s limits. When forward error correction
(FEC) is engaged, either through the serial control interface
bus or hardware (logic high at Pin 5), it is implemented using
the following MCNS-compatible field generator and primitive
polynomials:
p(x) = x8 + x4 + x3 + x2 + 1
Primitive Polynomial:
Code Generator Polynomial: g(x) = (x + a0)(x + a1)(x + a2)
. . . (x + a2t – 1)
The code-word structure is defined as follows:
N = K + 2t (bytes)
where:
N = code-word length
K = message length (in bytes), programmable from 16–255
t=
number of byte errors that can be corrected programmable
from 0–10.
A Code Word is the sum of the Message Length (in bytes) and
number of Check Bytes required to correct byte errors at the
–15–
AD9853
receive end. The values actually programmed on the serial control bus are “K” and “t,” which will define N as shown in the
above code-word structure equation. As can be seen from the
code-word structure equation, two check bytes are required to
correct each byte error. Setting t = 0 and K > 0 will bypass the
Reed-Solomon encoding process.
PREAMBLE INSERTION BLOCK
Since Reed-Solomon works on bytes of information and not
bits, a single byte error can be as small as one inverted bit out of
a byte, or as large as eight inverted bits of one byte; in either
instance the result is one byte error. For example, if the value
“t” is specified as 5, the R-S FEC could be correcting as many
as 40, or as few as 05, erroneous bits, but those errors must be
contained in 5 message bytes. If the errors are spread among
more than five bytes, the message will not be fully error corrected.
As shown in the block diagram of the AD9853, the circuit includes a programmable preamble insertion register. This register
is 96 bits long and is transmitted upon receiving the TXENABLE
signal. It is transmitted without being Reed-Solomon encoded
or scrambled. Ramp-up data, to allow for receiver synchronization, is included as the first bits in the preamble, followed by
user burst profile or channel equalization information. The first
bit of R-S encoded and scrambled information data is timed to
immediately follow the last bit of preamble data.
For most modulation modes, a minimum preamble is required.
This minimum is one symbol, two bits for DQPSK or four bits
for either 16-QAM or D16-QAM. No preamble is required for
either FSK or QPSK.
The position of the R-S encoder in the coding data path can be
switched with the randomizer by exercising Register 1, Bit D3,
via the serial control bus.
In conformance with DAVIC/DVB standards, the preamble is
not differentially coded in DQPSK mode. However the preamble data can be differentially precoded when loaded into the
preamble register. The last symbol of the preamble is used as
the reference point for the first internal differentially coded
symbol so the preamble and data will effectively be coded differentially. In the D16-QAM mode, the preamble is always differentially coded internally.
RANDOMIZER FUNCTION
MODULATION ENCODER
When using the R-S encoder, the message data needs to be
partitioned or “gapped” with “don’t care” data for the time
duration of the check bytes as shown in the timing diagram of
Figure 26. During the intervals between message data, the device ignores data at the input.
The next stage in the modulation chain is the randomizing or
“scrambling” stage. Randomizing is necessary due to the fact
that impairments in digital transmission can be a function of the
statistics of the digital source. Receiver symbol synchronization
is more easily maintained if the input sequence appears random
or equiprobable. Long strings of 0s or 1s can cause a bit or
symbol synchronizer to lose synchronization. If there are repetitive patterns in the data, discrete spurs can be produced, causing interchannel interference. In modulation schemes relying on
suppressed carrier transmission, nonrandom data can increase
the carrier feedthrough. Using a randomizer effectively “whitens”
the data.
The technique used in the AD9853 to randomize the data is to
perform a modulo 2 logic addition of the data with a pseudorandom sequence. The pseudorandom sequence is generated by
a shift register of length m with an exclusive OR combination of
the nth bit and the last (mth) bit of the shift register that is fed
back to the shift register input. By choosing the appropriate
feedback point, a maximal length sequence is generated. The
maximal length sequence will repeat after every 2m clock cycles,
but appears effectively “random” at the output. The criterion
for maximal length is that the polynomial 1 + xn + xm be irreducible and prime over the Galois field. The AD9853 contains
the following two polynomial configurations in hardware:
x15 + x14 +1 :MCNS (DOCSIS) compatible.
x6 + x5 +1
:DAVIC/DVB compatible.
The seed value is fully programmable for both configurations.
The seed value is reset prior to each burst and is used to calculate the randomizer bit, which is combined in an exclusive XOR
with the first bit of data from each burst. The first bit of data in
a burst is the MSB of the first symbol following the last symbol
of the internally generated preamble.
The preamble, followed by the encoded and scrambled data is
then modulation encoded according to the selected modulation
format. The available modulation formats are FSK, QPSK,
DQPSK, 16-QAM and D16-QAM. The corresponding symbol
constellations support the interactive HFC cable specifications
called out by MCNS (DOCSIS), 802.14 and DAVIC/DVB.
The data arrives at the modulation encoder at the input bit rate
and is demultiplexed as modulation encoded symbols into separate I and Q paths. For QPSK and DQPSK, the symbol rate is
one-half of the bit rate and each symbol is comprised of two
bits. For 16-QAM and D16-QAM, the symbol rate is onefourth the bit rate and each symbol is comprised of four bits. In
the FSK mode, although the 1 and 0 data is entered into the
serial data input, it effectively bypasses the encoding, scrambling
and modulation paths. The FSK data is directly routed to the
direct digital synthesizer (DDS) where it is used to switch the
DDS between two stored tuning words (F0:F1) to achieve FSK
modulation in a phase-continuous manner. By holding the input
at either 1 or 0, a single frequency continuous wave can be
output for system test or CW transmission purposes.
Differential encoding of data is frequently used to overcome
phase ambiguity error or a “false lock” condition that can be
introduced in carrier-recovery circuits used to demodulate the
signal. In straight QPSK and 16-QAM, the phase of the received signal is compared to that of a “recovered carrier” of
known phase to demodulate the signal in a coherent manner. If
the phase of the recovered carrier is in error, then demodulation
will be in error. Differential encoding of data at the transmit end
eliminates the need for absolute phase coherency of the recovered carrier at the receive end. If a coherent reference generated
by a phase lock loop experiences a phase inversion while demodulating in a differentially coded format, the errors would be
limited to the symbol during which the inversion occurred and
the following symbol. Differential coding uses the phase of the
“previously transmitted symbol” as a reference point to compare
to the current symbol. The change in phase from one symbol to
–16–
REV. C
AD9853
the next contains the message information and is used to demodulate the signal instead of the absolute phase of the signal.
The transmitter and receiver must use the same symbol derivation scheme.
0 and 1 yield a tradeoff between excess bandwidth in the frequency domain and tail suppression in the time domain.
Differential encoding in the AD9853 occurs while data still
exists as a serial data stream. When in straight QPSK or 16-QAM,
the serial data stream passes to the symbol mapper/format encoder stage without modification. When differential encoding is
engaged, the serial data stream is modified prior to the symbol
mapper/format stage according to Table VI. Only I1 and Q1 are
modified, even in the D16-QAM mode whose symbols are composed of Q1, I1, Q0, I0. In D16-QAM, only the two MSBs of
the 4-bit symbol are modified; furthermore, the “previously
transmitted symbol” referred to in Table VI are the two MSBs
of the previous 4-bit symbol.
Symbol mapping for QPSK and DQPSK are identical. Symbol
mapping for 16-QAM and D16-QAM are slightly different (see
Figure 37) in accordance with MCNS (DOCSIS) specifications.
Special Note: For most modulation modes, a minimum preamble is required. For DQPSK the minimum preamble is one
symbol (2 bits) and for either 16-QAM or D16-QAM the minimum preamble is one symbol (4 bits). For FSK or QPSK, no
preamble is required.
User should be additionally aware that in the DQPSK mode,
the preamble is not differentially encoded in accordance with
MCNS (DOCSIS) specifications. If the preamble must be differentially encoded, it can “pre-encoded” using the derivation in
Table VI. In D16-QAM, the preamble is always differentially
encoded as is the “payload” data.
When initiating a new differentially encoded transmission, the
“previously transmitted symbol” is always the last symbol of the
preamble.
PROGRAMMABLE PULSE-SHAPING FIR FILTERS
The I and Q data paths of the modulator each contain a pulse
shaping filter. Each is a 41-tap, linear phase FIR. They are used
to provide bandwidth containment and pulse shaping of the data
in order to minimize intersymbol interference. The filter coefficients are programmable, so any realizable linear phase response
characteristic may be implemented. The linear phase restriction
is due to the fact that the user may only define the center coefficient and the lower 20 coefficients. The hardware fills in the
upper 20 coefficients as a mirror image of the lower 20. This
forces a linear phase response. It should also be noted that the
pulse shaping filter upsamples the symbol rate by a factor of
four.
Normally, a square-root raised cosine (SRRC) response is desired.
In fact, the AD9853 Evaluation Board software driver implements
an SRRC response. When using the SRRC response, an excess
bandwidth factor (α) is defined that affects the low pass roll-off
characteristic of the filter (where 0 ≤ α ≤ 1). When α = 0, the
SRRC is an ideal low-pass filter with a “brick wall” at one-half
of the symbol rate (the Nyquist bandwidth of the data). Although
this provides maximum bandwidth containment, it has the adverse affect of causing the tails of the time domain response to
be large, which increases intersymbol interference (ISI). On the
other hand, when α = 1, the SRRC yields a smooth roll-off
characteristic that significantly reduces the time domain tails,
which improves ISI. Unfortunately, the cost of this benefit is a
doubling of the bandwidth of the data signal. Values of α between
REV. C
The FIR filter coefficients for the SRRC response may be calculated using a variety of methods. One such method uses the
Inverse Fourier Transform Integral to calculate the impulse response (time domain) from the SRRC frequency response (frequency domain). An example of this method is shown in Figure
33. Of course, this method requires that the SRRC frequency
response be known beforehand.
The FIR filters in the AD9853 are implemented in hardware
using a fixed point architecture of 10-bit, twos complement
integers. Thus, each of the filter coefficients, ai, is an integer
such that:
–512 ≤ ai ≤ 511
[i = 0, 1, … , 40]
PROGRAMMABLE INTERPOLATION FILTERS
The AD9853 employs two stages of interpolation filters in each
of the I and Q channels of the modulator. These filters are
implemented as Cascaded Integrator-Comb (CIC) filters. CIC
filters are unique in that they not only provide a low-pass frequency response characteristic, but also provide the ability to
have one sampling rate at the input and another sampling rate at
the output. In general, a CIC filter may either be used as an
interpolator (low-to-high sample rate conversion) or as a
decimator (high-to-low sample rate conversion). In the case of
the AD9853, the CIC filters are configured as interpolators,
only. Furthermore, the interpolation is done in two separate
stages with each stage designed so that the rate change is programmable. The first interpolator stage offers rate change ratios
of 3 to 31, while the second stage offers rate change ratios of 2
to 63.
As stated in the previous section, the data coming out of the
FIR filters is oversampled by four. Spectral images appear at
their output (a direct result of the sampling process). These
images are replicas of the baseband spectrum which are repeated at intervals of four times the symbol rate (the rate at
which the FIR filters sample the data). The images are an unwanted byproduct of the sampling process and effectively represent a source of noise.
Normally, the output of the FIR filters would be fed directly to
the input of the I and Q modulator. This means that the spectral
images produced by the FIRs would become part of the modulated signal—definitely not a desirable consequence. This is
where the CIC filters play their role. Since they have a low-pass
characteristic, they can be used to eliminate the spectral images
produced by the FIRs.
Frequency Response of the CIC Filters
The frequency response of a CIC filter is predictable. It can be
shown that the system function of a CIC filter is:
 R M −1 
H (z ) =  ∑ z − k 
 k=0

N
Where N is the number of cascaded integrator (or comb) sections, R is the rate change ratio, and M is the number of unit
delays in each integrator/comb stage. For the AD9853, two of
these variables are fixed as a result of the hardware implementation; specifically, N = 4 and M = 1. As mentioned earlier, R (the
rate change ratio) is programmable.
–17–
AD9853
SQUARE-ROOT RAISED COSINE (SRRC) FIR FILTER
COMPUTE AND PLOT SRRC FILTER COEFFICIENTS:
ttap :=
tap := 0..TAPS – 1
1
. tap – TAPS – 1
2
FreqScale
BW
...INVERSE FOURIER INTEGRAL COMPUTE SRRC IMPULSE RESPONSE (TIME DOMAIN) FROM
THE SRRC FREQUENCY RESPONSE (FREQUENCY DOMAIN). THE COS() FUNCTION REPLACES
THE NORMAL COMPLEX EXPONENTIAL BECAUSE WE ARE RESTRICTED TO REAL
FILTER COEFFICIENTS.
SRRC(f) . cos(2 . p . f . t)df
h(t) :=
0
htap := h(ttap)
h . SCALEPROC GAIN
max(h)
h := INT
...MAP THE FILTER TAP INDEX TO TIME DOMAIN (CENTERED AT T=0)
...SRRC FILTER COEFFICIENTS INTEGERIZED AND SCALED
SRRC IMPULSE RESPONSE
htap
500
0
0
10
5
15
20
25
30
35
40
TAP
hT =
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
3
2
–2
–5
–2
5
7
1
–7
–7
7
19
7
–34 –71 –48
71
18
19
20
260 438 511
...FIR FILTER
COEFFICIENTS
COMPUTE AND PLOT SRRC FREQUENCY RESPONSE:
freq_pts := 250
0.5
Df := freq_pts – 1
n := 0..freq_pts – 1
...DEFINE NUMBER OF FREQUENCY POINTS AND FREQUENCY STEP SIZE (FOR PLOTTING PURPOSES)
fn := Df . n
...CREATE VECTOR OF UNIFORMLY SPACED FREQUENCY POINTS {fmax = 0.5; A REQUIREMENT OF THE GAIN() FUNCTION},
K := (| gain(h,0) |)–1 Hn := K . | gain (h,fn) |
...NORMALIZED FREQUENCY RESPONSE
SRRC NORMALIZED FREQUENCY RESPONSE
0
Hn – dB
FREQUENCY SCALED TO SYMBOL RATE
–20
–40
–60
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY SCALE – fn
1.4
1.6
1.8
2.0
GLOBAL DECLARATIONS
CONSTANTS:
a 0.5
.
BW 0.5 (1 + a)
1
PROC_GAIN
511
SCALE
TAPS 41
FreqScale 4
...EXCESS BANDWIDTH FACTOR FOR SRRC FREQUENCY RESPONSE
...BANDWIDTH OF SRRC FILTER (RELATIVE TO SYMBOL RATE)
...PROCESSING GAIN OF CIC FILTERS (USED TO CORRELATE RESULTS WITH AD9853 EVAL. BD.)
...SETS MAX VALUE OF SRRC FILTER BASED ON FINITE WORD SIZE
...NUMBER OF FIR PULSE SHAPING FILTER TAPS
...UPSAMPLING RATIO OF FIR PULSE SHAPING FILTER (RELATIVE TO THE SYMBOL RATE)
FUNCTIONS:
InRange (x,a,b) (x a) . (x b)
...RETURNS 1 IF a <= x <= b, 0 OTHERWISE
INT(x) floor (x + 0.5)
...RETURNS NEAREST INTEGER TO x
.
...RATIO TO DECIBEL CONVERSION FUNCTION
dB(x)
if (| x | = 0, 200, 20 log (| x |))
.
SRRC(f)
passband
0.5 (1 – a)
...SRRC FREQUENCY RESPONSE FUNCTION
stopband
0.5 (1 + a)
(f IS RELATIVE TO THE SYMBOL RATE)
if InRange (f, 0, stopband)
1 if InRange (f, 0, passband)
p .
cos
(2 . f + a – 1) if InRange (f, passband, stopband)
4 .a
0 otherwise
Figure 33. Mathcad Simulation of a 41-Tap SRRC Filter
–18–
REV. C
AD9853
The frequency response, H(f), of a CIC filter is found by evaluating H(z) at z = e j(2πf/R):
 R M −1 − j 2πf / R k 
)
H( f ) =  ∑ e (


 k=0

the frequency scales of the two functions match. Thus, the
actual HCOMP function required is given by:
N
H COMP =
where f is relative to the input sample rate of the CIC filter.
With this formula, we can accurately predict the frequency
response of the CIC filters.
Compensating for CIC Roll-Off
As discussed previously, the CIC filters offer a low-pass characteristic that can be used to eliminate the spectral images produced by the FIR filters. Unfortunately, the CIC response is not
flat over the frequency range of the baseband signal. Thus, the
inherent attenuation (or roll-off) of the CIC filters distorts the
baseband data signal. So even though the CIC filters help to
eliminate the images described earlier, they introduce another
form of error to the baseband signal—frequency-dependent
amplitude distortion. This ultimately manifests itself as a higher
level of Error Vector Magnitude (EVM) at the output of the
I and Q modulator. Also, the larger the bandwidth of the
baseband signal, the more pronounced the CIC roll-off, the
greater the amplitude distortion and the worse the EVM performance. This is a serious problem because if a value of α =1 is
used for the SRRC response of the FIR filters, a doubling of the
bandwidth of the baseband signal results and hence, a degradation in EVM performance.
Fortunately, there is a way to compensate for the effects of CIC
roll-off. Since the frequency response of the CIC filters is predictable, it is possible to compensate for the CIC roll-off characteristic by adjusting the response of the FIR filters accordingly.
The adjustment is accomplished by modifying the FIR filter
response with a response that is the inverse of that of the CIC
filters. This is done by precompensating the FIR filters.
To perform CIC compensation, we simply define a function
(HCOMP) that has a response which is the inverse of the CIC
response. Specifically,
()
H COMP f =
1
()
H f
By multiplying the original FIR filter frequency response by
HCOMP, we obtain the necessary compensation.
Unfortunately, it’s not quite this simple. Recall that the coefficients of the baseband filter were computed using an inverse
Fourier transform integral which included the SRRC function.
In order to compensate for the CIC filter response, the SRRC
function must be multiplied by the HCOMP function. But the
frequency scale of the SRRC response is computed based on
frequencies relative to the symbol rate, while the HCOMP function is computed relative to the input sampling rate of the CIC
filter. The input CIC sampling rate happens to be the same as
the sample rate of the FIR filter (see Figure 36), or four times
the symbol rate. Thus, we have a frequency scaling problem.
This problem is easily corrected by introducing a frequency
scaling factor (FreqScale = 4) into the HCOMP function so that
REV. C
1


f
H

 FreqScale 
It should be noted that in compensating for the CIC roll-off,
only the first stage CIC filter need be considered. This is due to
the fact that at the output of the first stage CIC filter the
bandwidth of the signal is reduced to the point that the roll-off
introduced by the second stage is negligible in the region of the
baseband signal.
The CIC compensation method is demonstrated by example
(using MathCad) in Figures 34 and 35. An interpolation rate
(R) of 6 is used in the example. The improvement obtained by
compensating for the CIC response is graphically demonstrated
in Figure 35 which shows:
• the SRRC filter response (which is the desired overall response)
• the composite response of the SRRC in series with the CIC
filter (distorted response)
• the composite response of the compensated SRRC in series
with the CIC (corrected response)
Note that the ideal SRRC response and the compensated composite response are virtually identical in the region of the passband. Thus, the goal of correcting for the CIC filter response
has been accomplished.
There is one subtlety to be noted in the example. The CIC
compensation is only applied to the first 90% of the bandwidth
of the baseband signal (note the variable ␤ inside the integral).
It was found that compensation over the full 100% of the bandwidth produced a reduction in the suppression of signals in the
stopband region of the SRRC. This resulted in creating more
distortion than by not correcting for the CIC roll-off in the first
place. However, by slightly reducing the bandwidth over which
correction is applied, the stopband suppression is once again
restored and a significant improvement in EVM performance is
obtained.
Determining the Necessary Interpolator Rate Change Ratio
The AD9853 contains three stages of digital interpolation:
1) Fixed 4× Pulse Shaping FIR Filter.
2) Programmable 3 to 31 First Interpolation Filter.
3) Programmable 2 to 63 Second Interpolation Filter.
After the serial input data stream has been encoded into QPSK
or 16-QAM symbols, the symbol interpolation rate of the AD9853
is determined by the product of the three interpolating stages
listed above. In QPSK mode, the minimum symbol interpolation
rate that will work is 4 × 3 × 2 = 24; for 16-QAM the minimum
is 4 × 4 × 3 = 48. The maximum symbol interpolation rate is
4 × 31 × 63 = 7812. The symbol rate at the encoder output for
QPSK is equal to 1/2 the bit rate of the data and for 16-QAM it
is 1/4 the bit rate. Figure 36 is a partial block diagram of the
AD9853 and follows the path of the data stream from the input
of the I and Q encoder block to the output of the DAC.
–19–
AD9853
MODIFICATION OF SQUARE-ROOT RAISED COSINE (SRRC) FIR FILTER RESPONSE
TO COMPENSATE FOR CASCADED INTEGRATOR-COMB (CIC) FILTER RESPONSE
COMPUTE SRRC FILTER COEFFICIENTS:
ttap :=
tap := 0..TAPS – 1
1
. tap – TAPS – 1
2
FreqScale
...MAP THE FILTER TAP INDEX TO TIME DOMAIN (CENTERED AT t = 0)
BW
h(t) :=
...INVERSE FOURIER INTEGRAL COMPUTES SRRC IMPULSE RESPONSE
(TIME DOMAIN) FROM THE SRRC FREQUENCY RESPONSE (FREQUENCY DOMAIN).
THE COS() FUNCTION REPLACES THE NORMAL COMPLEX EXPONENTIAL
BECAUSE WE ARE RESTICTED TO REAL FILTER COEFFICIENTS.
SRRC(f) . cos(2 . p . f . t)df
0
htap := h(ttap)
h := INT
h . PROC_GAINSCALE
max(h)
...SRRC FILTER COEFFICIENTS INTEGERIZED AND SCALED
COMPUTE SRRC FILTER COEFFICIENTS MODIFIED
FOR CORRECTION OF CIC RESPONSE:
...CIC INTERPOLATION RATIO (USER PROGRAMMABLE)
R := 6
H(0,R)
BW
b . BW,
SRRC (f) . if f
h1(t) :=
0
h1tap := h1(ttap)
,1 . cos(2 . p . f . t)df
f
H FreqScale ,R
h1 . PROC_GAINSCALE
max(h1)
h1 := INT
...INVERSE FOURIER INTERGRAL MODIFIES THE SRRC RESPONSE
BY THE RECIPROCAL OF THE NORMALIZED CIC FREQUENCY
RESPONSE. THE MODIFICATION IS ONLY PERFORMED OVER THE
FRACTION OF THE SRRC BANDWIDTH AS SPECIFIED BY b.
...MODIFIED SRRC FILTER COEFFICIENTS INTEGERIZED AND SCALED TO 10-BIT RANGE
SRRC AND MODIFIED SRRC IMPULSE RESPONSE
500
htap
h1tap
0
0
10
5
15
20
25
30
35
40
TAP
hT =
0
h1T =
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
3
2
–2
–5
–2
5
7
1
–7
–7
7
19
7
–34 –71 –48
71
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
1
4
2
–3
–6
–1
7
9
1
–10 –9
8
24
12
–34 –78 –61
56
15
18
19
20
...FIR FILTER COEFFICIENTS
FOR SRRC RESPONSE
260 438 511
18
19
20
251 435 511
...FIR FILTER COEFFICIENTS
FOR SRRC RESPONSE
WITH CIC COMPENSATION
DISPLAY FREQUENCY RESPONSE PLOTS:
...NORMALIZED FREQUENCY RANGE [A REQUIREMENT OF MATHCAD'S GAIN() FUNCTION]
f:= 0,0.001.. 0.5
SCALEsrrc := (| gain(h,0) |)–1
SCALEsrrc := 5.559 . 10–4
SCALEcompsrrc := (| gain(h1,0) |)–1
SCALEcompsrrc := 5.79 . 10–4
SCALEcic := (| H(0,R) |)–1
SCALEcic := 7.716 . 10–4
...SCALE FACTORS TO ADJUST SRRC,
COMPENSATED SRRC, AND CIC
FREQUENCY RESPONSES TO UNITY AT f = 0
...FUNCTION TO COMPUTE NORMALIZED, UNCOMPENSATED FIR RESPONSE (SRRC) IN dB
FIR(f) := dB(SCALEsrrc . | gain(h,f) |)
...FUNCTION TO COMPUTE NORMALIZED CIC RESPONSE IN dB
CIC(f) := dB(SCALEcic . | H(f,R) |)
COMP(f) := dB(SCALEcompsrrc . | gain(h1,f) |) ...FUNCTION TO COMPUTE NORMALIZED, COMPENSATED FIR RESPONSE (SRRC + CIC–1) IN dB
SYSuncomp(f) := FIR(f) + CIC(f)
...FUNCTION TO COMPUTE OVERALL SYSTEM RESPONSE OF SRRC AND CIC TOGETHER IN dB
...FUNCTION TO COMPUTE OVERALL SYSTEM RESPONSE OF COMPENSATED SRRC AND CIC TOGETHER
SYScomp(f) := COMP(f) + CIC(f)
SRRC, CIC, AND CORRECTED SRRC RESPONSE
0
–20
FIR(f)
CIC(f)
COMP(f) –40
–60
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY SCALE – fn
1.4
1.6
1.8
2.0
Figure 34. Mathcad Simulation of 41-Tap SRRC Filter with CIC Compensation
–20–
REV. C
AD9853
RESPONSE OF NORMAL SRRC, NORMAL SRRC + CIC, AND COMPENSATED SRRC + CIC
0
–20
FIR(f)
SYSuncomp(f)
SYScomp(f) –40
–60
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY SCALE – f
FREQUENCY SCALED TO SYMBOL RATE
1.4
1.6
1.8
2.0
PASSBAND DETAIL
2
FIR(f)
SYSuncomp(f)
SYScomp(f)
–10
–22
–34
0.1
0
0.2
0.3
0.4
0.5
FREQUENCY SCALE – f
FREQUENCY SCALED TO SYMBOL RATE
0.6
GLOBAL DECLARATIONS
CONSTANTS:
a 0.5
b 0.9
BW 0.5 . (1+ a)
TAPS 41
SCALE
511
FreqScale 4
PROC_GAIN 1
N 4
M 1
...EXCESS BANDWIDTH FACTOR FOR SRRC FREQUENCY RESPONSE
...PORTION OF SRRC BANDWIDTH OVER WHICH APPLY CIC CORRECTION (0<b <= 1)
...BANDWIDTH OF SRRC FILTER (RELATIVE TO SYMBOLRATE)
...NUMBER OF FIR PULSE SHAPING FILTER TAPS
...SETS MAX VALUE OF FIR PULSE SHAPING FILTER BASED ON FINITE WORD SIZE
...UPSAMPLING RATIO OF FIR PULSE SHAPING FILTER (RELATIVE TO THE SYMBOL RATE)
...PROCESSING GAIN OF CIC FILTERS (USED TO CORRELATE RESULTS WITH AD9853 EVAL. BD.)
...NUMBER OF COMB/INTEGRATOR STAGES IN CIC FILTER
...UNIT DELAYS PER STAGE OF CIC FILTER
FUNCTIONS:
InRange (x,a,b)
(x a) . (x b)
INT(x) floor(x + 0.5)
dB(x) if (| x | = 0, –200, 20 . log (| x |))
e2j . p. f
z(f)
SRRC(f)
...RETURNS 1 IF a<= x <= b, 0 OTHERWISE
...RETURNS NEAREST INTEGER TO x
...RATIO TO DECIBEL CONVERSION FUNCTION
...Z TRANSFORM
passband
0.5 . (1 – a)
stopband
0.5 . (1 + a)
...SRRC FREQUENCY RESPONSE FUNCTION
1 if InRange (f, 0, stopband)
(f IS RELATIVE TO THE SYMBOL RATE)
if InRange (f, 0, passband)
p
cos
. (2 . f + a – 1) if InRange (f, passband, stopband)
4 .a
0 otherwise
R.M – 1
H(f,R)
S
z
N
f –k
R
...CIC FILTER TIME INDEX FREQUENCY RESPONSE FUNCTION
k=0
Figure 35. MathCad Simulation (Continued)
REV. C
–21–
0.7
AD9853
3
12
41 - TAP
FIR
I
MUX
13
23
INTER28
POLATOR
#1
SCALER
13
INTER25
POLATOR
#2
10
SCALER
10
20
COS(vC)
1
SYMBOL
CLOCK
I&Q
ENCODER
10
44
4M
SYSTEM
CLOCK
4N
M = 3...31
DDS
N = 2...63
23
Q
41 - TAP
FIR
MUX
13
INTERPOLATOR
#1
28
DAC
SIN(vC)
10
3
INVERSE
SINC
FILTER
13
SCALER
INTERPOLATOR 25
#2
20
10
SCALER
12
Figure 36. Block Diagram of AD9853 Data Path and Clock Stages
The goal of interpolation is to up-sample the baseband information to the system clock rate and to suppress aliases in the passband. The system clock rate is the sample rate of the sine and
cosine signal carriers generated by the DDS in the quadrature
modulator stage. Alias suppression is accomplished by the CIC
filters as described previously. For timing synchronization, the
overall interpolation rate must be set such that the bit rate of the
baseband signal be an even integer factor of the system clock
rate. The importance of the relationship between the data and
system clock rates can not be overstressed. It is restated here for
clarity:
The SYSTEM CLOCK RATE must be an EVEN INTEGER
MULTIPLE of the DATA BIT RATE.
Following is a design example that demonstrates the principles
outlined above.
System Requirements:
• Baseband Bit Rate
• Carrier Frequency
• Modulation Scheme
• System Power
1.024 Mb/s
49 MHz
16-QAM
3.3 V
It should be noted that with a 3.3 V power supply, the maximum system clock rate of the AD9853 is 126 MHz. This sets an
upper bound on the system clock.
The first consideration is to make sure that the required carrier
frequency is within the AD9853’s output frequency range. The
carrier frequency should be ≤ 40% of the system clock rate. The
given carrier frequency requirement of 49 MHz means that a
minimum system clock rate of 122.5 MHz is required; a value
within the range of the AD9853’s 126 MHz capability.
We must next ensure that the system clock rate is an even integer multiple of the input bit rate. Dividing the system clock rate
(122.5 MHz) by the data rate (1.024 Mbps) yields 119.63.
Obviously this is not an integer, so we must select the nearest
even integer value (in this case, 120) as the data rate multiplier.
Thus, a system clock rate of 122.88 MHz is required (120 ×
1.024 Mbps). With 6× REFCLK engaged, the reference clock
input will be 1/6th of the system clock rate, or 20.48 MHz.
Finally, the two interpolator rates must be determined. Since
the FIR filter and interpolator stages will be operating on 16-QAM
symbols, the data rate must be converted from bits/second to
symbols/second (baud). Each 16-QAM symbol is composed
of four serial data bits. Therefore, the baud rate at the input to
the FIR filter is 1.024 Mbps/4 = 256k baud. The FIR pulse
shaping filters up-sample by a factor of 4. This fixes the FIR
sample clock at 256k baud × 4, or 1.024 MSPS. With the FIR
sampling at a 1.024 MSPS rate, and a previously determined
system clock rate of 122.88 MHz, the interpolators must upsample by a factor of 120 (122.88/1.024 = 120).
Rule of Thumb: divide the interpolating burden as equally as
possible among the two interpolators.
Since the required rate change ratio is 120, select a value of 10
for interpolator #1 and 12 for interpolator #2 (10 × 12 = 120).
This satisfies the requirements for the two programmable interpolator stages.
Thus far we have established the rate change ratios for the interpolators. However, there is an additional consideration. By
default, the interpolators have an intrinsic gain (or loss) that is
dependent on the selected interpolation rate. Since there is the
potential to have overall CIC gains of greater than unity, care
must be taken to avoid the occurrence of overflow in the
interpolators.
Interpolator Scaling
Proper signal processing in the AD9853 depends on data propagating through the pulse-shaping filter and interpolator stages
with as flat a baseband response as possible. In addition to the
frequency response issue, it is also necessary to ensure that the
numerical data propagating through the interpolators does not
result in an overflow condition.
As mentioned earlier, the interpolators are implemented using a
CIC filter. In the AD9853, the CIC filter is designed using
fixed-point processing and two cascaded CIC filter sections
(Interpolator #1 and Interpolator #2). It is important to understand that in a CIC filter, the integration portion of the circuit
will require the accumulation of values based on the rate change
factor, R. This means that the size of the data word grows in a
manner dependent on the choice of R. In the case of Interpolator #1, the circuit is designed around a maximum R of 32 and
this results in an output register width of 28 bits. The design of
Interpolator #2 requires an output register width of 25 bits.
–22–
REV. C
AD9853
These register widths have been chosen to accommodate the
highest values of R for each interpolator. When values of R are
chosen that are less than the maximum value, then data will
accumulate only in the lesser significant bits of the output register. This is an important point to consider since only 13 bits of
28 are passed on from Interpolator #1 to Interpolator #2, and
only 10 bits of 25 are passed on from Interpolator #2 to the
I and Q modulator (see Figure 36). If only the most significant
bits were to be passed on, then low R values would result in
most (possibly all) of the bits being 0s because data would have
accumulated only in the less significant bits of the output register. Obviously, it is necessary to have a mechanism that allows
one to select which group of bits to pass on to the next stage in
order to prevent the loss of data by truncation.
Scaling Rule: For a particular interpolator, choose a nominal
Scaling Register value that is ONE LESS than the interpolation
rate (R) for the same interpolator.
For example, if Interpolator #1 is set for an interpolation rate of
6, then choose a Scaling Register value of 5 for Interpolator #1.
It has already been mentioned that the required number of bits
at the output of the CIC filter is a function of R. It turns out
that for values of R that are a power of 2, the number of bits
required to handle the growth of the output register is an integer. This results in a processing gain of unity for the CIC filter.
For values of R that are not a power of 2, the required number
of output bits is not an integer. This results in a processing gain
that is not unity. Tables IV and V detail the relationship between the Scaling Register values and the processing gain for
Interpolator #1 and Interpolator #2. Note that certain Scale
Register values for a particular R yield a processing gain greater
than unity. Thus, it is possible that the nominal Scaling Register
values will result in a total CIC processing gain of > 1.
In the AD9853 this mechanism is handled by means of the
Interpolator #1 and #2 Scaling Registers (control bus addresses
14h and 15h). The scaling word written into each register selects
a group of bits at the output of the appropriate interpolator. In
the case of Interpolator #1 this is a 13-bit group, while in the
case of Interpolator #2 it is a 10-bit group. Inspection of the
scaling registers indicates that Interpolator #1 uses a 5-bit scaling
word while Interpolator #2 uses a 6-bit scaling word.
WARNING: It is of utmost importance the user make certain
that the total processing gain of the data path be ≤ 1.
At first inspection it would seem as though there are 32 and 64
scaling steps for Interpolator #1 and #2, respectively. This is
not the case, however. The scaling word is actually decoded in a
nonlinear manner and there is considerable overlap; i.e., several
different register values may actually select the same group of
bits at the interpolator output. Table III lists the relationship
between the scaling word value and the highest bit of the interpolator output register which becomes the most significant bit
(MSB) of the group selected.
Table III. Interpolator Scale Bit Selection
Interpolator #1
Scaling
Register
Value
(Decimal)
Highest Bit
Selected
from
Output
Register
0
1
2
3–4
5
6
7–9
10–11
12–14
15–19
20–24
25–30
31
12
15
16
18
19
20
21
22
23
24
25
26
27
Interpolator #2
Scaling
Register
Value
(Decimal)
Highest Bit
Selected
from
Output
Register
0
1
2
3–4
5–6
7–10
11–14
15–21
22–30
31–44
45–62
63
12
14
15
16
17
18
19
20
21
22
23
24
That is, the product of the FIR gain, Interpolator #1 gain, and
Interpolator #2 gain must be ≤ 1. This is because total processing gains of > 1 may result in an overflow condition within the
CIC filters, which puts the hardware in a nonrecoverable state
(short of resetting the device). The contents of Tables IV and V
offer the user some flexibility in the choice of processing gains
for a particular interpolation rate. For example, let us assume
that an overall interpolation rate of 25 is required. A value of
R = 5 for both interpolators satisfies this requirement, which
leads to a Scale Register value of 4 for each interpolator. Note,
however, that under these conditions the processing gain for the
CIC filters alone is 3.053 (1.953 × 1.563).
There are two ways in which we can handle this situation. The
first is to scale the coefficients of the FIR filter by 0.3275 (1/3.053),
which reduces the total processing gain to 1. The disadvantage
here is that the FIR coefficients are 10-bit signed integers and
scaling by 0.3275 may result in an unacceptable level of truncation caused by the finite resolution. The second method makes
use of Tables IV and V. We can choose the Alternate Scale
Value of 5 (instead of 4) for Interpolator #2. This results in a
processing gain of 1.525 (1.953 × 0.781). We can now scale the
FIR coefficients by a more modest value of 0.6557 (1/1.525)
and net an overall gain of unity through the three stages. Of
course, we could just as easily have chosen the Alternate Scale
Value for Interpolator #1 and modified the FIR coefficients
accordingly. Typically, the choice of interpolator scale values
that results in an overall gain closest to (but not less than) one is
selected. Then the FIR coefficients are scaled downward to
yield unity gain.
Selection of the proper scaling value is dependent on the selection of R for the interpolator. It is desirable to choose a scale
value that ensures that the MSB of the selected group of bits
coincides with the highest useful bit in the output register. To
accomplish this condition, use the following rule:
REV. C
–23–
AD9853
Table V. Interpolator #2
Table IV. Interpolator #1
Rate
Change
Factor
(R)
Nominal
Scale
Value
(R-1)
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Nominal
Gain
Alternate
Scale
Value
Resulting
Gain
1.688
1.000
1.953
1.688
1.340
1.000
1.424
1.953
1.300
1.688
1.073
1.340
1.648
1.000
1.199
1.424
1.675
1.953
1.130
1.300
1.485
1.688
1.907
1.073
1.201
1.340
1.489
1.648
1.818
03
05
05
06
07
10
10
10
12
12
15
15
15
20
20
20
20
20
25
25
25
25
25
31
31
31
31
31
31
0.844
0.500
0.977
0.844
0.670
0.500
0.712
0.977
0.650
0.844
0.536
0.670
0.824
0.500
0.600
0.712
0.837
0.977
0.565
0.650
0.743
0.844
0.954
0.536
0.601
0.670
0.744
0.824
0.909
Rate
Change
Factor
(R)
Nominal
Scale
Value
(R-1)
Nominal
Gain
Alternate
Scale
Value
Resulting
Gain
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
1.000
1.125
1.000
1.563
1.125
1.531
1.000
1.266
1.563
1.891
1.125
1.320
1.531
1.758
1.000
1.129
1.266
1.410
1.563
1.723
1.891
1.033
1.125
1.221
1.320
1.424
1.531
1.643
1.758
1.877
1.000
1.063
1.129
1.196
1.266
1.337
1.410
1.485
1.563
1.642
1.723
1.806
1.891
1.978
1.033
1.079
1.125
1.172
1.221
1.270
1.320
1.372
1.424
1.477
1.531
1.586
1.643
1.700
1.758
1.817
1.877
1.938
02
03
05
05
07
07
11
11
11
11
15
15
15
15
22
22
22
22
22
22
22
31
31
31
31
31
31
31
31
31
45
45
45
45
45
45
45
45
45
45
45
45
45
45
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
0.500
0.563
0.500
0.781
0.563
0.766
0.500
0.633
0.781
0.945
0.563
0.660
0.766
0.879
0.500
0.564
0.633
0.705
0.781
0.861
0.945
0.517
0.563
0.610
0.660
0.712
0.766
0.821
0.879
0.938
0.500
0.532
0.564
0.598
0.633
0.668
0.705
0.743
0.781
0.821
0.861
0.903
0.945
0.989
0.517
0.539
0.563
0.586
0.610
0.635
0.660
0.686
0.712
0.739
0.766
0.793
0.821
0.850
0.879
0.908
0.938
0.969
–24–
REV. C
AD9853
Q
Q
10
(01)
11
(11)
1011
(0111)
1010
(0101)
1110
(1101)
1111
(1111)
1001
(0110)
1000
(0100)
1100
(1100)
1101
(1110)
I
I
00
(00)
01
(10)
Q
1001
(0110)
1110
(1101)
1111
(1111)
1010
(0101)
1000
(0100)
1100
(1100)
1101
(1110)
I
0001
(0010)
0000
(0000)
0100
(1000)
0110
(1001)
0011
(0011)
0010
(0001)
0101
(1010)
0111
(1011)
b. D16-QAM Symbol Mapping
REV. C
0000
(0000)
0100
(1000)
0101
(1010)
0011
(0011)
0010
(0001)
0110
(1001)
0111
(1011)
c. 16-QAM Gray-Coded Symbol Mapping
a. QPSK Symbol Mapping
1011
(0111)
0001
(0010)
Figure 37. Symbol Mapping for QPSK, 16-QAM, and DQAM,
Spectrum = I × COS + Q × SIN (Spectrum = I × COS – Q ×
SIN)
MIXERS, ADDER, INVERSE SINC FUNCTIONS
At the output of the Interpolation filters, the pulse-shaped, upsampled I and Q baseband data is multiplied with digitized
quadrature versions of the carrier, cos(ωCt) and sin(ωCt) respectively, which are provided by a direct digital synthesizer (DDS)
block. The DDS block has a 32-bit tuning word that results in
an extremely fine frequency tuning resolution of fCLOCK/2n, as
well as extremely fast output frequency switching. The multiplier
outputs are then summed to form the QPSK/QAM-modulated
signal. This signal is then filtered by an inverse sinc filter to
compensate for the SINx/x roll-off function inherent in the
digital-to-analog conversion process. The inverse sinc filter
flattens the gain response across the Nyquist bandwidth. This is
most critical for higher data rate signals that are placed on carriers at the high end of the spectrum where the uncompensated
SINx/x roll-off would be getting progressively steeper. Gain
attenuation across a channel will result in modulation quality
impairments, such as degraded error vector magnitude (EVM).
The spectral inversion bit, when enabled, inverts the Q data at the
input to the adder circuit in the quadrature amplitude modulator
section. This has the effect of reversing the direction of the phase
rotation around the constellation map. Positive phase rotation
on the I/Q constellation plane corresponds to counterclockwise
movement. For example, the symbols in parentheses on the
QPSK constellation in Figure 37 corresponds to a spectral
mapping of I × COS – Q × SIN. The phase rotation from symbol
value 11 to 01 is a positive 90 degree rotation. Traversing
around the constellation in a positive direction, there are also
positive 90 degree rotations from 01 to 00, 00 to 10, and 10
back to 11. If the spectral invert bit is disabled, providing the
spectral map I × COS + Q × SIN as shown in Figure 37, a phase
rotation from symbol value 11 to 01 now corresponds to a negative 90 degrees of phase rotation. Similarly, there are now negative 90 degree phase rotations from 01 to 00, 00 to 10 and 10
back to 11. In other words, the direction of phase rotation
–25–
AD9853
around the constellation has simply been reversed. This effect
also holds true for the 16-QAM and D16-QAM constellations
shown in the respective I × COS – Q × SIN and I × COS + Q ×
SIN mappings shown in Figure 37.
For example, if a full-scale output current of 20 mA is desired,
then RSET = 32(1.248/0.02), or approximately 2 kΩ. Every
doubling of the RSET value will halve the output current. Maximum output current is specified as 20 mA.
DIRECT DIGITAL SYNTHESIZER FUNCTION
The direct digital synthesizer (DDS) block delivers the sine/cosine
carriers that are digitally modulated by the I/Q data paths. The
DDS function is frequency tuned via the control bus with a
32-bit tuning word. This allows the AD9853’s output carrier
frequency to be very precisely tuned while still providing output
frequency agility.
The equation relating output frequency of the AD9853 digital
modulator to the frequency tuning word (FTWORD) and the
reference clock (REFCLK) is given as:
fOUT = (FTWORD × REFCLK)/232
where: fOUT and REFCLK frequencies are in Hz and FTWORD
is a decimal number from 0 to (232)/2
Example: Find the FTWORD for fOUT = 41 MHz and REFCLK
= 122.88 MHz
If fOUT = 41 MHz and REFCLK = 122.88 MHz, then:
FTWORD = 556AAAAA hex
Loading 556AAAAAh into control bus registers 16h–19h programs
the AD9853 for fOUT = 41 MHz, given a REFCLK frequency of
122.88 MHz.
D/A CONVERTER
Up to this point all the processing has been in the digital domain.
In order to pass the modulated signal onto the cable driver for
amplification to the levels required to drive the 75 ohm cable, a
digital-to-analog converter (DAC) is implemented. The DAC
needs to have good enough transient characteristics so as not to
add significant spurious in the spectrum. Typically the worst
spurs from the DAC are due to harmonics of the fundamental
signal and their aliases (please see the AD9850 complete-DDS
data sheet for a detailed explanation of aliased images). These
harmonics are worst case for the higher carrier frequencies. The
AD9853 contains a wideband 10-bit DAC which maintains
spurious-free dynamic range (SFDR) performance of –50 dBc
up to 42 MHz AOUT and –44 dBc up to 65 MHz AOUT.
The conversion process will produce aliased components at the
DAC output at n × fCLOCK ± fCARRIER (n = 1, 2, 3, ...). These
are typically filtered with an external RLC filter between the
DAC and the line driver amplifier. Again, it is important for this
analog filter to have a sufficiently flat gain and linear phase
response across the bandwidth of interest so as to avoid the
aforementioned modulation impairments. A relatively inexpensive seventh order elliptical low-pass filter is sufficient to suppress the aliased components for HFC network applications.
The full-scale output current range of the AD9853 is 5 mA–20 mA,
with 10 mA being the optimal value for best spurious-free
dynamic range (SFDR). Full-scale output currents outside of
this range will degrade SFDR performance. SFDR is also slightly
affected by output matching, that is, for best SFDR, the two
outputs should be equally terminated.
The output load should be located as close as possible to the
AD9853 package to minimize stray capacitance and inductance.
The load may be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer-coupled circuit. It is
best not to attempt to directly drive highly reactive loads (such
as an LC filter). Driving an LC filter without a transformer
requires that the filter be doubly terminated for best performance,
that is, the filter input and output should both be resistively
terminated with the appropriate values. The parallel combination of the two terminations will determine the load that the
AD9853 will see for signals within the filter passband. For example, a 50 Ω terminated input/output low-pass filter will look
like a 25 Ω load to the AD9853. The resistor at the filter input
will mask the reactive components of the LC filter and provide a
termination for signals outside the filter pass band.
The output compliance voltage of the AD9853 is –0.5 V to
+1.5 V. Any signal developed at the DAC output should not
exceed +1.5 V, otherwise, signal distortion will result. Furthermore, the signal may extend below ground as much as 0.5 V
without damage or signal distortion. The use of a transformer
with a grounded center-tap for common-mode rejection results
in signals at the AD9853 DAC output pins that are symmetrical
about ground.
As previously mentioned, by differentially combining the two
signals the user can provide some degree of common-mode
signal rejection. The amount of rejection is dependent upon
how closely the common-mode signals of each output are
matched in amplitude and phase. If the signals are exactly alike,
then ideally, there would be 100 percent rejection in a perfect
differential amplifier or combiner. A differential combiner might
consist of a transformer or an op amp. The object is to combine
or amplify only the difference between two signals and to reject
any common, usually undesirable, characteristic, such as 60 Hz
hum or “clock feed through” that is present on both input signals. The AD9853 true and complement outputs can be differentially combined and, in fact, are configured as such on the
AD9853-XXPCB evaluation board. This evaluation board
utilizes a broadband 1:1 transformer with a grounded, centertapped primary to perform differential combining of the two
DAC outputs.
The AD9853 provides true and complement outputs, Pins 24
and 25, which are current outputs. The full-scale output current
is set by the RSET resistor at Pin 18. The value of RSET for a
particular IOUT is determined using the following equation:
RSET = 32 (1.248 V/IOUT)
–26–
REV. C
AD9853
REFERENCE CLOCK MULTIPLIER
Due to the fact that the AD9853 is a DDS-based modulator, a
relatively high frequency system clock is required. For DDS
applications the carrier is typically limited to about 40% of
fCLOCK. For a 65 MHz carrier, the system clock required is
above 150 MHz. To avoid the cost associated with these high
frequency references, and the aggravating noise coupling issues
associated with operating a high frequency clock on a PC board,
the AD9853 provides an on-chip 6× clock multiplier. With the
6× on-chip multiplier, the input reference clock required for the
AD9853 can be kept in the 20 MHz to 30 MHz range, which
results in cost and system implementation savings. The 6×
REFCLK multiplier maintains clock integrity as evidenced by
the AD9853’s system phase noise characteristics of –100 dBc/Hz
and virtually no clock related spurious in the output spectrum.
External loop filter components consisting of a series resistor
(1.3 kΩ) and capacitor (0.01 µF) provide the compensation
zero for the 6× REFCLK PLL loop. The overall loop performance has been optimized for these component values.
Table VI. Derivation of Currently Transmitted Symbol
Quadrant
Current
Input
Bits
IQ
Quadrant
Phase
Change
MSBs of
Previously
Transmitted
Symbol
MSBs for
Currently
Transmitted
Symbol
00
00
00
00
01
01
01
01
11
11
11
11
10
10
10
10
0°
0°
0°
0°
90°
90°
90°
90°
180°
180°
180°
180°
270°
270°
270°
270°
11
01
00
10
11
01
00
10
11
01
00
10
11
01
00
10
11
01
00
10
01
00
10
11
00
10
11
01
10
11
01
00
worst case conditions. It is important to understand that a significant portion of the heat generated by the device is transferred to the environment via the package leads. The specified
θJA value assumes that the device is soldered to a multilayer
printed circuit board (PCB) with the device power and ground
pins connected directly to power and ground planes of the PCB.
The amount of power internally generated by the device is primarily dependent on four factors:
• Power Supply Voltage
• System Clock Rate
• Input Data Rate
• TXENABLE Duty Cycle (assuming the device is operated in
the burst data mode)
The power generated by the device increases with an increase in
any one of the four factors. It turns out that the contribution of
generated power due to the system clock rate, input data rate
and TXENABLE duty cycle may be ignored at power supply
voltages of less than 4 V (as the total power generated by the
device will not exceed 1.8 W). However, for supply voltages
greater than 4 V, operation at +85°C ambient temperature will
require a tradeoff among the other three factors; i.e., a reduced
system clock rate, a reduced data rate, a reduced TXENABLE
duty cycle, or some combination of the three. It should be mentioned, that operation at a power supply voltage of 4 V yields the
same level of performance as specified at 5 V operation. For
example, the user may still take advantage of the 165 MHz
maximum system clock rate specified for 5 V operation.
VDD
VDD
DIGITAL
OUT
IOUT
DIGITAL
IN
IOUTB
(b)
(a)
(c)
Figure 38. Equivalent I/O Circuits
AD9853-xxPCB EVALUATION BOARD
Note: This table applies to both DQPSK and D16-QAM formats.
In DQPSK a symbol is comprised of two bits that are denoted
as “ I(1) Q(1).” In this case, I(1) and Q(1) are the MSBs and
the table can be interpreted directly. In D16-QAM a symbol is
defined as comprised of four bits denoted as “I(1) Q(1) I(0) Q(0).”
I(1), Q(1) are the MSBs and I(0), Q(0) are the LSBs. As indicated in the table, only the MSBs I(1) and Q(1) are altered as a
function of the differential coding; I(0) and Q(0) are not altered.
DEVICE THERMAL CONSIDERATIONS
The AD9853 is specified to operate at an ambient temperature
of up to +85°C. The maximum junction temperature (TJ) is
specified at +150°C, which provides a worst case junction-to-air
differential of +65°C. Thus, with the specified θJA of +36°C/W,
a maximum device dissipation of 1.8 W is achievable under the
Two versions of evaluation boards are available for the AD9853
digital QPSK/16-QAM modulator: the AD9853-45PCB and
the AD9853-65PCB. The – 45 contains a 45 MHz low-pass
filter to support a 5 MHz–42 MHz output bandwidth and the
–65 has a 65 MHz low-pass filter to support a 5 MHz–65 MHz
output bandwidth.
Both versions of the evaluation board contain the AD9853
device, a REFCLOCK oscillator, a seventh order elliptic lowpass filter of the designated frequency, an AD8320 programmable cable driver amplifier, operating software for Windows®
3.1 or Windows 95, and a booklet of complete operating instructions and performance graphs. The evaluation board provides an optimal environment for menu-driven programming of
the devices and analysis of output spectral performance.
Windows is a registered trademark of Microsoft, Corporation.
REV. C
VDD
–27–
Part Number
On-Board Low-Pass Filter
AD9853-45PCB
AD9853-65PCB
45 MHz
65 MHz
AD9853
+5V
FEC
TXEN
TSTATE
RESET
BUSDAT
BUSCLK
C34
0.001mF
THREE-STATE BUFFER
U3
74ACT573
U4
74AC244
8D
7D
6D
5D
4D
3D
2D
1D
EN
12
13
14
15
16
17
18
19
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
OE
11
17
FECC
TXEE
TSAT
REST
DAT
BCLK
+5V
C21
0.1mF
1
SMB
J6
E1
E2
R3
50V
SOFTWARE CONTROL
OF TXENABLE
L2
100NH
(100NH)
L3
100NH
(150NH)
2
2
1
C7
100pF
(82pF)
TXEE
2
4
6
8
10
12
14
GND
TXE
R11
3.9kV
3
6
1
R6
25V
1:1
GND
DIGITAL
MODULATOR
DUT+V
C28
0.1mF
DUT+V
SMB
J3
PODN
R10
3.9kV
1
AD8320
EXTERNAL
POWERDOWN
C29
0.1mF
2
3
U1
4
5
6
7
AGND
TEST CLK
TEST OUT2
IOUTB
IOUT
TSTDATA IN
TEST LATCH
AD9853
DGND
DUT+V
SDI
TXE
DUT+V
C27
0.1mF
22
21
DUT+V
C25
0.1mF
DUT+V
C31
0.1mF
DUT+V
20
DUT+V
R4
GND
3.9kV
18
C24
0.1mF
19
DUT+V
17
16
15
R5
GND 1300V
14
C10
0.01mF
13
12
DUT+V
TESTOUT1
DUT+V
AD8320
POWERDOWN
SOURCE
SWITCH
NOTE:
C31 NORMALLY
NOT POPULATED
AVDD
DAC BL
AVDD
AGND
DAC RSET
NC
AGND
PLL FILTER
PLL VCC
PLL GND
GND
DVDD
DGND
C26
0.1mF
CA CLK
CA DATA
36
DGND
37
DVDD
38
REF CLK IN
39
DGND
40
DVDD
41
DATA IN
42
TX ENABLE
43
DVDD
44
DGND
C23
0.1mF
DUT+V
9 10 11
8
TST1
DUT+V
DUT+V
CLK
34
35
ADDRESS BIT
DGND
SW41
WHEN NOT USING T1A,
CONNECT E13 TO E14
AND LEAVE R3 AND
R6 IN PLACE
E14
TSTDATA EN
R1
50V
WHEN USING
TRANSFORMER T1A,
REMOVE R3 AND R6
TST1
TSTDATA OUT
CAC
CAD
EXTERNAL
CLK
AD8320 POWER-DOWN
SW1 FUNCTIONS
C30
0.1mF
DUT+V
DUT+V
+5V
+5V
C18
10mF
DUT+V
C19
10mF
CAD
CAC
CAE
C2
0.1mF GND
TB1
DUT+V
GND
+5V
GND
+10V
POWER INPUT
CONNECTOR
SMB 75
J8
75V
OUTPUT
PDN
+10V
+10V
+10V
C12
0.1mF
+10V
1
2
3
4
5
6
7
8
9
10
VCCL
SDATA
VIN
CLK
VREF
DATEN
GND AD8320 VCC
GND
VOCM
U2
GND
PD
BYP
VCC
GND
VCC
GND
VCC
GND
VOUT
R7
3.9kV
C15
0.1mF
C33
10mF
+10V
+10V
C14
C13
0.1mF
10mF
+10V
C20
10mF
1
2
3
4
5
4
2
GND
CA EN
SMB
J2
8
JUMPER FUNCTION
1-2
HARD POWER-DOWN
2-3
HARD POWER-DOWN
OR EXTERNAL CONTROL
VIA J3
NO
POWERED UP
JUMPER
T1A
T1 – 1T
SIG
FEC EN
1
GND
2
PDN
3
PODN
E13
1
3
5
7
9
11
13
DGND
DVDD
H3M
SW1
FILTER OUT/
AMP IN
REST
CLK
GND
7
AMP
SMB
J7
CAE
Y1
OUT
E11 E12
C9
56pF
(39pF)
33 32 31 30 29 28 27 26 25 24 23
VCC
IF CLOCK
REMOVE SOURCE IS
Y1
J2 (EXTERNAL)
R1
Y1 (XTAL)
E3 E4
2
+5V
+5V
14
2.2k PULL-UP
NETWORK
TO +5V
HI 4DM
J9
E8 E6 SMB
J4
HARD ENABLE OR
EXT. CONTROL VIA J4
1
C8
82pF
(82pF)
C17
0.1mF
CRYSTAL OSC.
2
3
4
5
6
7
8
7TH ORDER ELIPTIC 50V LOW PASS FILTER
VALUES IN PARENTHESES – 45 MHz FILTER
VALUES NOT IN PARENTHESES – 65 MHz FILTER
BUS CLK
BUSDAT IN
OPEN
L1
120NH
(180NH)
E7 E5
FUNCTION
HEADER CONNECTOR
FROM DG2020,
DATA GENERATOR
E7-E8
C5
22pF
(27pF)
TXENABLE
TXENABLE
JUMPER CONFIGURATION
TSTATE
RBAK
C4
33pF
(33pF)
C6
68pF
(33pF)
SIG
SIG
JUMPER
E5-E6
C3
7pF
(6.8pF)
1
E10
E9
LATCH
BUSCLK
BUSDAT
RESET
TXEN
BDAT
TSTATE
TSTAT
LATCH
DAC OUT/
FILTER IN
8PPT+5V
RZ1
3
2A4 2Y4
GND
15
5
2A3 2Y3
GND
13
7
2A2 2Y3
GND
11
9 RBAK
2A1 2Y2
BDAT
8
12 BDAT
1A4 1Y4
DAT
6
14
1A3 1Y3
4
16
1A2 1Y2
2
18
1A1 1Y1
+5V
1G 2G
C22
0.1mF
1
19
BDAT
LATCH
BUSCLK
BUSDAT
RESET
FEC
TXEN
9
8
7
6
5
4
3
2
LATCH
RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
R8
3.9kV
DUT+V
BCLK
"CENTRONICS"
PRINT PORT
CONN.
C36CRPX
J1
+10V
FECC
1
2
SMB
J10
EXTERNAL
FEC ENABLE
3
FEC (SW2) FUNCTIONS
C11
0.1mF
20
+10V
19
SW2
AMP
18
H3M
R2
C1
17
62V
+10V
0.1mF
16
SERIAL DATA IN
15
SDI
SMB
14
J5
13
C32
C16
SDI
0.1mF
12
0.1mF
R12
11
3.9kV
+10V
JUMPER FUNCTION
1-2
SOFT FEC
ENABLE/DISABLE
2-3
HARD FEC DISABLE
OPEN
HARD FEC ENABLE
OR EXTERNAL FEC
CONTROL VIA J11
+5V
PROGRAMMABLE
GAIN AMPLIFIER
Figure 39. Electrical Schematic of AD9853-xxPCB Evaluation Board
–28–
REV. C
AD9853
a. Layer 1 (Top) – Signal Routing and Ground Plane
c. Layer 3 – DUT +V, +5 V, and +12 V Power Plane
b. Layer 2 – Ground Plane
d. Layer 4 (Bottom) – Signal Routing
Figure 40. PCB Layout Patterns for the Four-Layer AD9853-xxPCB Evaluation Board
REV. C
–29–
AD9853
Plots of typical output spectrum from the AD9853-45PCB
evaluation board (conditions: DUT supply voltage = +3.3 V,
QPSK modulation, 2.048 Mb/s, 20.48 MHz ext. REFCLK,
6× REFCLK enabled, SRRC filter function, AOUT = 40 MHz,
α = 0.25, 50 MHz low-pass filter).
ATTEN 30dB 50V
Plots of typical output spectrum from the AD9853-65PCB
evaluation board (conditions: DUT supply voltage = +4.0 V,
QPSK modulation, 2.7792 Mb/s, 27.792 MHz ext. REFCLK,
6× REFCLK enabled, SRRC filter function, AOUT = 60 MHz,
α = 0.25, 70 MHz low-pass filter).
ATTEN 10dB 50V
TG off
–25
–25
–35
–35
–45
–45
–55
–55
–65
–65
–75
–75
–85
–85
–95
–95
–105
REF 50.0MHz
INC 10MHz
10.0MHz/div
500ms/div
–105
RES bw 60MHz
VID bw 5.4kHz
REF 100.0MHz
INC 20MHz
Figure 41. Direct DAC Output
ATTEN 30dB 50V
20.0MHz/div
1s/div
RES bw 10MHz
VID bw 5.4kHz
Figure 43. Direct DAC Output
ATTEN 30dB 50V
TG off
–25
–2.0
–35
12.0
–45
22.0
–55
32.0
–65
42.0
–75
TG off
2ND
HARMONIC
52.0
2ND HARMONIC
–85
62.0
–95
72.0
TG off
3RD
HARMONIC
82.0
–105
REF 50.0MHz
INC 10MHz
10.0MHz/div
500ms/div
REF 100.0MHz
INC 20MHz
RES bw 10MHz
VID bw 5.4kHz
Figure 42. Output of AD8320 Programmable Line Driver
Amplifier Driven by AD9853 Modulator
20.0MHz/div
1s/div
RES bw 10MHz
VID bw 5.4kHz
Figure 44. Output of AD8320 Programmable Line Driver
Amplifier Driven by AD9853 Modulator
–30–
REV. C
AD9853
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Metric Quad Flatpack (MQFP)
(S-44A)
0.096 (2.45)
MAX
0.041 (1.03)
0.029 (0.73)
44
C3361c–0–2/99
0.530 (13.45)
SQ
0.510 (12.95)
0.398 (10.10)
SQ
0.390 (9.90)
34
1
33
SEATING
PLANE
0.315 (8.00)
REF
TOP VIEW
(PINS DOWN)
0.010 (0.25)
MAX
0.009 (0.23)
0.005 (0.13)
23
22
12
0.031 (0.80)
BSC
0.018 (0.45)
0.012 (0.30)
PRINTED IN U.S.A.
0.083 (2.10)
0.077 (1.95)
11
REV. C
–31–