ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial Interface ADCs Check for Samples: ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955, ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 FEATURES DESCRIPTION • • • • • • • The ADS79XX is a 12/10/8-bit multichannel analog-to-digital converter family. The following table shows all twelve devices from this product family. 1 • • • • • • • • 1-MHz Sample Rate Serial Devices Product Family of 12/10/8-Bit Resolution Zero Latency 20-MHz Serial Interface Analog Supply Range: 2.7 to 5.25V I/O Supply Range: 1.7 to 5.25V Two SW Selectable Unipolar, Input Ranges: 0 to 2.5V and 0 to 5V Auto and Manual Modes for Channel Selection 12,8,4-Channel Devices can Share 16 Channel Device Footprint Two Programmable Alarm Levels per Channel Four Individually Configurable GPIOs for TSSOP package devices. One GPIO for QFN devices Typical Power Dissipation: 14.5 mW (+VA = 5V, +VBD = 3V) at 1 MSPS Power-Down Current (1 mA) Input Bandwidth (47 MHz at 3dB) 38-,30-Pin TSSOP and 32-,24-Pin QFN Packages APPLICATIONS • • • • • • • PLC / IPC Battery Powered Systems Medical Instrumentation Digital Power Supplies Touch Screen Controllers High-Speed Data Acquisition Systems High-Speed Closed-Loop Systems The devices include a capacitor based SAR A/D converter with inherent sample and hold. The devices accept a wide analog supply range from 2.7V to 5.25V. Very low power consumption makes these devices suitable for battery-powered and isolated power supply applications. A wide 1.7V to 5.25V I/O supply range facilitates a glue-less interface with the most commonly used CMOS digital hosts. The serial interface is controlled by CS and SCLK for easy connection with microprocessors and DSP. The input signal is sampled with the falling edge of CS. It uses SCLK for conversion, serial data output, and reading serial data in. The devices allow auto sequencing of preselected channels or manual selection of a channel for the next conversion cycle. There are two software selectable input ranges (0V 2.5V and 0V - 5V), four individually configurable GPIOs ( in case of TSSOP package devices), and two programmable alarm thresholds per channel. These features make the devices suitable for most data acquisition applications. The devices offer an attractive power-down feature. This is extremely useful for power saving when the device is operated at lower conversion speeds. The 16/12-channel devices from this family are available in a 38-pin TSSOP and 32 pin QFN package and the 4/8-channel devices are available in a 30-pin TSSOP and 24 pin QFN packages. MICROPOWER MULTI-CHANNEL ADS79XX FAMILY RESOLUTION NUMBER OF CHANNELS 12 BIT 10 BIT 8 BIT 16 ADS7953 ADS7957 ADS7961 12 ADS7952 ADS7956 ADS7960 8 ADS7951 ADS7955 ADS7959 4 ADS7950 ADS7954 ADS7958 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2010, Texas Instruments Incorporated ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ADS79XX BLOCK DIAGRAM REF MXO AINP Ch0 Ch1 +VA AGND ADC Ch2 SDO Compare Alarm Threshold Ch n* Control Logic & Sequencing GPIO BDGND SDI SCLK CS VBD NOTE: n* is number of channels (16,12,8, or 4) depending on the device from the ADS79XX product family. NOTE: 4 number of GPIO are available in TSSOP package devices only, QFN package devices offer only one GPIO. 2 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 ORDERING INFORMATION - 12-BIT MAXIMUM INTEGRAL LINEARITY (LSB) MODEL MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES AT RESOLUTION (BIT) NUMBER OF CHANNELS ADS7953 SB PACKAGE TYPE PACKAGE DESIGNATOR 38 pin TSSOP DBT TEMPERATURE RANGE ORDERING INFORMATION TRANSPORT MEDIA QTY ADS7953SBDBT Tube, 50 ADS7953SBDBTR Reel, 2000 16 32 pin QFN 38 pin TSSOP ADS7952 SB ADS7953SBRHBT Tube, 250 ADS7953SBRHBR Reel, 3000 RHB ADS7952SBDBT Tube, 50 ADS7952SBDBTR Reel, 2000 DBT 12 32 pin QFN ±1 ±1 ADS7952SBRHBT Tube, 250 ADS7952SBRHBR Reel, 3000 RHB 12 –40°C to 125°C 30 pin TSSOP ADS7951 SB ADS7951SBDBT Tube, 50 ADS7951SBDBTR Reel, 2000 DBT 8 24 pin QFN 30 pin TSSOP ADS7950 SB ADS7951SBRGET Tube, 250 ADS7951SBRGER Reel, 3000 RGE ADS7950SBDBT Tube, 50 ADS7950SBDBTR Reel, 2000 DBT 4 24 pin QFN 38 pin TSSOP ADS7953 S ADS7950SBRGET Tube, 250 ADS7950SBRGER Reel, 3000 RGE ADS7953SDBT Tube, 50 ADS7953SDBTR Reel, 2000 DBT 16 32 pin QFN 38 pin TSSOP ADS7952 S ADS7953SRHBT Tube, 250 ADS7953SRHBR Reel, 3000 RHB ADS7952SDBT Tube, 50 ADS7952SDBTR Reel, 2000 DBT 12 32 pin QFN ±1.5 ±2 ADS7952SRHBT Tube, 250 ADS7952SRHBR Reel, 3000 RHB 11 –40°C to 125°C 30 pin TSSOP ADS7951S ADS7951SDBT Tube, 50 ADS7951SDBTR Reel, 2000 DBT 8 24 pin QFN 30 pin TSSOP ADS7950 S ADS7951SRGET Tube, 250 ADS7951SRGER Reel, 3000 RGE ADS7950SDBT Tube, 50 ADS7950SDBTR Reel, 2000 DBT 4 24 pin QFN ADS7950SRGET Tube, 250 ADS7950SRGER Reel, 3000 RGE ORDERING INFORMATION - 10-BIT MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES AT RESOLUTION (BIT) ADS7957 S NUMBER OF CHANNELS PACKAGE TYPE PACKAGE DESIGNATOR 38 pin TSSOP DBT TEMPERATURE RANGE ORDERING INFORMATION TRANSPORT MEDIA QTY ADS7957SDBT Tube, 50 ADS7957SDBTR Reel, 2000 16 32 pin QFN 38 pin TSSOP ADS7956 S ADS7957SRHBT Tube, 250 ADS7957SRHBR Reel, 3000 RHB ADS7956SDBT Tube, 50 ADS7956SDBTR Reel, 2000 DBT 12 32 pin QFN ±0.5 ±0.5 10 Tube, 250 Reel, 3000 –40°C to 125°C 30 pin TSSOP ADS7955 S ADS7956SRHBT ADS7956SRHBR RHB ADS7955SDBT Tube, 50 ADS7955SDBTR Reel, 2000 DBT 8 24 pin QFN 30 pin TSSOP ADS7954 S ADS7955SRGET Tube, 250 ADS7955SRGER Reel, 3000 RGE ADS7954SDBT Tube, 50 ADS7954SDBTR Reel, 2000 DBT 4 24 pin QFN Copyright © 2008–2010, Texas Instruments Incorporated ADS7954SRGET Tube, 250 ADS7954SRGER Reel, 3000 RGE Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 3 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com ORDERING INFORMATION - 8-BIT MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES AT RESOLUTION (BIT) ADS7961 S NUMBER OF CHANNELS PACKAGE TYPE PACKAGE DESIGNATOR 38 pin TSSOP DBT TEMPERATURE RANGE ORDERING INFORMATION TRANSPORT MEDIA QTY ADS7961SDBT Tube, 50 ADS7961SDBTR Reel, 2000 16 32 pin QFN 38 pin TSSOP ADS7960 S ADS7961SRHBT Tube, 250 ADS7961SRHBR Reel, 3000 RHB ADS7960SDBT Tube, 50 ADS7960SDBTR Reel, 2000 DBT 12 32 pin QFN ±0.3 ±0.3 8 Tube, 250 Reel, 3000 –40°C to 125°C 30 pin TSSOP ADS7959 S ADS7960SRHBT ADS7960SRHBR RHB ADS7959SDBT Tube, 50 ADS7959SDBTR Reel, 2000 DBT 8 24 pin QFN 30 pin TSSOP ADS7958 S ADS7959SRGET Tube, 250 ADS7959SRGER Reel, 3000 RGE ADS7958SDBT Tube, 50 ADS7958SDBTR Reel, 2000 DBT 4 24 pin QFN ADS7958SRGET Tube, 250 ADS7958SRGER Reel, 3000 RGE ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT –0.3 to +VA +0.3 V +VA to AGND, +VBD to BDGND –0.3 to +7.0 V Digital input voltage to BDGND –0.3 to (7.0) V –0.3 to (+VA + 0.3) V Operating temperature range –40 to 125 °C Storage temperature range –65 to 150 °C 150 °C AINP or CHn to AGND Digital output to BDGND Junction temperature (TJ Max) Power dissipation (TJ Max–TA)/qJA qJA thermal impedance, DBT Package 100.6 °C/W qJA thermal impedance, RHB Package 34 °C/W qJA thermal impedance, RGE Package 38 °C/W DBT packaged versions of ADS79XX family devices are rated for MSL2 260°C per the JSTD-020 specifications and the RGE and RHB packaged versions of ADS79XX family devices are rated for MSL3 260C per JSTD-020 specifications (1) 4 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Range 1 0 Vref Range 2 while 2Vref ≤ +VA 0 2*Vref –0.20 VREF +0.20 –0.20 2*VREF +0.20 Range 1 Absolute input range Range 2 while 2Vref ≤ +VA Input capacitance Input leakage current TA = 125°C V V 15 rF 61 nA 12 Bits SYSTEM PERFORMANCE Resolution No missing codes Integral linearity Differential linearity ADS795XSB (2) 12 11 ADS795XSB (2) –1 ±0.5 1 –1.5 ±0.75 1.5 ADS795XS (2) ADS795XSB (2) –1 ±0.5 1 ADS795XS (2) –2 ±0.75 1.5 –3.5 ±1.1 3.5 –2 ±0.2 2 Offset error (4) Gain error Bits ADS795XS (2) Range 1 Range 2 ±0.2 Total unadjusted error (TUE) ±2 LSB (3) LSB LSB LSB LSB SAMPLING DYNAMICS Conversion time 20 MHz sclk 800 Acquisition time Maximum throughput rate 325 nSec nSec 20 MHz sclk 1.0 MHz Aperture delay 5 nsec Step response 150 nsec Over voltage recovery 150 nsec DYNAMIC CHARACTERISTICS Total harmonic distortion (5) 100 kHz Signal-to-noise ratio 100 kHz, ADS795XSB (2) 100 kHz, ADS795XS Signal-to-noise + distortion (2) –82 dB 70 71.7 dB 70 71.7 100 kHz, ADS795XSB (2) 69 71.3 100 kHz, ADS795XS (2) 68 71.3 dB Spurious free dynamic range 100 kHz 84 dB Small signal bandwidth At –3 dB 47 MHz Channel-to-channel crosstalk Any off-channel with 100kHz, Full-scale input to channel being sampled with DC input (isolation crosstalk). –95 From previously sampled to channel with 100kHz, Full-scale input to channel being sampled with DC input (memory crosstalk). –85 dB EXTERNAL REFERENCE INPUT (1) (2) (3) (4) (5) Ideal input span; does not include gain or offset error. ADS795X, where X indicates 0, 1, 2, or 3 LSB means Least Significant Bit. Measured relative to an ideal full-scale input Calculated on the first nine harmonics of the input frequency. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 5 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS Vref reference voltage at REFP (6) MIN TYP MAX 2.0 2.5 3.0 Reference resistance 100 UNIT V kΩ ALARM SETTING Higher threshold range 0 FFC Hex Lower threshold range 0 FFC Hex DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD) VIL +VBD = 5 V VIL +VBD = 3 V 0.8 VOH At Isource = 200 mA VOL At Isink = 200 mA Data format MSB first 0.4 V V Vdd-0.2 0.4 MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage +VBD supply voltage 2.7 3.3 5.25 1.7 3.3 5.25 At +VA = 2.7 to 3.6 V and 1MHz throughput Supply current (normal mode) At +VA = 2.7 to 3.6 V static state mA 1.05 mA At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA Power-down state supply current +VBD supply current V 1.8 1 +VA = 5.25V, fs = 1MHz mA 1 mA Power-up time 1 Invalid conversions after power up or reset 1 Number s mSec TEMPERATURE RANGE Specified performance (6) –40 125 °C Device is designed to operate over Vref = 2.0 V to 3.0 V. However one can expect lower noise performance at Vref < 2.4 V. This is due to SNR degradation resulting from lowered signal range. ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Range 1 0 Vref Range 2 while 2Vref ≤ +VA 0 2*Vref Range 1 –0.20 VREF +0.20 Range 2 while 2Vref ≤ +VA –0.20 2*VREF +0.20 Absolute input range Input capacitance Input leakage current TA = 125°C V V 15 rF 61 nA 10 Bits SYSTEM PERFORMANCE Resolution No missing codes (1) 6 10 Bits Ideal input span; does not include gain or offset error. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) MIN TYP MAX UNIT Integral linearity PARAMETER TEST CONDITIONS –0.5 ±0.2 0.5 LSB (2) Differential linearity –0.5 ±0.2 0.5 LSB Offset error (3) –1.5 ±0.5 1.5 LSB –1 ±0.1 1 Range 1 Gain error Range 2 ±0.1 LSB SAMPLING DYNAMICS Conversion time 20 MHz SCLK Acquisition time 800 325 Maximum throughput rate nSec nSec 20 MHz SCLK 1.0 MHz Aperture delay 5 nsec Step response 150 nsec Over voltage recovery 150 nsec –80 dB DYNAMIC CHARACTERISTICS Total harmonic distortion (4) 100 kHz Signal-to-noise ratio 100 kHz 60 Signal-to-noise + distortion 100 kHz 60 Spurious free dynamic range 100 kHz 82 dB Full power bandwidth At –3 dB 47 MHz Channel-to-channel crosstalk dB Any off-channel with 100kHz, Full-scale input to channel being sampled with DC input. –95 From previously sampled to channel with 100kHz, Full-scale input to channel being sampled with DC input. –85 dB EXTERNAL REFERENCE INPUT Vref reference voltage at REFP 2.0 Reference resistance 2.5 3.0 100 V kΩ ALARM SETTING Higher threshold range 000 FFC Hex Lower threshold range 000 FFC Hex DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD) VIL +VBD = 5 V VIL +VBD = 3 V VOH At Isource = 200 mA VOL At Isink = 200 mA Data format MSB first 0.8 0.4 V V Vdd-0.2 0.4 MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage 2.7 3.3 5.25 +VBD supply voltage 1.7 3.3 5.25 At +VA = 2.7 to 3.6 V and 1MHz throughput Supply current (normal mode) (2) (3) (4) At +VA = 2.7 to 3.6 V static state 1.8 1.05 V mA 1 mA At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA LSB means Least Significant Bit. Measured relative to an ideal full-scale input Calculated on the first nine harmonics of the input frequency. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 7 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Power-down state supply current +VBD supply current TYP MAX 1 +VA = 5.25V, fs = 1MHz UNIT mA 1 mA Power-up time 1 Invalid conversions after power up or reset 1 Numbers mSec TEMPERATURE RANGE Specified performance –40 125 °C ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Range 1 0 Vref Range 2 while 2Vref ≤ +VA 0 2*Vref Range 1 –0.20 VREF +0.20 Range 2 while 2Vref ≤ +VA –0.20 2*VREF +0.20 Absolute input range Input capacitance Input leakage current TA = 125°C V V 15 rF 61 nA 8 Bits SYSTEM PERFORMANCE Resolution No missing codes 8 Bits Integral linearity –0.3 ±0.1 0.3 LSB (2) Differential linearity –0.3 ±0.1 0.3 LSB –0.5 ±0.2 0.5 LSB –0.6 ±0.1 0.6 Offset error (3) Gain error Range 1 Range 2 ±0.1 LSB SAMPLING DYNAMICS Conversion time 20 MHz SCLK Acquisition time Maximum throughput rate 800 325 nSec nSec 20 MHz SCLK 1.0 MHz Aperture delay 5 nsec Step response 150 nsec Over voltage recovery 150 nsec –75 dB DYNAMIC CHARACTERISTICS Total harmonic distortion (4) 100 kHz Signal-to-noise ratio 100 kHz 49 Signal-to-noise + distortion 100 kHz 49 Spurious free dynamic range 100 kHz –78 dB Full power bandwidth At –3 dB 47 MHz (1) (2) (3) (4) 8 dB Ideal input span; does not include gain or offset error. LSB means Least Significant Bit. Measured relative to an ideal full-scale input Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER Channel-to-channel crosstalk TEST CONDITIONS MIN TYP Any off-channel with 100kHz, Full-scale input to channel being sampled with DC input. –95 From previously sampled to channel with 100kHz, Full-scale input to channel being sampled with DC input. –85 MAX UNIT dB ETERNAL REFERENCE INPUT Vref reference voltage at REFP 2.0 Reference resistance 2.5 3.0 V 100 kΩ ALARM SETTING Higher threshold range 000 FF Hex Lower threshold range 000 FF Hex DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD) VIL +VBD = 5 V VIL +VBD = 3 V VOH At Isource = 200 mA VOL At Isink = 200 mA 0.8 0.4 V Vdd-0.2 0.4 Data format MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage 2.7 3.3 5.25 V +VBD supply voltage 1.7 3.3 5.25 V At +VA = 2.7 to 3.6 V and 1MHz throughput Supply current (normal mode) 1.8 At +VA = 2.7 to 3.6 V static state mA At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA Power-down state supply current +VBD supply current mA 1.05 +VA = 5.25V, fs = 1MHz 1 mA 1 mA Power-up time 1 Invalid conversions after power up or reset 1 Numbers mSec TEMPERATURE RANGE Specified performance –40 125 °C MAX UNIT TIMING REQUIREMENTS (see Figure 45, Figure 46, Figure 47, and Figure 48) All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified) PARAMETER tconv tq (1) (2) Conversion time Minimum quiet sampling time needed from bus 3-state to start of next conversion TEST CONDITIONS (1) (2) MIN TYP +VBD = 1.8 V 16 +VBD = 3 V 16 +VBD = 5 V 16 +VBD = 1.8 V 40 +VBD = 3 V 40 +VBD = 5 V 40 SCLK ns 1.8V specifications apply from 1.7V to 1.9V, 3V specifications apply from 2.7V to 3.6V, 5V specifications apply from 4.75V to 5.25V. With 50-pF load Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 9 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com TIMING REQUIREMENTS (see Figure 45, Figure 46, Figure 47, and Figure 48) (continued) All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified) PARAMETER td1 tsu1 td2 th1 td3 Delay time, CS low to first data (DO–15) out Setup time, CS low to first rising edge of SCLK Delay time, SCLK falling to SDO next data bit valid Hold time, SCLK falling to SDO data bit valid Delay time, 16th SCLK falling edge to SDO 3-state TEST CONDITIONS (1) (2) MIN Setup time, SDI valid to rising edge of SCLK 38 +VBD = 3 V 27 +VBD = 5 V 17 +VBD = 1.8 V 8 +VBD = 3 V 6 +VBD = 5 V 4 35 +VBD = 3 V 27 +VBD = 5 V 17 +VBD = 1.8 V 7 +VBD = 3 V 5 +VBD = 5 V 3 Hold time, rising edge of SCLK to SDI valid tw1 td4 twh twl Pulse duration CS high Delay time CS high to SDO 3-state Pulse duration SCLK high Pulse duration SCLK low Frequency SCLK 10 Submit Documentation Feedback ns ns ns +VBD = 1.8 V 26 +VBD = 3 V 22 ns 13 +VBD = 1.8 V 2 +VBD = 3 V 3 ns 4 +VBD = 1.8 V 12 +VBD = 3 V 10 +VBD = 5 V UNIT ns +VBD = 1.8 V +VBD = 5 V th2 MAX +VBD = 1.8 V +VBD = 5 V tsu2 TYP ns 6 +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 ns +VBD = 1.8 V 24 +VBD = 3 V 21 +VBD = 5 V 12 +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 ns ns ns +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 MHz Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 DEVICE INFORMATION PIN CONFIGURATION (TOP VIEW) GPIO2 1 30 GPIO1 GPIO2 1 30 GPIO1 GPIO3 REFM 2 29 GPIO3 2 29 3 28 GPIO0 +VBD 3 28 GPIO0 +VBD REFP 4 27 BDGND REFM REFP 4 27 BDGND +VA AGND MXO 5 26 SDO +VA 5 26 SDO 6 25 25 24 AGND MXO 6 7 SDI SCLK 7 24 SDI SCLK 23 CS 22 AGND AINP 8 AINM 9 ADS7950 ADS7954 ADS7958 23 CS AINP 8 22 AGND AINM 9 AGND NC 10 21 +VA 11 20 CH0 CH3 12 19 NC 13 CH2 NC ADS7951 ADS7955 ADS7959 AGND CH7 10 21 +VA 11 20 CH0 CH6 12 19 18 NC CH1 CH5 13 18 CH1 CH2 14 17 NC CH4 14 17 CH3 15 16 NC NC 15 16 NC GPIO2 1 38 GPIO1 GPIO2 1 38 GPIO1 GPIO3 REFM 2 37 GPIO3 2 37 GPIO0 3 36 GPIO0 +VBD REFM 3 36 +VBD REFP 4 35 BDGND 4 35 BDGND +VA 5 34 SDO REFP +VA 5 34 SDO AGND MXO 6 33 AGND 6 33 7 32 SDI SCLK MXO 7 32 SDI SCLK AINP 8 31 CS AINP 8 31 CS AINM 9 30 AGND AINM 9 30 29 +VA 29 AGND +VA ADS7952 ADS7956 ADS7960 AGND NC 10 28 CH0 NC 12 27 NC 13 NC ADS7953 ADS7957 ADS7961 CH1 26 CH13 13 26 CH2 14 25 CH3 14 25 CH11 CH10 15 24 CH4 CH12 CH11 15 24 CH3 CH4 16 23 CH5 CH10 16 23 CH5 CH9 17 22 CH6 CH9 17 22 CH6 CH8 AGND 18 21 CH7 CH8 18 21 CH7 19 20 AGND AGND 19 20 AGND 32 AGND 11 SDI +VA SDO 27 +VBD 12 BDGND CH0 CH14 GPIO 28 CH1 CH2 11 REFM 10 REFP AGND CH15 25 24 1 MXO CS AGND AINP ADS7953/ ADS7957/ ADS7961 AINM CH15 +VA CH0 CH14 CH1 CH13 CH2 17 16 8 Copyright © 2008–2010, Texas Instruments Incorporated CH5 CH6 CH7 CH8 CH9 CH10 CH11 9 CH3 CH4 CH12 SCLK Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 11 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 32 AGND SDI SDO BDGND +VBD GPIO +VA REFM www.ti.com REFP SLAS605A – JUNE 2008 – REVISED JANUARY 2010 25 24 1 MXO SCLK CS AGND AINP ADS7952/ ADS7956/ ADS7960 AINM NC +VA NC NC NC CH11 CH0 17 16 8 CH6 CH5 CH4 GPIO +VBD BDGND CH3 CH7 REFM 19 18 24 +VA 1 SDI SCLK AGND ADS7951/ ADS7955/ ADS7959 MXO AINP CS AGND +VA AINM CH3 CH2 +VBD BDGND CH1 CH4 GPIO 19 18 24 CH0 SDO CH6 1 CH5 +VA 13 12 7 REFM 6 REFP CH7 SDI SCLK AGND ADS7950/ ADS7954/ ADS7958 MXO AINP CS AGND +VA AINM CH1 CH0 CH2 NC NC 13 12 7 NC 6 CH3 NC CH1 SDO CH8 REFP CH9 9 CH2 CH10 TERMINAL FUNCTIONS - TSSOP PACKAGES DEVICE NAME ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 PIN NAME I/O FUNCTION PIN NO. REFERENCE 12 4 4 4 4 REFP I Reference input 3 3 3 3 REFM I Reference ground Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 TERMINAL FUNCTIONS - TSSOP PACKAGES (continued) DEVICE NAME ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 PIN NAME I/O FUNCTION PIN NO. ADC ANALOG INPUT 8 8 8 8 AINP I Signal input to ADC 9 9 9 9 AINM I ADC input ground MULTIPLEXER 7 7 7 7 MXO O Multiplexer output 28 28 20 20 Ch0 I Analog channels for multiplexer 27 27 19 18 Ch1 I 26 26 18 14 Ch2 I 25 25 17 12 Ch3 I 24 24 14 - Ch4 I 23 23 13 - Ch5 I 22 22 12 - Ch6 I 21 21 11 - Ch7 I 18 18 - - Ch8 I 17 17 - - Ch9 I 16 16 - - Ch10 I 15 15 - - Ch11 I 14 - - - Ch12 I 13 - - - Ch13 I 12 - - - Ch14 I 11 - - - Ch15 I DIGITAL CONTROL SIGNALS 31 31 23 23 CS I Chip select input 32 32 24 24 SCLK I Serial clock input 33 33 25 25 SDI I Serial data input 34 34 26 26 SDO O Serial data output GENERAL PURPOSE INPUTS / OUTPUTS: These pins have programmable dual functionality. Refer to Table 8 for functionality programming 37 37 29 29 38 38 30 30 1 1 1 1 2 2 2 2 GPIO0 I/O General purpose input or output High alarm or High/Low alarm O Active high output indicating high alarm or high/low alarm depending on programming GPIO1 I/O General purpose input or output Low alarm O Active high output indicating low alarm GPIO2 I/O General purpose input or output Range I GPIO3 I/O PD I Selects range: High -> Range 2 / Low -> Range 1 General purpose input or output Active low power down input POWER SUPPLY AND GROUND 5, 29 5, 29 5, 21 5, 21 +VA — Analog power supply 6, 10, 19, 20, 30 6, 10, 19, 20, 30 6, 10, 22 6, 10, 22 AGND — Analog ground 36 36 28 28 +VBD — Digital I/O supply 35 35 27 27 BDGND — Digital ground NC PINS Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 13 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com TERMINAL FUNCTIONS - TSSOP PACKAGES (continued) DEVICE NAME ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 — 11, 12, 13, 14 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 PIN NAME I/O — — FUNCTION PIN NO. 15, 16 11, 13, 15, 16, 17, 19 Pins internally not connected, do not float these pins TERMINAL FUNCTIONS - QFN PACKAGES DEVICE NAME ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 PIN NAME I/O FUNCTION PIN NO. REFERENCE 31 31 24 24 REFP I Reference input 30 30 23 23 REFM I Reference ground ADC ANALOG INPUT 3 3 4 4 AINP I Signal input to ADC 4 4 5 5 AINM I ADC input ground 2 2 3 3 MXO O Multiplexer output 20 18 13 11 Ch0 I Analog-input channels for multiplexer 19 17 12 10 Ch1 I 18 16 11 9 Ch2 I 17 15 10 8 Ch3 I 16 14 9 - Ch4 I 15 13 8 - Ch5 I 14 12 7 - Ch6 I 13 11 6 - Ch7 I 12 10 - - Ch8 I 11 9 - - Ch9 I 10 8 - - Ch10 I 9 7 - - Ch11 I 8 - - - Ch12 I 7 - - - Ch13 I 6 - - - Ch14 I 5 - - - Ch15 I MULTIPLEXER DIGITAL CONTROL SIGNALS 23 23 16 16 CS I Chip select input 24 24 17 17 SCLK I Serial clock input 25 25 18 18 SDI I Serial data input 26 26 19 19 SDO O Serial data output GENERAL PURPOSE INPUT / OUTPUT: This pin has programmable dual functionality. Refer to Table 8 for functionality programming 29 29 22 22 GPIO0 I/O General purpose input or output High alarm or High/Low alarm O Active high output indicating high alarm or high/low alarm depending on programming +VA — Analog power supply POWER SUPPLY AND GROUND 21, 32 14 21, 32 1, 14 Submit Documentation Feedback 1, 14 Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 TERMINAL FUNCTIONS - QFN PACKAGES (continued) DEVICE NAME ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 1, 22 1, 22 28 28 27 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 PIN NAME I/O 2, 15 2, 15 AGND — Analog ground 21 21 +VBD — Digital I/O supply 27 20 20 BDGND — Digital ground 5, 6, 19, 20 — 6, 7, 12, 13 — — Pins internally not connected, do not float these pins FUNCTION PIN NO. NC PINS — Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 15 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARATERISTICS (all ADS79XX Family Devices) SUPPLY CURRENT vs SUPPLY VOLTAGE STATIC SUPPLY CURRENT vs SUPPLY VOLTAGE 1.5 3.5 2.5 2 1.5 +VA - Supply Current - mA 1.4 3 1.3 1.2 1.1 1 1 2.7 3.4 4.1 4.8 +VA - Supply Voltage - V 0.9 2.7 5.5 fS = 1 MSPS, VDD = 5.5 V 3.4 TA = 25°C +VA - Supply Current - mA 3.2 3 2.8 2.6 2.4 2.2 3.4 4.1 4.8 +VA - Supply Voltage - V 2 -40 5.5 15 70 TA - Free-Air Temperature - °C Figure 1. Figure 2. Figure 3. STATIC SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SAMPLE RATE SUPPLY CURRENT vs SAMPLE RATE 1.115 No Powerdown, TA = 25°C +VA - Supply Current - mA 1.105 1.1 1.095 1.09 1.085 1.08 125 2.5 2.5 VDD = 5.5 V 1.11 With Powerdown, TA = 25°C 5V 2 +VA - Supply Current - mA +VA - Supply Current - mA fS = 1 MSPS, TA = 25°C +VA - Supply Current - mA SUPPLY CURRENT vs FREE-AIR TEMPERATURE 2.7 V 1.5 1 0.5 2 5V 1.5 2.7 V 1 0.5 1.075 1.07 -40 Figure 4. 16 0 0 15 70 TA - Free-Air Temperature - °C Submit Documentation Feedback 125 0 200 400 600 800 fS - Sample Rate - KSPS Figure 5. 1000 0 100 200 300 400 fS - Sample Rate - KSPS 500 Figure 6. Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (12-Bit Devices Only) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE DNL max 0.4 0.2 0 -0.2 DNL min -0.4 -0.6 -0.8 0.6 INL max 0.4 0.2 0 -0.2 INL min -0.4 -0.6 -0.8 3.2 4.2 4.7 3.7 +VA - Supply Voltage - V 5.2 -1 2.7 5.5 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.8 0.6 DNL max 0.4 0.2 0 -0.2 DNL min -0.4 -0.6 -0.8 -1 -40 5.2 15 70 TA - Free-Air Temperature - °C 125 Figure 7. Figure 8. Figure 9. INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE OFFSET ERROR vs SUPPLY VOLTAGE OFFSET ERROR vs INTERFACE SUPPLY VOLTAGE 1 0.6 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 2 2 1.8 1.6 INL max Offset Error - LSBs 0.4 0.2 0 -0.2 INL min -0.4 +VBD = 1.8 V, fS = 1 MSPS, TA = 25°C 1.6 1.4 1.2 1 0.8 0.6 1.4 1.2 1 0.8 0.6 -0.6 0.4 0.4 -0.8 0.2 0.2 15 70 TA - Free-Air Temperature - °C 0 2.7 125 0.6 0 1.8 5.5 2.8 3.3 3.8 4.3 4.8 +VBD - Interace Supply - V Figure 11. Figure 12. GAIN ERROR vs SUPPLY VOLTAGE GAIN ERROR vs INTERFACE SUPPLY VOLTAGE OFFSET ERROR vs FREE-AIR TEMPERATURE 1 +VBD = 1.8 V, fS = 1 MSPS, TA = 25°C 0.8 0.6 Gain Error - LSBs 0.4 0.2 0 -0.2 -0.4 1.8 1.6 0.4 0.2 0 -0.2 -0.4 1.2 1 0.8 0.6 0.4 -0.8 -0.8 0.2 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 13. Copyright © 2008–2010, Texas Instruments Incorporated 2.3 2.8 3.3 3.8 4.3 4.8 +VBD - Interace Supply - V Figure 14. 5.3 5.5 +VA = 5.5 V, +VBD = 1.8 V, fS = 1 MSPS 1.4 -0.6 -1 1.8 5.3 5.5 2 +VA = 5.5 V, fS = 1 MSPS, TA = 25°C -0.6 -1 2.7 2.3 Figure 10. 1 0.8 3.4 4.1 4.8 +VA - Supply Voltage - V Offset Error - LSBs -1 -40 +VA = 5.5 V, fS = 1 MSPS, TA = 25°C 1.8 Offset Error - LSBs 0.8 INL - Integral Nonlinearity - LSBs fS = 1 MSPS, TA = 25°C 0.8 DNL - Differential Nonlinearity - LSBs 0.6 -1 2.7 Gain Error - LSBs 1 1 fS = 1 MSPS, TA = 25°C 0.8 INL - Integral Nonlinearity - LSBs DNL - Differential Nonlinearity - LSBs 1 DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 0 -40 15 70 TA - Free-Air Temperature - °C 125 Figure 15. Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 17 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves GAIN ERROR vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs SUPPLY VOLTAGE 1 SNR - Signal-to-Noise Ratio - dB 0.8 0.7 0.6 0.5 0.4 0.3 0.2 SINAD - Signal-to-Noise and Distortion - dB 72 +VA = 5.5 V, +VBD = 1.8 V, fS = 1 MSPS 0.9 Gain Error - LSBs SIGNAL-TO-NOISE + DISTORTION vs SUPPLY VOLTAGE 71.5 71 70.5 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 70 69.5 0.1 0 -40 15 70 TA - Free-Air Temperature - °C 70.5 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 70 69.5 69 2.7 5.5 3.4 4.1 4.8 +VA - Supply Voltage - V Figure 18. TOTAL HARMONIC DISTORTION vs SUPPLY VOLTAGE SPURIOUS FREE DYNAMIC RANGE vs SUPPLY VOLTAGE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE -83 -84 -85 -86 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C -87 -88 -89 -90 2.7 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 90 89 88 87 86 85 84 83 82 71.5 71 70.5 70 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 69.5 81 80 2.7 5.5 72 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C SNR - Signal-to-Noise Ratio - dB SFDR - Spurious Free Dynamic Range - dB -82 3.4 4.1 4.8 +VA - Supply Voltage - V 69 -40 5.5 15 70 TA - Free-Air Temperature - °C 125 Figure 19. Figure 20. Figure 21. SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 71.5 71 70.5 70 69.5 69 -40 15 70 TA - Free-Air Temperature - °C Figure 22. Submit Documentation Feedback 125 SFDR - Spurious Free Dynamic Range - dB -80 72 THD - Total Harmonic Distortion - dB THD - Total Harmonic Distortion - 71 Figure 17. -81 SINAD - Signal-to-Noise and Distortion - dB 3.4 4.1 4.8 +VA - Supply Voltage - V 71.5 Figure 16. -80 18 69 2.7 125 72 -81 -82 -83 -84 -85 -86 -87 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz -88 -89 -90 -40 15 70 TA - Free-Air Temperature - °C Figure 23. 125 90 89 88 87 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 86 85 84 83 82 81 80 -40 15 70 TA - Free-Air Temperature - °C 125 Figure 24. Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 72 71.5 71 70.5 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 70 69.5 69 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 73 -70 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 72.5 72 71.5 71 70.5 70 69.5 69 10 30 50 70 90 110 130 fIN - Input Frequency - KHz -72 -74 -76 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP -78 -80 -82 -84 -86 -88 -90 10 150 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 Figure 25. Figure 26. Figure 27. SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY (Across Different Source Resistance Values) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Across Different Source Resistance Values) 100 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 95 90 85 80 75 70 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 Figure 28. Copyright © 2008–2010, Texas Instruments Incorporated 72 -70 500 W 71.5 THD - Total Harmonic Distortion - dB SFDR - Spurious Free Dynamic Range - dB SINAD - Signal-to-Noise and Distortion - dB 72.5 SINAD - Signal-to-Noise and Distortion - dB SNR - Signal-to-Noise Ratio - dB 73 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY THD - Total Harmonic Distortion - dB SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 1000 W 71 10 W 70.5 70 69.5 69 20 100 W +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP 40 60 80 fIN - Input Frequency - KHz Figure 29. 100 -72 -74 -76 -78 +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP 1000 W 500 W -80 -82 -84 10 W 100 W -86 -88 -90 20 40 60 80 fIN - Input Frequency - KHz 100 Figure 30. Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 19 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves DIFFERENTIAL NONLINEARITY VARIATION ACROSS CHANNELS INTEGRAL NONLINEARITY VARIATION ACROSS CHANNELS 1 88 10 W 86 100 W 84 82 80 1000 W 500 W 78 76 +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP 74 72 70 20 40 60 80 fIN - Input Frequency - KHz 0.6 0.8 DNL max 0.4 0.2 0 -0.2 DNL min -0.4 -0.6 -0.8 0.4 0.2 0 -0.2 INL min -0.4 -0.6 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 5 10 Channel Number -1 0 15 5 10 Channel Number 15 Figure 31. Figure 32. Figure 33. OFFSET ERROR VARIATION ACROSS CHANNELS GAIN ERROR VARIATION ACROSS CHANNELS SIGNAL-TO-NOISE RATIO VARIATION ACROSS CHANNELS +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.2 1.2 EG - Gain Error - LSBs EO - Offset Error - LSBs 73 0.25 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 1.4 1 0.8 0.6 0.4 SNR - Signal-to-Noise Ratio - dB 1.6 0.15 0.1 0.05 0.2 0 5 10 15 Channel Number Figure 34. Submit Documentation Feedback 20 72.5 72 71.5 71 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 70.5 70 0 0 20 INL max 0.6 -0.8 -1 0 100 1 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.8 INL - Integral Nonlinearity - LSBs 90 DNL - Differential Nonlinearity - LSBs SFDR - Spurious Free Dynamic Range - dB SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (Across Different Source Resistance Values) 0 5 10 15 Channel Number Figure 35. 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Channel Number Figure 36. Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves CROSSTALK vs INPUT FREQUENCY +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 100 Isolation 71.5 71 80 Memory 60 40 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, CH0, CH1 20 70.5 0 0 70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Channel Number Figure 37. 50 100 150 200 fIN - Input Frequency - KHz 80 70 60 50 VI = 0 V 40 VI = 1.25 V 30 VI = 2.5 V 20 10 0 -40 -25 -10 5 250 Figure 39. TOTAL UNADJUSTED ERROR (TUE Min) 25 20 20 Number of Devices 25 15 10 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - °C Figure 38. TOTAL UNADJUSTED ERROR (TUE Max) 15 10 5 5 1 0.5 0.75 0 0.25 -0.5 -0.25 -0.75 2 -1 0.25 0.5 0.75 1 1.25 1.5 1.75 TUE Max - LSB -1.5 0 0 -1.25 Number of Devices AINP - Leakage Current - nA 72 +VA = 5 V, +VBD = 5 V 90 100 -1.75 72.5 INPUT LEAKAGE CURRENT vs FREE-AIR TEMPERATURE 120 73 Crosstalk - dB SINAD - Signal-to-Noise and Distortion - dB SIGNAL-TO-NOISE + DISTORTION VARIATION ACROSS CHANNELS TUE Min- LSB Figure 40. Copyright © 2008–2010, Texas Instruments Incorporated Figure 41. Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 21 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (12-Bit Devices Only) DNL 1 +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C 0.8 0.6 DNL - LSBs 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1024 2048 3072 4096 3072 4096 Code Figure 42. INL 1 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.8 0.6 INL - LSBs 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 1024 0 2048 Code Figure 43. FFT 0 +VA = 5 V +VBD = 5 V, fS = 1 MSPS, fIN = 100 kHz Npoints = 16384 -20 Amplitude - dB -40 -60 -80 -100 -120 -140 -160 0 100000 200000 300000 f - Frequency - Hz 400000 500000 Figure 44. 22 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 DETAILED DESCRIPTION DEVICE OPERATION The ADS7950 to ADS7961 are 12/10/8-bit multichannel devices. Figure 45, Figure 46, Figure 47, and Figure 48 show device operation timing. Device operation is controlled with CS, SCLK, and SDI. The device outputs its data on SDO. Frame n Frame n+1 CS 1 3 5 7 9 11 13 15 16 1 3 5 7 9 11 13 15 16 SCLK SDO Top 4 bit SDI 16 bit i/p word Conversion Mux chan change Acquisition phase tacq Acquisition 12 bit conversion result 16 bit i/p word Mux chan change Analog i/p settling after Chan change MUX GPO Top 4 bit 12 bit conversion result Conversion phase Data written (thr SDI) in frame n-1 Sampling instance Conversion phase tcnv Data written (thr SDI) in frame n GPI GPI status is latched in on CSfalling edge and transferred to SDO frame n Figure 45. Device Operation Timing Diagram Each frame begins with the falling edge of CS. With the falling edge of CS, the input signal from the selected channel is sampled, and the conversion process is initiated. The device outputs data while the conversion is in progress. The 16-bit data word contains a 4-bit channel address, followed by a 12-bit conversion result in MSB first format. There is an option to read the GPIO status instead of the channel address. (Refer to Table 1, Table 2, and Table 5 for more details.) The device selects a new multiplexer channel on the second SCLK falling edge. The acquisition phase starts on the fourteenth SCLK rising edge. On the next CS falling edge the acquisition phase will end, and the device starts a new frame. The TSSOP packaged device has four General Purpose IO (GPIO) pins, QFN versions have only one GPIO. These four pins can be individually programmed as GPO or GPI. It is also possible to use them for preassigned functions, refer to Table 10. GPO data can be written into the device through the SDI line. The device refreshes the GPO data on the CS falling edge as per the SDI data written in previous frame. Similarly the device latches GPI status on the CS falling edge and outputs the GPI data on the SDO line (if GPI read is enabled by writing DI04=1 in the previous frame) in the same frame starting with the CS falling edge. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 23 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com a 1/t throughput (single frame) CS tw 1 tsu 1 SCLK 1 3 2 4 th 1 td 1 DO15 SDO 5 6 14 15 16 DO-0 LSB td 2 td 3 DO13 DO12 DO-11 MSB DO-10 MSB-1 DO-2 LSB+2 DO-1 LSB+1 DI-13 DI-12 DI-11 DI-10 DI-2 DI-1 DO14 tq tsu2 SDI DI-15 DI-14 DI-0 th 2 Figure 46. Serial Interface Timing Diagram for 12-Bit Devices ( ADS7950/51/52/53) a CS CS\ 1/t throughput (single frame) tw1 tsu1 SCLK SDO 1 td1 DO15 2 th1 DO14 3 4 5 6 14 15 16 DO-0 - td2 td3 DO13 DO12 DO-11 MSB DO-10 MSB-1 DO-2 LSB DO-1 - DI-13 DI-12 DI-11 DI-10 DI-2 DI-1 tq tsu2 SDI DI-15 DI-14 DI-0 th2 Figure 47. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954/55/56/57) a CS CS\ tw1 tsu1 SCLK SDO 1/t throughput (single frame) 1 td1 DO15 2 th1 DO14 3 4 5 6 12 13 16 td2 td3 DO13 DO12 DO-11 MSB DO-10 MSB-1 DO-4 LSB DO-3 - DO-0 - DI-13 DI-12 DI-11 DI-10 DI-4 DI-3 DI-0 tq tsu2 SDI DI-15 DI-14 th2 Figure 48. Serial Interface Timing Diagram for 8-Bit Devices (ADS7958/59/60/61) The falling edge of CS clocks out DO-15 (first bit of the four bit channel address), and remaining address bits are clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out on the 4th SCLK falling edge and LSB on the 15th/13th/11th falling edge respectively for 12/10/8-bit devices. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge of SCLK. The device reads a sixteen bit word on the SDI pin while it outputs the data on the SDO pin. SDI data is latched on every rising edge of SCLK starting with the 1st clock as shown in Figure 46, Figure 47, and Figure 48. CS can be asserted (pulled high) only after 16 clocks have elapsed. 24 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits; the device flags out an alarm on GPIO0/GPIO1 depending on the GPIO program register settings (refer to Table 10). The alarm is asserted (under the alarm conditions) on the 12th falling edge of SCLK in the same frame when a data conversion is in progress. The alarm output is reset on the 10th falling edge of SCLK in the next frame. The device offers a power-down feature to save power when not in use. There are two ways to powerdown the device. It can be powered down by writing DI05 = 1 in the mode control register (refer to Table 1, Table 2, and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another way to powerdown the device is through GPIO in the case of the TSSOP packaged devices . GPIO3 can act as the PD input (refer to Table 10, to assign this functionality to GPIO3). This is an asynchronous and active low input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will power up again on the CS falling edge with DI05 = 0 in the mode control register and GPIO3 (PD) = 1. CHANNEL SEQUENCING MODES There are three modes for channel sequencing, namely Manual mode, Auto-1 mode, Auto-2 mode. Mode selection is done by writing into the control register (refer to Table 1, Table 2, and Table 5). A new multiplexer channel is selected on the second falling edge of SCLK (as shown in Figure 45) in all three modes. Manual mode: When configured to operate in Manual mode, the next channel to be selected is programmed in each frame and the device selects the programmed channel in the next frame. On powerup or after reset the default channel is 'Channel-0' and the device is in Manual mode. Auto-1 mode: In this mode the device scans pre-programmed channels in ascending order. A new multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate ‘program register’ for pre-programming the channel sequence. Table 3 and Table 4 show Auto-1 ‘program register’ settings. Once programmed the device retains ‘program register’ settings until the device is powered down, reset, or reprogrammed. It is allowed to exit and re-enter the Auto-1 mode any number of times without disturbing ‘program register’ settings. The Auto-1 program register is reset to FFFF/FFF/FF/F hex for the 16/12/8/4 channel devices respectively upon device powerup or reset; implying the device scans all channels in ascending order. Auto-2 mode: In this mode the user can configure the program register to select the last channel in the scan sequence. The device scans all channels from channel 0 up to and including the last channel in ascending order. The multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate ‘program register’ for pre-programming of the last channel in the sequence (multiplexer depth). Table 6 lists the ‘Auto-2 prog’ register settings for selection of the last channel in the sequence. Once programmed the device retains program register settings until the device is powered down, reset, or reprogrammed. It is allowed to exit and re-enter Auto-2 mode any number of times, without disturbing the ‘program register’ settings. On powerup or reset the bits D9-D6 of the Auto-2 program register are reset to F/B/7/3 hex for the 16/12/8/4 channel devices respectively; implying the device scans all channels in ascending order. DEVICE PROGRAMMING AND MODE CONTROL The following section describes device programming and mode control. These devices feature two types of registers to configure and operate the devices in different modes. These registers are referred as ‘Configuration Registers’. There are two types of ‘Configuration Registers’ namely ‘Mode control registers’ and ‘Program registers’. Mode Control Register A ‘Mode control register’ is configured to operate the device in one of three channel sequencing modes, namely Manual mode, Auto-1 Mode, Auto-2 Mode. It is also used to control user programmable features like range selection, device power-down control, GPIO read control, and writing output data into the GPIO. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 25 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com Program Registers The 'Program registers’ are used for device configuration settings and are typically programmed once on powerup or after device reset. There are different program registers such as ‘Auto-1 mode programming’ for pre-programming the channel sequence, ‘Auto-2 mode programming’ for selection of the last channel in the sequence, ‘Alarm programming’ for all 16 channels (or 12,8,4 channels depending on the device) and GPIO for individual pin configuration as GPI or GPO or a pre-assigned function. DEVICE POWER-UP SEQUENCE The device power-up sequence is shown in Figure 49. Manual mode is the default power-up channel sequencing mode and Channel-0 is the first channel by default. As explained previously, these devices offer Program Registers to configure user programmable features like GPIO, Alarm, and to pre-program the channel sequence for Auto modes. At ‘powerup or on reset’ these registers are set to the default values listed in Table 1 to Table 10. It is recommended to program these registers on powerup or after reset. Once configured; the device is ready to use in any of the three channel sequencing modes namely Manual, Auto-1, and Auto-2. 26 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 Device power up or reset Device operation in manual mode, Channel 0; SDO Invalid in first frame CS First frame CS Auto 1 register program (note 1) CS Auto 2 register program (note 1) CS Alarm register program (note 1) CS GPIO register program (note 1) CS CS Operation in Auto 1 mode Operation in manual mode CS Operation in Auto 2 mode (1) The device continues its operation in Manual mode channel 0 through out the programming sequence and outputs valid conversion results. It is possible to change channel, range, GPIO by inserting extra frames in between two programming blocks. It is also possible to bypass any programming block if the user does not intent to use that feature. (2) It is possible to reprogram the device at any time during operation, regardless of what mode the device is in. During programming the device continues its operation in whatever mode it is in and outputs valid data. Figure 49. Device Power-Up Sequence OPERATING IN MANUAL MODE The details regarding entering and running in Manual channel sequencing mode are illustrated in Figure 50. Table 1 lists the Mode Control Register settings for Manual mode in detail. Note that there are no Program Registers for manual mode. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 27 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com CS Frame: n-1 Device operation in Auto 1 or Auto 2 mode No Change to Manual mode? Yes CS Frame: n Request for Manual mode CS Frame: n+1 Entry into Manual Mode CS Frame: n+2 Operation in Manual mode * Sample: Samples and converts channel selected in ‘frame n-1’ * Mux : Selects channel incremented from previous frame as per auto sequence this channel will be acquired in this frame and sampled at start of ‘frame n+1’ * Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +1’ DI15..12 = 0001 binary …. Selects manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n-1’ I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects channel programmed in ‘frame n’(Manual mode) this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame .* SDI : Programming for ‘frame n+2’ DI15..12 = 0001 binary …. To continue in manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n+1’ * Mux : Selects channel programmed in ‘frame n+1’ (Manual mode), this channel will be acquired in this frame and sampled at start of ‘frame n+3’ * Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0001 binary …. Selects manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n+1’ I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same frame CS Continue operation in manual mode Figure 50. Entering and Running in Manual Channel Sequencing Mode 28 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 Table 1. Mode Control Register Settings for Manual Mode DESCRIPTION RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0001 Selects Manual Mode DI11 0 1 Enables programming of bits DI06-00. 0 Device retains values of DI06-00 from the previous frame. DI10-07 0000 This four bit data represents the address of the next channel to be selected in the next frame. DI10: MSB and DI07: LSB. e.g. 0000 represents channel- 0, 0001 represents channel-1 etc. DI06 0 0 Selects 2.5V i/p range (Range 1) 1 Selects 5V i/p range (Range 2) 0 Device normal operation (no powerdown) 1 Device powers down on 16th SCLK falling edge 0 SDO outputs current channel address of the channel on DO15..12 followed by 12 bit conversion result on DO11..00. DI05 DI04 0 0 1 DI03-00 (1) (2) 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel. DOI5 DOI4 DOI3 DOI2 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 DI02 DI01 DI00 GPIO3 (2) GPIO2 (2) GPIO1 (2) GPIO0 (2) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 29 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com OPERATING IN AUTO-1 MODE The details regarding entering and running in Auto-1 channel sequencing mode are illustrated in the flowchart in Figure 51. Table 2 lists the Mode Control Register settings for Auto-1 mode in detail. CS Frame: n-1 Device operation in Manual or Auto-2 mode No Change to Auto -1 mode? Yes CS Frame: n Request for Auto-1 mode CS Frame: n+1 Entry into Auto-1 Mode CS Frame: n+2 Operation in Auto-1 mode * Sample: Samples and converts channel selected in ‘frame n -1’ * Mux : Selects channel incremented from previous frame as per Auto -2 sequence, or channel programmed in previous frame in case of manual mode. This channel will be acquired in this frame and sampled at start of ‘frame n +1’ * Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n+1’ DI15..12 = 0010 binary …. Selects Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 = x, Device automatically resets channel to lowest number in Auto -1 sequence. DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n-1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects lowest channel# in Auto-1 sequence; this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +2’ DI15..12 = 0010 binary …. To continue in Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0, not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n+1’ (ie. Lowest channel# in Auto-1 sequence) * Mux : Selects next higher channel in Auto -1 sequence, this channel will be acquired in this frame and sampled at start of ‘frame n +3’ * Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0010 binary …. To continue in Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0 not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n+1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Continue operation in Auto -1 mode Figure 51. Entering and Running in Auto-1 Channel Sequencing Mode 30 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 Table 2. Mode Control Register Settings for Auto-1 Mode DESCRIPTION RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0010 Selects Auto-1 Mode DI11 0 1 Enables programming of bits DI10-00. 0 Device retains values of DI10-00 from previous frame. DI10 0 1 The channel counter is reset to the lowest programmed channel in the Auto-1 Program Register 0 The channel counter increments every conversion (No reset) DI09-07 000 xxx Do not care DI06 0 0 Selects 2.5V i/p range (Range 1) 1 Selects 5V i/p range (Range 2) 0 Device normal operation (no powerdown) 1 Device powers down on the 16th SCLK falling edge 0 SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion result on DO11..00. DI05 0 DI04 0 1 DI03-00 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel. DO15 DO14 DO13 DO12 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 GPIO3 (1) (2) DI02 (2) GPIO2 DI01 (2) GPIO1 DI00 (2) GPIO0 (2) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 31 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com The Auto-1 Program Register is programmed (once on powerup or reset) to pre-select the channels for the Auto-1 sequence. Auto-1 Program Register programming requires two CS frames for complete programming. In the first CS frame the device enters the Auto-1 register programming sequence and in the second frame it programs the Auto-1 Program Register. Refer to Table 2, Table 3, and Table 4 for complete details. CS Device in any operation mode No Program Auto 1 register? Yes SDI: DI15..12 = 1000 (Device enters Auto 1 programming sequence) CS Entry into Auto 1 register programming sequence CS SDI: DI15..0 as per tables 4,5 Auto 1 register programming End of Auto 1 register programming NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 52. Auto-1 Register Programming Flowchart Table 3. Program Register Settings for Auto-1 Mode DESCRIPTION RESET STATE BITS LOGIC STATE FUNCTION FRAME 1 DI15-12 NA 1000 DI11-00 NA Do not care Device enters Auto-1 program sequence. Device programming is done in the next frame. All 1s 1 (individual bit) FRAME 2 DI15-00 A particular channel is programmed to be selected in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits; e.g. DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00 A particular channel is programmed to be skipped in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits; e.g. DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00 0 (individual bit) Table 4. Mapping of Channels to SDI Bits for 16,12,8,4 Channel Devices Device (1) SDI BITS DI15 DI14 DI13 DI12 DI11 DI10 DI09 DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01 DI00 16 Chan 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 12 Chan X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 8 Chan X X X X X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 4 Chan X X X X X X X X X X X X 1/0 1/0 1/0 1/0 (1) 32 When operating in Auto-1 mode, the device only scans the channels programmed to be selected. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 OPERATING IN AUTO-2 MODE The details regarding entering and running in Auto-2 channel sequencing mode are illustrated in Figure 53. Table 5 lists the Mode Control Register settings for Auto-2 mode in detail. CS Frame: n-1 Device operation in Manual or Auto -1 mode No Change to Auto- 2 mode ? Yes CS Frame: n Request for Auto-2 mode CS Frame: n+1 Entry into Auto-2 Mode CS Frame: n+2 Operation in Auto-2 mode * Sample: Samples and converts channel selected in ‘frame n-1’ * Mux : Selects channel incremented from previous frame as per Auto-1 sequence, or channel programmed in previous frame in case of manual mode. . This channel will be acquired in this frame and sampled at start of ‘frame n +1’ * Range: As programmed in ‘frame n-1’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n+1’ DI15..12 = 0011 binary …. Selects Auto-2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 = x, Device automatically resets to channel 0. DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n -1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects channel0 (Auto-2 sequence always starts with Ch -0); this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +2’ DI15..12 = 0011 binary …. To continue in Auto -2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0, not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel 0 * Mux : Selects next higher channel in Auto -2 sequence, this channel will be acquired in this frame and sampled at start of ‘frame n+3’ * Range: As programmed in ‘frame n+1’. Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0011 binary …. To continue in Auto -2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0 not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n+1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Continue operation in Auto-2 mode Figure 53. Entering and Running in Auto-2 Channel Sequencing Mode Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 33 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com Table 5. Mode Control Register Settings for Auto-2 Mode DESCRIPTION RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0011 Selects Auto-2 Mode DI11 0 1 Enables programming of bits DI10-00. 0 Device retains values of DI10-00 from the previous frame. DI10 0 1 Channel number is reset to Ch-00. 0 Channel counter increments every conversion.(No reset). DI09-07 000 xxx Do not care DI06 0 0 Selects 2.5V i/p range (Range 1) 1 Selects 5V i/p range (Range 2) 0 Device normal operation (no powerdown) 1 Device powers down on the 16th SCLK falling edge 0 SDO outputs the current channel address of the channel on DO15..12 followed by the 12-bit conversion result on DO11..00. DI05 0 DI04 0 1 DI03-00 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel. DO15 DO14 DO13 DO12 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device ignores data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 GPIO3 (1) DI02 (1) GPIO2 DI01 (1) GPIO1 DI00 (1) GPIO0 (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. The Auto-2 Program Register is programmed (once on powerup or reset) to pre-select the last channel (or sequence depth) in the Auto-2 sequence. Unlike Auto-1 Program Register programming, Auto-2 Program Register programming requires only 1 CS frame for complete programming. See Figure 54 and Table 6 for complete details. CS Device in any operation mode No Program Auto 2 register? Yes CS SDI: Di15..12 = 1001 DI9..6 = binary address of last channel in the sequence refer tables 6 Auto 2 register programming End of Auto 2 register programming NOTE: The device continues its operation in the selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 54. Auto-2 Register Programming Flowchart 34 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 Table 6. Program Register Settings for Auto-2 Mode RESET STATE BITS DESCRIPTION LOGIC STATE FUNCTION DI15-12 NA 1001 DI11-10 NA Do not care Auto-2 program register is selected for programming DI09-06 NA aaaa DI05-00 NA Do not care This 4-bit data represents the address of the last channel in the scanning sequence. During device operation in Auto-2 mode, the channel counter starts at CH-00 and increments every frame until it equals “aaaa”. The channel counter roles over to CH-00 in the next frame. CONTINUED OPERATION IN A SELECTED MODE Once a device is programmed to operate in one of the modes, the user may want to continue operating in the same mode. Mode Control Register settings to continue operating in a selected mode are detailed in Table 7. Table 7. Continued Operation in a Selected Mode RESET STATE BITS DESCRIPTION LOGIC STATE FUNCTION DI15-12 0001 0000 The device continues to operate in the selected mode. In Auto-1 and Auto-2 modes the channel counter increments normally, whereas in the Manual mode it continues with the last selected channel. The device ignores data on DI11-DI00 and continues operating as per the previous settings. This feature is provided so that SDI can be held low when no changes are required in the Mode Control Register settings. DI11-00 All '0' Device ignores these bits when DI15-12 is set to 0000 logic state PROGRAMMING ALARM THRESHOLDS There are two Alarm Program Registers per channel, one for setting the high alarm threshold and the other for setting the low alarm threshold. For ease of programming, two alarm programming registers per channel, corresponding to four consecutive channels, are assembled into one group (a total eight registers). There are four such groups for 16 channel devices and 3/2/1 such groups for 12/8/4 channel devices respectively. The grouping of the various channels for each device in the ADS79XX family is listed in Table 8. The details regarding programming the alarm thresholds are illustrated in the flowchart in Figure 55. Table 9 lists the details regarding the Alarm Program Register settings. Table 8. Grouping of Alarm Program Registers GROUP NO. REGISTERS APPLICABLE FOR DEVICE 0 High and low alarm for channel 0, 1, 2, and 3 ADS7953..50, ADS7957..54, ADS7961..58 1 High and low alarm for channel 4, 5, 6, and 7 ADS7953..51, ADS7957..55, ADS7961..59 2 High and low alarm for channel 8, 9, 10, and 11 ADS7953 and 52, ADS7957 and 56, ADS7961 and 60 3 High and low alarm for channel 12, 13, 14, and 15 ADS7953, ADS7957, ADS7961 Each alarm group requires 9 CS frames for programming their respective alarm thresholds. In the first frame the device enters the programming sequence and in each subsequent frame it programs one of the registers from the group. The device offers a feature to program less than eight registers in one programming sequence. The device exits the alarm threshold programming sequence in the next frame after it encounters the first ‘Exit Alarm Program’ bit high. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 35 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 CS www.ti.com Device in any operation mode No Program alarm thresholds? Yes SDI: DI15..12 = 11XX (xx indicates group of four channels; refer table 8) Device enters alarm register programming sequence CS Entry into alarm register programming sequence CS SDI: DI15..0 as per table 8 (program alarm thresholds) Alarm register programming sequence No Yes DI12 = 1? Yes Program another group of four channels? No End of alarm programing NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 55. Alarm Program Register Programming Flowchart Table 9. Alarm Program Register Settings DESCRIPTION BITS RESET STATE LOGIC STATE FUNCTION FRAME 1 DI15-12 NA 1100 Device enters ‘alarm programming sequence’ for group 0 1101 Device enters ‘alarm programming sequence’ for group 1 1110 Device enters ‘alarm programming sequence’ for group 2 1111 Device enters ‘alarm programming sequence’ for group 3 Note: DI15-12 = 11bb is the alarm programming request for group bb. Here ‘bb’ represents the alarm programming group number in binary format. DI11-14 NA Do not care FRAME 2 AND ONWARDS 36 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 Table 9. Alarm Program Register Settings (continued) DESCRIPTION BITS RESET STATE LOGIC STATE FUNCTION DI15-14 NA cc Where “cc” represents the lower two bits of the channel number in binary format. The device programs the alarm for the channel represented by the binary number “bbcc”. Note that “bb” is programmed in the first frame. DI13 NA 1 High alarm register selection 0 Low alarm register selection 0 Continue alarm programming sequence in next frame 1 Exit Alarm Programming in the next frame. Note: If the alarm programming sequence is not terminated using this feature then the device will remain in the alarm programming sequence state and all SDI data will be treated as alarm thresholds. Do not care DI12 NA DI11-10 NA xx DI09-00 All ones for high alarm register and all zeros for low alarm register This 10-bit data represents the alarm threshold. The 10-bit alarm threshold is compared with the upper 10-bit word of the 12-bit conversion result. The device sets off an alarm when the conversion result is higher (High Alarm) or lower (Low Alarm) than this number. For 10-bit devices, all 10 bits of the conversion result are compared with the set threshold. For 8-bit devices, all 8 bits of the conversion result are compared with DI09 to DI02 and DI00, 01 are 'do not care'. PROGRAMMING GPIO REGISTERS NOTE GPIO 1 to 3 are available only in TSSOP packaged devices. The QFN device offers 'GPIO 0' only. As a result, all references related to 'GPIO 0' only are valid in the case of QFN package devices. The device has four General Purpose Input and Output (GPIO) pins. Each of the four pins can be independently programmed as General Purpose Output (GPO) or General Purpose Input (GPI). It is also possible to use the GPIOs for some pre-assigned functions (refer to Table 10 for details). GPO data can be written into the device through the SDI line. The device refreshes the GPO data on every CS falling edge as per the SDI data written in the previous frame. Similarly, the device latches GPI status on the CS falling edge and outputs it on SDO (if GPI is read enabled by writing DI04 = 1 during the previous frame) in the same frame starting on the CS falling edge. The details regarding programming the GPIO registers are illustrated in the flowchart in Figure 56. Table 10 lists the details regarding GPIO Register programming settings. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 37 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com CS Device in any operation mode No Program GPIO register? Yes SDI: DI15..12 = 0100 Refer table 9 for DI11..00 data CS GPIO register programming End of GPIO register programming NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 56. GPIO Program Register Programming Flowchart Table 10. GPIO Program Register Settings RESET STATE BITS DESCRIPTION LOGIC STATE FUNCTION DI15-12 NA 0100 Device selects GPIO Program Registers for programming. DI11-10 00 00 Do not program these bits to any logic state other than ‘00’ DI09 0 1 Device resets all registers in the next CS frame to the reset state shown in the corresponding tables (it also resets itself). 0 Device normal operation 1 Device configures GPIO3 as the device power-down input. 0 GPIO3 remains general purpose I or O. Program 0 for QFN packaged devices. 1 Device configures GPIO2 as device range input. 0 GPIO2 remains general purpose I or O. Program 0 for QFN packaged devices. 000 GPIO1 and GPIO0 remain general purpose I or O. Valid setting for QFN packaged devices. xx1 Device configures GPIO0 as ‘high or low’ alarm output. This is an active high output. GPIO1 remains general purpose I or O. Valid setting for QFN packaged devices. 010 Device configures GPIO0 as high alarm output. This is an active high output. GPIO1 remains general purpose I or O. Valid setting for QFN packaged devices. 100 Device configures GPIO1 as low alarm output. This is an active high output. GPIO0 remains general purpose I or O. Setting not allowed for QFN packaged devices. 110 Device configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high outputs. Setting not allowed for QFN packaged devices. DI08 0 DI07 0 DI06-04 000 Note: The following settings are valid for GPIO which are not assigned a specific function through bits DI08..04 DI03 0 DI02 0 DI01 0 DI00 38 0 1 GPIO3 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO3 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO2 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO2 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO1 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO1 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO0 pin is configured as general purpose output. Valid setting for QFN packaged devices. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 Table 10. GPIO Program Register Settings (continued) BITS RESET STATE DESCRIPTION LOGIC STATE 0 FUNCTION GPIO0 pin is configured as general purpose input. Valid setting for QFN packaged devices. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 39 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com APPLICATION INFORMATION ANALOG INPUT The ADS79XX device family offers 12/10/8-bit ADCSs with 16/12/8/4 channel multiplexers for analog input. The multiplexer output is available on the MXO pin. AINP is the ADC input pin. The devices offers flexibility for a system designer as both signals are accessible esternally. Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be processed independently. In this condition it is recommended to limit source impedance to 50Ω or less. Higher source impedance may affect the signal settling time after a multiplexer channel change. This condition can affect linearity and total harmonic distortion. MXO AINP GPIO 0, H Alarm Ch0 Ch1 GPIO 1, L Alarm Ch2 GPIO 2, Range GPIO 3, PD From sensors, INA etc. There is a restriction on source impedance. RSOURCE £ 50 W ADC SDO To Host SDI SCLK CS Chn* REF 10 mF REF5025 o/p GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all references related to 'GPIO 0' only are valid in case of QFN package devices. Figure 57. Typical Application Diagram Showing MXO Shorted to AINP Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the restriction on source impedance to a large extent. Refer to the typical characteristics section for the effect of source impedance on device performance. The typical characteristics show that the device has respectable performance with up to 1kΩ source impedance. This topology (including a common ADC driver) is useful when all channel signals are within the acceptable range of the ADC. In this case the user can save on signal conditioning circuit for each channel. 40 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 High Input impedance PGA (or non inverting buffer like THS4031) PGA Gain Control GPIO 1, 2, 3 MXO AINP GPIO 0 H/L Alarm Ch0 Ch1 Ch2 From sensors, INA etc. Source impedance has very little effect on performance. Refer to Typical Characteristics for details. ADC SDO To Host SDI SCLK CS Chn* REF 10 mF REF5025 o/p GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all references related to 'GPIO 0' only are valid in case of QFN package devices. Figure 58. Typical Application Diagram Showing Common Buffer/PGA for all Channels When the converter samples an input, the voltage difference between AINP and AGND is captured on the internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS79XX charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the Ch0 .. Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 41 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com 80 W ohm MXO Ch0 AINP 200 Wohm 3 pF 5 pF 7 pF Chn 20M W ohm 3 pF Ch0 assumed to be on Chn assumed to be off Figure 59. ADC and Mux Equivalent Circuit REFERENCE The ADS79XX can operate with an external 2.5V ± 10mV reference. A clean, low noise, well-decoupled reference voltage on the REF pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF5025 can be used to drive this pin. A 10-mF ceramic decoupling capacitor is required between the REF and GND pins of the converter. The capacitor should be placed as close as possible to the pins of the device. POWER SAVING The ADS79XX devices offer a power-down feature to save power when not in use. There are two ways to powerdown the device. It can be powered down by writing DI05 = 1 in the Mode Control register (refer to Table 1, Table 2 and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another way to powerdown the device is through GPIO. GPIO3 can act as a PD input (refer to Table 10, for assigning this functionality to GPIO3). This is an asynchronous and active low input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will powerup again on the CS falling edge while DI05 = 0 in the Mode Control register and GPIO3 (PD) = 1. DIGITAL OUTPUT As discussed previously in the Device Operation section, the digital output of the ADS79XX devices is SPI compatible. The following table lists the output codes corresponding to various analog input voltages. Table 11. Ideal Input Voltages and Output Codes for 12-Bit Devices (ADS7950/51/52/53) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → Vref Range 2 → 2×Vref Least significant bit (LSB) Vref/4096 2Vref/4096 Full scale Vref – 1 LSB 2Vref – 1 LSB 1111 1111 1111 FFF Midscale Vref/2 Vref 1000 0000 0000 800 Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 0111 1111 1111 7FF Zero 0V 0V 0000 0000 0000 000 STRAIGHT BINARY BINARY CODE HEX CODE Table 12. Ideal Input Voltages and Output Codes for 10-Bit Devices (ADS7954/55/56/57) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → Vref Range 2 → 2×Vref Least significant bit (LSB) Vref/1024 2Vref/1024 Full scale Vref – 1 LSB 2Vref – 1 LSB 11 1111 1111 3FF Midscale Vref/2 Vref 10 0000 0000 200 Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 01 1111 1111 1FF Zero 0V 0V 00 0000 0000 000 42 Submit Documentation Feedback STRAIGHT BINARY BINARY CODE HEX CODE Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 Table 13. Ideal Input Voltages and Output Codes for 8-Bit Devices (ADS7958/59/60/61) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → Vref Range 2 → 2×Vref Least significant bit (LSB) Vref/256 2Vref/256 Full scale Vref – 1 LSB 2Vref – 1 LSB 1111 1111 FF Midscale Vref/2 Vref 1000 0000 80 Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 0111 1111 7F Zero 0V 0V 0000 0000 00 Copyright © 2008–2010, Texas Instruments Incorporated STRAIGHT BINARY BINARY CODE HEX CODE Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 43 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605A – JUNE 2008 – REVISED JANUARY 2010 www.ti.com REVISION HISTORY Changes from Original (June 2008) to Revision A Page • Added QFN information to Features ..................................................................................................................................... 1 • Added QFN information to Description ................................................................................................................................. 1 • Added QFN information to 12-bit ordering information ......................................................................................................... 3 • Added QFN information to 10-bit ordering information ......................................................................................................... 3 • Added QFN information to 8-bit ordering information ........................................................................................................... 4 • Changed thermal impedance for DBT package in absolute maximum ratings .................................................................... 4 • Changed thermal impedance for RHB package in absolute maximum ratings .................................................................... 4 • Changed thermal impedance for RGE package in absolute maximum ratings .................................................................... 4 • Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ..................................................... 5 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 5 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 5 • Added Total unadjusted error (TUE) specification ................................................................................................................ 5 • Changed reference voltage at REFP min and max values .................................................................................................. 6 • Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ..................................................... 6 • Added Note to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ............................................................................ 6 • Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 6 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 6 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 6 • Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 7 • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 7 • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 7 • Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 8 • Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 test conditions ............................. 8 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 8 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 8 • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 9 • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 9 • Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 test conditions ............................. 9 • Changed tsu1 values from max to min ................................................................................................................................. 10 • Changed tsu2 values from max to min ................................................................................................................................. 10 • Changed VEE to AGND and VCC to +VA on 38-pin TSSOP pinout ................................................................................. 11 • Added QFN pinout .............................................................................................................................................................. 11 • Added QFN pinout .............................................................................................................................................................. 12 • Added QFN pinout .............................................................................................................................................................. 12 • Added QFN pinout .............................................................................................................................................................. 12 • Added terminal functions for QFN packages ...................................................................................................................... 14 • Changed ADS7950/4/8 QFN package MXO pin from 7 to 3 .............................................................................................. 14 • Added TOTAL UNADJUSTED ERROR (TUE Max) graph ................................................................................................. 21 • Added TOTAL UNADJUSTED ERROR (TUE Min) graph .................................................................................................. 21 • Changed GPIO pins description ......................................................................................................................................... 23 • Added device powerdown through GPIO in the case of the TSSOP packaged devices ................................................... 25 • Added note to Table 1 ........................................................................................................................................................ 29 • Added note to Table 1 ........................................................................................................................................................ 29 44 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605A – JUNE 2008 – REVISED JANUARY 2010 • Added note to Table 2 ........................................................................................................................................................ 31 • Added note to Table 2 ........................................................................................................................................................ 31 • Added note to Table 5 ........................................................................................................................................................ 34 • Changed DI12 = 1? from No or No to Yes or No in Figure 55 ........................................................................................... 36 • Added note to Programming GPIO Registers description .................................................................................................. 37 • Added QFN information to Table 10 ................................................................................................................................... 38 • Added note to Figure 57 ..................................................................................................................................................... 40 • Added note to Figure 58 ..................................................................................................................................................... 41 Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 45 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7950SBDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 B ADS7950SBDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 B ADS7950SBDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 B ADS7950SBDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 B ADS7950SBRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7950 B ADS7950SBRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7950 B ADS7950SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 ADS7950SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 ADS7950SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 ADS7950SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 ADS7950SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7950 ADS7950SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7950 ADS7951SBDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 B ADS7951SBDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 B ADS7951SBDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 B ADS7951SBDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 B Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Jan-2013 Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7951SBRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS 7951 B ADS7951SBRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS 7951 B ADS7951SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 ADS7951SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 ADS7951SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 ADS7951SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 ADS7951SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS 7951 ADS7951SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS 7951 ADS7952SBDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 B ADS7952SBDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 B ADS7952SBDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 B ADS7952SBDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 B ADS7952SBRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7952 B ADS7952SBRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7952 B ADS7952SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 ADS7952SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Jan-2013 Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7952SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 ADS7952SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 ADS7952SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7952 ADS7952SRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7952 ADS7953SBDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 B ADS7953SBDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 B ADS7953SBDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 B ADS7953SBDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 B ADS7953SBRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7953 B ADS7953SBRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7953 B ADS7953SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 ADS7953SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 ADS7953SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 ADS7953SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 ADS7953SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7953 ADS7953SRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7953 ADS7954SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7954 Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Jan-2013 Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7954SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7954 ADS7954SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7954 ADS7954SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7954 ADS7954SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7954 ADS7954SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7954 ADS7955SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 ADS7955SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 ADS7955SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 ADS7955SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 ADS7955SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7955 ADS7955SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7955 ADS7956SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7956 ADS7956SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7956 ADS7956SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7956 ADS7956SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7956 ADS7956SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7956 ADS7956SRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7956 ADS7957SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7957 Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Jan-2013 Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7957SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7957 ADS7957SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7957 ADS7957SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7957 ADS7957SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7957 ADS7957SRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7957 ADS7958SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 ADS7958SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 ADS7958SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 ADS7958SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 ADS7958SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7958 ADS7958SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7958 ADS7959SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 ADS7959SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 ADS7959SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 ADS7959SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 ADS7959SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7959 ADS7959SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7959 ADS7960SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 Addendum-Page 5 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Jan-2013 Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7960SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 ADS7960SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 ADS7960SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 ADS7960SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7960 ADS7960SRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7960 ADS7961SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 ADS7961SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 ADS7961SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 ADS7961SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 ADS7961SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7961 ADS7961SRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7961 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 6 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS7955 : • Automotive: ADS7955-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 7 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7950SBDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7950SBRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7950SBRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7950SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7950SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7950SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7951SBDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7951SBRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7951SBRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7951SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7951SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7951SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7952SBDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7952SBRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7952SBRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7952SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7952SRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7952SRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7953SBDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7953SBRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7953SBRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7953SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7953SRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7953SRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7954SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7954SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7954SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7955SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7955SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7955SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7956SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7957SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7958SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7958SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7958SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7959SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7959SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7959SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7960SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7961SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7950SBDBTR ADS7950SBRGER TSSOP DBT 30 2000 367.0 367.0 38.0 VQFN RGE 24 3000 367.0 367.0 35.0 ADS7950SBRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7950SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7950SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7950SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7951SBDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7951SBRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7951SBRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7951SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7951SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7951SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7952SBDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7952SBRHBR QFN RHB 32 3000 367.0 367.0 35.0 ADS7952SBRHBT QFN RHB 32 250 210.0 185.0 35.0 ADS7952SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7952SRHBR QFN RHB 32 3000 367.0 367.0 35.0 ADS7952SRHBT QFN RHB 32 250 210.0 185.0 35.0 ADS7953SBDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7953SBRHBR QFN RHB 32 3000 367.0 367.0 35.0 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7953SBRHBT QFN RHB 32 250 210.0 185.0 35.0 ADS7953SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7953SRHBR QFN RHB 32 3000 367.0 367.0 35.0 ADS7953SRHBT QFN RHB 32 250 210.0 185.0 35.0 ADS7954SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7954SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7954SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7955SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7955SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7955SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7956SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7957SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7958SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7958SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7958SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7959SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7959SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7959SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7960SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7961SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 Pack Materials-Page 4 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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