Preliminary Technical Data Single Channel, 12/16-Bit, Serial Input, Current Source & Voltage Output DAC AD5412/AD5422 FEATURES GENERAL DESCRIPTION 12/16-Bit Resolution and Monotonicity Current Output Ranges: 4–20mA, 0–20mA or 0–24mA 0.1% typ Total Unadjusted Error (TUE) 5ppm/°C Output Drift Voltage Output Ranges: 0-5V, 0-10V, ±5V, ±10V, 10% over-range 0.05% Total Unadjusted Error (TUE) 3ppm/°C Output Drift Flexible Serial Digital Interface On-Chip Output Fault Detection On-Chip Reference (10 ppm/°C Max) Asynchronous CLEAR Function Power Supply Range AVDD : 10.8V to 40 V AVSS : -26.4V to -3V/0V Output Loop Compliance to AVDD – 2.5 V Temperature Range: -40°C to +85°C TSSOP and LFCSP Packages The AD5412/AD5422 is a low-cost, precision, fully integrated 12/16-bit converter offering a programmable current source and programmable voltage output designed to meet the requirements of industrial process control applications. The output current range is programmable to 4mA to 20 mA, 0mA to 20mA or an overrange function of 0mA to 24mA. Voltage output is provided from a separate pin that can be configured to provide 0V to 5V, 0V to 10V, ±5V or ±10V output ranges, an over-range of 10% is available on all ranges. Analog outputs are short and open circuit protected and can drive capacitive loads of 1uF and inductive loads of 1H. The device is specified to operate with a power supply range from 10.8 V to 40 V. Output loop compliance is 0 V to AVDD – 2.5 V. The flexible serial interface is SPI and MICROWIRE compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The device also includes a power-on-reset function ensuring that the device powers up in a known state and an asynchronous CLEAR pin which sets the outputs to zero-scale / mid-scale voltage output or the low end of the selected current range. The total output error is typically ±0.1% in current mode and ±0.05% in voltage mode. APPLICATIONS Process Control Actuator Control PLC Table 1. Pin Compatible Devices Part Number AD5420 AD5410 Description Single Channel, 16-Bit, Serial Input Current Source DAC Single Channel, 12-Bit, Serial Input Current Source DAC Rev. PrF Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD5412/AD5422 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Features ............................................................................................ 30 Applications....................................................................................... 1 fault alert...................................................................................... 30 General Description ......................................................................... 1 voltage output short circuit protection.................................... 30 Revision History ............................................................................... 2 Voltage ouTput over-range........................................................ 30 Functional Block Diagram .............................................................. 3 voltage output force-sense......................................................... 30 Specifications..................................................................................... 4 Asynchronous Clear (CLEAR) ................................................. 30 AC Performance Characteristics ................................................ 7 Internal Reference ...................................................................... 30 Timing Characteristics ................................................................ 8 External current setting resistor............................................... 30 Absolute Maximum Ratings.......................................................... 10 Digital Power Supply.................................................................. 30 ESD Caution................................................................................ 10 External boost function............................................................. 31 Pin Configuration and Function Descriptions........................... 11 External compensation capacitor............................................. 31 Typical Performance Characteristics Voltage output............... 13 digital Slew rate control ............................................................. 31 Typical Performance Characteristics current output ............... 17 IOUT Filtering Capacitors (LFCSP Package)............................. 32 Typical Performance Characteristics general ............................ 20 Applications Information .............................................................. 33 Terminology .................................................................................... 22 driving inductive loads .............................................................. 33 Theory of Operation ...................................................................... 24 Transient voltage protection ..................................................... 33 Architecture................................................................................. 24 Single connector for IOUT AND Vout ......................................... 33 Serial Interface ............................................................................ 24 Galvanically Isolated Interface ................................................. 33 Power-on state............................................................................. 27 Microprocessor Interfacing....................................................... 33 Transfer Function ....................................................................... 27 Layout Guidelines....................................................................... 34 Data Register ............................................................................... 28 Thermal and supply considerations......................................... 35 Control Register.......................................................................... 28 Outline Dimensions ....................................................................... 36 RESET register ............................................................................ 28 Ordering Guide .......................................................................... 37 Status register .............................................................................. 29 REVISION HISTORY PrF – Preliminary Version, April 25, 2008 Rev. PrF | Page 2 of 38 Preliminary Technical Data AD5412/AD5422 FUNCTIONAL BLOCK DIAGRAM DVCC SELECT CLEA R SELECT DVCC CAP1* CAP2* AV SS AD5412/AD5422 R2 R3 BOOST CLEA R LATCH SCLK SDIN SDO AV DD INPUT SHIFT REGISTER AND CONTROL LOGIC 16 / 12/16-Bit DAC IOUT FAULT R SET R1 POWER ON RESET VREF +VSENSE RANGE SCALING VOUT -VSENSE DGND* REFOUT AGND REFIN *LFCSP Package Figure 1. Rev. PrF | Page 3 of 38 CCOMP AD5412/AD5422 Preliminary Technical Data SPECIFICATIONS AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external; DVCC = 2.7 V to 5.5 V, VOUT : RL = 1 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL = 50mH; all specifications TMIN to TMAX, ±10 V / 0 to 24 mA range unless otherwise noted. Table 2. Parameter VOLTAGE OUTPUT Output Voltage Ranges ACCURACY Bipolar Output Resolution Value1 Unit 0 to 5 0 to 10 -5 to +5 -10 to +10 V V V V Output unloaded 16 12 0.1 Bits Bits % FSR max Differential Nonlinearity (DNL) Bipolar Zero Error ±3 ±0.012 ±0.024 ±1 ±5 ppm typ % FSR max % FSR max LSB max mV max Bipolar Zero TC2 Zero-Scale Error ±3 ±1 ppm FSR/°C max mV max Zero-Scale TC2 Gain Error ±3 ±0.05 ppm FSR/°C max % FSR max Gain TC2 Full-Scale Error ±8 0.05 ppm FSR/°C max % FSR max ±3 ppm FSR/°C max 16 12 0.1 Bits Bits % FSR max Differential Nonlinearity (DNL) Zero Scale Error ±0.012 ±0.024 ±1 +10 % FSR max % FSR max LSB max mV max Zero Scale TC2 Offset Error Gain Error ±3 ±10 ±0.05 ppm FSR/°C max mV max % FSR max Gain TC2 Full-Scale Error ±3 0.05 ppm FSR/°C max % FSR max ±3 ppm FSR/°C max 0.8 TBD V max V max Total Unadjusted Error (TUE) TUE TC2 Relative Accuracy (INL) Full-Scale TC2 Unipolar Output Resolution Total Unadjusted Error (TUE) Relative Accuracy (INL) Full-Scale TC2 OUTPUT CHARACTERISTICS2 Headroom Test Conditions/Comments Rev. PrF | Page 4 of 38 AD5422 AD5412 Over temperature, supplies, and time, typically 0.05% FSR AD5422 AD5412 Guaranteed monotonic @ 25°C, error at other temperatures obtained using bipolar zero TC @ 25°C, error at other temperatures obtained using zero scale TC @ 25°C, error at other temperatures obtained using gain TC @ 25°C, error at other temperatures obtained using gain TC AVSS = 0 V AD5422 AD5412 Over temperature, supplies, and time, typically 0.05% FSR AD5422 AD5412 Guaranteed monotonic (at 16 bit-resolution) @ 25°C, error at other temperatures obtained using gain TC @ 25°C, error at other temperatures obtained using gain TC @ 25°C, error at other temperatures obtained using gain TC 0.5V typ. Output Unloaded TBD typ. 1KΩ Load on Output Preliminary Technical Data AD5412/AD5422 Value1 ±3 ±12 ±15 20 2 Unit ppm FSR/°C max ppm FSR/500 hr typ ppm FSR/1000 hr typ mA typ kΩ min 20 TBD 1 0.3 10 TBD nF max nF max µF max Ω typ µs typ µV/V 0 to 24 0 to 20 4 to 20 mA mA mA Differential Nonlinearity (DNL) Offset Error Offset Error Drift Gain Error 16 12 ±0.3 ±5 ±0.012 ±0.024 ±1 ±0.05 ±5 ±0.02 Bits Bits % FSR max ppm/°C typ % FSR max % FSR max LSB max % FSR max µv/°C typ % FSR max Gain TC2 Full-Scale Error ±8 0.05 ppm FSR/°C max % FSR max ±8 ppm FSR/°C AVDD - 2.5 TBD TBD 1200 1 1 50 V max ppm FSR/500 hr typ ppm FSR/1000 hr typ Ω max H max µA/V max MΩ typ 5 30 4 to 5 V nom kΩ min V min to V max ±1% for specified performance Typically 40 kΩ 4.998 to 5.002 ±10 18 120 ±40 ±50 TBD V min to V max ppm/°C max µV p-p typ nV/√Hz typ ppm/500 hr typ ppm/1000 hr typ nF max @ 25°C Parameter Output Voltage TC Output Voltage Drift vs. Time Short-Circuit Current Load Capacitive Load Stability RL = ∞ RL = 2 kΩ RL = ∞ DC Output Impedance Power-On Time DC PSRR CURRENT OUTPUT Output Current Ranges ACCURACY Resolution Total Unadjusted Error (TUE) TUE TC2 Relative Accuracy (INL) Full-Scale TC2 OUTPUT CHARACTERISTICS2 Current Loop Compliance Voltage Output Current Drift vs. Time Resistive Load Inductive Load DC PSRR Output Impedance REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Reference Range Reference Output Output Voltage Reference TC Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Output Voltage Drift vs. Time2 Capacitive Load Rev. PrF | Page 5 of 38 Test Conditions/Comments Vout = ¾ of Full-Scale For specified performance External compensation capacitor of 4nF connected. AD5422 AD5412 Over temperature, supplies, and time, typically 0.1% FSR AD5422 AD5412 Guaranteed monotonic @ 25°C, error at other temperatures obtained using gain TC @ 25°C, error at other temperatures obtained using gain TC @ 10 kHz AD5412/AD5422 Parameter Load Current Short Circuit Current Line Regulation2 Load Regulation2 Thermal Hysteresis2 DIGITAL INPUTS2 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance DIGITAL OUTPUTS 2 SDO VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance FAULT VOL, Output Low Voltage VOL, Output Low Voltage VOH, Output High Voltage POWER REQUIREMENTS AVDD AVSS |AVSS | + AVDD DVCC Input Voltage Output Voltage Output Load Current Short Circuit Current AIDD AISS DICC Power Dissipation 1 2 Preliminary Technical Data Value1 5 7 10 TBD TBD Unit mA typ mA typ ppm/V typ ppm/mA ppm 2 0.8 ±1 10 V min V max µA max pF typ 0.4 DVCC − 0.5 ±1 V max V min µA max 5 pF typ 0.4 0.6 3.6 V max V typ V min 10.8 to 40 -26.4 to 0 10.8 to 52.8 V min to V max V min to V max V min to V max 2.7 to 5.5 4.5 5 20 TBD TBD 1 TBD TBD TBD V min to V max V typ mA typ mA typ mA mA mA max mW typ mW typ mW typ Test Conditions/Comments DVCC = 2.7 V to 5.5 V, JEDEC compliant Temperature range: -40°C to +85°C; typical at +25°C. Guaranteed by characterization. Not production tested. Rev. PrF | Page 6 of 38 Per pin Per pin sinking 200 µA sourcing 200 µA 10kΩ pull-up resistor to DVCC @ 2.5 mA 10kΩ pull-up resistor to DVCC Internal supply disabled DVCC can be overdriven up to 5.5V Output unloaded Output unloaded VIH = DVCC, VIL = GND, TBD mA typ AVDD = 40V, AVSS = 0 V, VOUT unloaded AVDD = 40V, AVSS = -15 V, VOUT unloaded AVDD = 15V, AVSS = -15 V, VOUT unloaded Preliminary Technical Data AD5412/AD5422 AC PERFORMANCE CHARACTERISTICS AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external; DVCC = 2.7 V to 5.5 V, VOUT : RL = 1 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL = 50mH; all specifications TMIN to TMAX, ±10 V / 0 to 24 mA range unless otherwise noted. Table 3. Parameter1 DYNAMIC PERFORMANCE VOLTAGE OUTPUT Output Voltage Settling Time Slew Rate Power-On Glitch Energy Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Feedthrough Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise (100 kHz Bandwidth) 1/f Corner Frequency Output Noise Spectral Density AC PSRR CURRENT OUTPUT Output Current Settling Time AC PSRR 1 Unit Test Conditions/Comments 8 10 5 1 10 10 20 1 0.1 80 1 100 TBD µs typ µs max µs max V/µs typ nV-sec typ nV-sec typ mV typ nV-sec typ LSB p-p typ µV rms max kHz typ nV/√Hz typ dB Full-scale step (10 V) to ±0.03% FSR TBD TBD TBD µs typ µs typ dB To 0.1% FSR , L = 1H To 0.1% FSR , L < 1mH 200mV 50/60Hz Sinewave superimposed on power supply voltage. Guaranteed by characterization, not production tested. Rev. PrF | Page 7 of 38 512 LSB step settling (16-Bit LSB) 16-Bit LSB Measured at 10 kHz 200mV 50/60Hz Sinewave superimposed on power supply voltage. AD5412/AD5422 Preliminary Technical Data TIMING CHARACTERISTICS AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external; DVCC = 2.7 V to 5.5 V, VOUT : RL = 1 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL = 50mH; all specifications TMIN to TMAX, ±10 V / 0 to 24 mA range unless otherwise noted. Table 4. Parameter1, 2, 3 Write Mode t1 t2 t3 t4 t5 t5 t6 t7 t8 t9 t10 Readback Mode t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 Daisychain Mode t21 t22 t23 t24 t25 t26 t27 t28 t29 Limit at TMIN, TMAX Unit Description 33 13 13 13 40 5 5 5 40 20 5 ns min ns min ns min ns min ns min µs min ns min ns min ns min ns min µs max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time LATCH high time (After a write to the CONTROL register) Data setup time Data hold time LATCH low time CLEAR pulsewidth CLEAR activation time 82 33 33 13 40 5 5 40 40 33 ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO4 = 15pF) LATCH rising edge to SDO tri-state 82 33 33 13 40 5 5 40 40 ns min ns min ns min ns min ns min ns min ns min ns min ns max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO4 = 15pF) 1 Guaranteed by characterization. Not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 CL SDO = Capacitive load on SDO output. 2 Rev. PrF | Page 8 of 38 Preliminary Technical Data AD5412/AD5422 t1 SCLK 1 2 24 t3 t2 t4 t5 LATCH t7 t6 SDIN t8 DB23 DB0 t9 CLEAR t10 OUTPUT Figure 2. Write Mode Timing Diagram t11 SCLK 1 2 t12 2 1 24 t13 t14 8 9 23 22 24 t15 LATCH t16 SDIN t17 t18 DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ t 20 t 19 SDO X UNDEFINED DATA X X X DB15 FIRST 8 BITS ARE DON’T CARE BITS DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 3. Readback Mode Timing Diagram t21 SCLK 1 2 25 24 26 48 t22 t23 t24 t25 LATCH t26 SDIN DB23 DB0 INPUT WORD FOR DAC N SDO DB23 DB23 t28 DB0 INPUT WORD FOR DAC N-1 t 29 DB0 t27 DB23 UNDEFINED DB0 INPUT WORD FOR DAC N Figure 4. Daisychain Mode Timing Diagram Rev. PrF | Page 9 of 38 t 20 AD5412/AD5422 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter AVDD to AGND, DGND AVSS to AGND, DGND AVDD to AVSS DVCC to AGND, DGND Digital Inputs to AGND, DGND Digital Outputs to AGND, DGND REFIN/REFOUT to AGND, DGND VOUT to AGND, DGND IOUT to AGND, DGND AGND to DGND Operating Temperature Range (TA) Industrial Storage Temperature Range Junction Temperature (TJ max) 24-Lead TSSOP Package θJA Thermal Impedance 40-Lead LFCSP Package θJA Thermal Impedance Power Dissipation Lead Temperature Soldering Rating −0.3V to 48V +0.3 V to −48 V -0.3V to 60V −0.3 V to +7 V −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to DVCC + 0.3 V or 7V (whichever is less) −0.3 V to +7 V AVSS to AVDD −0.3V to AVDD -0.3V to +0.3V −40°C to +851°C −65°C to +150°C 125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 42°C/W Power dissipated on chip must be de-rated to keep junction temperature below 125°C. Assumption is max power dissipation condition is sourcing 24mA into Ground from AVDD with a 3mA on-chip current. 28°C/W (TJ max – TA)/ θJA JEDEC Industry Standard J-STD-020 Rev. PrF | Page 10 of 38 Preliminary Technical Data AD5412/AD5422 AGND 11 GND 12 15 REFIN NC +VSENSE VOUT NC AVDD -VSENSE AVSS NC 29 CAP2 GND 3 28 CAP1 AD5412/ AD5422 27 BOOST 26 IOUT TOP VIEW (Not to Scale) 25 NC 24 CCOMP SDIN 8 23 DVCC SELECT SDO 9 22 NC NC 10 21 NC CLEAR SELECT 4 CLEAR 5 14 REFOUT 13 RSET Figure 5. TSSOP Pin Configuration 31 11 12 13 14 15 16 17 18 19 20 NC SDO 10 16 DVCC SELECT 32 NC 9 33 30 SCLK 7 17 CCOMP 34 FAULT 2 LATCH 6 18 NC 35 REFIN SDIN 8 36 REFOUT SCLK 37 RSET LATCH 7 38 GND 6 20 BOOST TOP VIEW (Not to Scale) 19 I OUT 39 AVSS CLEAR SELECT 5 CLEAR 21 VOUT 4 40 NC 1 DGND GND 22 +VSENSE NC 23 -VSENSE AD5412/ AD5422 3 NC FAULT NC 24 AVDD 1 AGND AVSS DVCC 2 DVCC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. LFCSP Pin Configuration Table 6. Pin Function Descriptions TSSOP Pin No. 1 LFCSP Pin No. 14,37 Mnemonic AVSS 2 3 39 2 DVCC FAULT 4,12 18 GND NC 5 3,15 1,10,11,19, 20,21,22,25,30, 31,35,38,40 4 6 5 CLEAR SELECT CLEAR 7 6 LATCH 8 7 SCLK 9 10 8 9 SDIN SDO 11 N/A 12 13 AGND DGND 13 16 RSET 14 15 17 18 REFOUT REFIN 16 23 DVCC SELECT 17 24 CCOMP Description Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be connected to 0V if output voltage range is unipolar. Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. Fault alert, This pin is asserted low when an open circuit is detected in current mode or an over temperature is detected. Open drain output, must be connected to a pull-up resistor. These pins must be connected to 0V. No Connection. Do not connect to this pin. Selects the voltage output clear value, either zero-scale or mid-scale code. See Table 21 Active High Input. Asserting this pin will set the current output to the bottom of the selected range or will set the voltage output to the user selected value (zero-scale or mid-scale). Positive edge sensitive latch, a rising edge will parallel load the input shift register data into the DAC register, also updating the output. Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the rising edge of SCLK. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is valid on the rising edge of SCLK . See Figure 3 and Figure 4. Ground reference pin for analog circuitry. Ground reference pin for digital circuitry. (AGND and DGND are internally connected in TSSOP package). An external, precision, low drift 15kΩ current setting resistor can be connected to this pin to improve the IOUT temperature drift performance. Refer to Features section. Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV. External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for specified performance. This pin when connected to GND disables the internal supply and an external supply must be connected to the DVCC pin. Leave this pin unconnected to enable the internal supply. Refer to features section. Optional compensation capacitor connection for the voltage output buffer. Connecting a 4nF capacitor between this pin and the VOUT pin will allow the voltage output to drive up to 1µF. It should be noted that the addition of this capacitor will reduce the Rev. PrF | Page 11 of 38 AD5412/AD5422 Preliminary Technical Data TSSOP Pin No. LFCSP Pin No. Mnemonic 19 20 26 27 IOUT BOOST N/A N/A 21 28 29 32 CAP1 CAP2 VOUT 22 23 24 Paddle 33 34 36 Paddle +VSENSE -VSENSE AVDD AVSS Description bandwidth of the output amplifier increasing the settling time. Current output pin. Optional external transistor connection. Connecting an external transistor will reduce the power dissipated in the AD5412/AD5422. Refer to the features section. Connection for optional output filtering capacitor. Refer to Features section. Connection for optional output filtering capacitor. Refer to Features section. Buffered Analog Output Voltage. The output amplifier is capable of directly driving a 1 kΩ, 2000 pF load. Sense connection for the positive voltage output load connection. Sense connection for the negative voltage output load connection. Positive Analog Supply Pin. Voltage ranges from 10.8V to 60V. Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be connected to 0V if output voltage range is unipolar. Rev. PrF | Page 12 of 38 Preliminary Technical Data AD5412/AD5422 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT Figure 7. Integral Non Linearity Error vs DAC Code (Four Traces) Figure 10. Integral Non Linearity vs. Temperature (Four Traces) Figure 8. Differential Non Linearity Error vs. DAC Code (Four Traces) Figure 11. Differential Non Linearity vs. Temperature (Four Traces) Figure 9. Total Unadjusted Error vs. DAC Code (Four Traces) Figure 12. Integral Non Linearity vs. Supply Voltage (Four Traces) Rev. PrF | Page 13 of 38 AD5412/AD5422 Preliminary Technical Data Figure 13.Differential Non Linearity Error vs. Supply Voltage (Four Traces) Figure 16. Total Unadjusted Error vs.Reference Voltage (Four Traces) Figure 14. Integral Non Linearity Error vs. Reference Voltage (Four traces) Figure 17. Total Unadjusted Error vs. Supply Voltage (Four Traces) Figure 15. Differential Non Linearity Error vs. Reference Voltage (Four Traces) Figure 18. Offset Error vs.Temperature Rev. PrF | Page 14 of 38 Preliminary Technical Data AD5412/AD5422 Figure 19. Bipolar Zero Error vs. Temperature Figure 22. Source and Sink Capability of Output Amplifier Zero-Scale Loaded Figure 20. Gain Error vs. Temperature Figure 23.Full-Scale Positive Step Figure 21. Source and Sink Capability of Output Amplifier Full-Scale Code Loaded Figure 24. Full-Scale Negative Step Rev. PrF | Page 15 of 38 AD5412/AD5422 Preliminary Technical Data Figure 25. Digital-to-Analog Glitch Energy Figure 28. VOUT vs. Time on Power-up Figure 26. Peak-to-Peak Noise (0.1Hz to 10Hz Bandwidth) Figure 29. VOUT vs, Time on Output Enabled Figure 27. Peak-to-Peak Noise (100kHz Bandwidth) Rev. PrF | Page 16 of 38 Preliminary Technical Data AD5412/AD5422 TYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUT Figure 30. Integral Non Linearity vs. Code Figure 33. Integral Non Linearity vs. Temperature Figure 31.Differential Non Linearity vs. Code Figure 34. Differential Non Linearity vs. Temperature Figure 32. Total Unadjusted Error vs. Code Figure 35. Integral Non Linearity vs. Supply Rev. PrF | Page 17 of 38 AD5412/AD5422 Preliminary Technical Data Figure 36. Differential Non Linearity vs. Supply Voltage Figure 39. Total Unadjusted Error vs. Reference Voltage Figure 37. Integral Non Linearity vs. Reference Voltage Figure 40. Total Unadjusted Error vs. Supply Voltage Figure 38. Differential Non Linearity vs. Reference Voltage Figure 41. Offset Error vs. Temperature Rev. PrF | Page 18 of 38 Preliminary Technical Data AD5412/AD5422 Figure 42. Gain Error vs. Temperature Figure 44. IOUT vs. Time on Power-up Figure 43. Voltage Compliance vs. Temperature Figure 45. IOUT vs. Time on Output Enabled Rev. PrF | Page 19 of 38 AD5412/AD5422 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS GENERAL Figure 46. DICC vs.Logic Input Voltage Figure 49. DVCC Output Voltage vs. DICC Load Current Figure 47. AIDD/AISS vs AVDD/AVSS Figure 50. Refout Turn-on Transient Figure 48. AIDD vs AVDD Figure 51. Refout Output Noise (0.1Hz to 10Hz Bandwidth) Rev. PrF | Page 20 of 38 Preliminary Technical Data AD5412/AD5422 Figure 52. Refout Output Noise (100kHz Bandwidth) Figure 55. Refout Histogram of Thermal Hysteresis Figure 53. Refout Line Transient Figure 56. Refout Voltage vs. Load Current Figure 54. Refout Load Transient Rev. PrF | Page 21 of 38 AD5412/AD5422 Preliminary Technical Data TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 7. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 10. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724R/ AD5734R/AD5754R are monotonic over their full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure TBD. Bipolar Zero TC Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Full-Scale Error Full-Scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed in percent of full-scale range (% FSR). Negative Full-Scale Error/Zero-Scale Error Negative full-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be negative full-scale − 1 LSB. A plot of zero-scale error vs. temperature can be seen in Figure TBD Zero-Scale TC This is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. A plot of settling time can be seen in Figure TBD Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltageoutput D/A converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure TBD Gain TC This is a measure of the change in gain error with changes in temperature. Gain Error TC is expressed in ppm FSR/°C. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Current Loop Voltage Compliance The maximum voltage at the IOUT pin for which the output currnet will be equal to the programmed value. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5412/AD5422 is powered-on. It is specified as the area of the glitch in nV-sec. See Figure TBD Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure TBD Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure TBD. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Reference TC Rev. PrF | Page 22 of 38 Preliminary Technical Data AD5412/AD5422 Reference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/°C. Line Regulation −40°C to +85°C and back to +25°C. This is a typical value from a sample of parts put through such a cycle. See Figure TBDfor a histogram of thermal hysteresis. VO _ HYS = VO (25° C) − VO _ TC Line regulation is the change in reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V. VO _ HYS ( ppm) = Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA. Thermal Hysteresis VO (25° C) − VO _ TC VO (25° C) × 10 6 where: VO(25°C) = VO at 25°C VO_TC = VO at 25°C after temperature cycle Thermal hysteresis is the change of reference output voltage after the device is cycled through temperatures from +25°C to Rev. PrF | Page 23 of 38 AD5412/AD5422 Preliminary Technical Data THEORY OF OPERATION The AD5412/AD5422 is a precision digital to current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop and unipolar/bipolar voltage outputs. The current ranges available are; 0 to 20mA, 0 to 24mA and 4 to 20mA, the voltage ranges available are; 0 to 5V, ±5V, 0 to 10V and ±10V, a 10% over-range is available on all voltage output ranges. The current and voltage outputs are available on separate pins and only one is active at any one time. The desired output configuration is user selectable via the CONTROL register. ARCHITECTURE The DAC core architecture of the AD5412/AD5422 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 57. The 4 MSBs of the 12/16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects 1 of 15 matched resistors to either ground or the reference buffer output. The remaining 8/12 bits of the dataword drive switches S0 to S7/S11 of a 8/12-bit voltage mode R2R ladder network. VOUT 2R 2R 2R 2R 2R 2R 2R S0 S1 S7/S11 E1 E2 E15 VREF 8/12-BIT R-2R LADDER FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 57. DAC Ladder Structure The voltage output from the DAC core is either converted to a current (see diagram, Figure 58) which is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground or it is buffered and scaled to output a software selectable unipolar or bipolar voltage range (See diagram, Figure 59). The current and voltage are output on separate pins and cannot be output simultaneously. AV DD +VSENSE 12/16-BIT DAC RANGE SCALING VOUT -VSENSE R1 RL VCM -1V to +3V REFIN Figure 59. Voltage Output Voltage Output Amplifier The voltage output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 1 kΩ in parallel with 1 µF (with addition of external compensation capacitor) to AGND. The source and sink capabilities of the output amplifier can be seen in Figure 22. The slew rate is 1 V/µs with a full-scale settling time of 10 µs, (10V step). Figure 59 shows the voltage output driving a load, RL on top of a common mode voltage, (VCM) of -1V to +3V. In output module applications where a cable could possibly become disconnected from +VSENSE resulting in the amplifier loop being broken and possibly resulting in large destructive voltages on VOUT, a resistor, R1, of value 2kΩ to 5kΩ should be included as shown to ensure the amplifier loop is kept closed. If remote sensing of the load is not required, +VSENSE should be connected to VOUT and -VSENSE should be connected to GND. When changing ranges on the voltage output a glitch may occur, for this reason it is recommended that the output is disabled by setting the OUTEN bit of the Control register to logic low before changing the output voltage range, this will prevent a glitch from occuring. Driving Large Capacitive Loads The voltage output amplifier is capable of driving capacitive loads of up to 1uF with the addition of a non-polarised 4nF compensation capacitor between the CCOMP and VOUT pins. Without the compensation capacitor, up to 20nF capacitive loads can be driven. Reference Buffers R2 R3 The AD5412/AD5422 can operate with either an external or internal reference. The reference input has an input range of 4 V to 5 V, 5 V for specified performance. This input voltage is then buffered before it is applied to the DAC. T2 12/16-BIT DAC A2 T1 A1 IOUT R1 SERIAL INTERFACE The AD5412/AD5422 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI®, QSPI™, MICROWIRE™, and DSP standards. Figure 58. Voltage to Current conversion circuitry Rev. PrF | Page 24 of 38 Preliminary Technical Data AD5412/AD5422 Input Shift Register latched on the rising edge of LATCH. Data will continue to be clocked in irrespective of the state of LATCH, on the rising edge of LATCH the data that is present in the input register will be latched, in other words the last 24 bits to be clocked in before the rising edge of LATCH is the data that is latched. The timing diagram for this operation is shown in Figure 2. The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the rising edge of SCLK. The input register consists of 8 address bits and 16 data bits as shown in Table 7. The 24 bit word is unconditionally Table 7. Input Shift Register Format MSB D23 D22 D21 D20 D19 D18 ADDRESS WORD D17 D16 D15 D14 D13 D12 D11 01010101 01010110 D9 D8 D7 DATA WORD CONTROLLER Table 8. Control Word Functions Address Word 00000000 00000001 00000010 D10 Function No Operation (NOP) DATA Register Readback register value as per Read Address (See Table 10) CONTROL Register RESET Register DATA OUT D6 D5 D4 D3 D2 AD5412/ AD5422* SDIN SERIAL CLOCK SCLK CONTROL OUT LATCH DATA IN SDO SDIN Standalone Operation The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can only be used if LATCH is taken high after the correct number of data bits have been clocked in. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data. The rising edge of SCLK that clocks in the MSB of the dataword marks the beginning ot the write cycle. Exactly 24 rising clock edges must be applied to SCLK before LATCH is brought high. If LATCH is brought high before the 24th rising SCLK edge, the data written will be invalid. If more than 24 rising SCLK edges are applied before LATCH is brought high, the input data will also be invalid. AD5412/ AD5422* SCLK LATCH SDO SDIN AD5412/ AD5422* SCLK LATCH SDO *ADDITIONAL PINS OMITTED FOR CLARITY Figure 60. Daisy Chaining the AD5412/AD5422 Rev. PrF | Page 25 of 38 D1 LSB D0 AD5412/AD5422 Preliminary Technical Data Daisy-Chain Operation must be used, and LATCH must be taken high after the final clock to latch the data. See Figure 4 for a timing diagram. For systems that contain several devices, the SDO pin can be used to daisy chain the devices together as shown in Figure 60. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Daisychain mode is enabled by setting the DCEN bit of the CONTROL register. The first rising edge of SCLK that clocks in the MSB of the dataword marks the beginning of the write cycle. SCLK is continuously applied to the input shift register. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is valid on the rising edge of SCLK, having been clocked out on the previous falling SCLK edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5412/AD5422 devices in the chain. When the serial transfer to all devices is complete, LATCH is taken high. This latches the input data in each device in the daisy chain. The serial clock can be a continuous or a gated clock. Readback Operation Readback mode is invoked by setting the address word and read address as shown in Table 9 and Table 10 when writing to the input register. The next write to the AD5412/AD5422 should be a NOP command which will clock out the data from the previously addressed register as shown in Figure 3. By default the SDO pin is disabled, after having addressed the AD5412/AD5422 for a read operation, a rising edge on LATCH will enable the SDO pin in anticipation of data being clocked out, after the data has been clocked out on SDO, a rising edge on LATCH will disable (tri-state) the SDO pin once again. To read back the data register for example, the following sequence should be implemented: 1. 2. Write 0x020001 to the input register. This configures the part for read mode with the data register selected. Follow this with a second write, a NOP condition, 0x000000 During this write, the data from the register is clocked out on the SDO line. A continuous SCLK source can only be used if LATCH is taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles Table 9. Input Shift Register Contents for a read operation MSB D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 1 0 X X X X X X X X X X X X X X Table 10. Read Address Decoding Read Address 00 01 10 Function Read Status Register Read Data Register Read Control Register Rev. PrF | Page 26 of 38 LSB D1 D0 Read Address Preliminary Technical Data AD5412/AD5422 Table 11. POWER-ON STATE TRANSFER FUNCTION Output Range +5 V +10 V ±5 V ±10 V Voltage Output Current Output For a unipolar voltage output range, the output voltage can be expressed as: For the 0 to 20mA, 0 to 24mA and 4 to 20mA current output ranges the output current is respectively expressed as: On power-up of the AD5412/AD5422, the power-on-reset circuit ensures that all registers are loaded with zero-code, as such both outputs will be disabled. (VOUT and IOUT in tri-state). D VOUT = VREFIN × Gain ⎡⎢ N ⎤⎥ ⎣2 ⎦ ⎡ 20mA ⎤ I OUT = ⎢ N ⎥ × D ⎣ 2 ⎦ For a bipolar voltage output range, the output voltage can be expressed as: D VOUT = VREFIN × Gain ⎡⎢ N ⎣2 ⎡ 24mA ⎤ I OUT = ⎢ N ⎥ × D ⎣ 2 ⎦ ⎤ − Gain × VREFIN ⎥⎦ 2 ⎡16mA ⎤ I OUT = ⎢ N ⎥ × D + 4mA ⎣ 2 ⎦ where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. VREFIN is the reference voltage applied at the REFIN pin. Gain is an internal gain whose value depends on the output range selected by the user as shown in Table 11. Gain Value 1 2 2 4 where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. Rev. PrF | Page 27 of 38 AD5412/AD5422 Preliminary Technical Data DATA REGISTER The DATA register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the DATA register is entered in positions D15 to D4 for the AD5412 and D15 to D0 for the AD5422 as shown in Table 12 and Table 13. Table 12. Programming the AD5412 Data Register MSB D15 D14 D13 D12 D11 D10 D9 12-BIT DATA WORD D8 D7 D6 D5 D4 D3 X D2 X D1 X LSB D0 X D1 LSB D0 Table 13. Programming the AD5422 Data Register MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 16-BIT DATA WORD D6 D5 D4 D3 D2 CONTROL REGISTER The CONTROL register is addressed by setting the address word of the input shift register to 0x55. The data to be written to the CONTROL register is entered in positions D15 to D0 as shown in Table 14. The CONTROL register functions are shown in Table 15. Table 14. Programming the CONTROL Register MSB D15 CLRSEL D14 OVRRNG D13 REXT D12 OUTEN D11 D10 D9 SR CLOCK D8 D7 D6 D5 SR STEP D4 SREN D3 DCEN D2 R2 D1 R1 LSB D0 R0 Table 15. Control Register Functions Option CLRSEL Description See Table 21 for a description of the CLRSEL operation Setting this bit increases the voltage output range by 10%. Further details in Features section Setting this bit selects the external current setting resistor, Further details in Features section Output enable. This bit must be set to enable the outputs, The range bits select which output will be functional. See Features Section. Digital Slew Rate Control See Features Section. Digital Slew Rate Control Digital Slew Rate Control enable Daisychain enable Output range select. See Table 16 OVRRNG REXT OUTEN SR CLOCK SR STEP SREN DCEN R2,R1,R0 Table 16. Output Range Options R2 0 0 0 0 1 1 1 R1 0 0 1 1 0 1 1 R0 0 1 0 1 1 0 1 Output Range Selected 0 to +5V Voltage Range 0 to 10V Voltage Range ±5V Voltage Range ±10V Voltage Range 4 to 20 mA Current Range 0 to 20 mA Current Range 0 to 24 mA Current Range RESET REGISTER The RESET register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the RESET register is entered in positions D15 to D0 as shown in Table 17. The RESET register options are shown in Table 17 and Table 18. Table 17. Programming the RESET Register MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 Table 18. RESET register Functions Option RESET Description Setting this bit performs a reset operation, restoring the AD5412/AD5422 to its power-on state Rev. PrF | Page 28 of 38 D3 D2 D1 LSB D0 RESET Preliminary Technical Data AD5412/AD5422 STATUS REGISTER The STATUS register is a read only register. The STATUS register functionality is shown in Table 19 and Table 20. Table 19. Decoding the STATUS Register MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 IOUT FAULT Table 20. STATUS Register Functions Option IOUT FAULT SLEW ACTIVE OVER TEMP Description This bit will be set if a fault is detected on the IOUT pin. This bit will be set while the output value is slewing (slew rate control enabled) This bit will be set if the AD5412/AD5422 core temperature exceeds approx. 150°C. Rev. PrF | Page 29 of 38 D1 SLEW ACTIVE LSB D0 OVER TEMP AD5412/AD5422 Preliminary Technical Data FEATURES FAULT ALERT ASYNCHRONOUS CLEAR (CLEAR) The AD5412/AD5422 is equipped with a FAULT pin, this is an open-drain output allowing several AD5412/AD5422 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios; CLEAR is an active high clear that allows the voltage output to be cleared to either zero-scale code or mid-scale code, userselectable via the CLEAR SELECT pin or the CLRSEL bit of the CONTROL register as described in Table 21. (The Clear select feature is a logical OR function of the CLEAR SELECT pin and the CLRSEL bit). The Current output will clear to the bottom of its programmed range. It is necessary to maintain CLEAR high for a minimum amount of time (see Figure 2) to complete the operation. When the CLEAR signal is returned low, the output remains at the cleared value.The pre-clear value can be restored by pulsing the LATCH signal low without clocking any data. A new value cannot be programmed until the CLEAR pin is returned low. 1) 2) The Voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The IOUT current is controlled by a PMOS transistor and internal amplifier as shown in Figure 58. The internal circuitry that develops the fault output avoids using a comparator with “window limits” since this would require an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approxiamately one volt of remaining drive capability (when the gate of the output PMOS transistor nearly reaches ground). Thus the FAULT output activates slightly before the compliance limit is reached. Since the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain and an output error does not occur before the FAULT output becomes active. If the core temperature of the AD5412/AD5422 exceeds approx. 150°C. The IOUT FAULT and OVER TEMP bits of the STATUS register are used in conjunction with the FAULT pin to inform the user which one of the fault conditions caused the FAULT pin to be asserted. See Table 19 and Table 20. VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION Under normal operation the voltage output will sink/source 10mA and maintain specified operation. The maximum current that the voltage output will deliver is approx. 20mA, this is the short circuit current. VOLTAGE OUTPUT OVER-RANGE An over-range facility is provided on the voltage output. When enabled via the CONTROL register, the selected output range will be over-ranged by 10%. VOLTAGE OUTPUT FORCE-SENSE The +VSENSE and –VSENSE pins are provided to facilitate remote sensing of the load connected to the voltage output. If the load is connected at the end of a long or high impedance cable, sensing the voltage at the load will allow the output amplifier to compensate and ensure the correct voltage is applied across the load. This function is limited only by the available power supply headroom. Table 21. CLEAR SELECT Options CLRSEL 0 1 Output Unipolar Output Range 0V Mid-Scale Value Bipolar Output Range 0V Negative Full-Scale As well as defining the output value for a clear operation, the CLRSEL bit and CLEAR SELECT pin also define the default output value. On selection of a new voltage range the output value will be as defined in Table 21. It is recommended, to avoid glitches on the output, that before changing voltage ranges the output be disabled by setting the OUTEN bit of the Control register to logic low. When OUTEN is set to logic high the output will go to the default value as defined by CLRSEL and CLEAR SELECT. INTERNAL REFERENCE The AD5412/AD5422 contains an integrated +5V voltage reference with initial accuracy of ±2mV max and a temperature drift coefficient of ±10 ppm/°C max. The reference voltage is buffered and externally available for use elsewhere within the system. See Figure 56 for a load regulation graph of the Integrated reference. EXTERNAL CURRENT SETTING RESISTOR Referring to Figure 58, R1 is an internal sense resistor as part of the voltage to current conversion circuitry. The stability of the output current over temperature is dependent on the stability of the value of R1. As a method of improving the stability of the output current over temperature an external precision 15kΩ low drift resistor can be connected to the RSET pin of the AD5412/AD5422 to be used instead of the internal resistor R1. The external resistor is selected via the CONTROL register. See Table 14. DIGITAL POWER SUPPLY By default, the DVCC pin accepts a power supply of 2.7V to 5.5V, alternatively, via the DVCC SELECT pin an internal 4.5V power supply may be output on the DVCC pin for use as a digital power Rev. PrF | Page 30 of 38 Preliminary Technical Data AD5412/AD5422 supply for other devices in the system or as a termination for pull-up resistors. This facility offers the advantage of not having to bring a digital supply across an isolation barrier. The internal power supply is enabled by leaving the DVCC SELECT pin unconnected. To disable the internal supply DVCC SELECT should be tied to 0V. DVCC is capable of supplying up to 5mA of current, for a load regulation graph see Figure 49. define the rate of change of the output value.Table 22 and Table 23 outline the range of values for both the SR CLOCK and SR STEP parameters. Table 22. Slew Rate Step Size options SR STEP 000 001 010 011 100 101 110 111 EXTERNAL BOOST FUNCTION The addition of an external boost transistor as shown in Figure 61 will reduce the power dissipated in the AD5412/AD5422 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). A discrete NPN transistor with a breakdown voltage, BVCEO, greater than 60V can be used.The external boost capability has been developed for those users who may wish to use the AD5412/AD5422 at the extremes of the supply voltage, load current and temperature range. The boost transistor can also be used to reduce the amount of temperature induced drift in the part. This will minimise the temperature induced drift of the on-chip voltage reference, which improves on drift and linearity. SR CLOCK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AD5412/ AD5422 IOUT 1k 0.022 F RLOAD Figure 61. External Boost Configuration EXTERNAL COMPENSATION CAPACITOR The voltage output can ordinarily drive capacitive loads of up to 20nF, if there is a requirement to drive greater capacitive loads, of up to 1uF, an external compensation capacitor can be connected between the CCOMP and VOUT pins. The additon of the capacitor will keep the output voltage stable but will also reduce the bandwidth and increase the settling time of the voltage output. DIGITAL SLEW RATE CONTROL The Slew Rate Control feature of the AD5412/AD5422 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled the output value will change at a rate limited by the output drive circuitry and the attached load. If the user wishes to reduce the slew rate this can be achieved by enabling the slew rate control feature.With the feature enabled via the SREN bit of the CONTROL register, (See Table 14) the output, instead of slewing directly between two values, will step digitally at a rate defined by two parameters accessible via the CONTROL register as shown in Table 14. The parameters are SR CLOCK and SR STEP. SR CLOCK defines the rate at which the digital slew will be updated. SR STEP defines by how much the output value will change at each update. Together both parameters AD5422 Step Size (LSBs) 1 2 4 8 16 32 64 128 Table 23. Slew Rate Update Clock Options MJD31C OR PBSS8110Z BOOST AD5412 Step Size (LSBs) 1/16 ⅛ ¼ ½ 1 2 4 8 Update Clock Frequency (Hz) 257732 198413 152439 131579 115741 69444 37594 25773 20161 16026 10288 8278 6897 5525 4237 3300 The time it will take for the output to slew over a given output range can be expressed as follows; SlewTime = OutputChange StepSize × UpdateClockFrequency × LSBSize Where: Slew Time is expressed in seconds Output Change is expressed in Amps for IOUT or Volts for VOUT When the slew rate control feature is enabled, all output changes will change at the programmed slew rate, for example if the CLEAR pin is asserted the output will slew to the clear value at the programmed slew rate. The output can be halted at its current value with a write to the CONTROL register. To avoid halting the output slew, the SLEW ACTIVE bit can be read to check that the slew has completed before writing to the AD5412/AD5422 registers. See Table 19.The update clock frequency for any given value will be the same for all output ranges, the step size however will vary across output ranges for a given value of step size as the LSB size will be different for each output range.Table 24 shows the range of programmable slew times for a full-scale change on any of the output ranges. The values were obtained using the Slew Time equation above. Rev. PrF | Page 31 of 38 AD5412/AD5422 Preliminary Technical Data Update Clock Frequency (Hz) Table 24. Programmable Slew Time values in seconds for a full-scale change on any output range. 257732 198413 152439 131579 115741 69444 37594 25773 20161 16026 10288 8278 6897 5525 4237 3300 1 0.25 0.33 0.43 0.50 0.57 0.9 1.7 2.5 3.3 4.1 6.4 7.9 9.5 12 15 20 2 0.13 0.17 0.21 0.25 0.28 0.47 0.87 1.3 1.6 2.0 3.2 4.0 4.8 5.9 7.7 9.9 4 0.06 0.08 0.11 0.12 0.14 0.24 0.44 0.64 0.81 1.0 1.6 2.0 2.4 3.0 3.9 5.0 8 0.03 0.04 0.05 0.06 0.07 0.12 0.22 0.32 0.41 0.51 0.80 1.0 1.2 1.5 1.9 2.5 IOUT FILTERING CAPACITORS (LFCSP PACKAGE) Two capacitors may be placed between the pins CAP1, CAP2 and AVDD as shown in Figure 62. Step Size (LSBs) 16 0.016 0.021 0.027 0.031 0.035 0.06 0.11 0.16 0.20 0.26 0.40 0.49 0.59 0.74 0.97 1.24 32 0.008 0.010 0.013 0.016 0.018 0.03 0.05 0.08 0.10 0.13 0.20 0.25 0.30 0.37 0.48 0.62 64 0.004 0.005 0.007 0.008 0.009 0.015 0.03 0.04 0.05 0.06 0.10 0.12 0.15 0.19 0.24 0.31 alternative to the Digital Slew Rate Control feature or in addition to it as a means of smoothing out the steps caused by the digital code increments. C1 C2 AVDD CAP1 C1 CAP2 AV DD C2 AVDD R3 CAP1 AD5412/ AD5422 128 0.0020 0.0026 0.0034 0.0039 0.0044 0.007 0.014 0.020 0.025 0.03 0.05 0.06 0.07 0.09 0.12 0.16 BOOST R2 CAP2 DAC IOUT 12.5K 40K AGND R1 Figure 62. IOUT Filtering Capacitors These two pins are only available on the LFCSP package. The capacitors form a filter on the current output circuitry as shown in Figure 63 reducing the bandwidth and the rate of change of the output current. These capacitors can be used as an Rev. PrF | Page 32 of 38 Figure 63. IOUT Filter Circuitry IOUT Preliminary Technical Data AD5412/AD5422 APPLICATIONS INFORMATION DRIVING INDUCTIVE LOADS IOUT When driving inductive or poorly defined loads connect a 0.01µF capacitor between IOUT and GND. This will ensure stability with loads beyond 50mH. There is no maximum capacitance limit. The capacitive component of the load may cause slower settling. The Digital Slew Rate Control feature may also prove useful in this situation. AD5412/ AD5422 +VSENSE VOUT -VSENSE TRANSIENT VOLTAGE PROTECTION The AD5412/AD5422 contains ESD protection diodes which prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. In order to protect the AD5412/AD5422 from excessively high voltage transients , external power diodes and a surge current limiting resistor is required, as shown in Figure 64. The constraint on the resistor value is that during normal operation the output level at IOUT must remain within its voltage compliance limit of AVDD – 2.5V and the two protection diodes and resistor must have appropriate power ratings. Further protection can be provided with Transient Voltage Suppressors or Transorbs, these are available as both unidirectional (protects against positive high voltage transients) and bidirectional (protects against both positive and negative high voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. It is recommended that all field connected nodes are protected. AVDD AVDD AD5412/ AD5422 IOUT RP AGND IOUT / VOUT Figure 65. Connecting IOUT and VOUT to one connector When the AD5412/AD5422 is configured for a voltage output the IOUT pin will be in tri-state, when configured for a current output the VOUT pin will be in tri-state, the function of the buffer is to prevent current leakage to ground through the +VSENSE pin when the current output is enabled, the +VSENSE pin is internally connected to AGND through a resistance of approx. 40kΩ. GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur. The iCoupler® family of products from Analog Devices provides voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5412/AD5422 make it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 66 shows a 4-channel isolated interface to the AD5412/AD5422 using an ADuM1400. For further information, visit http://www.analog.com/icouplers. RLOAD Controller Serial Clock Out Figure 64. Output Transient Voltage Protection Serial Data Out SINGLE CONNECTOR FOR IOUT AND VOUT Typically in analog output modules that facilitate both current and voltage outputs there is a seperate connector for each current output and for each voltage output even though either the voltage output or the current output can be used at any one time, this results in a redundant connector. For instance in an 8 channel current and voltage output module there will be 16 connectors and only 8 of these will be in use at any one time resulting in 8 redundant connectors. The AD5412/AD5422 can be configured with the IOUT and VOUT pins connected together and to one connector, thus removing the redundant connector and allowing for a reduced sized connector block. Figure 65 shows that with an external buffer amplifier the AD5412/AD5422 can be configured with a single output connector for current and voltage output. SYNC Out Control out ADuM1400 * VIA VIB VIC VID ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE VOA VOB VOC VOD To SCLK To SDIN To LATCH To CLEAR *ADDITIONAL PINS OMITTED FOR CLARITY Figure 66. Isolated Interface MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5412/AD5422 is via a serial bus that uses protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a latch signal. The AD5412/AD5422 require a 24-bit dataword with data valid on the rising edge of SCLK. Rev. PrF | Page 33 of 38 AD5412/AD5422 Preliminary Technical Data For all interfaces, the DAC output update is initiated on the rising edge of LATCH. The contents of the registers can be read using the readback function. LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5412/AD5422 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5412/AD5422 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5412/AD5422 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5412/AD5422 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feed through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. Rev. PrF | Page 34 of 38 Preliminary Technical Data AD5412/AD5422 THERMAL AND SUPPLY CONSIDERATIONS The AD5412/AD5422 is designed to operate at a maximum junction temperature of 125°C. It is important that the device is not operated under conditions that will cause the junction temperature to exceed this value . Excessive junction temperature can occur if the AD5412/AD5422 is operated from the maximum AVDD and driving the maximum current (24mA) directly to ground. In this case the ambient temperature should be controlled or AVDD should be reduced. The conditions will depend on the device package. 2.5 At maximum ambient temperature of 85°C the 24-lead TSSOP package can dissipate 950mW and the 40-lead LFCSP package can dissipate 1.42W. To ensure the junction temperature does not exceed 125°C while driving the maximum current of 24mA directly into ground (also adding an on-chip current of 3mA), AVDD should be reduced from the maximum rating to ensure the package is not required to dissipate more power than stated above. See Table 25, Figure 67 and Figure 68. 45 TSSOP LFCSP 2 41 39 Supply Voltage (V) Power Dissipation (W) TSSOP LFCSP 43 1.5 1 37 35 33 31 0.5 29 27 0 25 40 45 50 55 60 65 70 Ambient Temperature (°C) 75 80 85 25 35 45 55 65 75 85 Ambient Temperature (°C) Figure 67. Maximum Power Dissipation Vs Ambient Temperature Figure 68. Maximum Supply Voltage Vs Ambient Temperature Table 25. Thermal and Supply considerations for each package TSSOP Maximum allowed power dissipation when operating at an ambient temperature of 85°C Maximum allowed ambient temperature when operating from a supply of 40V and driving 24mA directly to ground. Maximum allowed supply voltage when operating at an ambient temperature of 85°C and driving 24mA directly to ground. TJ max − TA Θ JA LFCSP = 125 − 85 TJ max − TA = 950 mW Θ JA 42 ( ) TJ max − PD × Θ JA = 125 − 40 × 0.027 × 42 = 79°C TJ max − TA AI DD × Θ JA = 125 − 85 0.027 × 42 = 35V Rev. PrF | Page 35 of 38 = 125 − 85 = 1.42W 28 ( ) TJ max− PD × Θ JA = 125 − 40 × 0.027 × 28 = 85°C TJ max − TA AI DD × Θ JA = 125 − 85 0.027 × 28 = 53V AD5412/AD5422 Preliminary Technical Data OUTLINE DIMENSIONS 5.02 5.00 4.95 7.90 7.80 7.70 24 13 4.50 4.40 4.30 3.25 3.20 3.15 EXPOSED PAD (Pins Up) 6.40 BSC 1 12 BOTTOM VIEW TOP VIEW 1.05 1.00 0.80 0.15 0.05 SEATING PLANE 0.10 COPLANARITY 8° 0° 0.20 0.09 0.30 0.19 0.65 BSC 0.75 0.60 0.45 050806-A 1.20 MAX COMPLIANT TO JEDEC STANDARDS MO-153-ADT Figure 69. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters 6.00 BSC SQ 0.60 MAX 0.60 MAX 31 30 PIN 1 INDICATOR TOP VIEW 0.50 BSC 5.75 BCS SQ 0.50 0.40 0.30 12° MAX 40 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOT TOM VIEW) 21 20 10 11 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 70. 40-Lead Lead Frame Chip Scale Package (CP-40) Dimensions shown in millimeters Rev. PrF | Page 36 of 38 101306-A 1.00 0.85 0.80 PIN 1 INDICATOR Preliminary Technical Data AD5412/AD5422 ORDERING GUIDE Model AD5412AREZ AD5412BREZ AD5412ACPZ AD5412BCPZ AD5422AREZ AD5422BREZ AD5422ACPZ AD5422BCPZ Resolution 12 Bits 12 Bits 12 Bits 12 Bits 16 Bits 16 Bits 16 Bits 16 Bits Temperature Range -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C Rev. PrF | Page 37 of 38 Package Description 24 Lead TSSOP_EP 24 Lead TSSOP_EP 40 Lead LFCSP 40 Lead LFCSP 24 Lead TSSOP_EP 24 Lead TSSOP_EP 40 Lead LFCSP 40 Lead LFCSP Package Option RE-24 RE-24 CP-40 CP-40 RE-24 RE-24 CP-40 CP-40 AD5412/AD5422 Preliminary Technical Data NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06996-0-4/08(PrF) Rev. PrF | Page 38 of 38