[AK5357] AK5357 24Bit 96kHz ΔΣ ADC GENERAL DESCRIPTION The AK5357 is a stereo A/D Converter with wide sampling rate of 4kHz ∼ 96kHz and is suitable for multimedia audio system. The AK5357 achieves high accuracy and low cost by using Enhanced dual bit ΔΣ techniques. The AK5357 requires no external components because the analog inputs are single-ended. The audio interface has two formats (MSB justified, I2S) and can correspond to many systems like Karaoke, surround. FEATURES Stereo ΔΣ ADC On-Chip Digital Anti-Alias Filtering Single-ended Input Digital HPF for DC-Offset cancel S/(N+D): 88dB@5V, 86dB@3V for 48kHz DR: 102dB@5V, 100dB@3V for 48kHz S/N: 102dB@5V, 100dB@3V for 48kHz Sampling Rate Ranging from 4kHz to 96kHz Master Clock: 256fs/384fs/512fs/768fs (4kHz ∼ 48kHz) 256fs/384fs (48kHz ∼ 96kHz) Input level: TTL/CMOS selectable Master / Slave Mode Audio Interface: 24bit MSB justified / I2S selectable Power Supply: 2.7 ∼ 5.5V Ta = −20 ∼ 85°C (ET), −40 ∼ 85°C (VT), −40 ∼ 105°C (KT) Small 16pin TSSOP Package AK5381 Pin-compatible VA AGND MCLK VD DGND Clock Divider AINL AINR VCOM ΔΣ Modulator Decimation Filter ΔΣ Modulator Decimation Filter LRCK SCLK Serial I/O Interface Voltage Reference CKS2 CKS1 CKS0 PDN SDTO DIF 2009/03 MS0294-E-03 -1- [AK5357] ■ Ordering Guide AK5357ET AK5357VT AK5357KT AKD5357 −20 ∼ +85°C 16pin TSSOP (0.65mm pitch) −40 ∼ +85°C 16pin TSSOP (0.65mm pitch) −40 ∼ +105°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK5357 ■ Pin Layout AINR 1 16 CKS0 AINL 2 15 CKS2 CKS1 3 14 DIF VCOM 4 13 PDN AGND 5 12 SCLK VA 6 11 MCLK VD 7 10 LRCK DGND 8 9 SDTO Top View ■ Compatibility with AK5353 and AK5381 S/(N+D) DR Master Mode HPF OFF TTL Level Mode VIH@TTL Level Mode VA (Analog Supply) VD (Digital Supply) Pin #3 Pin #15 Pin #16 AK5353 84dB 96dB Not Available Not Available 4kHz to 96kHz 2.2V 2.7 to 5.5V@fs=48kHz 4.5 to 5.5V@fs=96kHz 4.5 to 5.5V@fs=96kHz VREF TTL TST AK5381 96dB 106dB Available Available 4kHz to 48kHz 2.4V AK5357 88dB 102dB Available Available 4kHz to 96kHz 2.2V 4.5 to 5.5V@fs=48/96kHz 2.7 to 5.5V@fs=48/96kHz 3.0 to 5.5V@fs=96kHz CKS1 CKS2 CKS0 2.7 to 5.5V@fs=96kHz CKS1 CKS2 CKS0 2009/03 MS0294-E-03 -2- [AK5357] PIN / FUNCTION No. Pin Name I/O 1 2 3 AINR AINL CKS1 I I I 4 VCOM O 5 6 7 8 AGND VA VD DGND - 9 SDTO O 10 LRCK I/O 11 MCLK I 12 SCLK I/O 13 PDN I 14 DIF I 15 16 CKS2 CKS0 I I Function Rch Analog Input Pin Lch Analog Input Pin Mode Select 1 Pin Common Voltage Output Pin, VA/2 Bias voltage of ADC input. Analog Ground Pin Analog Power Supply Pin, 2.7 ∼ 5.5V Digital Power Supply Pin, 2.7 ∼ 5.5V Digital Ground Pin Audio Serial Data Output Pin “L” Output at Power-down mode. Output Channel Clock Pin “L” Output in Master Mode at Power-down mode. Master Clock Input Pin Audio Serial Data Clock Pin “L” Output in Master Mode at Power-down mode. Power Down Mode Pin “H”: Power up, “L”: Power down Audio Interface Format Pin “H” : 24bit I2S Compatible, “L” : 24bit MSB justified Mode Select 2 Pin Mode Select 0 Pin Note: All digital input pins should not be left floating. ■ Handling of Unused Pin The unused input pins should be processed appropriately as below. Classification Analog Pin Name AINL AINR Setting This pin should be open. This pin should be open. 2009/03 MS0294-E-03 -3- [AK5357] ABSOLUTE MAXIMUM RATINGS (AGND=DGND=0V; Note 1) Parameter Analog Power Supplies: Digital |AGND – DGND| (Note 1) Input Current, Any Pin Except Supplies Analog Input Voltage (AINL, AINR, CKS1 pins) Digital Input Voltage (All digital input pins except CKS1 pin) AK5357ET Ambient Temperature (powered applied) AK5357VT AK5357KT Storage Temperature Symbol VA VD ΔGND IIN VINA VIND Ta Ta Ta Tstg min −0.3 −0.3 −0.3 −0.3 −20 −40 −40 −65 max 6.0 6.0 0.3 ±10 VA+0.3 VD+0.3 85 85 105 150 Units V V V mA V V °C °C °C °C Note 1. All voltages with respect to ground. Note 2. AGND and DGND must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND=DGND=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital Symbol VA VD min 2.7 2.7 typ 5.0 5.0 max 5.5 VA Units V V Note 1. All voltages with respect to ground. Note 3. The power up sequence between VA and VD is not critical. WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. 2009/03 MS0294-E-03 -4- [AK5357] ANALOG CHARACTERISTICS (Ta=25°C; VA=VD=5.0V; AGND=DGND=0V; fs=48kHz, 96kHz; SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Resolution 24 Bits AK5357ET 2.7 3.0 3.3 Vpp Input Voltage (Note 4) VA=5V fs=48kHz AK5357VT 2.85 3.0 3.15 Vpp fs=96kHz 2.7 3.0 3.3 VA=3V 1.8 Vpp S/(N+D) (−1dBFS) VA=5V fs=48kHz 78 88 dB fs=96kHz 86 dB VA=3V fs=48kHz 86 dB fs=96kHz 84 dB DR (−60dBFS) VA=5V fs=48kHz, A-weighted 94 102 dB fs=96kHz 88 97 dB VA=3V fs=48kHz, A-weighted 100 dB fs=96kHz 95 dB VA=5V fs=48kHz, A-weighted S/N 94 102 dB fs=96kHz 88 97 dB VA=3V fs=48kHz, A-weighted 100 dB fs=96kHz 95 dB Input Resistance fs=48kHz 13 20 kΩ fs=96kHz 9 14 kΩ Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0.1 0.5 dB Gain Drift 100 ppm/°C Power Supply Rejection (Note 5) 50 dB Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) mA 17 11 VA mA 5 3 VD (fs=48kHz) (Note 6) mA 9 6 VD (fs=96kHz) (Note 7) Power down mode (PDN pin = “L”) (Note 8) μA 100 10 VA+VD Note 4. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage. Vin = 0.6 x VA (Vpp). Note 5. PSR is applied to VA and VD with 1kHz, 50mVpp. Note 6. VD=2mA@3V Note 7. VD=4mA@3V Note 8. All digital input pins are held VD or DGND. 2009/03 MS0294-E-03 -5- [AK5357] FILTER CHARACTERISTICS (fs=48kHz) (Ta=Tmin ∼ Tmax; VA=VD=2.7 ∼ 5.5V) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 9) ±0.1dB PB 0 −0.2dB 20.0 −3.0dB 23.0 Stopband SB 28 Passband Ripple PR Stopband Attenuation SA 68 Group Delay Distortion ΔGD 0 Group Delay (Note 10) GD 16 ADC Digital Filter (HPF): Frequency Response (Note 9) −3dB FR 1.0 −0.1dB 6.5 FILTER CHARACTERISTICS (fs=96kHz) (Ta=Tmin ∼ Tmax; VA=VD=2.7 ∼ 5.5V) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 9) ±0.1dB PB 0 −0.2dB 40.0 −3.0dB 46.0 Stopband SB 56 Passband Ripple PR Stopband Attenuation SA 68 Group Delay Distortion ΔGD 0 Group Delay (Note 10) GD 16 ADC Digital Filter (HPF): Frequency Response (Note 9) −3dB FR 2.0 −0.1dB 13.0 max Units 18.9 - kHz kHz kHz kHz dB dB μs 1/fs ±0.04 Hz Hz max Units 37.8 - kHz kHz kHz kHz dB dB μs 1/fs ±0.04 Hz Hz Note 9. The passband and stopband frequencies scale with fs. For example, PB=18.9kHz@±0.1dB is 0.39375 × fs. Note 10. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC. 2009/03 MS0294-E-03 -6- [AK5357] DC CHARACTERISTICS (CMOS Level Mode) (Ta=Tmin ∼ Tmax; VA=VD=2.7 ∼ 5.5V) Parameter Symbol min typ High-Level Input Voltage VIH 70%VD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=−1mA) VOH VD−0.5 Low-Level Output Voltage (Iout=1mA) VOL Input Leakage Current Iin - max 30%VD 0.5 ±10 Units V V V V μA DC CHARACTERISTICS (TTL Level Mode) (Ta=Tmin ∼ Tmax; VA=VD=4.5 ∼ 5.5V) Parameter Symbol min typ 70%VD VIH High-Level Input Voltage (CKS2-0 pins) 2.2 VIH (All pins except CKS2-0 pins) VIL Low-Level Input Voltage (CKS2-0 pins) VIL (All pins except CKS2-0 pins) High-Level Output Voltage (Iout=−1mA) VOH VD−0.5 Low-Level Output Voltage (Iout=1mA) VOL Input Leakage Current Iin - max 30%VD 0.8 0.5 ±10 Units V V V V V V μA 2009/03 MS0294-E-03 -7- [AK5357] SWITCHING CHARACTERISTICS (Ta=Tmin ∼ Tmax; VA=VD=2.7 ∼ 5.5V; CL=20pF) Parameter Symbol min Master Clock Timing 1.024 fCLK Frequency 0.4/fCLK tCLKL Pulse Width Low 0.4/fCLK tCLKH Pulse Width High LRCK Frequency fs 4 Duty Cycle Slave mode 45 Master mode Audio Interface Timing Slave mode 160 tSCK SCLK Period 65 tSCKL SCLK Pulse Width Low 65 tSCKH Pulse Width High 30 tLRSH LRCK Edge to SCLK “↑” (Note 11) 30 tSHLR SCLK “↑” to LRCK Edge (Note 11) 2 tLRS LRCK to SDTO (MSB) (Except I S mode) tSSD SCLK “↓” to SDTO Master mode fSCK SCLK Frequency dSCK SCLK Duty −20 tMSLR SCLK “↓” to LRCK −20 tSSD SCLK “↓” to SDTO Reset Timing PDN Pulse Width (Note 12) PDN “↑” to SDTO valid at Slave Mode (Note 13) PDN “↑” to SDTO valid at Master Mode (Note 13) tPD tPDV tPDV typ max Units 36.864 MHz ns ns 96 55 kHz % % 50 35 35 ns ns ns ns ns ns ns 20 35 Hz % ns ns 64fs 50 150 4132 4129 ns 1/fs 1/fs Note 11. SCLK rising edge must not occur at the same time as LRCK edge. Note 12. The AK5357 can be reset by bringing the PDN pin = “L”. Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”. 2009/03 MS0294-E-03 -8- [AK5357] ■ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tSCK VIH SCLK VIL tSCKH tSCKL Clock Timing VIH LRCK VIL tSHLR tLRSH VIH SCLK VIL tLRS tSSD SDTO 50%VD Audio Interface Timing (Slave mode) 2009/03 MS0294-E-03 -9- [AK5357] LRCK 50%VD tMSLR dSCK SCLK 50%VD tSSD SDTO 50%VD Audio Interface Timing (Master mode) VIH PDN VIL tPDV SDTO 50%VD tPD PDN VIL Power Down & Reset Timing 2009/03 MS0294-E-03 - 10 - [AK5357] OPERATION OVERVIEW ■ System Clock MCLK (256fs/384fs/512fs), SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF), the input level (CMOS or TTL) and master/slave are selected by CKS2-0 pins as shown in Table 2. All external clocks (MCLK, SCLK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not provided, the AK5357 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5357 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be provided unless the PDN pin = “L”. fs 32kHz 44.1kHz 48kHz 96kHz MCLK 256fs 384fs 512fs 768fs 8.192MHz 12.288MHz 16.384MHz 24.576MHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 12.288MHz 18.432MHz 24.576MHz 36.864MHz 24.576MHz 36.864MHz N/A N/A Table 1. System Clock Example (N/A: Not available) CKS2 CKS1 CKS0 Input Level L L L CMOS L L H CMOS L L H H L H CMOS CMOS H L L TTL H H H L H H H L H CMOS CMOS HPF Master/Slave MCLK 256/384fs (∼ 96kHz) ON Slave 512/768fs (∼ 48kHz) 256/384fs (∼ 96kHz) OFF Slave 512/768fs (∼ 48kHz) ON Master 256fs (∼ 96kHz) ON Master 512fs (∼ 48kHz) 256/384fs (∼ 96kHz) ON Slave 512/768fs (∼ 48kHz) Reserved ON Master 384fs (∼ 96kHz) ON Master 768fs (∼ 48kHz) Table 2. Mode Select SCLK ≥ 48fs or 32fs ≥ 48fs or 32fs 64fs 64fs ≥ 48fs or 32fs 64fs 64fs Note: SDTO outputs 16bit data at SCLK=32fs. ■ Audio Interface Format Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK frequency fixed to 1fs. Mode 0 1 DIF pin L H SDTO LRCK SCLK 24bit, MSB justified H/L ≥ 48fs or 32fs 24bit, I2S Compatible L/H ≥ 48fs or 32fs Table 3. Audio Interface Format Figure Figure 1 Figure 2 2009/03 MS0294-E-03 - 11 - [AK5357] LRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 SCLK(64fs) SDTO(o) 23 22 4 3 2 1 0 23 22 4 3 2 1 0 23 23:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 SCLK(64fs) SDTO(o) 23 22 4 3 2 1 0 23 22 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing ■ Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz) and scales with sampling rate (fs). HPF is controlled by CKS2-0 pins (Table 2). If HPF setting (ON/OFF) is changed when the AK5357 is in operation, click noise occurs by changing DC offset. It is recommended that HPF setting is changed when the PDN pin = “L”. 2009/03 MS0294-E-03 - 12 - [AK5357] ■ Power down The AK5357 is placed in the power-down mode by bringing the PDN pin “L” and the digital filter is also reset at the same time. This reset should always be executed after power-up. In the power-down mode, the VCOM is the same voltage as AGND. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode. During initialization, the ADC digital output data of both channels are forced to a 2’s complement “0”. The ADC outputs settle in the value corresponding to the input signals after the initialization was completed (Settling approximately takes the group delay time). (1) PDN Internal State Normal Operation Power-down Initialize Normal Operation GD (2) GD A/D In (Analog) A/D Out (Digital) Clock In MCLK,LRCK,SCLK (3) “0”data Idle Noise “0”data Idle Noise (4) Notes: (1) 4132/fs in slave mode and 4129/fs in master mode. (2) Digital output corresponding to analog input has the group delay (GD). (3) A/D output is “0” data at the power-down state. (4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5357 should be in the power-down state. Figure 3. Power-down/up sequence example ■ System Reset The AK5357 should be reset once by bringing the PDN pin “L” after power-up. In slave mode, the internal timing starts clocking by the rising edge (falling edge at mode 1) of LRCK after exiting from reset and power down state by MCLK. The AK5357 is power down state until LRCK is input. In master mode, the internal timing starts when MCLK is input. 2009/03 MS0294-E-03 - 13 - [AK5357] SYSTEM DESIGN Figure 4 shows the system connection diagram. The evaluation board demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Rch In 10u + Lch In + 10u 0.47u 1 AINR CKS0 16 2 AINL CKS2 15 3 CKS1 DIF 14 4 VCOM PDN 13 5 Analog 5V + 10u 0.1u + 10u 0.1u AK5357 AGND Mode Control Reset SCLK 12 6 VA MCLK 11 7 VD LRCK 10 8 DGND SDTO 9 Audio Controller Analog Ground System Ground Note: - AGND and DGND of the AK5357 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. - The CKS1 pin should be connected to VA or AGND. Figure 4. Typical Connection Diagram Digital Ground Analog Ground System Controller 1 AINR CKS0 16 2 AINL CKS2 15 3 CKS1 4 VCOM 5 AGND SCLK 12 6 VA MCLK 11 7 VD LRCK 10 8 DGND SDTO DIF 14 AK5357 PDN 13 9 Figure 5. Ground Layout Note: - AGND and DGND must be connected to the same analog ground plane. 2009/03 MS0294-E-03 - 14 - [AK5357] 1. Grounding and Power Supply Decoupling The AK5357 requires careful attention to power supply and grounding arrangements. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. AGND and DGND of the AK5357 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5357 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference The voltage input to VA sets the analog input range. VCOM are 50%VA and normally connected to AGND with a 0.1μF ceramic capacitor. A ceramic capacitor 0.47μF attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from these pins. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5357. 3. Analog Inputs The ADC inputs are single-ended and internally biased to the common voltage (50%VA) with 20kΩ (typ@fs=48kHz) resistance. The input signal range scales with the supply voltage and nominally 0.6xVA Vpp (typ). The ADC output data format is 2’s complement. The DC offset is removed by the internal HPF. The AK5357 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK5357 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. 2009/03 MS0294-E-03 - 15 - [AK5357] PACKAGE 16pin TSSOP (Unit: mm) 1.1 (max) *5.0±0.1 16 9 8 1 0.13 M 6.4±0.2 *4.4±0.1 A 0.65 0.22±0.1 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate 2009/03 MS0294-E-03 - 16 - [AK5357] MARKING (AK5357ET) AKM 5357ET XXYYY 1) 2) 3) Pin #1 indication Date Code: XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code: 5357ET 2009/03 MS0294-E-03 - 17 - [AK5357] MARKING (AK5357VT) AKM 5357VT XXYYY 4) 5) 6) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 5357VT 2009/03 MS0294-E-03 - 18 - [AK5357] MARKING (AK5357KT) AKM 5357KT XXYYY 7) 8) 9) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 5357KT 2009/03 MS0294-E-03 - 19 - [AK5357] REVISION HISTORY Date (YY/MM/DD) 04/2/24 06/01/11 Revision 00 01 Reason First Edition Specification Addition Page Contents P.2 Ordering Guide AK5357ET was added. MARKING AK5357ET was added. ANALOG CHARACTERISTICS of AK5357VT Input Voltage VA=5V; fs=48kHz 2.7V(min) →2.85V(min) 3.3V(max) → 3.15V(max) AK5357KT (-40 ∼ 105°C) was added. P.18 07/11/22 02 Specification Change 09/03/27 03 Product Addition P5 IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. 2009/03 MS0294-E-03 - 20 -