LF PA K 56D BUK7K6R8-40E Dual N-channel 40 V, 6.8 mΩ standard level MOSFET 6 November 2013 Product data sheet 1. General description Dual standard level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 2. Features and benefits • • • • • Dual MOSFET Q101 compliant Repetitive avalanche rated Suitable for thermally demanding environments due to 175 °C rating True standard level gate with VGS(th) of greater than 1 V at 175 °C 3. Applications • • • • 12 V Automotive systems Motors, lamps and solenoid control Transmission control Ultra high performance power switching 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 40 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 1 - - 40 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 64 W VGS = 10 V; ID = 20 A; Tj = 25 °C; - 5.8 6.8 mΩ - 9.1 - nC Static characteristics FET1 and FET2 RDSon drain-source on-state resistance Fig. 12 Dynamic characteristics FET1 and FET2 QGD gate-drain charge ID = 20 A; VDS = 32 V; VGS = 20 V; Tj = 25 °C; Fig. 14; Fig. 15 Scan or click this QR code to view the latest information for this product BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 6 D2 drain2 7 D1 drain1 8 D1 drain1 Simplified outline 8 7 6 Graphic symbol 5 D1 D1 S1 D2 D2 G1 S2 G2 mbk725 1 2 3 4 LFPAK56D (SOT1205) 6. Ordering information Table 3. Ordering information Type number Package BUK7K6R8-40E Name Description Version LFPAK56D Plastic single ended surface mounted package (LFPAK56D); 8 leads SOT1205 7. Marking Table 4. Marking codes Type number Marking code BUK7K6R8-40E 76E840 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 40 V VDGR drain-gate voltage RGS = 20 kΩ; Tj ≥ 25 °C; Tj ≤ 175 °C - 40 V VGS gate-source voltage Tj ≤ 175 °C; DC -20 20 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 1 - 40 A Tmb = 100 °C; VGS = 10 V; Fig. 1 - 40 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4 - 276 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 64 W BUK7K6R8-40E Product data sheet All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 2 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET Symbol Parameter Tstg Conditions Min Max Unit storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode FET1 and FET2 IS source current Tmb = 25 °C - 40 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 276 A - 130 mJ Avalanche Ruggedness FET1 and FET2 EDS(AL)S non-repetitive drain-source avalanche energy [1] [2] ID = 40 A; Vsup ≤ 40 V; VGS = 10 V; [1][2] Tj(init) = 25 °C; Fig. 3 Refer to application note AN10273 for further information Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 003aaj739 100 03aa16 120 ID (A) Pder (%) 80 80 60 40 (1) 40 20 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 Continuous drain current as a function of mounting base temperature BUK7K6R8-40E Product data sheet Fig. 2. 0 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 6 November 2013 50 © NXP N.V. 2013. All rights reserved 3 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET 003aaj673 103 IAL (A) 102 (1) 10 (2) 1 (3) 10-1 10-2 10-3 Fig. 3. 10-2 10-1 1 tAL (ms) 10 Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2 003aaj738 103 ID (A) Limit RDSon = V DS / ID 102 tp =10 µ s 100 µ s 10 1 ms DC 1 10 ms 100 ms 10-1 10-1 Fig. 4. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 2.36 K/W BUK7K6R8-40E Product data sheet All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 4 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient Minimum footprint; mounted on a printed circuit board - 95 - K/W 003aaj748 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 0.05 10-1 0.02 P 10-2 tp T δ= single shot tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 t T 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 2.4 3 4 V 1 - - V - - 4.5 V VDS = 40 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 20 A; Tj = 25 °C; - 5.8 6.8 mΩ - 11 13.4 mΩ Static characteristics FET1 and FET2 V(BR)DSS VGS(th) Fig. 10; Fig. 11 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 10; Fig. 11 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 10; Fig. 11 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 12 VGS = 10 V; ID = 20 A; Tj = 175 °C; Fig. 12; Fig. 13 BUK7K6R8-40E Product data sheet All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 5 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET Symbol Parameter Conditions Min Typ Max Unit Dynamic characteristics FET1 and FET2 QG(tot) total gate charge ID = 20 A; VDS = 32 V; VGS = 10 V; - 28.9 - nC QGS gate-source charge Tj = 25 °C; Fig. 14; Fig. 15 - 7 - nC QGD gate-drain charge ID = 20 A; VDS = 32 V; VGS = 20 V; - 9.1 - nC Tj = 25 °C; Fig. 14; Fig. 15 Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 1460 1947 pF Coss output capacitance Tj = 25 °C; Fig. 16 - 324 389 pF Crss reverse transfer capacitance - 197 270 pF td(on) turn-on delay time VDS = 32 V; RL = 1.6 Ω; VGS = 10 V; - 8.9 - ns tr rise time RG(ext) = 5 Ω; Tj = 25 °C; ID = 20 A - 15.4 - ns td(off) turn-off delay time - 19.4 - ns tf fall time - 16.5 - ns Source-drain diode FET1 and FET2 VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.78 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 20.6 - ns Qr recovered charge VDS = 20 V; Tj = 25 °C - 11.3 - nC 003aaj729 60 003aaj731 40 gfs (S) 50 RDSon (mΩ ) 30 40 30 20 20 10 10 0 Fig. 6. 0 10 20 30 ID (A) 0 40 Forward transconductance as a function of drain current; typical values BUK7K6R8-40E Product data sheet Fig. 7. 0 4 12 16 VGS (V) 20 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 6 November 2013 8 © NXP N.V. 2013. All rights reserved 6 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET 003aaj732 50 6.5 ID (A) 40 7 ID (A) 5.5 6 003aaj730 250 5 200 VGS (V) = 4.5 30 150 20 100 4 10 Tj = 175 °C 50 Tj = 25 ° C 3.5 0 Fig. 8. 0 1 2 3 VDS(V) 0 4 Output characteristics: drain current as a Fig. 9. function of drain-source voltage; typical values 003aah028 10-1 ID (A) 0 2 4 min typ max max 3 typ 10-4 2 min 10-5 1 10-6 0 2 4 VGS (V) 0 -60 6 Fig. 10. Sub-threshold drain current as a function of gate-source voltage BUK7K6R8-40E Product data sheet 10 12 VGS (V) 003aah027 4 10-3 8 Transfer characteristics: drain current as a function of gate-source voltage; typical values 5 VGS(th) (V) 10-2 6 0 60 120 T j (°C) 180 Fig. 11. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 7 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET 003aaj736 50 RDSon (mΩ ) 40 4 a 4.5 30 003aaj813 2 1.6 1.2 V GS (V) = 5 0.8 20 5.5 6 10 6.5 7 10 0 0 10 20 30 0.4 40 ID (A) 0 -60 50 Fig. 12. Drain-source on-state resistance as a function of drain current; typical values 0 60 120 VGS (V) ID 180 Fig. 13. Normalized drain-source on-state resistance factor as a function of junction temperature 003aaj733 10 VDS Tj (°C) VGS(pl) 32 V 8 VDS =14 V 6 VGS(th) VGS 4 QGS1 QGS2 QGS QGD QG(tot) 2 003aaa508 0 Fig. 14. Gate charge waveform definitions 0 10 20 QG (nC) 30 Fig. 15. Gate-source voltage as a function of gate charge; typical values BUK7K6R8-40E Product data sheet All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 8 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET 003aaj734 104 003aaj735 40 IS (A) C (pF) 10 Ciss 30 Coss 20 3 Crss 102 Tj = 175 °C 10 10 10-1 1 10 VDS (V) 0 102 0 0.3 Tj = 25 °C 0.6 0.9 VSD (V) 1.2 Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values BUK7K6R8-40E Product data sheet All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 9 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET 11. Package outline Plastic single ended surface mounted package (LFPAK56D); 8 leads E A SOT1205 A b1 c1 L1 mounting base D H D1 D2 L 1 2 3 e b (8x) 4 w X c A E1 E2 A1 C θ Lp detail X 0 2.5 A max 1.05 nom min mm 5 mm scale Dimensions Unit y C c c1 D(1) D1(1) A1 b b1 0.1 0.50 4.4 0.25 0.30 4.70 0.0 0.35 4.1 0.19 0.24 4.45 4.8 D2 (ref) 3.5 E(1) E1(1) 5.30 1.8 4.95 1.6 E2 0.85 e 1.27 H L L1 Lp 6.2 1.3 0.55 0.85 5.9 0.8 0.30 0.40 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version References IEC JEDEC JEITA w y θ 0.25 0.1 8° 0° sot1205_po European projection Issue date 13-02-19 13-02-21 SOT1205 Fig. 18. Package outline LFPAK56D (SOT1205) BUK7K6R8-40E Product data sheet All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 10 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Preview — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. 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Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 11 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK7K6R8-40E Product data sheet All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 12 / 13 BUK7K6R8-40E NXP Semiconductors Dual N-channel 40 V, 6.8 mΩ standard level MOSFET 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP N.V. 2013. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 6 November 2013 BUK7K6R8-40E Product data sheet All information provided in this document is subject to legal disclaimers. 6 November 2013 © NXP N.V. 2013. All rights reserved 13 / 13