CDP1871A,
CDP1871AC
REFERENCE APP NOTE 7374
CMOS Keyboard Encoder
August 1996
Features
Description
• Directly Interfaces with CDP1800-Series Microprocessor
The CDP1871A is a keyboard encoder designed to
directly interface between a CDP1800-series microprocessor and a mechanical keyboard array, providing
up to 53 ASCII coded keys and 32 HEX coded keys,
as shown in the system diagram (Figure 1).
• Low Power Dissipation
• Three-State Outputs
• Scans and Generates Code for 53 Key ASCII Keyboard Plus
32 HEX Keys (SPST Mechanical Contact Switches)
• Shift, Control, and Alpha Lock Input
• RC-Controlled Debounce Circuitry
• Single Supply 4V to 10.5V . . . . . . . . . . . . . (CDP1871A)
4V to 6.5V . . . . . . . . . . . . . (CDP1871AC)
• N-Key Lockout
Ordering Information
PACKAGE
TEMP. RANGE
PDIP
-40oC to +85oC CDP1871ACE
PLCC
-40oC to +85oC CDP1871ACQ
SBDIP
-40oC
Burn-In
to
+85oC
5V
CDP1871ACD
CDP1871ACDX
10V
PKG.
NO.
CDP1871AE E40.6
-
N44.65
The keyboard may consist of simple single-pole
single-throw (SPST) mechanical switches. Inputs are
provided for alpha-lock, control, and shift functions,
allowing 160 unique codes. An external R-C input is
available for user-selectable debounce times. The Nkey lock-out feature prevents unwanted key codes if
two or more keys are pressed simultaneously.
The CDP1871A and CDP1871AC are functionally
identical. They differ in that the CDP1871A has a
recommended operating voltage range of 4V to 10.5V,
and the CDP1871AC has a recommended operating
voltage range 4V to 6.5V. These types are supplied in
40 lead dual-in-line ceramic packages (D suffix), and
40 lead dual-in-line plastic packages (E suffix), and 44
lead plastic chip-carrier packages (Q suffix).
CDP1871AD D40.6
-
D40.6
Pinouts
D1
VDD
SHIFT
6
5
4
3
2
1
44 43 42 41 40
NC
D2
ALPHA
D3
DEBOUNCE
NC
D5
7
39
RPT
D6
8
38
TPB
D7
9
37
DA
D8
10
36
BUS 7
D9
11
35
BUS 6
D10
12
34
BUS 5
D11
13
33
BUS 4
S1
14
32
BUS 3
S2
15
31
BUS 2
S3
16
30
BUS 1
S4
17
29
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-66
NC
BUS 0
CS4
CS3
CS2
CS1
VSS
S8
18 19 20 21 22 23 24 25 26 27 28
S7
VDD
SHIFT
CONTROL
ALPHA
DEBOUNCE
RTP
TPB
DA
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0
CS4
CS3
CS2
CS1
D4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
S6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
S5
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
S1
S2
S3
S4
S5
S6
S7
S8
VSS
CONTROL
44 LEAD PLCC
(Q Suffix) TOP VIEW
40 LEAD PDIP, CERDIP
TOP VIEW
File Number
1374.2
CDP1871A, CDP1871AC
VDD
0.1µF
100K
36
40
DEBOUNCE
21
N0-N2
CONTROL
23
24
MRD
34
TPB
CDP1800-SERIES
CPU
11
CS1,
CS2,
CS3
D11
CS4
TPB
UP TO 11 SETS
OF 8 SWITCHES EACH
CDP1871A
VDD
SHIFT
39
CONTROL
38
1
SHIFT
D1
CONTROL
ALPHA LOCK
37
ALPHA
NORMAL
BUS0-BUS7
BUS0-BUS7
25
S1
S2
S3
S4
S5
S6
S7
S8
12
13
14
15
16
17
18
19
32
8 BIT DATA BUS
FIGURE 1. TYPICAL CDP1800 SERIES MICROPROCESSOR SYSTEM USING THE CDP1871A
CS1 21
CS
SCAN CLOCK
CS2 22
THREE-STAGE
SCAN COUNTER
FIVE-STAGE
SCAN COUNTER
CS3 23
BUS ENABLE
CS4 24
CONTROL
LOGIC
TPB 34
25 BUS 0
C1-C3
KEY
DETECT
F/F
VDD
RX
THREE-STATE
OUTPUT
BUFFERS
C4-C8
32 BUS 7
DEBOUNCE
36
CX
RN
VDD
40
VSS
20
DA 33
STATUS
LATCHES
KEY DOWN
DETECT
LATCH
RPT 35
RPD
1 OF 8
MUX
RPD
II
DECODER/
DRIVERS
FROM
KEY BOARD
12
SENSE
LINES
RPD
RPD
TO
KEY BOARD
19
1
DI
DRIVE
LINES
FIGURE 2. CDP1871A BLOCK DIAGRAM
4-67
11
DII
37
39
ALPHA SHIFT
38
CONTROL
CDP1871A, CDP1871AC
Absolute Maximum Ratings
Thermal Information
(All Voltages Referenced to VSS Terminal)
CDP1871A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1871AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
60
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
50
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
60
18
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Package Type E and Q . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
At TA = -40 to +85oC. For maximum reliability, operating conditions should be selected
so that operation is always within the following ranges:
Recommended Operating Conditions
LIMITS
CDP1871AD, CDP1871AE
VDD
(V)
PARAMETER
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
VSS
VDD
VSS
VDD
V
5
DC
0.4
DC
0.4
MHz
10
DC
0.8
-
-
MHz
Supply Voltage Range
Recommended Input Voltage
Range
Clock Input Frequency, TPB
(Keyboard Capacitance = 200 pF)
fCL
CDP1871ACD, CDP1871ACE
NOTE:
1. Printed-circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
Static Electrical Specifications
At TA = -40 to +85oC, Unless Otherwise Specified
CONDITIONS
LIMITS
CDP1871AD
CDP1871AE
PARAMETER
Quiescent Device
Current
Output Low Drive (Sink)
Current (Except Debounce
and D1-D11)
Debounce
D1-D11
IDD
IOL
IOL
IOL
CDP1871ACD
CDP1871ACE
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE1)
TYP
MAX
UNITS
-
0.5
5
-
0.1
50
-
1
200
µA
-
0, 10
10
-
1
200
-
-
-
µA
0.4
0, 5
5
0.5
1
-
0.5
1
-
mA
0.5
0, 10
10
1
2
-
-
-
-
mA
0.4
0, 5
5
0.75
1.5
-
0.75
1.5
-
mA
0.5
0, 10
10
1
2
-
-
-
-
mA
0.4
0, 5
5
0.05
0.1
-
0.05
0.1
-
mA
0.5
0, 10
10
0.1
0.2
-
-
-
-
mA
4-68
CDP1871A, CDP1871ACCDP1871A, CDP1871AC
Static Electrical Specifications
At TA = -40 to +85oC, Unless Otherwise Specified (Continued)
CONDITIONS
LIMITS
CDP1871AD
CDP1871AE
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE1)
TYP
MAX
UNITS
4.6
0, 5
5
-0.3
-0.6
-
-0.3
-0.6
-
mA
9.5
0, 10
10
-0.75
-1.5
-
-
-
-
mA
0.5, 4.5
-
5
-
-
1.5
-
-
1.5
V
1, 9
-
10
-
-
3
-
-
-
V
0.5, 4.5
-
5
3.5
-
-
3.5
-
-
V
1, 9
-
10
7
-
-
-
-
-
V
0.4
-
5
2.0
3.3
4.0
2.0
3.3
4.0
V
0.5
-
10
4.0
6.3
8.0
-
-
-
V
0.4
-
5
0.8
1.8
3.0
0.8
1.8
3.0
V
0.5
-
10
1.9
4.0
6.0
-
-
-
V
0.4
0, 5
5
0.3
1.6
2.6
0.3
1.6
2.6
V
0.5
0, 10
10
0.7
2.3
4.7
-
-
-
V
-
0, 5
5
-
0
0.05
-
0
0.05
V
-
0, 10
10
-
0
0.05
-
-
-
V
-
0, 5
5
4.95
5
-
4.95
5
-
V
-
0, 10
10
9.95
10
-
-
-
-
V
-
0, 5
5
-
0.01
1
-
0.01
1
µA
-
0, 10
10
-
0.01
1
-
-
-
µA
0, 5
0, 5
5
-
0.01
1
-
0.02
2
µA
0, 10
0, 10
10
-
0.02
2
-
-
-
µA
RPD
-
-
-
7
14
24
7
14
24
kΩ
IOPER
0.5, 4.5
0, 5
5
-
0.6
-
-
0.6
-
mA
1, 9
0, 10
10
-
2.7
-
-
-
-
mA
PARAMETER
Output High Drive (Source)
Current
Input Low Voltage
(Except Debounce)
Input High Voltage
(Except Debounce)
Debounce Schmitt Trigger
Input Voltage
IOH
VIL
VIH
VD
Positive Trigger Voltage
Negative Trigger Voltage
Hysteresis
Output Voltage Low Level
Output Voltage High Level
Input Leakage Current
(Except S1-S8, Shift,
Control)
Three-State Output Leakage
Current
Pull-Down Resistor Value
(S1-S8, Shift, Control)
CDP1871ACD
CDP1871ACE
VN
VH
VOL
VOH
IIN
IOUT
Operating Current
(All Outputs Unloaded)
fCL = 0.4MHz
fCL = 0.8MHz
NOTE:
1. Typical values are for TA = +25oC and nominal VDD.
4-69
CDP1871A, CDP1871AC
Functional Description of
CDP1871A Terminals
D1 - D11 (Outputs):
TPB (Input):
Drive lines for the 11 x 8 keyboard switch matrix. These
outputs are connected through the external switch matrix to
the sense lines (S1 - S8).
The input clock used to drive the scan generator and reset
the status flag (DA). This input is normally connected to the
TPB output of the CDP1800-series microprocessor.
S1 - S8 (Inputs):
RPT (Output):
Sense lines for the 11 x 8 keyboard maxtrix. These inputs
have internal pull-down resistors and are driven high by
appropriate drive line when a keyboard switch is closed.
The repeat output flag which is used to indicate that a key is
still closed after data has been read from the CDP1871A
(DA = high). It remains low as long as the key is closed and
is used for an autorepeat function, under CPU control. This
output is normally connected to a flag input (EF1 - EF4) of
the CDP1800-series microprocessor.
CS1, CS2, CS3, CS4 (Inputs):
Chip select inputs, which are used to enable the three-state
data bus outputs (BUS 0 - BUS 7) and to enable the resetting of the status flag (DA), which occurs on the low-to-high
transition of TPB. These four inputs are normally connected
to the N-lines (N0-N2) and MRD output of the CDP1800series microprocessor. (Table 2)
DEBOUNCE (Input):
This input is connected to the junction of an external resistor
to VDD and capacitor to VSS. It provides a debounce time
delay (t ≅ RC) after the release of a key. If a debounce is not
desired, the external pull-up resistor is still required.
BUS 0 - BUS 7 (Outputs):
Three-state data bus outputs which provide the ASCll and
HEX codes of the detected keys. The outputs are normally
connected to the BUS 0 - BUS 7 terminals of the CDP1800series microprocessor.
DA (Output):
The data available output flag which is set low when a valid
key closure is detected. It is reset high by the low-to-high
transition of TPB when data is read from the CDP1871A.
This output is normally connected to a flag input (EF1 - EF4)
of the CDP1800-series microprocessor.
ALPHA, SHIFT, CONTROL (Inputs):
A high on the SHIFT or CONTROL inputs will be internally
latched (after the debounce time) and the drive and sense
line decoding will be modified as shown in Table 3. They are
normally connected to the keyboard, but produce no code by
themselves. The SHIFT and CONTROL inputs have internal
pull-down resistors to simplify use with momentary contact
switches. The ALPHA input is not latched and is designed for
a standard SPDT switch to provide an alpha-lock function.
When ALPHA = 1 the drive and sense line decoding will be
modified as shown in Table 3.
VDD, VSS:
VDD is the positive supply voltage input. VSS is the most
negative supply voltage terminal and is normal connected to
ground. All outputs swing from VSS to VDD. The
recommended input voltage swing is from VSS to VDD.
TABLE 1. SWITCH INPUT FUNCTIONS
NOTE:
CONTROL
SHIFT
ALPHA
KEY FUNCTION
0
0
0
Normal
1
X
X
Control
0
1
X
Shift
0
0
1
Alpha
X = Don’t Care
4-70
CDP1871A, CDP1871AC
TABLE 2. VALID N-LINE CONNECTIONS
CDP1871A SIGNAL
CS4
CS3
CS2
CS1
CPU INPUT
INSTRUCTION
MRD
N2
N0
N1
INP5
MRD
N0
N1
N2
INP3
MRD
N2
N1
N0
INP6
CPU
CDP1800- Series Signal
TABLE 3. DRIVE AND SENSE LINE KEYBOARD CONNECTIONS (NOTE 2)
DRIVE LINES
SENSE
LINES
S1
D1
SP
D2
0
0
S2
!
“
1
)
#
2
*
$
3
+
%
4
<
&
5
=
‘
-
-
6
>
6
S8
,
,
5
S7
;
;
4
S6
:
:
3
S5
9
9
2
S4
8
8
1
S3
(
D3
.
.
7
?
7
/
/
‘
D4
@
H
D5
H
P
D6
P
X
X
@
NUL
h
BS
p
DLE
x
CA
N
A
A
I
I
Q
Q
Y
Y
a
SOH
i
HT
q
DC1
y
EM
B
B
J
J
R
R
Z
Z
b
STX
j
LF
r
DC2
z
SU
B
C
C
K
K
S
S
{
[
c
ETX
k
VT
s
DC3
[
ES
C
D
D
L
L
T
T
|
|
\
EOT
I
FF
t
DC4
\
FS
E
E
M
M
U
U
}
]
e
ENQ
m
CR
u
NA
K
]
GS
F
F
N
N
V
V
~
↑
f
ACK
n
SO
v
SY
N
↑
RS
G
G
O
O
W
W
Del
-
BEL
o
SHIFT (Note 1)
ALPHA (Note 1)
NORMAL
CONTROL (Note 1)
SI
W
ETB
-
D8
D9
D10
D11
Space
801
8816
9016
9816
8916
9116
9916
8A16
9216
9A16
8B16
9316
9B16
8C16
9416
9C16
8D16
9516
9D16
8E16
9616
9E16
8F16
9716
9F16
6
811
6
Line
Feed
821
Escape
831
6
841
Carriage
Return
6
6
Delete
US
NOTES:
= No Response
2. Showing ASCII outputs for all combinations with and without SHIFT, ALPHA LOCK and CONTROL.
3. Drive lines 8, 9, 10 and 11 generate non-ASCII hex values which can be used for special codes.
4-71
851
861
KEY:
1. CONTROL overrides SHIFT and ALPHA
6
6
d
g
D7
871
6
CDP1871A, CDP1871AC
TABLE 4. HEXIDECIMAL VALUES OF ASCII CHARACTERS
MSD
b7
0
b6
BITS
0
0
0
b5
0
0
0
1
1
1
1
0
1
0
1
1
0
0
1
1
1
1
0
1
HEX
LSD
b4
b3
b2
b1
0
1
2
3
4
5
6
7
0
0
0
0
0
NUL
DLE
SP
0
@
P
\
p
0
0
0
1
1
SOH
DC1
!
1
A
Q
a
q
0
0
1
0
2
STX
DC2
“
2
B
R
b
r
0
0
1
1
3
ETX
DC3
#
3
C
S
c
s
0
1
0
0
4
EOT
DC4
$
4
D
T
d
t
0
1
0
1
5
ENQ
NAK
%
5
E
U
e
u
0
1
1
0
6
ACK
SYN
&
6
F
V
f
v
0
1
1
1
7
BEL
ETB
/
7
G
W
g
w
1
0
0
0
8
BS
CAN
(
8
H
X
h
x
1
0
0
1
9
HT
EM
)
9
I
Y
i
y
1
0
1
0
A
LF
SUB
*
:
J
Z
j
z
1
0
1
1
B
VT
ESC
+
;
K
[
k
{
1
1
0
0
C
FF
FS
,
<
L
\
l
|
|
1
1
0
1
D
CR
GS
-
=
M
]
m
}
1
1
1
0
E
SO
RS
.
>
N
↑
n
~
1
1
1
1
F
SI
US
/
?
O
-
o
DEL
Operation
The CDP1871A is made up of two major sections: the
counter/scan-selection logic and the control logic (Figure 2).
The counter and scan-selection logic scans the keyboard
array using the drive lines (D1-D11) and the sense lines (S1S8). The outputs of the internal 5-stage scancounter are
conditionally encoded by the ALPHA, SHIFT, and CONTROL
inputs (Table 1, Table 3) and are used to drive the D1-D11
output lines high one at a time. Each D1-D11 output may
drive up to eight keys, which are sampled by the sense line
inputs (S1-S8). The S1-S8 inputs are enabled by the internal
3-stage scancounter.
outputs (C1 - C8) represent the ASCII and HEX key codes
and are used to drive the BUS 0 - BUS 7 outputs, which
interface directly to the CDP1800-Series data bus. The BUS
0 - BUS 7 outputs, which are normally three-stated, are
enabled by decoding the CS inputs during a CPU input
instruction (Table 2). The low-to-high transition of TPB during
the input instruction resets the DA output high. Once the DA
output has been reset, it cannot go low again until the
present key is released and a new keydown condition is
detected. (This prevents unwanted repeated keycode outputs which may be caused by fast software routines).
The control logic interfaces with the CDP1800-series I/O and
timing signals to establish timing and status conditions for
the CDP1871A.
After the depressed key is released and the debounce delay
(determined by RX, CX) has occurred, the scan clock inhibit
is removed, allowing the scancounters to advance on the following high-to-low transitions of TPB. This provides an N-key
lockout feature, which prevents the entry of erroneous codes
when two or more keys are pressed simultaneously. The first
key pressed in the scanning order is recognized, while all
other keys pressed are ignored until the first key is released
The TPB input clocks the scancounters and is also used to
reset the Data Available output (DA). When a valid keydown
condition is detected on a sense line, the control logic inhibits the clock to the scancounters on the next low-to-high transition of TPB and the DA output is set low. The scancounter
4-72
CDP1871A, CDP1871AC
(CX) is discharged, providing a key closure debounce time ≅
RNCX. This discharge is sensed by the Schmitt-trigger
inverter, which clocks the DA flip-flop (latching the DA output
low and inhibiting the scan clock). (The DA F/F is reset by
the low-to-high transition of TPB when the CS inputs are
enabled). When a valid key-release is detected RN is disabled and CX begins to charge through the external resistor
(RX), providing a key-release debounce time ≅ RXCX. This
charge time is again sensed by the Schmitt-trigger inverter,
enabling the scan clock to continue on the next high-to-low
transitions of TPB, after the current keycode data is read by
the CPU.
and read by the CPU, at which time the next key pressed in
the scanning order is detected. If the first key remains closed
after the CPU reads the data and resets the DA output, on
the low-to-high transition of TPB, an auxiliary signal (RPT) is
generated and is available to the CPU to indicate an autorepeat condition. The RPT output is reset high at the end of
the debounce delay after the depressed key is released.
The DEBOUNCE input provides a terminal connection for an
external user-selected RC circuit to eliminate false detection
of a keydown condition caused by keyboard noise. The operation of the DEBOUNCE circuit is shown in Figure 2 (Pin
36). When a valid keydown is detected, the on-chip activeresistor device (RN) is enabled and the external capacitor
Dynamic Electrical Specifications
At TA = -40 to +85oC, VDD ±5%, Unless Otherwise Specified
LIMITS
CDP1871AD, CDP1871AE
PARAMETER
Clock Cycle Time
Clock Pulse Width High
tCC
tCWH
Data Available Valid Delay
Data Available Invalid Delay
Scan Count Delay
(Non-Repeat)
Data Out Valid Delay
Data Out Hold Time
Repeat Valid Delay
Repeat Invalid Delay
tDAL
tDAH
tCD1
tCDV
tCDH
tRPL
tRPH
CDP1871ACD, CDP1871ACE
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
5
-
-
-
-
-
-
Note 2
10
-
-
-
-
-
-
Note 2
5
100
40
-
100
40
-
ns
10
50
20
-
-
-
-
ns
5
-
260
500
-
260
500
ns
10
-
130
250
-
-
-
ns
5
-
70
150
-
70
150
ns
10
-
35
75
-
-
-
ns
5
-
850
1900
-
850
1900
ns
10
-
425
950
-
-
-
ns
5
-
120
250
-
120
250
ns
10
-
60
125
-
-
-
ns
5
-
100
200
-
100
200
ns
10
-
50
100
-
-
-
ns
5
-
150
400
-
150
400
ns
10
-
75
200
-
-
-
ns
5
-
350
700
-
350
700
ns
10
-
170
350
-
-
-
ns
NOTES:
1. Typical values are for TA = +25oC and nominal VDD.
2. tCC = tCWH + tCWL
tCWL = tCD1 + KC
k = 0.9ns per pF
c = Keyboard capacitance (pF)
4-73
CDP1871A, CDP1871AC
tCC
TPB
tCWL
tCWH
KEY
CLOSURE
OPEN
CLOSED
tDAL
tDAH
DA
RPT
RNCX
RXCX
DEBOUNCE
tCD1
D1-D11
NEXT COUNT
PRESENT COUNT
CS
(NOTE)
tCDH
tCDV
BUS0-BUS7
VALID
NOTE: CS = CS1 • CS2 • CS3 • CS4
CS1, CS2, CS3 = (CPU N-LINES)
CS4 (MRD) is High for CPU Input Instruction
FIGURE 3. CDP1871A DYNAMIC TIMING DIAGRAM (NON-REPEAT)
TPB
KEY
DEPRESSED
OPEN
CLOSED
tDAH
DA
tRPH
tRPL
RPT
RXCX
DEBOUNCE
D1-D11
NEXT COUNT
PRESENT COUNT
CS
(NOTE)
tCDV
BUS0-BUS7
tCDH
VALID
NOTE: CS = CS1 • CS2 • CS3 • CS4
CS1, CS2, CS3 = (CPU N-LINES)
CS4 (MRD) is High for CPU Input Instruction
FIGURE 4. FIGURE 4. CDP1871A DYNAMIC TIMING DIAGRAM (REPEAT)
4-74
CDP1871A, CDP1871AC
START
MAIN
PROGRAM
N
DA
=0?
Y
INPUT KEY
DATA
STORE KEY
DATA
DATA =
ASCII CTRL
CHAR. OR
HEX
CODE
?
Y
N
DISPLAY
CHARACTER
PERFORM CONTROL
FUNCTION
IS
CHAR. A
REPEATABLE
CHAR.
?
N
Y
DELAY
Y
RPT
=0?
N
FIGURE 5. TYPICAL SYSTEM SOFTWARE FLOWCHART FOR CDP1871A, CDP1871AC
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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