Cypress CY2308SXC-3T 3.3v zero delay buffer Datasheet

CY2308
3.3V Zero Delay Buffer
Features
■
Zero input-output propagation delay, adjustable by
capacitive load on FBK input
■
Multiple configurations, see “Available CY2308 Configurations” on page 3
■
Multiple low skew outputs
■
Two banks of four outputs, three-stateable by two select
inputs
■
10 MHz to 133 MHz operating range
■
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
■
Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
■
3.3V operation
■
Industrial Temperature available
Input Decoding” on page 2”. If all output clocks are not
required, Bank B is three-stated. The input clock is directly
applied to the output for chip and system testing purposes by
the select inputs.
The CY2308 PLL enters a power down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than
50 μA of current draw. The PLL shuts down in two additional
cases as shown in the table “Select Input Decoding” on
page 2.
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
Functional Description
The CY2308 is a 3.3V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven into the
FBK pin and obtained from one of the outputs. The
input-to-output skew is less than 350 ps and output-to-output
skew is less than 200 ps.
The CY2308 has two banks of four outputs each that is
controlled by the Select inputs as shown in the table “Select
The CY2308 is available in five different configurations as
shown in the table “Available CY2308 Configurations” on
page 3. The CY2308–1 is the base part where the output
frequencies equal the reference if there is no counter in the
feedback path. The CY2308–1H is the high drive version of the
–1 and rise and fall times on this device are much faster.
The CY2308–2 enables the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration and
output frequencies depend on the output that drives the
feedback pin. The CY2308–3 enables the user to obtain 4X
and 2X frequencies on the outputs.
The CY2308–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308–5H is a high drive version with REF/2 on both
banks.
Logic Block Diagram
/2
REF
FBK
PLL
MUX
/2
CLKA1
CLKA2
Extra Divider (–3, –4)
CLKA3
Extra Divider (–5H)
CLKA4
S2
Select Input
Decoding
S1
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –3)
Cypress Semiconductor Corporation
Document Number: 38-07146 Rev. *E
•
198 Champion Court
CLKB4
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 03, 2007
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CY2308
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC
Top View
REF
CLKA1
1
16
2
15
CLKA2
VDD
3
14
4
13
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Table 1. Pin Definitions - 16 Pin SOIC
Pin
Signal
Description
1
REF[1]
2
CLKA1[2]
Clock output, Bank A
3
[2]
CLKA2
Clock output, Bank A
4
VDD
3.3V supply
5
GND
Input reference frequency, 5V tolerant input
Ground
6
[2]
CLKB1
Clock output, Bank B
7
CLKB2[2]
Clock output, Bank B
8
[3]
S2
Select input, bit 2
Select input, bit 1
9
S1[3]
10
CLKB3[2]
Clock output, Bank B
11
[2]
CLKB4
Clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
[2]
Clock output, Bank A
14
CLKA3
15
CLKA4[2]
Clock output, Bank A
16
FBK
PLL feedback input
Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
0
Tri-State
Tri-State
PLL
Y
0
1
Driven
Tri-State
PLL
N
Driven[4]
Reference
Y
Driven
PLL
N
1
0
1
1
Driven
[4]
Driven
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0.
Document Number: 38-07146 Rev. *E
Page 2 of 15
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CY2308
Available CY2308 Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
CY2308–1
Bank A or Bank B
Reference
Reference
CY2308–1H
Bank A or Bank B
Reference
Reference
CY2308–2
Bank A
Reference
Reference/2
CY2308–2
Bank B
2 X Reference
Reference
CY2308–3
Bank A
2 X Reference
Reference or Reference[5]
CY2308–3
Bank B
4 X Reference
2 X Reference
CY2308–4
Bank A or Bank B
2 X Reference
2 X Reference
CY2308–5H
Bank A or Bank B
Reference /2
Reference /2
Zero Delay and Skew Control
Table 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK pin and CLKA/CLKB Pins
To close the feedback loop of the CY2308, the FBK pin is driven
from any of the eight available output pins. The output driving the
FBK pin drives a total load of 7 pF plus any additional load that
it drives. The relative loading of this output to the remaining
outputs adjusts the input-output delay. This is shown in the
Table 2.
If input-output delay adjustments are required, use the Zero
Delay and Skew Control graph to calculate loading differences
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
“CY2308: Zero Delay Buffer.”
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
Note
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
Document Number: 38-07146 Rev. *E
Page 3 of 15
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CY2308
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
Storage Temperature .................................. –65°C to +150°C
DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V
Junction Temperature .................................................. 150°C
DC Input Voltage REF ........................................... –0.5 to 7V
Static Discharge Voltage
(MIL-STD-883, Method 3015).................................... >2000V
Operating Conditions for Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
3.0
3.6
V
0
70
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, below 100 MHz
–
30
pF
Load Capacitance, from 100 MHz to 133 MHz
–
15
pF
CIN
Input Capacitance[6]
–
7
pF
tPU
Power up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
50
ms
Min
Max
Unit
Electrical Characteristics for Commercial Temperature Devices
Parameter
Description
Test Conditions
VIL
Input LOW Voltage
–
0.8
V
VIH
Input HIGH Voltage
2.0
–
V
IIL
Input LOW Current
VIN = 0V
–
50.0
μA
IIH
Input HIGH Current
VIN = VDD
–
100.0
μA
VOL
Output LOW Voltage[7]
IOL = 8 mA (–1, –2, –3, –4)
IOL = 12 mA (–1H, –5H)
–
0.4
V
VOH
Output HIGH Voltage[7]
IOH = –8 mA (–1, –2, –3, –4)
IOH = –12 mA (–1H, –5H)
2.4
–
V
IDD (PD mode)
Power Down Supply Current REF = 0 MHz
–
12.0
μA
IDD
Supply Current
Unloaded outputs, 100 MHz REF,
Select inputs at VDD or GND
–
45.0
mA
–
70.0
(–1H,–5H)
mA
Unloaded outputs, 66 MHz REF
(–1, –2, –3, –4)
–
32.0
mA
Unloaded outputs, 33 MHz REF
(–1, –2, –3, –4)
–
18.0
mA
Note
6. Applies to both Ref Clock and FBK.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07146 Rev. *E
Page 4 of 15
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CY2308
Switching Characteristics for Commercial Temperature Devices [8]
Min.
Typ.
Max.
Unit
t1
Parameter
Output Frequency
Name
30-pF load, All devices
Test Conditions
10
–
100
MHz
t1
Output Frequency
20-pF load, –1H, –5H devices[9]
10
–
133.3
MHz
t1
Output Frequency
15-pF load, –1, –2, –3, –4 devices
10
–
133.3
MHz
Duty Cycle[7] = t2 ÷ t1
(–1, –2, –3, –4, –1H, –5H)
Measured at 1.4V, FOUT = 66.66 MHz
30-pF load
40.0
50.0
60.0
%
Duty Cycle[7] = t2 ÷ t1
(–1, –2, –3, –4, –1H, –5H)
Measured at 1.4V, FOUT <50.0 MHz
15-pF load
45.0
50.0
55.0
%
t3
Rise Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30-pF load
–
–
2.20
ns
t3
Rise Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15-pF load
–
–
1.50
ns
t3
Rise Time[7]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30-pF load
–
–
1.50
ns
t4
Fall Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30-pF load
–
–
2.20
ns
t4
Fall Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15-pF load
–
–
1.50
ns
t4
Fall Time[7]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30-pF load
–
–
1.25
ns
t5
Output to Output Skew on
same Bank
(–1, –2, –3, –4)[7]
All outputs equally loaded
–
–
200
ps
Output to Output Skew
(–1H, –5H)
All outputs equally loaded
–
–
200
ps
Output Bank A to Output
All outputs equally loaded
Bank B Skew (–1, –4, –5H)
–
–
200
ps
Output Bank A to Output
Bank B Skew (–2, –3)
–
–
400
ps
All outputs equally loaded
t6
Delay, REF Rising Edge to Measured at VDD/2
FBK Rising Edge[7]
–
0
±250
ps
t7
Device to Device Skew[7]
Measured at VDD/2 on the FBK pins of
devices
–
0
700
ps
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V on –1H,
–5H device using Test Circuit 2
1
–
tJ
Cycle to Cycle Jitter[7]
(–1, –1H, –4, –5H)
Measured at 66.67 MHz, loaded outputs,
15-pF load
–
75
200
ps
Measured at 66.67 MHz, loaded outputs,
30-pF load
–
–
200
ps
Measured at 133.3 MHz, loaded outputs,
15-pF load
–
–
100
ps
Measured at 66.67 MHz, loaded outputs
30-pF load
–
–
400
ps
Measured at 66.67 MHz, loaded outputs
15-pF load
–
–
400
ps
Stable power supply, valid clocks presented
on REF and FBK pins
–
–
1.0
ms
tJ
tLOCK
Cycle to Cycle Jitter[7]
(–2, –3)
PLL Lock Time[7]
V/ns
Notes
8. All parameters are specified with loaded outputs.
9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz.
Document Number: 38-07146 Rev. *E
Page 5 of 15
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CY2308
Operating Conditions for Industrial Temperature Devices
Min
Max
Unit
VDD
Parameter
Supply Voltage
Description
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
–40
85
°C
CL
Load Capacitance, below 100 MHz
–
30
pF
Load Capacitance, from 100 MHz to 133 MHz
–
15
pF
CIN
Input Capacitance[6]
–
7
pF
tPU
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
50
ms
Min
Max
Unit
Electrical Characteristics for Industrial Temperature Devices
Parameter
Description
Test Conditions
VIL
Input LOW Voltage
–
0.8
V
VIH
Input HIGH Voltage
2.0
–
V
IIL
Input LOW Current
VIN = 0V
–
50.0
μA
IIH
Input HIGH Current
VIN = VDD
–
100.0
μA
VOL
Output LOW Voltage[7]
IOL = 8 mA (–1, –2, –3, –4)
IOL = 12 mA (–1H, –5H)
–
0.4
V
VOH
Output HIGH Voltage[7]
IOH = –8 mA (–1, –2, –3, –4)
IOH = –12 mA (–1H, –5H)
2.4
–
V
IDD (PD mode)
Power Down Supply Current
REF = 0 MHz
–
25.0
μA
IDD
Supply Current
Unloaded outputs, 100 MHz,
Select inputs at VDD or GND
–
45.0
mA
–
70(–1H,–5H)
mA
Unloaded outputs, 66 MHz REF
(–1, –2, –3, –4)
–
35.0
mA
Unloaded outputs, 66 MHz REF
(–1, –2, –3, –4)
–
20.0
mA
Document Number: 38-07146 Rev. *E
Page 6 of 15
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CY2308
Switching Characteristics for Industrial Temperature Devices [8]
Min
Typ
Max
Unit
t1
Parameter
Output Frequency
30 pF load, All devices
10
–
100
MHz
t1
Output Frequency
20 pF load, –1H, –5H devices[9]
10
–
133.3
MHz
t1
Output Frequency
15 pF load, –1, –2, –3, –4 devices
10
–
133.3
MHz
Duty Cycle[7] = t2 ÷ t1
(–1, –2, –3, –4, –1H, –5H)
Measured at 1.4V, FOUT = 66.66 MHz
30 pF load
40.0
50.0
60.0
%
Duty Cycle[7] = t2 ÷ t1
(–1, –2, –3, –4, –1H, –5H)
Measured at 1.4V, FOUT <50.0 MHz
15 pF load
45.0
50.0
55.0
%
t3
Rise Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30 pF load
–
–
2.50
ns
t3
Rise Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15 pF load
–
–
1.50
ns
t3
Rise Time[7]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30 pF load
–
–
1.50
ns
t4
Fall Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30 pF load
–
–
2.50
ns
t4
Fall Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15 pF load
–
–
1.50
ns
t4
Fall Time[7]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30 pF load
–
–
1.25
ns
t5
Output to Output Skew on
All outputs equally loaded
same Bank (–1, –2, –3, –4)[7]
–
–
200
ps
Output to Output Skew
(–1H, –5H)
All outputs equally loaded
–
–
200
ps
Output Bank A to Output
Bank B Skew (–1, –4, –5H)
All outputs equally loaded
–
–
200
ps
Output Bank A to Output
Bank B Skew (–2, –3)
All outputs equally loaded
–
–
400
ps
t6
Delay, REF Rising Edge to
FBK Rising Edge[7]
Measured at VDD/2
–
0
±250
ps
t7
Device to Device Skew[7]
Measured at VDD/2 on the FBK pins of
devices
–
0
700
ps
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V on –1H,
–5H device using Test Circuit 2
1
–
–
V/ns
tJ
Cycle to Cycle Jitter[7]
(–1, –1H, –4, –5H)
Measured at 66.67 MHz, loaded outputs,
15 pF load
–
75
200
ps
Measured at 66.67 MHz, loaded outputs,
30 pF load
–
–
200
ps
Measured at 133.3 MHz, loaded outputs,
15 pF load
–
–
100
ps
Measured at 66.67 MHz, loaded outputs
30 pF load
–
–
400
ps
Measured at 66.67 MHz, loaded outputs
15 pF load
–
–
400
ps
Stable power supply, valid clocks
presented on REF and FBK pins
–
–
1.0
ms
tJ
tLOCK
Name
Cycle to Cycle Jitter[7]
(–2, –3)
PLL Lock Time[7]
Document Number: 38-07146 Rev. *E
Test Conditions
Page 7 of 15
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CY2308
Switching Waveforms
Figure 2. Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
Figure 3. All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
3.3V
0V
t4
t3
Figure 4. Output-Output Skew
OUTPUT
1.4V
1.4V
OUTPUT
t5
Figure 5. Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
FBK
t6
Figure 6. Device-Device Skew
VDD/2
FBK, Device 1
VDD/2
FBK, Device 2
t7
Document Number: 38-07146 Rev. *E
Page 8 of 15
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CY2308
Typical Duty Cycle[10] and IDD Trends[11] for CY2308–1,2,3,4
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
58
56
56
54
52
33 MHz
50
66 MHz
48
100 MHz
46
44
Duty Cycle (% )
Duty Cycle (% )
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
54
33 MHz
52
66 MHz
50
100 MHz
48
133 MHz
46
44
42
42
40
3
3.1
3.2
3.3
3.4
3.5
40
3.6
3
VDD (V)
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
60
60
58
58
56
54
-40C
52
0C
50
25C
48
70C
46
85C
44
Duty Cycle (%)
Duty Cycle (%)
56
54
-40C
52
0C
50
25C
48
70C
46
85C
44
42
42
40
40
20
40
60
80
100
120
140
20
40
60
Frequency (MHz)
80
100
120
140
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
140
140
120
120
100
100
80
33 M Hz
66 M Hz
60
80
33 M Hz
60
66 M Hz
100 M Hz
100 M Hz
40
40
20
20
0
0
0
2
4
6
N umb er o f Lo ad ed Out p ut s
8
0
2
4
6
8
N umb er o f Lo ad ed Out p ut s
Notes
10. Duty Cycle is taken from typical chip measured at 1.4V.
11. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current.
(n = number of outputs; C = Capacitance load per output (F); V = Voltage Supply (V); f = frequency (Hz).
Document Number: 38-07146 Rev. *E
Page 9 of 15
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CY2308
Typical Duty Cycle[10] and IDD Trends[11] for CY2308–1H, 5H
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
58
56
56
54
52
33 MHz
50
66 MHz
48
100 MHz
46
Duty Cycle (% )
Duty Cycle (% )
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
54
66 MHz
50
100 MHz
48
133 MHz
46
44
44
42
42
40
33 MHz
52
40
3
3.1
3.2
3.3
3.4
3.5
3.6
3
3.1
3.2
VDD (V)
3.4
3.5
3.6
Duty
Cycle
Vs Frequency
Duty
Cycle
Vs VDD
(for 15
15pF
pFLoads
Loadsover
overFrequency
Temperature
- 3.3V)
(for
- 3.3V,
25C)
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
60
60
60
58
58
58
56
56
54
-40C
52
0C
50
25C
48
70C
46
85C
Duty
Cycle (%
Duty Cycle
(%))
56
Duty Cycle (%)
3.3
VDD (V)
54
54
-40C
33 M
Hz
0C
52
52
66 MHz
25C
100 MHz
70C
133 MHz
85C
50
50
48
48
46
46
44
44
44
42
42
42
40
40
40
20
40
60
80
100
120
320
140
40
3.1
60
3.2
80
3.3
100
3.4
120
3.5
140
3.6
Frequency
VDD (V) (MHz)
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
140
140
120
120
100
100
33 MHz
80
60
33 MHz
80
66 MHz
60
100 MHz
66 MHz
100 MHz
40
40
20
20
0
0
0
0
2
4
6
N u m b e r o f L o a d e d Ou t p u t s
Document Number: 38-07146 Rev. *E
2
4
6
8
8
N u m b e r o f L o a d e d Ou t p u t s
Page 10 of 15
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CY2308
Test Circuits
Test Circuit 1
Test Circuit 2
VDD
V DD
0.1 μF
Outputs
CLK OUT
0.1 μF
GND
Test Circuit for all parameters except t8
Document Number: 38-07146 Rev. *E
10 pF
V DD
V DD
GND
CLK out
Outputs
1 KΩ
C LOAD
0.1 μF
1 KΩ
0.1 μF
GND
GND
Test Circuit for t8, Output slew rate on –1H, –5 device
Page 11 of 15
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CY2308
Ordering Information
Ordering Code
Package Type
Operating Range
CY2308SC–1
16-pin 150 mil SOIC
Commercial
CY2308SC–1T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SI–1
16-pin 150 mil SOIC
Industrial
CY2308SI–1T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SC–1H
16-pin 150 mil SOIC
Commercial
CY2308SC–1HT
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SI–1H
16-pin 150 mil SOIC
Industrial
CY2308SI–1HT
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308ZC–1H
16-pin 150 mil TSSOP
Commercial
CY2308ZC–1HT
16-pin 150 mil TSSOP - Tape and Reel
Commercial
CY2308ZI–1H
16-pin 150 mil TSSOP
Industrial
CY2308ZI–1HT
16-pin 150 mil TSSOP - Tape and Reel
Industrial
CY2308SC–2
16-pin 150 mil SOIC
Commercial
CY2308SC–2T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SI–2
16-pin 150 mil SOIC
Industrial
CY2308SI–2T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SC–3
16-pin 150 mil SOIC
Commercial
CY2308SC–3T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SC–4
16-pin 150 mil SOIC
Commercial
CY2308SC–4T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SI–4
16-pin 150 mil SOIC
Industrial
CY2308SI–4T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SC–5HT
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXC–1
16-pin 150 mil SOIC
Commercial
CY2308SXC–1T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI–1
16-pin 150 mil SOIC
Industrial
CY2308SXI–1T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SXC–1H
16-pin 150 mil SOIC
Commercial
CY2308SXC–1HT
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI–1H
16-pin 150 mil SOIC
Industrial
CY2308SXI–1HT
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308ZXC–1H
16-pin 150 mil TSSOP
Commercial
CY2308ZXC–1HT
16-pin 150 mil TSSOP - Tape and Reel
Commercial
CY2308ZXI–1H
16-pin 150 mil TSSOP
Industrial
CY2308ZXI–1HT
16-pin 150 mil TSSOP - Tape and Reel
Industrial
CY2308SXC–2
16-pin 150 mil SOIC
Commercial
CY2308SXC–2T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI–2
16-pin 150 mil SOIC
Industrial
CY2308SXI–2T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SXC–3
16-pin 150 mil SOIC
Commercial
CY2308SXC–3T
16-pin 150 mil SOIC - Tape and Reel
Commercial
Pb-Free
Document Number: 38-07146 Rev. *E
Page 12 of 15
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CY2308
Ordering Information
(continued)
Ordering Code
Package Type
Operating Range
CY2308SXI–3
16-pin 150 mil SOIC
Industrial
CY2308SXI–3T
16-pin 150 mil SOIC -Tape and Reel
Industrial
CY2308SXC–4
16-pin 150 mil SOIC
Commercial
CY2308SXC–4T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI–4
16-pin 150 mil SOIC
Industrial
CY2308SXI–4T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SXC–5H
16-pin 150 mil SOIC
Commercial
CY2308SXC–5HT
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI–5H
16-pin 150 mil SOIC
Industrial
CY2308SXI–5HT
16-pin 150 mil SOIC - Tape and Reel
Industrial
Document Number: 38-07146 Rev. *E
Page 13 of 15
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CY2308
Package Drawings and Dimensions
16-Pin (150 Mil) SOIC S16.15
16 Lead (150 Mil) SOIC
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.386[9.804]
0.393[9.982]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068-*B
16-Pin TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05 gms
PART #
4.30[0.169]
4.50[0.177]
Z16.173
STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
Document Number: 38-07146 Rev. *E
Page 14 of 15
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CY2308
Document History Page
Document Title: CY2308 3.3V Zero Delay Buffer
Document Number: 38-07146
REV.
ECN NO.
Issue Date
Orig. of
Change
**
110255
12/17/01
SZV
*A
118722
10/31/02
RGL
Added Note 1 in page 2.
*B
121832
12/14/02
RBI
Power up requirements added to Operating Conditions Information
*C
235854
See ECN
RGL
Added Pb-Free Devices
*D
310594
See ECN
RGL
Removed obsolete parts in the ordering information table
Specified typical value for cycle-to-cycle jitter
*E
1344343
See ECN
Description of Change
Changed from Specification number: 38-00528 to 38-07146
KVM/VED Brought the Ordering Information Table up to date: removed three obsolete parts
and added two parts
Changed titles to tables that are specific to commercial and industrial temperature
ranges
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07146 Rev. *E
Revised August 03, 2007
Page 15 of 15
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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